Power module and power conversion device

Abstract

The embodiment of the invention provides a power module and a power conversion device. The power module includes: a first metal-clad substrate; the chipset is arranged on the first metal-clad layer substrate, and the chipset comprises at least two chips; the connecting sheet covers one side, deviating from the first metal-coated substrate, of the chip group, each connecting unit is electrically connected with a corresponding chip, every two adjacent connecting units are connected through the main body in a first direction, each connecting arm is arranged corresponding to two adjacent chips of the chip group, the connecting arms are connected with the first metal-coated substrate, and the first metal-coated substrate is arranged on the main body. The shortest distance between the connecting arm and one of the two adjacent chips is the first shortest distance, the shortest distance between the connecting arm and the other one of the two adjacent chips is the second shortest distance, and the difference value between the first shortest distance and the second shortest distance is within the preset threshold value, so that the current path of each chip can be balanced, and the current path of each chip can be balanced. Parasitic parameter differences among the chips are reduced, so that the dynamic current sharing characteristic of the parallel chips is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power module and a power conversion device. Background Art

[0002] With the development of power electronics technology, power modules have attracted more and more attention. The electrical connection of semiconductor chips in power modules is mainly achieved by aluminum wire welding technology, which connects the semiconductor chip electrodes to the metal layer on the surface of the substrate through aluminum wires. However, when more chips are arranged in the power module, the number of aluminum wires will increase accordingly. More aluminum wires will increase the parasitic inductance of the power module. When multiple chips are connected in parallel, multiple aluminum wire connections will cause uneven currents between the multiple parallel chips. Uneven currents will cause uneven heat generation of the parallel chips. Local heating will seriously affect the performance of the chip, and thus the performance of the power module. Summary of the invention

[0003] The embodiments of the present application provide a power module and a power conversion device that can help reduce parasitic inductance and improve current.

[0004] In a first aspect, an embodiment of the present application provides a power module, the power module comprising:

[0005] a first metal-clad substrate;

[0006] A chipset, disposed on the first metal-clad substrate, the chipset comprising at least two chips arranged in a straight line along a first direction, the first direction being parallel to a plane where a side of the chip is away from the first metal-clad substrate;

[0007] A connecting piece, the connecting piece covers the side of the chipset away from the first metal-clad substrate, the connecting piece includes a main body, at least two connecting units and at least one connecting arm, each connecting unit is electrically connected to a corresponding chip, each adjacent two connecting units are connected in a first direction through the main body to each connecting arm corresponding to two adjacent chips of the chipset, the connecting arm is connected to the first metal-clad substrate, the shortest distance between the connecting arm and one of the two adjacent chips of the chipset is a first shortest distance, the shortest distance between the connecting arm and the other of the two adjacent chips is a second shortest distance, and the difference between the first shortest distance and the second shortest distance is not greater than 30% of the first shortest distance.

[0008] The chips in the chipset are connected in parallel through connecting plates. Since the connecting plates are wider than the commonly used aluminum wires, their flow paths are larger, which is conducive to strengthening the connectivity between multiple chips, improving the consistency of parasitic parameters between parallel chips, and thus optimizing the dynamic current sharing between multiple parallel chips.

[0009] The contact between the aluminum wire and the chip is point contact, and the aluminum wire is more likely to detach from the chip. In the present application, the contact between the connecting piece and the chip is surface contact, which improves the connection strength between the connecting piece and the chip. In this way, the structural reliability between multiple chips is enhanced and the stability of current transmission is ensured. In addition, the chips in the chipset are arranged in a straight line along the first direction, and the connecting piece covers the side of the chipset away from the first metal-clad substrate. In this way, two adjacent chips are connected by the shortest straight line path. Since the connecting piece and the chip are in surface contact, it is also beneficial to improve the transient heat dissipation capability of the power module.

[0010] Each connection unit is electrically connected to a corresponding chip, and each two adjacent connection units are connected in the first direction through the main body, that is, two adjacent chips are connected through the main body in the shortest straight line path. Multiple chips in the parallel chipset are connected in the shortest straight line path through the connecting sheet to reduce the interconnection parasitic inductance between the chips.

[0011] Each connecting arm is set corresponding to two adjacent chips in the chipset, the shortest distance between the connecting arm and one chip is the first shortest distance, the shortest distance between the connecting arm and another chip is the second shortest distance, and the difference between the first shortest distance and the second shortest distance is not greater than 30% of the first shortest distance. Among the two adjacent chips, one chip, the connecting piece and the first metal-clad substrate form a first interconnection path, and the other chip, the connecting piece and the first metal-clad substrate form a second interconnection path. The first interconnection path and the second interconnection path are roughly symmetrical, which is conducive to balancing the current paths of each chip and reducing the differences in parasitic parameters between each chip, thereby further improving the dynamic current sharing characteristics of the parallel chips.

[0012] According to the first aspect, in a possible implementation, each chip includes a first source and a second source arranged along a first direction, and in two adjacent chips of the chip group, the first source of one chip is arranged adjacent to the second source of the other chip, and the connecting unit is electrically connected to the first source and the second source of the corresponding chip, and the connecting arm is protruding on the main body and bends and extends toward the first metal-clad substrate, so that the connecting arm extends to a pre-connection position with the first metal-clad substrate.

[0013] In a possible implementation, the connection point between the connecting arm and the first metal-clad substrate is located on the midline of the shortest connection line between two adjacent chips. The first shortest distance and the second shortest distance can be considered the same.

[0014] According to the first aspect, in a possible implementation, the chip also includes a gate wiring, a first source, a gate wiring, and a second source are arranged along a first direction, and each connection unit also includes a first contact portion, an avoidance space, and a second contact portion arranged in sequence along the first direction, the first contact portion contacts the first source, the second contact portion contacts the second source, and the avoidance space has an avoidance opening arranged toward the gate wiring, and the position of the avoidance opening corresponds to the position of the gate wiring.

[0015] The size of the chip is very small, and the gate wiring is easily damaged due to the stress, making the chip unusable. In this possible implementation, the position of the avoidance opening of the avoidance space corresponds to the position of the gate wiring, so that the connection piece avoids the gate wiring, reducing the stress of the connection piece on the gate wiring, which is conducive to reducing the possibility of gate wiring damage and extending the cycle life of the power module.

[0016] According to the first aspect, in a possible implementation, at least two connection holes are formed on the main body, each connection unit is arranged in a corresponding connection hole, the first contact portion is connected to the hole wall of the connection hole, and the second contact portion is connected to the hole wall of the connection hole.

[0017] According to the first aspect, in a possible implementation, the main body and the first metal-clad substrate are spaced apart. In each connection unit, at least one of the first contact portion and the second contact portion is connected to the main body, the first contact portion connected to the main body and the second contact portion connected to the main body both include a connection segment and a contact segment, at least a portion of the connection segment is bent relative to the main body, the connection segment is connected between the main body and the contact segment, the contact segment of the first contact portion contacts the corresponding first source electrode, and the contact segment of the second contact portion contacts the corresponding second source electrode.

[0018] In this possible implementation, the bending section is bent relative to the main body, and the contact section is connected to the main body through the bending section, so that the main body is above the chip, thereby improving the layout flexibility of the power module.

[0019] According to the first aspect, in a possible implementation, the power module further includes a plastic package, which wraps the first metal-clad substrate, the chipset and the connecting piece. A first glue locking hole is provided at the connection between the connecting section and the main body, and the plastic package fills the first glue locking hole.

[0020] The plastic encapsulation body is prone to delamination at the bends of the structural parts and the continuous large-area plane areas of the structural parts, which affects the sealing of the power module. In this possible implementation, since a first glue locking hole is provided at the connection between the connecting section and the main body, the plastic encapsulation body fills the first glue locking hole, which reduces the possibility of delamination of the plastic encapsulation body at the connection between the main body and the connecting section, and / or reduces the diffusion of the delamination of the plastic encapsulation body to the surface of the chip, which is conducive to improving the sealing of the power module.

[0021] According to the first aspect, in a possible implementation, the power module further includes a plastic package, which wraps the first metal-clad substrate, the chipset and the connecting piece, and a second glue locking hole is provided on the main body, and the plastic package fills the second glue locking hole.

[0022] The plastic encapsulation body is prone to delamination at the bends of the structural parts and the continuous large-area plane areas of the structural parts, which affects the sealing of the power module. In this possible implementation, since the second glue locking hole is provided on the main body, the plastic encapsulation body fills the second glue locking hole, which reduces the possibility of delamination of the plastic encapsulation body at the main body or reduces the diffusion of the delamination of the plastic encapsulation body to the surface of the chip, which is conducive to improving the sealing of the power module.

[0023] According to the first aspect, in a possible implementation, in at least one connection unit, the first contact portion and the second contact portion are spaced apart in the first direction, the avoidance space is a groove that penetrates the connection sheet in the second direction, and the second direction is perpendicular to the chip away from the plane where the first metal-clad substrate is located.

[0024] In this possible implementation, the avoidance space is a groove that penetrates the connecting piece in the second direction, so as to further reduce the stress of the connecting piece on the gate wiring.

[0025] According to the first aspect, in a possible implementation, at least one connecting unit also includes a bending portion, which is connected between the first contact portion and the second contact portion in a first direction, and the bending portion protrudes in a direction away from the first metal-clad substrate, and the first contact portion, the bending portion, and the second contact portion form an avoidance space.

[0026] In this possible implementation, the first contact portion and the second contact portion are fixedly connected via the bent portion, which is beneficial to enhancing the strength of the connecting piece.

[0027] According to the first aspect, in a possible implementation manner, a buffer hole is provided on the bent portion and penetrates the bent portion along a second direction, and the second direction is perpendicular to a plane where the chip is away from the first metal-clad substrate.

[0028] In this possible implementation, the buffer hole is used to reduce and buffer the stress applied by the connecting piece to the chip, which helps to reduce the possibility of chip damage due to the stress of the connecting piece and improves the cycle life of the power module.

[0029] According to the first aspect, in a possible implementation, the first metal-clad substrate includes a first insulating substrate and a mounting metal layer covering the first insulating substrate, the chip group is arranged on the side of the mounting metal layer away from the first insulating substrate, the number of the mounting metal layers is multiple, and the multiple mounting metal layers are arranged at intervals on the first insulating substrate, the multiple mounting metal layers include a first mounting metal layer, a second mounting metal layer, a third mounting metal layer and a fourth mounting metal layer, the second mounting metal layer includes a first extension portion, a groove and a second extension portion, one end of the first extension portion is connected to one end of the second extension portion, the first mounting metal layer, the first extension portion, the groove, the second extension portion and the third mounting metal layer are arranged in sequence along a third direction, at least a portion of the fourth mounting metal layer is located in the groove, the third direction is parallel to the plane where the chip is away from the first metal-clad substrate, and the third direction is perpendicular to the first direction.

[0030] In this possible implementation, multiple chipsets are helpful to improve the working efficiency of the power module.

[0031] According to the first aspect, in a possible implementation, the power module also includes an input end and an output end, and the input end and the output end are located at opposite ends of the first metal-clad substrate in the first direction. The metal-clad substrate power module is a half-bridge arm power module, and the input end includes a first power positive pin, a second power positive pin and a third power negative pin. The first power positive pin is electrically connected to the first mounting metal layer, the second power positive pin is electrically connected to the third mounting metal layer, the third power negative pin is electrically connected to the fourth mounting metal layer, and the output end is electrically connected to the second mounting metal layer.

[0032] In this possible implementation, three power pins are provided at the input end, which is beneficial to improving the current flow path of the power module at the input end, reducing the parasitic inductance in the power loop, and reducing the switching loss.

[0033] According to the first aspect, multiple chipsets include a first chipset, a second chipset, a third chipset and a fourth chipset, the first chipset is located on the first mounting metal layer, the second chipset is located on the second mounting metal layer, the third chipset is located on the third mounting metal layer, and the fourth chipset is located on the second extension portion, the connecting arm on the first chipset is electrically connected to the second mounting metal layer, the connecting arm on the second chipset is electrically connected to the fourth mounting metal layer, and the connecting arm on the third chipset is electrically connected to the second mounting metal layer, the first chipset, the second chipset, the fourth chipset and the third chipset are arranged in sequence along a third direction, the connecting arm on the first chipset is electrically connected to the first extension portion, the connecting arm on the second chipset is electrically connected to the fourth metal layer, the connecting arm on the third chipset is electrically connected to the second extension portion, and the connecting arm on the fourth chipset is electrically connected to the fourth mounting metal layer.

[0034] In this possible implementation, the power module is a half-bridge arm power module, and the power module also includes an upper bridge part and a lower bridge part, the upper bridge part includes a first chipset, a third chipset, a first power positive pin and a second power positive pin, and the lower bridge part includes a second chipset, a fourth chipset, and a third power negative pin. In the third direction, the upper bridge part of the half-bridge arm power module is located in the two outer columns, and the lower bridge part is located in the two middle columns. The upper bridge part has two power pins located on the outer side, and the lower bridge part has one power pin located in the middle. The design of three power pins and connecting pieces reduces the parasitic inductance and switching loss of the power circuit.

[0035] According to the first aspect, in a possible implementation, the power module also includes a second metal-clad substrate and electronic components, the second metal-clad substrate is located on the first metal-clad substrate, the electronic components are located on a side of the second metal-clad substrate away from the first metal-clad substrate, and are electrically connected to the second metal-clad substrate.

[0036] Since the size of electronic components is generally small, if the electronic components are directly soldered on the first metal-clad substrate, it is necessary to open an insulating groove on the metal layer of the first metal-clad substrate to electrically connect the two electrodes of the electronic components to the metal layers on both sides of the insulating groove. Opening the insulating groove on the first metal-clad substrate will reduce the chip layout space, and the first metal-clad substrate is provided with a large number of chips. Etching grooves in the metal layer on the first metal-clad substrate may damage the pre-arranged chips or other electronic components.

[0037] In this possible implementation, electronic components are transferred through the second metal-clad substrate, which simplifies the electronic component welding process. Compared with directly welding the electronic components on the metal layer of the first metal-clad substrate, the step of opening an insulating groove on the metal layer of the first metal-clad substrate can be saved, making the circuit design on the first metal-clad substrate simpler. Insulating grooves can be provided in advance on the second metal-clad substrate according to the size of the electronic components and the positions of the two electrodes of the electronic components. The insulating grooves can be etched on the second metal-clad substrate without affecting the performance of the chip on the first metal-clad substrate, and then the electronic components are electrically connected to the second metal-clad substrate.

[0038] According to the first aspect, in a possible implementation, a terminal metal layer is further provided on a side of the first metal-clad substrate facing the chip, the terminal metal layer is located at one end of the first metal-clad substrate in a first direction, the second metal-clad substrate is arranged close to the terminal metal layer, and the terminal metal layer is connected to the second metal-clad substrate through a second conductive wire.

[0039] In this possible implementation, the second metal-clad substrate is disposed close to the terminal metal layer, which reduces the bonding length between the second metal-clad substrate and the terminal metal layer, thereby facilitating improving the space utilization of the power module.

[0040] According to the first aspect, in a possible implementation manner, the electronic component includes a thermistor, and the thermistor is used to monitor the temperature of the chip.

[0041] According to the first aspect, in a possible implementation, at least one chip also includes a gate, the electronic component is a gate resistor, the second metal-clad substrate includes a first substrate electrode and a second substrate electrode arranged with an insulating interval, the two ends of the gate resistor are respectively electrically connected to the first substrate electrode and the second substrate electrode, the first substrate electrode is used to receive a driving current, and the second substrate electrode is electrically connected to the gate of the chip through a first conductive line.

[0042] In this possible implementation, the second metal-clad substrate is used to transfer the gate resistor, so that the process of welding the gate resistor is simple.

[0043] According to the first aspect, in a possible implementation manner, in the second direction, a first bonding layer is further provided between the side of the chip facing away from the connection sheet and the first metal-clad substrate, and the first bonding layer includes at least one of solder and sintering material.

[0044] In this possible implementation, the chip is fixed on the first metal-clad substrate by sintering or welding, which is beneficial to improving the connection stability between the chip and the first metal-clad substrate.

[0045] According to the first aspect, in a possible implementation manner, the power module further includes a heat sink, and the heat sink is located on a side of the first metal-clad substrate away from the chip.

[0046] According to the first aspect, in a possible implementation, the power module also includes a fixed layer. In the second direction, the fixed layer is located between the heat sink and the side of the metal-clad substrate away from the chip. The fixed layer includes at least one of solder and sintered material. The second direction is perpendicular to the plane where the chip is away from the first metal-clad substrate.

[0047] In order to improve the heat dissipation effect, the heat sink can be fixed on the side of the first metal-clad substrate away from the chip through a fixing layer. Compared with the method of bonding the heat sink to the first metal-clad substrate with thermal conductive silicone, sintering or welding is used, and the thermal conductivity effect is better than that of thermal conductive silicone.

[0048] According to the first aspect, in a possible implementation manner, the connecting piece is an integrally formed structure.

[0049] In this possible implementation, the one-piece molding structure can improve the smoothness of current flow, reduce the resistance to current flow, improve current sharing and reduce inductance, and can also improve the reliability of the connecting piece.

[0050] According to the first aspect, in a possible implementation manner, the power module further includes a power pin, the power pin is electrically connected to the first metal-clad substrate, and the power pin includes at least one bending structure.

[0051] During the application of the power module, the power pin may be subjected to greater stress. For example, when the power pin is connected to the battery pack, the power pin may be subjected to greater stress. Since a bending structure is provided in the power pin, the bending structure is beneficial for buffering the stress, thereby reducing the possibility of cracking of the plastic package due to the stress exerted on the power pin, and also reducing the possibility of damage to the input and output ends due to the stress exerted on the power pin.

[0052] According to the first aspect, in a possible implementation, when the number of chips in the chipset is not less than 3, all chips in the chipset are arranged at equal intervals along the first direction. This is conducive to further improving the consistency of parasitic parameters between parallel chips, thereby optimizing the dynamic current sharing between multiple parallel chips.

[0053] In a second aspect, the present application provides a power conversion device, comprising a circuit board and a power module according to the first aspect, wherein the power module is arranged on the circuit board.

[0054] In a third aspect, the present application provides a power assembly, comprising the power conversion device described in the second aspect and a drive motor connected to the power conversion device.

[0055] In a fourth aspect, the present application provides a photovoltaic system, comprising a photovoltaic component and a power module according to the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of the structure of a vehicle provided in one embodiment of the present application;

[0057] Figure 2 A structural block diagram of a powertrain provided in one embodiment of the present application;

[0058] Figure 3 A schematic diagram of the structure of a photovoltaic system provided in one embodiment of the present application;

[0059] Figure 4 A three-dimensional assembly diagram of a power module provided in an embodiment of the present application;

[0060] Figure 5 for Figure 4 A three-dimensional assembly schematic diagram of the power module shown in another perspective;

[0061] Figure 6 for Figure 4 A three-dimensional exploded schematic diagram of a power module shown;

[0062] Figure 7 A schematic diagram of a stacked structure of a power module provided in one embodiment of the present application;

[0063] Figure 8 is a schematic diagram of a chipset disposed on a first metal layer substrate;

[0064] Fig. 9 A schematic plan view of a chip provided in one embodiment of the present application;

[0065] Fig.10a It is a schematic diagram of assembling the first metal-clad substrate, the chipset and the connecting sheet;

[0066] Fig.10b for Fig.10a An enlarged schematic diagram of a local area A1;

[0067] Fig.11a is a schematic assembly diagram of the first metal-clad substrate, the chipset and the connecting sheet from another perspective;

[0068] Fig.11b for Fig.11a An enlarged schematic diagram of a local area A2;

[0069] Fig.12 A three-dimensional schematic diagram of a connecting sheet provided in an embodiment of the present application;

[0070] Fig.13a It is a perspective view of the assembly of the first metal-clad substrate, the chipset and the connecting sheet;

[0071] Fig.13b for Fig.13a An enlarged schematic diagram of the local area A3 shown;

[0072] Fig.14 A top view of the first metal-clad substrate, the chipset, and the connecting sheet assembled together;

[0073] Fig.15 A top view of the first metal-clad substrate and the chipset assembled together;

[0074] Fig.16a This is a three-dimensional assembly diagram of the power module after removing the plastic package;

[0075] Fig.16b for Fig.16a An enlarged schematic diagram of a local area A4;

[0076] Fig.17A three-dimensional schematic diagram of a connecting sheet provided in an embodiment of the present application;

[0077] Fig.18 A schematic diagram of the connection between a portion of a connecting sheet provided in one embodiment of the present application and a chip. DETAILED DESCRIPTION

[0078] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a vehicle provided in one embodiment of the present application. The vehicle 1000 includes a vehicle body 300, a battery pack 200, and a powertrain 100. The battery pack 200 and the powertrain 100 are both mounted on the vehicle body 300. The battery pack 200 is used to provide direct current to the powertrain 100. The powertrain 100 is used to provide power for the vehicle 1000. The vehicle 1000 also includes other necessary or non-essential structures, which are not described in detail in this application.

[0079] See also Figure 2 , Figure 2 This is a structural block diagram of a powertrain provided in one embodiment of the present application, in which the powertrain 100 includes a power conversion device 101 and a drive motor 103. The power conversion device 101 includes a circuit board 10 and a power module 30 disposed on the circuit board 10. The power module 30 includes an input terminal 301 and an output terminal 303. The input terminal 301 is a DC input terminal, and the output terminal 303 is an AC output terminal. The input terminal 301 of the power module 30 is electrically connected to the battery pack 200, and the output terminal 303 of the power module 30 is electrically connected to the drive motor 103. The power module 30 is used to convert the DC power output by the battery pack 200 into AC power, and transmit the AC power to the drive motor 103. Among them, the power module 30 is a semiconductor device that converts the voltage, current, frequency, etc. of the DC power output by the battery pack 200.

[0080] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a photovoltaic system provided in one embodiment of the present application. The power module 30 of the present application can also be used in a photovoltaic system, which includes a power conversion device 101 and a photovoltaic module 105. The photovoltaic module 105 is electrically connected to the power conversion device 101, and the direct current generated by the photovoltaic module 105 is converted into alternating current through the power module 30. The alternating current output by the power module 30 is transmitted to power-consuming equipment, such as base stations, data centers, etc.

[0081] A power module usually includes a copper-clad substrate and multiple chips. The electrical connection of the semiconductor chips in the power module is mainly achieved by aluminum wire welding technology, which connects the semiconductor chip electrodes to the metal layer on the surface of the substrate through aluminum wires. However, when more chips are arranged in the power module, the number of aluminum wires will increase accordingly. More aluminum wires will increase the parasitic inductance of the power module, and when multiple chips are connected in parallel, the multiple aluminum wire connections will cause uneven currents between the multiple parallel chips. Uneven currents will cause uneven heat generation of the parallel chips. Localized heating will seriously affect the performance of the chip, and thus the performance of the power module.

[0082] Based on this, an embodiment of the present application provides a power module 30, please refer to Figure 4 , Figure 5 and Figure 6 , Figure 4 This is a three-dimensional assembly diagram of a power module provided in an embodiment of the present application. Figure 5 for Figure 4 The three-dimensional assembly diagram of the power module shown in another perspective, Figure 6 for Figure 4 The three-dimensional exploded schematic diagram of the power module shown in the figure, the power module 30 also includes a heat sink 31, a first metal-clad substrate 32, a chipset 33, a connecting piece 34 and a plastic package 35. The first metal-clad substrate 32 is mounted on one side of the heat sink 31. The heat sink 31 is used to dissipate heat for the power module 30. The chipset 33 is arranged on the first metal-clad substrate 32. The chipset 33 includes a plurality of chips 330. The connecting piece 34 is arranged on the side of the corresponding chipset 33 away from the first metal-clad substrate 32, and is used to connect the plurality of chips 330 in the chipset 33 in parallel. The plastic package 35 wraps the first metal-clad substrate 32, the plurality of chipsets 33 and the plurality of connecting pieces 34 together. It can be understood that the number of chips 330 in the chipset 33 is at least two. The input end 301 and the output end 303 are both connected to the first metal-clad substrate 32.

[0083] In one possible implementation, see again Figure 4 The input end 301 and the output end 303 both include a power pin 360. The input end 301 is connected to the battery pack 200 through the power pin 360, and the output end 303 is connected to the battery pack 200 through a power pin 360. The power pin 360 includes at least one bending structure 3601, and the bending structure 3601 is used to buffer stress. The power pins 360 of the input end 301 and the output end 303 are partially exposed outside the plastic package 35.

[0084] During the application of the power module 30, the power pin 360 may be subjected to greater stress. For example, when the power pin 360 is connected to the battery pack 200, the power pin 360 may be subjected to greater stress. Since a bending structure 3601 is provided in the power pin 360, the bending structure 3601 is conducive to buffering the stress, thereby reducing the possibility of cracking of the plastic package due to the stress exerted on the power pin 360, and also reducing the possibility of damage to the input end 301 and the output end 303 due to the stress exerted on the power pin 360.

[0085] The power pin 360 can be made of copper bar, aluminum plate and other materials. The power pin 360 is usually used for overcurrent and has a certain width. The power pin 360 is connected to the external connection bar (or metal terminal) by bolt connection, laser welding, or other methods. The power pin 360 can be partially exposed outside the plastic package 35.

[0086] See also Figure 7 , Figure 7 A schematic diagram of the stacked structure of a power module provided in an embodiment of the present application, wherein the heat sink 31 is located on the side of the first metal-clad substrate 32 away from the chip 330. The heat sink 31 may be a water-cooled heat sink or an air-cooled heat sink, which is not limited here, and is used to dissipate heat from the power module 30 and improve the power density of the power module 30. In the second direction, the heat sink 31 and the side of the first metal-clad substrate 32 away from the chip 330 are connected by a fixing layer 310. In this embodiment, in order to improve the heat dissipation effect, the fixing layer 310 is solder, that is, the heat sink 31 can be soldered to the side of the first metal-clad substrate 32 away from the chip 330 by solder. Compared with the method of bonding the heat sink 31 to the first metal-clad substrate 32 by using thermally conductive silicone, the thermal conductivity of the welding material is better than that of the thermally conductive silicone by welding.

[0087] It can be understood that the fixing layer 310 can also be a sintered material, and the fixing layer 310 includes at least one of solder and a sintered material.

[0088] The heat sink 31 includes a heat sink bottom plate 311 and heat dissipation teeth 313 disposed on the heat sink bottom plate 311. The heat dissipation teeth 313 can be exposed outside the plastic package body 35.

[0089] The first metal-clad substrate 32 includes a first insulating substrate 321, a mounting metal layer 323 and a fixed metal layer 325 which are stacked. In some embodiments of the present application, the first metal-clad substrate 32 may be an active metal brazed copper (AMB) substrate. The AMB substrate has good comprehensive properties such as thermal conductivity and mechanical strength. The first insulating substrate 321 may be a ceramic substrate. The ceramic substrate may be a ceramic substrate such as Si3N4, AlN, etc. The mounting metal layer 323 and the fixed metal layer 325 may be copper (Cu). Cu may be welded to the first insulating substrate 321 by a welding process. It is understood that the present application does not limit the first insulating substrate 321 to a ceramic substrate, which may be an insulating substrate of other materials, the mounting metal layer 323 may be a metal such as aluminum, and the fixed metal layer 325 may be a metal such as aluminum. A circuit is provided in the mounting metal layer 323. The device located on the first metal-clad substrate 32 may be connected to the metal layer of the first metal-clad substrate 32 by one or more weldings.

[0090] The chipset 33 is located on a side of the mounting metal layer 323 away from the first insulating substrate 321. Figure 8 , Figure 8 The schematic diagram of the chipset 33 being arranged on the first metal layer substrate, wherein the multiple chips 330 in the chipset 33 are arranged in a straight line along the first direction. The multiple chips 330 in the chipset 33 are arranged at equal intervals along the first direction to improve the consistency of parasitic parameters between the parallel chips 330 in the chipset 33, thereby optimizing the dynamic current sharing between the multiple parallel chips 330. The first direction is parallel to the plane where the side of the chip 330 is away from the first metal layer substrate 32. The second direction is perpendicular to the plane where the side of the chip 330 is away from the first metal layer substrate 32. The third direction is parallel to the plane where the side of the chip 330 is away from the first metal layer substrate 32. Any two of the first direction, the second direction, and the third direction are perpendicular to each other. In some embodiments of the present application, the first direction can be Figure 8 The Y direction shown in FIG. 1 may be the stacking direction of the first insulating substrate 321 and the mounting metal layer 323, and the third direction may be the stacking direction of the first insulating substrate 321 and the mounting metal layer 323. Figure 8 It is understood that when the number of chips 330 in the chipset 33 is not less than 3, all chips 330 in the chipset 33 are arranged at equal intervals along the first direction. The present application does not limit the arrangement of multiple chips 330 in the chipset 33 at equal intervals along the first direction.

[0091] See also Fig. 9 , Fig. 9This is a schematic plan view of a chip provided in an embodiment of the present application, wherein each chip 330 includes a chip body 3301, a first source 3302, a second source 3303, a gate wiring 3305, a gate 3306, a first Kelvin source 3307, and a second Kelvin source 3308. The first source 3302, the second source 3303, the gate wiring 3305, the gate 3306, the first Kelvin source 3307, and the second Kelvin source 3308 are all disposed in the chip body 3301. The gate wiring 3305 is located inside the chip 330.

[0092] The first source 3302, the second source 3303, the gate wiring 3305, the gate 3306, the first Kelvin source 3307 and the second Kelvin source 3308 are all electrically connected to the mounting metal layer 323. The first source 3302, the second source 3303, the gate wiring 3305, the gate 3306, the first Kelvin source 3307 and the second Kelvin source 3308 can be arranged in two columns on the chip body 3301. The first source 3302, the second source 3303, and the gate wiring 3305 are arranged in sequence in the first column along the first direction. The gate 3306, the first Kelvin source 3307 and the second Kelvin source 3308 are arranged in sequence in the second column along the first direction. The first column and the second column are arranged along the third direction. The second direction, the first direction, and the third direction are different from each other.

[0093] In some embodiments of the present application, the chip 330 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The material of the chip body 3301 is SIC (silicon carbide), which can increase the operating frequency of the chip 330, and reduce the volume of the chip 330 while meeting the same operating frequency, so that more space can be reserved on the first metal-clad substrate 32 for installing electronic components of the power module 30, such as thermistors, gate resistors, etc., and the higher the operating frequency of the chip 330, the smaller the volume of the peripheral electronic components of the power module 30, such as capacitors and coils, etc.

[0094] In some embodiments of the present application, within the same chipset 33 , the first row of the first source 3302 , the second source 3303 , and the gate wiring 3305 on all the chips 330 are located on the same side of the chip 330 , that is, all the chips 330 in the same chipset 33 have the same orientation.

[0095] See also Fig.10a , Fig.10b , Fig.11a and Fig.11b , Fig.10a It is a schematic diagram of the assembly of the first metal-clad substrate, the chipset and the connecting sheet. Fig.10b for Fig.10a An enlarged schematic diagram of a local area A1, Fig.11a FIG. 1 is a schematic diagram of the assembly of the first metal-clad substrate, the chipset and the connecting sheet from another perspective. Fig.11b for Fig.11a The enlarged schematic diagram of the local area A2 of the chipset 33 shows that the connecting piece 34 covers the side of the chipset 33 away from the first metal-clad substrate 32, the connecting piece 34 is electrically connected to the first source 3302, and the connecting piece 34 is electrically connected to the second source 3303.

[0096] In the related art, the electrical connection of the semiconductor chips in the power module is mainly achieved by aluminum wire welding technology. When more chips are arranged in the power module, the number of aluminum wires will increase accordingly. More aluminum wires will increase the parasitic inductance of the power module, and when multiple chips are connected in parallel, the multiple aluminum wire connections will cause uneven current between the multiple parallel chips. The uneven current will cause uneven heat generation of the parallel chips. Local heating will seriously affect the performance of the chip, and thus affect the performance of the power module.

[0097] In the present application, multiple chips 330 in the chipset 33 are connected in parallel through a connecting piece 34. The connection path on the connecting piece 34 is larger than that of the aluminum wire, which strengthens the connection between the multiple chips 330 in the chipset 33, improves the consistency of the parasitic parameters between the parallel chips 330, and further optimizes the dynamic current sharing between the multiple parallel chips 330; and the connecting piece 34 can also increase the structural reliability of the interconnection of the multiple chips 330 and ensure the stability of current transmission. In addition, compared with multiple aluminum wires to achieve parallel connection between multiple chips 330, the setting of the connecting piece 34 is conducive to simplifying the structure of the power module 30.

[0098] The contact between the aluminum wire and the chip is point contact, and the aluminum wire is more likely to detach from the chip. The contact between the connecting piece 34 and the chip 330 is surface contact, which improves the connection strength between the connecting piece 34 and the chip 330. In this way, the structural reliability between multiple chips 330 is enhanced and the current transmission stability is ensured.

[0099] Furthermore, the chips 330 in the chipset 33 are arranged in a straight line along the first direction, and the connecting sheet 34 covers the side of the chipset 33 away from the first metal-clad substrate, so that two adjacent chips 330 are connected by the shortest straight line path.

[0100] Please refer to Fig.10a , Fig.10b , Fig.11a and Fig.11b and Fig.12 , Fig.12A three-dimensional schematic diagram of a connecting piece provided in an embodiment of the present application, the connecting piece 34 includes a main body 341, a plurality of connecting units 342 and at least one connecting arm 343. The main body 341 covers the side of the mounting metal layer 323 away from the first insulating substrate 321. The plurality of connecting units 342 are fixedly connected to the main body 341. Every two adjacent connecting units 342 are connected in the first direction through the main body 341. In some embodiments of the present application, every two adjacent chips 330 in the chipset 33 form a gap 3300 in the first direction (such as Figure 8 ). The orthographic projection of the main body 341 connected between the two connecting units 342 along the first direction is at least partially located in the area where the corresponding gap 3300 is located on the first metal-clad substrate 32. The connecting unit 342 is in contact with the first source 3302 and the second source 3303, so that all chips 330 in the chipset 33 are connected in parallel. The connecting arm 343 is connected to the mounting metal layer 323.

[0101] The first source 3302 and the first metal-clad substrate 32, the second source 3303 and the first metal-clad substrate 32 of the multiple chips 330 in the chipset 33 are connected by the connecting piece 34, each connecting unit 342 is electrically connected to a corresponding chip 330, and every two adjacent connecting units 342 are connected in the first direction by the main body 341, that is, the connecting piece 34 realizes the shortest straight line path connection between the first source 3302 and the second source 3303 of every two chips 330, which is beneficial to minimize the interconnection parasitic inductance between the multiple chips 330 of the chipset 33, and reduce the switching process under high voltage and high current and the risk of high-frequency oscillation in short-circuit conditions.

[0102] In some embodiments of the present application, the connecting sheet 34 is a metal sheet, and the connecting sheet 34 is an integrally formed structure formed by stamping. It can be understood that the present application does not limit the material of the connecting sheet 34, and the present application does not limit the forming method of the connecting sheet 34. The connecting sheet 34 can conduct electricity.

[0103] In some embodiments of the present application, the main body 341 is substantially a flat plate structure, and the main body 341 includes a plurality of connection holes 3411 arranged at intervals along the first direction for setting the connection unit 342 .

[0104] The number of connection units 342 corresponds to the number of chips 330 in the chipset 33. Each connection unit 342 is arranged corresponding to a connection hole 3411. The connection unit 342 includes a first contact portion 3424, an avoidance space 3425 and a second contact portion 3426 arranged in sequence along the first direction. The first contact portion 3424 is connected to the hole wall of the connection hole 3411, and the second contact portion 3426 is connected to the hole wall of the connection hole 3411. The first contact portion 3424 contacts the first source 3302, and the second contact portion 3426 contacts the second source 3303. The avoidance space 3425 and the gate wiring 3305 are arranged in the second direction. The avoidance space 3425 has an avoidance opening arranged toward the gate wiring 3305. The position of the avoidance opening is arranged corresponding to the position of the gate wiring 3305.

[0105] In some embodiments of the present application, the first contact portion 3424 and the second contact portion 3426 are pads, the first contact portion 3424 is connected to the first source electrode 3302 by welding, and the second contact portion 3426 is connected to the first source electrode 3302 by welding.

[0106] The size of the chip is very small, and the gate wiring is easily damaged due to the stress, making the chip unusable. In the present application, the avoidance space 3425 and the gate wiring 3305 are arranged along the second direction, that is, the avoidance space 3425 is set at the position of the connecting piece 34 corresponding to the gate wiring 3305. In this way, the connecting piece 34 is arranged away from the gate wiring 3305, reducing the stress of the connecting piece 34 on the gate wiring 3305, which is conducive to reducing the possibility of damage to the gate wiring 3305 and extending the cycle life of the power module 30.

[0107] In some embodiments of the present application, the avoidance space 3425 is a groove that penetrates the connecting piece 34 in the second direction, and the avoidance space 3425 extends from one end of the connecting section 3427 of the second contact portion 3426 away from the contact segment 3429 of the second contact portion 3426 to one end where the connecting section 3427 of the second contact portion 3426 is connected to the connecting hole 3411, so as to increase the length of the avoidance space 3425 and further reduce the stress of the connecting piece 34 on the gate wiring 3305.

[0108] In some embodiments of the present application, the first contact portion 3424 and the second contact portion 3426 both include a fixedly connected connection segment 3427 and a contact segment 3429. The connection segment 3427 is bent relative to the main body 341. The connection segment 3427 of the first contact portion 3424 is connected between the hole wall of the connection hole 3411 and the contact segment 3429 of the first contact portion 3424. The connection segment 3427 of the second contact portion 3426 is connected between the hole wall of the connection hole 3411 and the contact segment 3429 of the second contact portion 3426. The vertical distance between the contact segment 3429 and the chip 330 in the second direction is smaller than the vertical distance between the main body 341 and the chip 330 in the second direction. The contact segment 3429 is connected to the main body 341 through the connection segment 3427, so that the main body 341 and the mounting metal layer 323 are separated by the plastic package 35. In some embodiments of the present application, the connection segment 3427 includes a curved surface structure, and the setting of the curved surface structure can reduce the possibility of the connection piece 34 breaking during molding. It is understandable that the connecting section 3427 may also include a flat plate structure.

[0109] The plastic encapsulation body is prone to delamination at the bend of the structural parts and the continuous large-area plane area of ​​the structural parts, which affects the sealing of the power module. A first glue locking hole 3415 is provided at the connection between the connecting section 3427 and the main body 341, and a second glue locking hole 3417 is provided on the main body 341. The plastic encapsulation body 35 fills the first glue locking hole 3415 and the second glue locking hole 3417. Since the first glue locking hole 3415 is provided at the connection between the connecting section 3427 and the main body 341, and the plastic encapsulation body 35 fills the first glue locking hole 3415, the possibility of delamination of the plastic encapsulation body 35 at the connection between the main body 341 and the connecting section 3427 is reduced, and / or the delamination of the plastic encapsulation body 35 is reduced to the surface of the chip 330, which is conducive to improving the sealing of the power module 30. Since the second glue-locking hole 3417 is provided on the main body 341, the plastic package 35 fills the second glue-locking hole 3417, which reduces the possibility of the plastic package 35 being delaminated at the main body 341 or reduces the delamination of the plastic package 35 spreading to the surface of the chip 330, which is beneficial to improving the sealing of the power module 30. The shape of the first glue-locking hole 3415 is not limited to circular, elliptical, waist hole, etc., and the shape of the second glue-locking hole 3417 is not limited to circular, elliptical, waist hole, etc.

[0110] See also Fig.13a and Fig.13b , Fig.13a It is a perspective view of the assembly of the first metal-clad substrate, the chipset and the connecting sheet. Fig.13b for Fig.13aIn the enlarged schematic diagram of the local area A3 shown, each connecting arm 343 is provided corresponding to two adjacent chips 330 in the chipset 33, and the connecting arm 343 is connected to the first metal-clad substrate 32. The shortest distance between the connecting arm 343 and one of the two adjacent chips 330 is a first shortest distance B1, and the shortest distance between the connecting arm 343 and the other of the two adjacent chips 330 is a second shortest distance B2, and the difference between the first shortest distance B1 and the second shortest distance B2 is not greater than 30% of the first shortest distance.

[0111] Of the two adjacent chips 330, one chip 330, the connecting piece 34 and the first metal-clad substrate 32 form a first interconnection path, and the other chip 330, the connecting piece 34 and the first metal-clad substrate 32 form a second interconnection path. The first interconnection path and the second interconnection path are roughly symmetrical, which is conducive to balancing the current paths of each chip 330 and reducing the difference in parasitic parameters between each chip 330, thereby further improving the dynamic current sharing characteristics of the parallel chips 330. The shortest distance between the connecting arm 343 and one of the two adjacent chips 330 in the first direction can be equal to or roughly equal to the shortest distance between the connecting arm 343 and the other of the two adjacent chips 330 in the first direction.

[0112] The chip 330 is roughly square, and includes four connected chip edges 3309, and the connection between every two chip edges 3309 forms an intersection. Among two adjacent chips 330 of the chip group 330, the intersection of the first chip 330 closest to the corresponding connecting arm 343 is E1, and the intersection of the second chip 330 closest to the corresponding connecting arm 343 is E2. E1 and E2 are arranged roughly along the first direction. E2 is located on the side of the second chip 330 close to the first chip 330 in the first direction, and E1 is located on the side of the first chip 330 close to the connecting arm 343 in the third direction. E2 is located on the side of the second chip 330 close to the first chip 330 in the first direction, and E2 is located on the side of the second chip 330 close to the connecting arm 343 in the third direction.

[0113] The connection point between the connecting arm 343 and the first metal-clad substrate 32 is located on the midline C2 of the shortest connection line C1 of two adjacent chips 330. In some embodiments of the present application, the connecting arm 343 includes a first edge 3431 and a second edge 3433 arranged opposite to each other along a first direction, and the first edge 3431 and the second edge 3433 are both fixedly connected to the main body 341, and the connection point between the first edge 3431 and the main body 341 is D1, and the connection point between the second edge 3433 and the main body 341 is D2. The shortest distance between D1 and E1 is the first shortest distance B1. The connection point between the second edge 3433 and the main body 341 is D2, and the shortest distance between D1 and E2 is the second shortest distance B2.

[0114] In some embodiments of the present application, the connecting arm 343 is bent relative to the main body 341 , and a third glue locking groove 3418 is provided at the connection between the connecting arm 343 and the main body 341 .

[0115] In some embodiments of the present application, the connecting arm 343 may be symmetrical about the center line C2, so that multiple connecting pieces 34 of the same structure can be used in the power module 30, which facilitates the assembly of the power module 30 and reduces the cost of the power module 30. It is understood that the connecting arm 343 may not be symmetrical about the center line C2.

[0116] It can be understood that the present application does not limit the structure of the connecting arm 343 .

[0117] In some implementations of this application, please refer to Fig.14 and Fig.15 , Fig.14 It is a top view of the first metal-clad substrate, the chipset, and the connecting sheet assembled together. Fig.15 The top view of the first metal-clad substrate and the chipset assembled together, the number of mounting metal layers 323 is multiple, and the multiple mounting metal layers 323 are arranged at intervals on the first insulating substrate 321. A groove 3230 is formed between each two adjacent mounting metal layers 323 to insulate the multiple mounting metal layers 323 from each other. The multiple mounting metal layers 323 include a first mounting metal layer 3231, a second mounting metal layer 3232, a third mounting metal layer 3233 and a fourth mounting metal layer 3234. The first mounting metal layer 3231 and the third mounting metal layer 3233 are electrically connected to the input end 301, the second mounting metal layer 3232 is electrically connected to the output end 303, and the fourth mounting metal layer 3234 is electrically connected to the input end 301. The first mounting metal layer 3231, the second mounting metal layer 3232, and the third mounting metal layer 3233 are arranged in sequence along the third direction. The second mounting metal layer 3232 includes a first extension 3235, a groove 3236 and a second extension 3237. One end of the first extension portion 3235 is connected to one end of the second extension portion 3237, and the first extension portion 3235 and the second extension portion 3237 form a groove 3236 for accommodating the fourth mounting metal layer 3234. At least a portion of the fourth mounting metal layer 3234 is located in the groove 3236. In the third direction, the first mounting metal layer 3231 and the first extension portion 3235 are located on a first side of the fourth mounting metal layer 3234, and the third mounting metal layer 3233 and the second extension portion 3237 are located on a second side of the fourth mounting metal layer 3234. It can be understood that the present application does not limit the positions of the first mounting metal layer 3231, the second mounting metal layer 3232, the third mounting metal layer 3233 and the fourth mounting metal layer 3234.

[0118] In some embodiments of the present application, there are multiple chipsets 33 to improve the working efficiency of the power module 30. The multiple chipsets 33 include a first chipset 331, a second chipset 332, a third chipset 333, and a fourth chipset 334. The first chipset 331 is located on the first mounting metal layer 3231, the second chipset 332 is located on the first extension 3235, the third chipset 333 is located on the third mounting metal layer 3233, and the fourth chipset 334 is located on the second extension 3237. The first chipset 331, the second chipset 332, the fourth chipset 334, and the third chipset 333 are sequentially arranged along the third direction.

[0119] In some embodiments of the present application, the spacing between every two adjacent chips 330 in all chipsets 33 along the first direction is the same, so as to improve the consistency of the parasitic parameters of the parallel chips 330 of all chipsets 33 in the power module 30. For example, the spacing between every two adjacent chips 330 in the first chipset 331 along the first direction is the first spacing, the spacing between every two adjacent chips 330 in the second chipset 332 along the first direction is the second spacing, the spacing between every two adjacent chips 330 in the third chipset 333 along the first direction is the third spacing, and the spacing between every two adjacent chips 330 in the fourth chipset 334 along the first direction is the fourth spacing, and the first spacing, the second spacing, the third spacing, and the fourth spacing are the same. It can be understood that the present application does not limit the spacing between every two adjacent chips 330 in all chipsets 33 along the first direction to be the same.

[0120] The first chipset 331, the second chipset 332, the third chipset 333 and the fourth chipset 334 are provided with connecting pieces 34 on one side away from the first insulating substrate 321. The connecting piece 34 on the first chipset 331 is electrically connected to the second mounting metal layer 3232, the connecting piece 34 on the second chipset 332 is electrically connected to the fourth mounting metal layer 3234, and the connecting piece 34 on the third chipset 333 is electrically connected to the second extension 3237. The connecting piece 34 on the fourth chipset 334 is electrically connected to the fourth mounting metal layer 3234.

[0121] The connecting arm 343 of the connecting piece 34 on the first chipset 331 is electrically connected to the first extension 3235, the connecting arm 343 of the connecting piece 34 on the second chipset 332 is electrically connected to the fourth mounting metal layer 3234, the connecting arm 343 of the connecting piece 34 on the third chipset 333 is electrically connected to the second extension 3237, and the connecting arm 343 of the connecting piece 34 on the fourth chipset 334 is electrically connected to the fourth mounting metal layer 3234. The connecting piece 34 is connected to the corresponding mounting metal layer 323 through the connecting arm 343. There are one or more connection points between the connecting piece 34 and the corresponding mounting metal layer 323, and the distance between each connecting arm 343 and the two nearest chips 330 is equal or approximately equal, and the path is symmetrical, which is conducive to achieving symmetry of the interconnection path between each chip 330 and the connected mounting metal layer 323, balancing the current path of each chip 330, reducing the difference in parasitic parameters between the chips 330, and thus improving the dynamic current sharing characteristics of the parallel chips 330.

[0122] In some embodiments of the present application, in the third direction, the first source 3302 of the chip 330 of the first chipset 331 is disposed on a side of the chip 330 close to the third chipset 333, the first source 3302 of the chip 330 of the second chipset 332 is disposed on a side of the chip 330 close to the third chipset 333, the first source 3302 of the chip 330 of the third chipset 333 is disposed on a side of the chip 330 close to the first chipset 331, and the first source 3302 of the chip 330 of the fourth chipset 334 is disposed on a side of the chip 330 close to the first chipset 331, that is, the first chipset 331 and the second chipset 332 have the same orientation, and the third chipset 333 and the fourth chipset 334 have the same orientation. The connecting arm 343 of the connecting piece 34 on the first chipset 331 is disposed on a side of the main body 341 of the first chipset 331 facing the first extension portion 3235. The connecting arm 343 of the connecting piece 34 on the second chipset 332 is disposed on a side of the main body 341 on the second chipset 332 facing the second extension portion 3237. The connecting arm 343 of the connecting piece 34 on the third chipset 333 is disposed on a side of the main body 341 on the third chipset 333 facing the second extension portion 3237. The connecting arm 343 of the connecting piece 34 on the fourth chipset 334 is disposed on a side of the main body 341 on the fourth chipset 334 facing the first extension portion 3235. That is, the connecting piece 34 on the first chipset 331 and the connecting piece 34 on the second chipset 332 are oriented in the same direction, that is, the connecting piece 34 on the third chipset 333 and the connecting piece 34 on the fourth chipset 334 are oriented in the same direction.

[0123] Since the connection piece 34 on the first chipset 331 and the connection piece 34 on the second chipset 332 have the same orientation, the connection piece 34 on the third chipset 333 and the connection piece 34 on the fourth chipset 334 have the same orientation, the first chipset 331 and the second chipset 332 have the same orientation, and the third chipset 333 and the fourth chipset 334 have the same orientation, the interconnection path between the connection piece 34 on the first chipset 331 and the first extension portion 3235 is roughly mirror-symmetrical with the interconnection path between the connection piece 34 on the third chipset 333 and the second extension portion 3237, and the interconnection path between the connection piece 34 on the second chipset 332 and the fourth mounting metal layer 3234 is roughly mirror-symmetrical with the interconnection path between the connection piece 34 on the fourth chipset 334 and the fourth mounting metal layer 3234, which balances the current paths between the chipsets 33, reduces the parasitic parameter differences between the chips 330, and further improves the dynamic current sharing characteristics of the parallel chips 330.

[0124] In some embodiments of the present application, the input terminal 301 is located at the first end of the power module 30, and the output terminal 303 is located at the second end of the power module 30. The power pins of the input terminal 301 include a first power positive pin 361, a second power positive pin 363, and a third power negative pin 365. The first power positive pin 361 is electrically connected to the first mounting metal layer 3231, the second power positive pin 363 is electrically connected to the third mounting metal layer 3233, the third power negative pin 365 is electrically connected to the fourth mounting metal layer 3234, and the output terminal 303 is electrically connected to the second mounting metal layer 3232. In the third direction, the third power negative pin 365 is located between the first power positive pin 361 and the second power positive pin 363.

[0125] In some embodiments of the present application, the power module 30 is a half-bridge arm power module, and the power module 30 also includes an upper bridge part and a lower bridge part. The upper bridge part includes a first chipset 331, a third chipset 333, a first power positive pin 361 and a second power positive pin 363, and the lower bridge part includes a second chipset 332, a fourth chipset 334, and a third power negative pin 365. By setting three power pins at the input end 301, it is beneficial to improve the current flow path of the power module 30 at the input end 301, reduce the parasitic inductance in the power loop, and reduce the switching loss.

[0126] The first power positive electrode pin 361, the first mounting metal layer 3231, the first chipset 331, the connecting piece 34 on the first chipset 331, the first extension 3235, and the output end 303 can form a first current flow path. The second power positive electrode pin 363, the third mounting metal layer 3233, the third chipset 333, the connecting piece 34 on the third chipset 333, the second extension 3237, and the output end 303 can form a second current flow path. The output end 303, the first extension 3235, the second chipset 332, the connecting piece 34 on the second chipset 332, the fourth mounting metal layer 3234, and the third power negative electrode pin 365 can form a third current flow path. The output end 303, the second extension 3237, the fourth chipset 334, the connecting piece 34 on the fourth chipset 334, the fourth mounting metal layer 3234, and the third power negative electrode pin 365 can form a fourth current flow path. The first current flow path is substantially symmetrical to the second current flow path, and the third current flow path is substantially symmetrical to the fourth current flow path.

[0127] The current may flow to the first power positive pin 361 , the first mounting metal layer 3231 , the first chipset 331 , the connecting piece 34 on the first chipset 331 , the first extension portion 3235 , and the output end 303 .

[0128] The current may flow to the second power positive pin 363 , the third mounting metal layer 3233 , the third chipset 333 , the connecting piece 34 on the third chipset 333 , the second extension portion 3237 , and the output end 303 .

[0129] The current may flow to the output end 303 , the first extension portion 3235 , the second chipset 332 , the connection sheet 34 on the second chipset 332 , the fourth mounting metal layer 3234 , and the third power cathode pin 365 .

[0130] The current may flow to the output end 303 , the second extension portion 3237 , the fourth chipset 334 , the connection sheet 34 on the fourth chipset 334 , the fourth mounting metal layer 3234 , and the third power cathode pin 365 .

[0131] It can be understood that two of the first power positive pin 361, the second power positive pin 363 and the third power negative pin 365 can be negative pins, and the other one of the first power positive pin 361, the second power positive pin 363 and the third power negative pin 365 can be a positive pin.

[0132] It can be understood that the number of power pins in the input end 301 is not limited, and the input end 301 only needs to include pins with different polarities.

[0133] Please continue reading Figure 7A first bonding layer 36 is also provided between the side of the chip 330 facing away from the connecting piece 34 and the mounting metal layer 323, and the first bonding layer 36 is used to fix the chip 330 on the corresponding mounting metal layer 323. In a possible implementation, the first bonding layer 36 is a sintered material, that is, the chip 330 is connected to the mounting metal layer 323 through the sintered material. Exemplarily, the sintered material can be formed by silver paste, copper paste or silver film. The silver paste can include at least one of micrometer silver paste (Micrometersilver particle paste) and nanometer silver paste (Nanometersilver particle paste). Among them, micrometer silver paste refers to a silver paste made of micrometer silver particles and organic solvents, which is low in cost and safe. Generally, sintering is carried out under pressure, the sintered material has high density, the interface of the bonded body is firmly bonded, and the bonding reliability is high.

[0134] In order to improve the reliability of sintering bonding and reduce the cost, the sintering material of the present application can be formed by using micrometer silver particle paste.

[0135] In order to improve the reliability of sintering bonding, the elastic modulus, thermal expansion coefficient (CTE), etc. of the sintering material can be adjusted by adding materials to the sintering material. Exemplarily, the sintering material includes a main material and a filler filled in the main material; wherein the main material includes at least one of silver paste, copper paste or silver film, the filler is formed of a material with good bonding properties with the main material, and the thermal expansion coefficient of the filler is less than the thermal expansion coefficient of the main material, thereby improving the sintering bonding reliability.

[0136] Taking the main material as micron silver paste as an example, fillers are added to the micron silver paste to reduce the thermal expansion coefficient of the micron silver paste, reduce the bonding stress, and thus improve the bonding reliability of silver sintering. Exemplarily, the filler may include at least one of nickel (Ni), Ni alloy, copper (Cu), copper-plated nickel, titanium (Ti), Ti alloy, iron (Fe), Fe alloy, Kovar (Kovar, iron-nickel-cobalt alloy 4J29) and SiC powder, etc., which are not limited here.

[0137] In the present application, the mounting metal layer 323 is generally copper. When the sintering material is a silver paste or a silver film, in order to improve the bonding performance between the sintering material and the mounting metal layer 323, the mounting metal layer 323 can be silver-plated at the sintering location, that is, the mounting metal layer 323 is covered with a silver-plated layer in the area corresponding to the sintering material. Exemplarily, the thickness of the silver-plated layer can be controlled between 0.1 μm and 30 μm. If the bonding performance between the sintering material itself and the first metal-clad substrate 32 is relatively good, silver plating is not required. For example, when the sintering material is a copper paste, the first metal-clad substrate 32 does not need to be silver-plated at the sintering location.

[0138] It can be understood that the first bonding layer 36 can also be solder, that is, the chip 330 is connected to the mounting metal layer 323 through a welding process.

[0139] It can be understood that the first bonding layer 36 includes at least one of solder and sintering material.

[0140] Please refer to Figure 7 , Fig.16a , Fig.16b , Fig.16a This is a three-dimensional assembly diagram of the power module after removing the plastic package. Fig.16b for Fig.16a In a possible implementation, the power module 30 further includes a second metal-clad substrate 37 and electronic components 38 (such as Fig.16b As shown in FIG. 1 , the second metal-clad substrate 37 is located on the side of the mounting metal layer 323 of the first metal-clad substrate 32 away from the first insulating substrate 321. The electronic component 38 is located on the side of the second metal-clad substrate 37 away from the first metal-clad substrate 32 and is electrically connected to the second metal-clad substrate 37.

[0141] Since the size of electronic components is generally small, if the electronic components are directly soldered on the first metal-clad substrate 32, it is necessary to open an insulating groove on the metal layer of the first metal-clad substrate 32 to electrically connect the two electrodes of the electronic components to the metal layers on both sides of the insulating groove. Opening the insulating groove on the first metal-clad substrate 32 will reduce the layout space of the chip 330, and the first metal-clad substrate 32 is provided with a large number of chips 330. Etching grooves in the metal layer on the first metal-clad substrate 32 may damage the pre-arranged chips 330 or other electronic components. In this embodiment, electronic components are transferred through the second metal-clad substrate 37, so that the electronic component welding process is simple. Compared with directly welding the electronic components on the metal layer of the first metal-clad substrate 32, the step of opening an insulating groove on the metal layer of the first metal-clad substrate 32 can be saved, so that the circuit design on the first metal-clad substrate 32 is simpler. Insulating grooves can be pre-provided on the second metal-clad substrate 37 according to the size of the electronic components and the positions of the two electrodes of the electronic components. The insulating grooves can be etched on the second metal-clad substrate 37 without affecting the performance of the chip 330 on the first metal-clad substrate 32, and then the electronic components are electrically connected to the second metal-clad substrate 37.

[0142] The second metal-clad substrate 37 includes a second insulating substrate 371 and metal layers on both sides of the second insulating substrate 371 , and the electronic component 38 is electrically connected to the metal layer on the side of the second insulating substrate 371 away from the first metal-clad substrate 32 .

[0143] In a possible implementation, the electronic component 38 includes a gate resistor 381 (eg, Figure 7 and Fig.16b As shown in FIG. 1 , the second metal-clad substrate 37 is located on the mounting metal layer 323. The second metal-clad substrate 37 includes a first substrate electrode 375 and a second substrate electrode 377 that are insulated and spaced apart. The two ends of the gate resistor 381 are electrically connected to the first substrate electrode 375 and the second substrate electrode 377, respectively. The first substrate electrode 375 is used to receive a driving current, and the second substrate electrode 377 is electrically connected to the gate 3306 of the chip 330 through a first conductive line 380. The second metal-clad substrate 37 is used to transfer the gate resistor 381, so that the welding process of the gate resistor 381 is simple.

[0144] Among them, the first substrate electrode 375 and the second substrate electrode 377 are partial metal layers on the second insulating substrate 371. The insulating part between the first substrate electrode 375 and the second substrate electrode 377 is set according to the size of the gate resistor 381, so that there is an insulating gap between the first substrate electrode 375 and the second substrate electrode 377.

[0145] Exemplarily, there is a groove between the first substrate electrode 375 and the second substrate electrode 377, and the first substrate electrode 375 and the second substrate electrode 377 are insulated and spaced apart by the groove. The first substrate electrode 375, the second substrate electrode 377 and the groove can be formed by etching the metal layer on one side of the second metal-clad substrate 37.

[0146] In some embodiments of the present application, Fig.16b As shown, a terminal metal layer 324 is further provided on one side of the first metal-clad substrate 32 facing the chip 330. The terminal metal layer 324 is located at one end of the first metal-clad substrate 32 where the output terminal 303 is located. The second metal-clad substrate 37 is disposed close to the terminal metal layer 324. The terminal metal layer 324 and the second metal-clad substrate 37 are electrically connected through a second conductive wire 391. The second metal-clad substrate 37 is disposed close to the terminal metal layer 324, which reduces the bonding length between the second metal-clad substrate 37 and the terminal metal layer 324, and is beneficial to improving the space utilization of the power module 30.

[0147] The power module 30 also includes a signal terminal 392 (eg Fig.16b As shown), the signal terminal 392 is provided on the terminal metal layer 324, the external control circuit sends a driving current to the signal terminal 392, and after the first substrate electrode 375 receives the driving current, please combine Fig.16b, the driving current flows into the gate 3306 of the chip 330 through the signal terminal 392, the terminal metal layer 324, the second conductive line 391, the first substrate electrode 375, the gate resistor 381, the second substrate electrode 377 and the first conductive line 380 in sequence, wherein the gate 3306 can drive the first source 3302 and the second source 3303 to conduct after receiving the driving current. The gate resistor 381 is used to improve the switching performance of the chip 330, and can suppress the high-frequency oscillation generated when multiple chips 330 are connected in parallel. The first conductive line 380 and the second conductive line 391 are transmission lines, such as aluminum wires, copper wires, etc.

[0148] The second metal-clad substrate 37 further includes a metal layer located on the side of the second insulating substrate 371 away from the first substrate electrode 375 and the second substrate electrode 377, and the metal layer is soldered to the mounting metal layer 323 on the surface of the first metal-clad substrate 32 through solder. The solder can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-reinforced, and SnSb10.

[0149] The gate resistor 381 may be soldered on the first substrate electrode 375 and the second substrate electrode 377 by soldering.

[0150] The signal terminal 392 can be soldered to the terminal metal layer 324 at the edge of the first metal-clad substrate 32. The solder can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-reinforced, and SnSb10.

[0151] In one embodiment, when the gate resistor 381 and the second metal-clad substrate 37 are each one, the gates 3306 of the multiple chips 330 in the first chip group 331 are electrically connected to the gate resistor 381 of the same second metal-clad substrate 37 through a conductive wire. That is, one gate resistor 381 controls the conduction or cutoff of the first source 3302 and the second source 3303 in the multiple chips 330.

[0152] In one embodiment, when there are multiple gate resistors 381 and the second metal-clad substrate 37, and each gate resistor 381 is disposed on the second metal-clad substrate 37, the gate 3306 of each chip 330 is electrically connected to the gate resistor 381 of one of the second metal-clad substrates 37 through a conductive wire. That is, one gate resistor 381 controls the conduction or cutoff of the first source 3302 and the second source 3303 in one chip 330. For example, there are multiple gate resistors 381, and the multiple gate resistors 381 include a first gate resistor 3811, a second gate resistor 3812, a third gate resistor 3813, and a fourth gate resistor 3814. The first chipset 331 is connected in series with the first gate resistor 3811, the second chipset 332 is connected in series with the second gate resistor 3812, the third chipset 333 is connected in series with the third gate resistor 3813, and the fourth chipset 334 is connected in series with the fourth gate resistor 3814. It can be understood that one or more of the first chipset 331 , the second chipset 332 , the third chipset 333 and the fourth chipset 334 are connected in series with the gate resistor 381 , or the gate resistor 381 is not provided in the power module 30 .

[0153] If the electronic components are directly soldered on the first metal-clad substrate 32, since the electronic components need to pass current, two insulatingly spaced connecting electrodes need to be set on the first metal-clad substrate 32. For example, a connecting metal layer is etched on the metal layer on the side of the first metal-clad substrate 32 away from the first insulating substrate 321, and the connecting metal layer is insulated from other parts of the other mounting metal layers. Grooves are then etched on the connecting metal layer to form two insulatingly spaced connecting electrodes. At this time, part of the connecting metal layer and part of the metal welding layer between the two connecting electrodes need to be removed through an etching process. The larger the etching size along the third direction Z, the larger the aperture of the groove between the two connecting electrodes, or the larger the size between the two connecting electrodes, while the size of the electronic components (such as the gate resistor 381) is smaller, it cannot be soldered on the two connecting electrodes, or the welding reliability will be poor.

[0154] Based on this, in the present embodiment, the electronic components 38 are transferred via the second metal-clad substrate 37, wherein the metal on the second metal-clad substrate 37 is directly bonded to the second insulating substrate 371, so that the formed first substrate electrodes 375 and the second substrate electrodes 377 are also directly adhered to the surface of the second insulating substrate 371, and there is no metal welding layer between the first substrate electrodes 375 and the second substrate electrodes 377 and the second insulating substrate 371, and when etching and grooves to form the first substrate electrodes 375 and the second substrate electrodes 377, there is no need to etch the metal welding layer, so that the size between the first substrate electrodes 375 and the second substrate electrodes 377 can be controlled to be smaller, which is conducive to welding electronic components (such as the gate resistor 381).

[0155] In one embodiment, the first metal-clad substrate 32 is an active metal welding substrate. An active metal welding substrate refers to a metal layer such as a copper layer or an aluminum layer welded on the two side surfaces of an insulating substrate by metal solder, wherein the circuits required by the power module 30 such as the mounting metal layer 323 and the terminal metal layer 324 can be formed by etching the copper layer. The material of the first insulating substrate 321 in the first metal-clad substrate 32 can be Si3N4 or AlN, so that the welding reliability of the first insulating substrate 321 and the metal layers on both sides is stronger, and it has good thermal conductivity, which can improve the heat dissipation effect of the power module 30.

[0156] In one embodiment, the second metal-clad substrate 37 is a copper-clad ceramic substrate. The second insulating substrate 371 is an Al2O3 ceramic substrate or an AlN ceramic substrate, and the metal layer (such as copper foil) is directly bonded to the second insulating substrate 371 at a high temperature. Exemplarily, the copper foil is directly bonded to the Al2O3 ceramic substrate at a high temperature, and then the copper foil is formed into the first substrate electrode 375 and the second substrate electrode 377 as required. There is no other metal layer between the copper foil and the Al2O3 ceramic substrate, so that the spacing between the first substrate electrode 375 and the second substrate electrode 377 can be small, which is conducive to welding the gate resistor 381.

[0157] In a possible implementation, the first metal-clad substrate 32 is an insulating metal substrate. The insulating metal substrate includes an insulating resin layer and metal layers located on both sides of the insulating resin layer. When the thickness of the metal layer is greater than or equal to 0.6 mm, the power module 30 has a higher power density. The second metal-clad substrate 37 can be provided to transfer electronic components to reduce the process difficulty of welding electronic components.

[0158] Please continue reading Fig.16b In a possible implementation, the power module 30 includes two second metal-clad substrates 37, both of which can be used to weld the gate resistor 381, and one of the second metal-clad substrates 37 can also be used to weld the thermistor 383. In some embodiments, only one second metal-clad substrate 37 can be used to weld the thermistor 383.

[0159] In this embodiment, the electronic component 38 further includes a thermistor 383, which is disposed near the chip 330, and the thermistor 383 is used to monitor the temperature of the chip 330. The second metal-clad substrate 37 further includes a third substrate electrode 378 and a fourth substrate electrode 379 disposed at an insulating interval, and the two ends of the thermistor 383 are electrically connected to the third substrate electrode 378 and the fourth substrate electrode 379, respectively. In some embodiments, the second metal-clad substrate 37 is located on a side of the third mounting metal layer 3233 away from the first insulating substrate 321, and is disposed adjacent to the chip 330 located on the third mounting metal layer 3233, and the thermistor 383 is used to monitor the temperature of the chip 330. That is, the second metal-clad substrate 37 used for transferring the thermistor 383 is located on the same metal layer as the chip 330, for example, both are located on the third mounting metal layer 3233, or both are located on the first mounting metal layer 3231, or both are located on the second mounting metal layer 3232. The present application does not limit the second metal-clad substrate 37 of the thermistor 383 to be disposed on the third mounting metal layer 3233 . In other embodiments, the second metal-clad substrate 37 of the thermistor 383 and the chip 330 are disposed on other metal layers according to the design requirements of the power module 30 .

[0160] The thermistor 383 may be soldered to the first substrate electrode 375 and the second substrate electrode 377 by soldering.

[0161] The second metal-clad substrate 37 may be soldered on the surface of the mounting metal layer 323 facing away from the first insulating substrate 321 by soldering.

[0162] In this embodiment, the first metal-clad substrate 32 is an active metal solder substrate or an insulating metal substrate, and the second metal-clad substrate 37 is a copper-clad ceramic substrate.

[0163] In some embodiments, the metal layer on the second metal-clad substrate 37 can be used as a signal routing, which is beneficial to improving the flexibility of the circuit distribution of the power module 30. Part of the circuit can be made of the metal layer on the first metal-clad substrate 32, and part of the circuit can be made of the metal layer on the second metal-clad substrate 37, making the circuit distribution more flexible.

[0164] In one possible implementation, see Fig.17 and Fig.18 , Fig.17 This is a three-dimensional schematic diagram of a connecting sheet provided in an embodiment of the present application. Fig.18A schematic diagram of the connection between a portion of the connecting sheet and a chip provided in an embodiment of the present application, wherein the main body 341 and the connecting unit 342 are alternately arranged along the first direction, and a main body 341 is connected between every two connecting units 342. In this way, the width of the main body 341 portion in the third direction can be reduced, thereby reducing the manufacturing cost of the connecting sheet 34. In the first direction, the first contact portion 3424 in the connecting unit 342 at the first end of the connecting sheet 34 is fixedly connected to the adjacent main body 341, the second contact portion 3426 in the connecting unit 342 at the second end of the connecting sheet 34 is fixedly connected to the adjacent main body 341, and the first contact portion 3424 and the second contact portion 3426 in the connecting unit 342 at the non-end position of the connecting sheet 34 are both fixedly connected to the main body 341. The first contact portion 3424 contacts and is electrically connected to the first source electrode 3302, and the second contact portion 3426 contacts and is electrically connected to the second source electrode 3303.

[0165] The connection unit 342 further includes a bending portion 3428, which is connected between the first contact portion 3424 and the second contact portion 3426 in the first direction. The bending portion 3428 protrudes in a direction away from the first insulating substrate 321, and the first contact portion 3424, the bending portion 3428, and the second contact portion 3426 enclose an escape space 3425. The escape space 3425 and the gate wiring 3305 are arranged along the second direction. The escape space 3425 has an escape opening arranged toward the corresponding chip 330, so that there is a gap between the bending portion 3428 and the corresponding chip 330, and the gate wiring 3305 of the chip 330 will not be contacted. The first contact portion 3424 and the second contact portion 3426 are fixedly connected by the bending portion 3428, which is conducive to enhancing the strength of the connecting piece 34. The bending portion 3428 is provided with a buffer hole 3435 that penetrates the bending portion 3428 along the second direction. The buffer hole 3435 is used to reduce and buffer the stress applied to the chip 330 by the connecting piece 34, which is beneficial to reduce the possibility of damage to the chip 330 due to the stress of the connecting piece 34, and improve the cycle life of the power module 30. The buffer hole 3435 can be a through hole that passes through the bent portion 3428 along the second direction. The buffer hole 3435 may not be a through hole. The shape of the buffer hole 3435 can be circular, square, etc., and the present application does not limit the shape of the buffer hole 3435.

[0166] The power module 30 provided in the present application adopts a 3-power pin design, the source electrode (including the first source electrode 3302 and the second source electrode 3303) on the front side of the chip 330 facing away from the first metal-clad substrate 32 adopts a connecting piece (clip) 34 to realize the interconnection of multiple chips 330, has no built-in gate-level resistors or uses gate-level resistors less than the number of parallel wafers, thereby achieving better electrical performance.

[0167] The power module 30 provided in the present application adopts single-sided direct cooling, chip silver sintering on the first metal-clad substrate (AMB) 32, the source of the parallel chip 330 and the metal layers on the first metal-clad substrate 32 are interconnected by a connecting piece 34, and a second metal-clad substrate (DBC) 37, so that the power density and reliability of the power module 30 are further improved.

[0168] The three power pin designs and multi-chip parallel clip design provided in this application significantly improve the parasitic inductance, switching loss, and current sharing characteristics of the power loop.

[0169] The clip design of the power module 30 provided in the present application can improve dynamic current sharing and ensure that there is no high-frequency oscillation risk in the switching process and short-circuit conditions under high voltage and high current, and increase the power cycle life of the power module 30. It also increases the combined surface area of ​​the connecting piece 34 and the plastic package body 35, and reduces the occurrence rate of plastic package delamination.

[0170] The package has a gate resistor 381 with fewer number of parallel chips or a design without a gate resistor 381, which reduces the number of components in the package and thus reduces the module failure rate caused by potential component failure, saves layout space on the first metal-clad substrate (AMB), and simplifies the packaging process.

[0171] The second metal-clad substrate 37 with a smaller area can be used to lead out the thermistor 383 and the gate resistor 381, and the jumper of the signal circuit can greatly save the layout space on the first metal-clad substrate, solve the problem that such small surface mounted devices (SMD) cannot be directly soldered on the thick copper first metal-clad substrate (AMB) 32, and at the same time ensure the reliability of the SMD devices.

[0172] The power row bending design of the power pin can effectively reduce the stress on the plastic package during module application and improve module reliability.

[0173] The module with a heat sink is sintered or welded and then plastic-sealed to improve the reliability of the module. The present application provides a high-reliability, strong heat dissipation, high-power density plastic-sealed module and a manufacturing solution.

[0174] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0175] In addition, in the present application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0176] In the present application, expressions including ordinal numbers such as "first" and "second" may modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used to distinguish one element from other elements. For example, a first user device and a second user device indicate different user devices, although the first user device and the second user device are both user devices. Similarly, without departing from the scope of the present application, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0177] When a component is referred to as being "connected" or "accessed" to another component, it should be understood that the component is not only directly connected to or accessed to the other component, but also another component may exist between the component and the other component. On the other hand, when a component is referred to as being "directly connected" or "directly accessed" to another component, it should be understood that there is no component between them.

[0178] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A power module, characterized in that: The power module comprises: a first metal-clad substrate; A chipset, disposed on the first metal-clad substrate, the chipset comprising at least two chips arranged in a straight line along a first direction, the first direction being parallel to a plane where a side of the chips is away from the first metal-clad substrate; A connecting sheet, the connecting sheet covers the side of the chipset away from the first metal-clad substrate, the connecting sheet comprises a main body, at least two connecting units and at least one connecting arm, each connecting unit is electrically connected to a corresponding chip, and every two adjacent connecting units are connected in the first direction through the main body, and the connecting arm is protruding from the main body; Each of the connecting arms is arranged corresponding to two adjacent chips of the chipset, the connecting arm is electrically connected to the first metal-clad substrate, the shortest distance between the connecting arm and one of the two adjacent chips is a first shortest distance, the shortest distance between the connecting arm and the other of the two adjacent chips of the chipset is a second shortest distance, and the difference between the first shortest distance and the second shortest distance is not greater than 30% of the first shortest distance.

2. The power module according to claim 1, characterized in that: Each of the chips includes a first source and a second source arranged along a first direction. In two adjacent chips of the chip group, the first source of one chip is arranged adjacent to the second source of the other chip. The connecting unit is electrically connected to the first source and the second source of the corresponding chip. The connecting arm is protruding from the main body and bends and extends toward the first metal-clad substrate.

3. The power module according to claim 2, characterized in that: Each of the chips further includes a gate wiring, and the first source, the gate wiring, and the second source are arranged along the first direction; Each of the connection units also includes a first contact portion, an avoidance space, and a second contact portion which are sequentially arranged along the first direction, the first contact portion contacts the first source, the second contact portion contacts the second source, the avoidance space has an avoidance opening which is arranged toward the gate wiring, and the position of the avoidance opening corresponds to the position of the gate wiring.

4. The power module according to claim 3, characterized in that: At least two connection holes are formed on the main body, each connection unit corresponds to one connection hole, the first contact portion is connected to the hole wall of the corresponding connection hole, and the second contact portion is connected to the hole wall of the corresponding connection hole.

5. The power module according to claim 3 or 4, characterized in that: The main body is spaced apart from the first metal-clad substrate, and in each of the connecting units, at least one of the first contact portion and the second contact portion is connected to the main body; The first contact portion connected to the main body and the second contact portion connected to the main body both include a connecting segment and a contact segment, at least a portion of the connecting segment is bent relative to the main body, the connecting segment is connected between the main body and the contact segment, the contact segment of the first contact portion contacts the corresponding first source electrode, and the contact segment of the second contact portion contacts the corresponding second source electrode.

6. The power module according to claim 5, characterized in that: The power module further includes a plastic package, which wraps the first metal-clad substrate, the chipset and the connecting sheet; A first glue locking hole is provided at the connection point between the connecting section and the main body, and the plastic sealing body fills the first glue locking hole.

7. The power module according to any one of claims 2 to 5, characterized in that: The power module further includes a plastic package body, which wraps the first metal-clad substrate, the chipset and the connecting sheet. A second glue locking hole is provided on the main body, and the plastic package body fills the second glue locking hole.

8. The power module according to any one of claims 3 to 7, characterized in that: In at least one of the connection units, the first contact portion and the second contact portion are spaced apart in the first direction, the avoidance space is a slot penetrating the connection sheet in the second direction, and the second direction is perpendicular to the plane where the chip is away from the first metal-clad substrate.

9. The power module according to any one of claims 2 to 8, characterized in that: At least one of the connection units further includes a bending portion, which is connected between the first contact portion and the second contact portion in the first direction, and which protrudes in a direction away from the first metal-clad substrate. The first contact portion, the bending portion, and the second contact portion enclose the avoidance space.

10. The power module according to claim 9, characterized in that: The bending portion is provided with a buffer hole penetrating the bending portion along the second direction.

11. The power module according to any one of claims 2 to 10, characterized in that: The first metal-clad substrate comprises a first insulating substrate and a mounting metal layer covering the first insulating substrate, and the chipset is arranged on a side of the mounting metal layer away from the first insulating substrate; There are multiple mounting metal layers, and the multiple mounting metal layers are arranged at intervals on the first insulating substrate. The multiple mounting metal layers include a first mounting metal layer, a second mounting metal layer, a third mounting metal layer and a fourth mounting metal layer. The second mounting metal layer includes a first extension portion, a groove and a second extension portion. One end of the first extension portion is connected to one end of the second extension portion. The first mounting metal layer, the first extension portion, the groove, the second extension portion and the third mounting metal layer are arranged in sequence along a third direction. At least a part of the fourth mounting metal layer is located in the groove. The third direction is parallel to the plane where the chip is away from the first metal-clad substrate, and the third direction is perpendicular to the first direction.

12. The power module according to claim 11, characterized in that: The power module further includes an input end and an output end, wherein the input end and the output end are located at two opposite ends of the first metal-clad substrate in the first direction; The power module is a half-bridge arm power module, the input end includes a first power positive pin, a second power positive pin and a third power negative pin, the first power positive pin is electrically connected to the first mounting metal layer, the second power positive pin is electrically connected to the third mounting metal layer, the third power negative pin is electrically connected to the fourth mounting metal layer, and the output end is electrically connected to the second mounting metal layer.

13. The power module according to claim 12, characterized in that: The plurality of chipsets include a first chipset, a second chipset, a third chipset and a fourth chipset, the first chipset is located on the first mounting metal layer, the second chipset is located on the second mounting metal layer, the third chipset is located on the third mounting metal layer, and the fourth chipset is located on the second extension portion; The connecting arm on the first chipset is electrically connected to the first extension portion, the connecting arm on the second chipset is electrically connected to the fourth metal layer, the connecting arm on the third chipset is electrically connected to the second extension portion, and the connecting arm on the fourth chipset is electrically connected to the fourth mounting metal layer.

14. The power module according to any one of claims 1 to 13, characterized in that: The power module further includes a second metal-clad substrate and electronic components. The second metal-clad substrate is located on the first metal-clad substrate. The electronic components are located on a side of the second metal-clad substrate away from the first metal-clad substrate and are electrically connected to the second metal-clad substrate.

15. The power module according to claim 14, characterized in that: A terminal metal layer is also provided on the side of the first metal-clad substrate facing the chip. The terminal metal layer is located at one end of the first metal-clad substrate in the first direction. The second metal-clad substrate is arranged close to the terminal metal layer. The terminal metal layer and the second metal-clad substrate are connected via a second conductive wire.

16. The power module according to claim 14, characterized in that: At least one of the chips also includes a gate, the electronic component is a gate resistor, the second metal-clad substrate includes a first substrate electrode and a second substrate electrode arranged with an insulating interval, the two ends of the gate resistor are electrically connected to the first substrate electrode and the second substrate electrode respectively, the first substrate electrode is used to receive a driving current, and the second substrate electrode is electrically connected to the gate of the chip through a first conductive line.

17. The power module according to any one of claims 1 to 16, characterized in that: When the number of chips in the chipset is not less than 3, all the chips in the chipset are arranged at equal intervals along the first direction.

18. A power conversion device, characterized in that: It comprises a circuit board and a power module according to any one of claims 1 to 17, wherein the power module is arranged on the circuit board.

Images