Semiconductor device and semiconductor package including same

Abstract

The invention relates to a semiconductor device and a semiconductor package including the same. The semiconductor device includes: an interconnect region including a lower interconnect on a device region; an insulating structure on the interconnection region; a lower conductive pattern in the insulating structure; a first conductive via electrically connecting the lower conductive pattern to the lower interconnect; an upper conductive pattern on the insulating structure; and a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to the lower conductive pattern. The second conductive path comprises a second metal layer and a second barrier layer; and the upper conductive pattern includes a third barrier layer extending from the second barrier layer and on a portion of an upper surface of the insulating structure, a third metal layer on the third barrier layer and extending from the second metal layer, an upper metal layer on the third metal layer, and an upper anti-reflection layer on the upper metal layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor device and a semiconductor package including the same. Background Art

[0002] As the demand for high performance, speed and / or versatility of semiconductor devices increases, the integration density of semiconductor devices also increases. When manufacturing semiconductor devices to provide high integration density, it may be necessary to implement fine patterns, i.e., patterns with fine widths or fine pitches. In addition, a high integration density of semiconductor devices mounted on a semiconductor package may be necessary. Summary of the invention

[0003] Example embodiments of the present disclosure are directed to providing a semiconductor package having a test pad having a reduced size.

[0004] According to an example embodiment of the present disclosure, a semiconductor device includes: a semiconductor substrate; a device region on the semiconductor substrate; an interconnect region including a lower interconnect on the device region; an insulating structure on the interconnect region; a lower conductive pattern in the insulating structure; a first conductive path electrically connecting at least one of the lower conductive patterns to the lower interconnect of the interconnect region; an upper conductive pattern on the insulating structure; and a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to at least one of the lower conductive patterns, wherein the first conductive path includes a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, wherein the second conductive path includes a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer, and wherein the upper conductive pattern includes: a third barrier layer extending from the second barrier layer and on a portion of an upper surface of the insulating structure opposite to the substrate; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; an upper metal layer on the third metal layer; and an upper anti-reflection layer on the upper metal layer.

[0005] According to an example embodiment of the present disclosure, a semiconductor package includes: a plurality of semiconductor devices stacked sequentially on a buffer chip; an adhesive layer between the plurality of semiconductor devices; and a sealant on the buffer chip and the plurality of semiconductor devices, wherein the semiconductor devices respectively include: an insulating structure on a semiconductor substrate; a via pad below the semiconductor substrate; a through electrode electrically connected to the via pad and penetrating the semiconductor substrate; a lower conductive pattern in the insulating structure; a first conductive path on the lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to at least one of the lower conductive patterns; and a connecting pad electrically connected to one of the upper conductive patterns, wherein the first conductive path respectively includes a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, wherein the second conductive path respectively includes a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer, wherein the upper conductive pattern respectively includes a third barrier layer extending from the second barrier layer and on a portion of the upper surface of the insulating structure; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; an upper metal layer on the third metal layer; and an upper anti-reflection layer on the upper metal layer.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes: an insulating structure on a semiconductor substrate; a lower conductive pattern in the insulating structure; a first conductive path on a lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; and a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to the lower conductive pattern, wherein the first conductive path includes a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, respectively, wherein the second conductive path includes a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer, respectively, and wherein the upper conductive pattern includes a first conductive layer extending from the second conductive path; a second conductive layer on the first conductive layer; and a third conductive layer on the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0009] Figure 2 is a diagram showing an example implementation according to the present disclosure Figure 1 An enlarged plan view of a portion of a semiconductor device shown in;

[0010] Figure 3Ais a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0011] Figure 3B is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 3C is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Fig.10 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0015] Fig.11A is a cross-sectional view showing a semiconductor package including a semiconductor device according to an example embodiment of the present disclosure;

[0016] Fig. 11B is a diagram showing an example implementation according to the present disclosure Fig.11A An enlarged cross-sectional view of a portion of a semiconductor package shown in;

[0017] Fig.12 is a cross-sectional view showing a semiconductor package including a semiconductor device according to an example embodiment of the present disclosure; and

[0018] Fig.13 , Fig.14A and Fig. 14B , Fig.15 , Fig.16A and Fig. 16B , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 and Fig.26 are cross-sectional views and enlarged cross-sectional views sequentially illustrating manufacturing processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings. The terms "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. The terms "comprising", "comprising...", "including" and / or "comprising..." when used herein specify the presence of the elements described, but do not exclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more related listed items. The term "connected" may be used herein to refer to physical and / or electrical connections. When a component or layer is referred to herein as "directly on..." or "directly in contact with" or "directly connected", there are no intervening components or layers. Similarly, when components are "close to" each other, there may be no intervening components.

[0020] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments. Figure 2 is a diagram showing a method according to an example embodiment Figure 1 An enlarged plan view of a portion of the semiconductor device shown in Figure 1 Area "A" in the.

[0021] Reference Figure 1 and Figure 2 , the semiconductor substrate or wafer W may include a device region DR and a scribe region SL between the device regions DR. The scribe region SL may extend in a first horizontal direction D1 and a second horizontal direction D2 intersecting the first horizontal direction D1. The device region DR may be provided in the first horizontal direction D1 and the second horizontal direction D2, and may be surrounded by the scribe region SL. Through a dicing process to be described later, the device region DR may be separated along the scribe region SL and a semiconductor device 100 may be formed. The terms "surrounding" or "covering" or "filling" that may be used herein may not require completely surrounding, covering or filling the described element or layer, but may, for example, refer to partially surrounding, covering or filling the described element or layer.

[0022] In example embodiments, in the device region DR, a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a nonvolatile memory device such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM) may be provided. In example embodiments, in the device region DR, a logic device such as a microprocessor, an analog device, or a digital signal processor may be provided.

[0023] Figure 3A FIG. 1 is a diagram showing a semiconductor device according to an example embodiment. Figure 2 A cross-sectional view taken along line II' in FIG.

[0024] Figure 3B is an enlarged view showing a portion of a semiconductor device according to an example embodiment, showing Figure 3A Area "B" in the

[0025] Figure 3C is a plan view illustrating a semiconductor device according to example embodiments.

[0026] Reference FIG. 3A to FIG. 3C The semiconductor device 100 may include a semiconductor substrate 102, a device region 110 on the semiconductor substrate 102, an interconnection region 120 on the device region 110, an insulating structure 130 on the interconnection region 120, an interlayer insulating layer 128 between the interconnection region 120 and the insulating structure 130, a lower conductive pattern 137 disposed in the insulating structure 130, a first conductive path 129 connecting the lower conductive pattern 137 to the interconnection region 120, an upper conductive pattern 150 on the insulating structure 130, and a second conductive path 138 connecting the upper conductive pattern 150 to the lower conductive pattern 137. The semiconductor device 100 may further include a passivation structure P including a protective layer 160, a first passivation layer 164 on the protective layer 160, and a second passivation layer 168 on the first passivation layer 164.

[0027] The semiconductor substrate 102 may include a device region DR and a scribe line region SL between the device regions DR. The scribe line region SL may include an edge region ER and a cutting region CR between the edge regions ER. The edge region ER may surround the device region DR. The cutting region CR may refer to a portion separated during a dicing process described later. The semiconductor substrate 102 may include a semiconductor material. For example, the semiconductor substrate 102 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon on insulator (SOI) substrate. The semiconductor substrate 102 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0028] The device region 110 may include an integrated circuit device 112, an internal interconnection 114, and a lower interlayer insulating layer 116. The integrated circuit device 112 may include a memory cell array including a switching device and a data storage element, and a logic device including a MOSFET, a capacitor, and a resistor. The internal interconnection 114 may be disposed on the integrated circuit device 112 and may be electrically connected to at least one of the integrated circuit devices 112. The integrated circuit device 112 may be disposed in the device region DR. The internal interconnection 114 may be disposed in the device region DR and the edge region ER, and in some example embodiments, the internal interconnection 114 may also be disposed in the cutting region CR. The lower interlayer insulating layer 116 may cover the semiconductor substrate 102, the integrated circuit device 112, and the internal interconnection 114. The internal interconnection 114 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. The lower interlayer insulating layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the lower interlayer insulating layer 116 may include silicon oxide.

[0029] The interconnection region 120 may be formed on the device region 110. The interconnection region 120 may include a lower insulating layer 122, a lower contact 124, and a lower interconnection 126. The lower insulating layer 122 may be sequentially deposited on the lower interlayer insulating layer 116. The lower interconnection 126 may be disposed in the device region DR and may be buried in the lower insulating layer 122. At least one lower interconnection 126 may be electrically connected to the integrated circuit device 112. The lower interconnection 126 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. For example, the lower interconnection 126 may include copper (Cu).

[0030] The insulating structure 130 may be formed on the interconnection region 120. The insulating structure 130 may include a first upper insulating layer 132, a second upper insulating layer 134, and a third upper insulating layer 136, and a lower conductive pattern 137 may be formed in the insulating structure 130. In example embodiments, a portion of the second upper insulating layer 134 that overlaps the lower conductive pattern 137 in a vertical direction may protrude upward. The second upper insulating layer 134 may include a material having an etching selectivity relative to the first upper insulating layer 132. For example, the first upper insulating layer 132 may include a high density plasma (HDP) oxide. The second upper insulating layer 134 may include silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. In example embodiments, the third upper insulating layer 136 may include silicon oxide. For example, the third upper insulating layer 136 may include tetraethyl orthosilicate (TEOS).

[0031] An interlayer insulating layer 128 may be formed between the interconnection region 120 and the insulating structure 130. A first conductive via 129 may penetrate the interlayer insulating layer 128. The first conductive via 129 may connect the lower conductive pattern 137 to the interconnection region 120. The interlayer insulating layer 128 may include oxide, nitride, or a combination thereof.

[0032] The lower conductive pattern 137 may include a lower metal layer 137a and a lower anti-reflection layer 137b on the lower metal layer 137a. The lower metal layer 137a may include a conductive material. The lower metal layer 137a may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au) or a combination thereof. For example, the lower metal layer 137a may include aluminum (Al). The lower anti-reflection layer 137b may be formed to protect the lower conductive pattern 137 during etching of the first upper insulating layer 132, the second upper insulating layer 134, and the third upper insulating layer 136 to form the second conductive path 138. The lower anti-reflection layer 137b may include at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and tungsten carbonitride (WCN). For example, the lower anti-reflection layer 137b may include titanium nitride (TiN).

[0033] The first conductive path 129 may include a first barrier layer 129b and a first metal layer 129a disposed along the sidewall. The first barrier layer 129b may cover the side surface and the lower surface of the first metal layer 129a. The first metal layer 129a may include a conductive material, such as tungsten (W). The first metal layer 129a and the lower metal layer 137a may include different materials, but example embodiments thereof are not limited thereto. The first barrier layer 129b may include a metal nitride such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN), such as titanium nitride (TiN).

[0034] Hereinafter, the second metal layer 138a of the second conductive path 138 may include an upper vertical portion 138a1 which is a portion disposed at a level lower than that of the upper surface of the third upper insulating layer 136 with respect to the upper surface of the third upper insulating layer 136, and an upper horizontal portion 138a2 which is a portion disposed at a level higher than that of the upper surface of the third upper insulating layer 136. The second barrier layer 138b of the second conductive path 138 may include a first upper portion 138b1 which is a portion disposed at a level lower than that of the upper surface of the third upper insulating layer 136, and a second upper portion 138b2 which is a portion disposed at a level higher than that of the upper surface of the third upper insulating layer 136. The terms “higher” and “lower” are used herein relative to a reference system (e.g., relative to the semiconductor substrate 102). The second upper portion 138 b 2 may be referred to as a third barrier layer 138 b 2 , and the upper horizontal portion 138 a 2 may be referred to as a third metal layer 138 a 2 .

[0035] The upper conductive pattern 150 may include a second upper portion 138b2 of the second barrier layer 138b covering a portion of the upper surface of the insulating structure 130, an upper horizontal portion 138a2 of the second metal layer 138a covering the second barrier layer 138b on the insulating structure 130, an upper metal layer 150a on the second metal layer 138a, and an upper anti-reflective layer 150b on the upper metal layer 150a. In example embodiments, the upper conductive pattern 150 may include an upper horizontal portion 138a2 and a second upper portion 138b2. In example embodiments, each upper conductive pattern 150 may include a third barrier layer 138b2 extending from the first upper portion 138b1 and covering a portion of the upper surface of the insulating structure 130, and a third metal layer 138a2 disposed on the third barrier layer 138b2 and the upper vertical portion 138a1 and extending from the upper vertical portion 138a1. The upper conductive pattern 150 may include first conductive layers 138a2 and 138b2 extending from the second conductive path 138, a second conductive layer 150a on the first conductive layers 138a2 and 138b2, and a third conductive layer 150b on the second conductive layer 150a. The first conductive layers 138a2 and 138b2 may include a third metal layer 138a2 (upper horizontal portion 138a2) extending from the upper vertical portion 138a1 and a third barrier layer 138b2 (second upper portion 138b2) extending from the first upper portion 138b1. The second conductive layer 150a and the third conductive layer 150b may be referred to as an upper metal layer 150a and an upper anti-reflective layer 150b, respectively.

[0036] The thickness Tu of each upper conductive pattern 150 may be greater than the thickness Tb of each lower conductive pattern 137. The thickness Duu of the upper metal layer 150a may be greater than the thickness Dub of the second metal layer 138a on the upper surface of the insulating structure 130. For example, the thickness Duu of the upper metal layer 150a may be greater than the thickness Dub of the upper horizontal portion 138a2. In example embodiments, since the upper horizontal portion 138a2 of the second metal layer 138a exists below the upper metal layer 150a, the upper metal layer 150a may be spaced apart from the upper surface of the insulating structure 130. For example, the upper metal layer 150a may be spaced apart from the upper surface of the third upper insulating layer 136. The second metal layer 138a may include a portion in the upper conductive pattern 150 (that is, the upper horizontal portion 138a2) and a portion extending from the portion into the insulating structure 130 (that is, the upper vertical portion 138a1). In other words, the upper conductive pattern 150 may include a portion of the second metal layer 138a from which the second metal layer 138a continuously extends into the via opening, so that the upper vertical portion 138a1 in the via opening and the upper horizontal portion 138a2 outside the via opening form an integral or single structure. The semiconductor device 100 as described above can reduce the contact resistance by increasing the contact area between the upper metal layer 150a and the second metal layer 138a (specifically, by increasing the contact area between the upper metal layer 150a and the upper horizontal portion 138a2 of the second metal layer 138a), and due to the second metal layer 138a in the upper conductive pattern 150, the electromigration characteristics of the upper conductive pattern 150 can be improved. For example, the upper metal layer 150a may include aluminum (Al), and the first metal layer 129a or the second metal layer 138a may include tungsten (W), so that the electromigration characteristics of the upper conductive pattern 150 can be improved. Therefore, a semiconductor device 100 with improved electrical characteristics and reliability can be provided.

[0037] The upper anti-reflection layer 150b may be formed to protect the upper conductive pattern 150 in the process of etching the passivation structure P to form the opening OP. The upper metal layer 150a may include a conductive material, such as aluminum (Al). The upper anti-reflection layer 150b may include at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and tungsten carbon nitride (WCN). For example, the upper anti-reflection layer 150b may include titanium nitride (TiN).

[0038] The second conductive path 138 may include a second barrier layer 138b and a second metal layer 138a disposed along the sidewall. The second barrier layer 138b (that is, the first upper portion 138b1) may cover the side surface and the lower surface of the second metal layer 138a. The second metal layer 138a may include a conductive material, such as tungsten (W). The second metal layer 138a and the upper metal layer 150a may include different materials, but example embodiments thereof are not limited thereto. The second barrier layer 138b may include a metal nitride such as tantalum nitride (TaN), titanium nitride (TiN) or tungsten nitride (WN), such as titanium nitride (TiN). The first conductive path 129 and the second conductive path 138 may have similar structures. In example embodiments, the second barrier layer 138b may be disposed between the insulating structure 130 and the second metal layer 138a. For example, the second barrier layer 138b may cover a portion of the upper surface of the third upper insulating layer 136. That is, the second upper portion 138b2 may cover a portion of the upper surface of the third upper insulating layer 136.

[0039] The passivation structure P may include a protective layer 160, a first passivation layer 164, and a second passivation layer 168. The passivation structure P may cover an inner wall of the trench T formed along the cutting region CR.

[0040] The protective layer 160 may be conformally formed along at least a portion of the second barrier layer 138b and the upper conductive pattern 150. The protective layer 160 may include the same material as the third upper insulating layer 136, and may include, for example, TEOS. In example embodiments, since the second barrier layer 138b (that is, the second upper portion 138b2) exists between the protective layer 160 and the third upper insulating layer 136, the protective layer 160 and the third upper insulating layer 136 may be distinguished from each other, but example embodiments thereof are not limited thereto.

[0041] The first passivation layer 164 may cover the protective layer 160. The first passivation layer 164 may include silicon oxide, such as TEOS. The second passivation layer 168 may be conformally formed along the first passivation layer 164 and the trench T. The second passivation layer 168 may include silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. For example, the second passivation layer 168 may include silicon nitride.

[0042] The guard ring 140 disposed in the edge region ER may extend in a horizontal direction to surround the device region DR. Figure 3CAs shown, the guard ring 140 may have a quadrilateral shape, but the exemplary embodiment thereof is not limited thereto. According to another exemplary embodiment, the guard ring 140 may have a circular or elliptical shape. The cutting region CR may be disposed outside the guard ring 140 (i.e., outside the periphery of the guard ring 140) and may surround the guard ring 140. The trench T may extend in one or more horizontal directions along the cutting region CR.

[0043] Figures 4 to 9 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to example embodiments.

[0044] Reference Figure 4 In the semiconductor device 100a, the thickness Duu of the upper metal layer 150a may be substantially equal to or less than the thickness Dub of the second metal layer 138a on the upper surface of the insulating structure 130. For example, the thickness Duu of the upper metal layer 150a may be substantially equal to or less than the thickness Dub of the upper horizontal portion 138a2 on the upper surface of the insulating structure 130. In example embodiments, in the later described Fig.18 and Fig.19 In the process of FIG. 1 , the upper horizontal portion 138 a 2 of the second metal layer 138 a may be configured to have a greater thickness, and the upper metal layer 150 a may be configured to have a thickness smaller than that of the upper horizontal portion 138 a 2 .

[0045] Reference Figure 5 In the semiconductor device 100b, the second metal layer 138a may be in direct contact with the upper surface of the insulating structure 130. This is because, in the later described Fig.17 In the process of FIG. 1 , the second barrier layer 138 b may be formed in the second via hole VH2 and may not be formed on the upper surface of the third upper insulating layer 136 , or in Fig.18 In the process in, the process may be performed after the second upper portion 138b2 of the second barrier layer 138b on the third upper insulating layer 136 is removed by a planarization process before forming the second metal layer 138a.

[0046] The protection layer 160 may be conformally formed along the insulating structure 130 and the upper conductive pattern 150. In example embodiments, a boundary between the protection layer 160 and the third upper insulating layer 136 may not be recognized, and since the second upper portion 138b2 of the second barrier layer 138b does not exist on the upper surface of the third upper insulating layer 136, the protection layer 160 may be integrally connected to the third upper insulating layer 136, that is, as a single layer without a boundary therebetween.

[0047] Reference Figure 6In the semiconductor device 100c, the upper conductive pattern 150 may further include an upper barrier layer 151 between the upper metal layer 150a and the upper horizontal portion 138a2 of the second metal layer 138a. The upper barrier layer 151 may be formed to cover the upper surface of the upper horizontal portion 138a2 of the second metal layer 138a. The upper barrier layer 151 may include Ti, TiN, Ta, TaN, WN, or a combination thereof.

[0048] Reference Figure 7 In the semiconductor device 100d, each upper conductive pattern 150 may further include an oxide layer 152 between the upper metal layer 150a and the upper anti-reflection layer 150b. In the process of forming the upper anti-reflection layer 150b on the upper metal layer 150a, the oxide layer 152 may be formed by a thermal treatment process. The oxide layer 152 may include a conductive metal oxide.

[0049] Reference Figure 8 In the semiconductor device 100e, each lower conductive pattern 137 may include a first barrier layer 129b covering a portion of an upper surface of the interlayer insulating layer 128 and a first metal layer 129a covering the first barrier layer 129b on the interlayer insulating layer 128. For example, the lower conductive pattern 137 may include a second lower portion 129b2 of the first barrier layer 129b, a lower horizontal portion 129a2 of the first metal layer 129a, a lower metal layer 137a, and a lower anti-reflective layer 137b.

[0050] The first metal layer 129a may include a lower vertical portion 129a1 which is a portion disposed at a level lower than that of the upper surface of the interlayer insulating layer 128 with respect to the upper surface of the interlayer insulating layer 128, and a lower horizontal portion 129a2 which is a portion disposed at a level higher than that of the upper surface of the interlayer insulating layer 128 with respect to the semiconductor substrate 102. The first barrier layer 129b may include a first lower portion 129b1 which is a portion disposed at a level lower than that of the upper surface of the interlayer insulating layer 128 with respect to the semiconductor substrate 102, and a second lower portion 129b2 which is a portion disposed at a level higher than that of the upper surface of the interlayer insulating layer 128 with respect to the semiconductor substrate 102.

[0051] In example embodiments, the lower conductive pattern 137 and the upper conductive pattern 150 may have similar structures. The first metal layer 129a may include a portion (that is, a lower horizontal portion 129a2) in the lower conductive pattern 137 and a portion (that is, a lower vertical portion 129a1) extending from the portion into the interlayer insulating layer 128. The thickness Dbu of the lower metal layer 137a may be greater than the thickness Dbb of the first metal layer 129a on the upper surface of the interlayer insulating layer 128. For example, the thickness Dbu of the lower metal layer 137a may be greater than the thickness Dbb of the lower horizontal portion 129a2 on the upper surface of the interlayer insulating layer 128. The semiconductor device 100e may reduce the contact resistance by increasing the contact area between the lower metal layer 137a and the lower horizontal portion 129a2 of the first metal layer 129a. Therefore, a semiconductor device 100e having improved electrical characteristics and reliability may be provided.

[0052] Reference Fig. 9 In the semiconductor device 100f, the thickness Dbu of the lower metal layer 137a may be substantially equal to or less than the thickness Dbb of the first metal layer 129a on the upper surface of the interlayer insulating layer 128. Figures 15 to 16B In the process of FIG. 1 , the first metal layer 129 a (specifically, the lower horizontal portion 129 a 2 ) may be configured to have a greater thickness, and the lower metal layer 137 a may be configured to have a smaller thickness than the lower horizontal portion 129 a 2 of the first metal layer 129 a .

[0053] Fig.10 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0054] Reference Fig.10 , the semiconductor device 100g may further include a through electrode 170, a via insulating layer 172, a lower passivation layer 180, and a via pad 190. The through electrode 170 may vertically penetrate the semiconductor substrate 102 and the device region 110, and may be connected to the interconnection region 120. The via insulating layer 172 may cover the side surface of the through electrode 170. The through electrode 170 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and gold (Au) or a combination thereof. The via insulating layer 172 may include an insulating material such as silicon oxide.

[0055] The lower passivation layer 180 may cover the lower surface of the semiconductor substrate 102, and the through electrode 170 may penetrate the lower passivation layer 180. The via pad 190 may be disposed on the lower surface of the lower passivation layer 180, and may be connected to the through electrode 170. The via pad 190 may be electrically connected to the interconnection region 120 through the through electrode 170. According to another example embodiment, the via pad 190 may overlap the lower passivation layer 180 in a horizontal direction, and a side surface of the via pad 190 may be in contact with the lower passivation layer 180.

[0056] Fig.11A is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to example embodiments.

[0057] Fig. 11B is a diagram showing a method according to an example embodiment Fig.11A An enlarged cross-sectional view of a portion of a semiconductor package shown in Fig.11A Area "C" in the.

[0058] Reference Fig.11A and Fig. 11B , the semiconductor package 1000 of the present disclosure may be configured as a high bandwidth memory (HBM) package. The semiconductor package 1000 may include a package substrate PS, an interposer IP mounted on the package substrate PS, a memory package 800 mounted on the interposer IP, and a processor chip 900. The interposer IP may electrically connect the memory package 800 to the processor chip 900.

[0059] The memory package 800 may include a buffer chip 805, a first semiconductor device 810, a second semiconductor device 820, a third semiconductor device 830, and a fourth semiconductor device 840 that may be stacked sequentially. The buffer chip 805 and the first to fourth semiconductor devices 810, 820, 830, and 840 may have the same structure as the reference Figure 3A and Figure 3B The structure of the semiconductor device 100 described above is the same as or similar to that of the structure described above, and may include, for example, components corresponding to the upper conductive pattern 150 and the lower conductive pattern 137. In addition, the second to fourth semiconductor devices 820, 830, and 840 may include components corresponding to the through-electrode 170, the via insulating layer 172, the lower passivation layer 180, and the via pad 190.

[0060] In an example embodiment, the buffer chip 805 may be configured as a semiconductor chip of a different type from the first to fourth semiconductor devices 810, 820, 830, and 840. For example, the buffer chip 805 may be configured as a logic chip, and the first to fourth semiconductor devices 810, 820, 830, and 840 may be configured as a memory chip. The logic chip may include a microprocessor, an analog device, or a digital signal processor. The memory chip may include a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0061] The memory package 800 may further include an adhesive layer 850 and a sealant 860. The adhesive layer 850 may be disposed between the buffer chip 805 and the first semiconductor device 810 and between the first to fourth semiconductor devices 810, 820, 830, and 840. The adhesive layer 850 may be a non-conductive film (NCF) or a non-conductive glue (NCP). The sealant 860 may be a resin containing epoxy resin or polyimide. For example, the resin may include a bisphenol-based epoxy resin, a polycyclic aromatic epoxy resin, an o-cresol novolac epoxy resin, a biphenyl epoxy resin, or a naphthyl epoxy resin.

[0062] The processor chip 900 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), a mobile application, or a digital signal processor (DSP) chip.

[0063] like Fig. 11B As shown, the memory package 800 may further include conductive bumps 855 between the second semiconductor device 820 and the third semiconductor device 830 and between the third semiconductor device 830 and the fourth semiconductor device 840. The first to fourth semiconductor devices 810, 820, 830, and 840 may further include connection pads 195 connected to the upper conductive pattern 150. The upper conductive pattern 150 and the lower conductive pattern 137 may be configured to be connected to the Figure 3A and Figure 3B The components of the semiconductor device 100 shown in FIG. 1 are the same or similar. For example, the upper conductive pattern 150 and the lower conductive pattern 137 may be configured as Figure 8 The semiconductor device 100e shown in FIG. Fig. 9 The components of the semiconductor device 100f shown in FIG. 1 are the same. The connection pad 195 may be filled with Fig.108 and 840. The conductive bump 855 may be formed by passing through the passivation structure P and may be in contact with the upper conductive pattern 150. The connecting pad 195 may penetrate the passivation structure P and may be in contact with the side surface of the structure. The conductive bump 855 may connect the via pad 190 to the connecting pad 195 between the adjacent semiconductor devices 820, 830, and 840. The adhesive layer 850 may cover the side surfaces of the via pad 190, the connecting pad 195, and the conductive bump 855. According to another example embodiment, the conductive bump 855 may not be provided, and the via pad 190 and the connecting pad 195 may be in direct contact with each other.

[0064] Fig.12 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to example embodiments.

[0065] Reference Fig.12 , the semiconductor package 1100 may include a substrate 2 , an adhesive member 10 , a bonding wire 20 , and a sealant 30 . The semiconductor package 1100 may further include a semiconductor device 100 on the substrate 2 .

[0066] The substrate 2 may include an upper pad 3, a lower pad 5, an internal interconnect 6, and an external connection terminal 7. In an example embodiment, the substrate 2 may be implemented as a printed circuit board and may include an insulating material such as a phenolic resin, an epoxy resin, or a prepreg. In another example embodiment, the substrate 2 may be configured as a redistribution layer in which an insulating material and a conductive material are stacked. The upper pad 3 and the lower pad 5 may be formed by forming a metal layer on a base of the substrate 2 and patterning the metal layer.

[0067] The upper pad 3 may be disposed on the upper surface of the substrate 2 and may be electrically connected to the semiconductor device 100. The lower pad 5 may be disposed on the lower surface of the substrate 2, and the upper pad 3 may be electrically connected to the corresponding lower pad 5 through the internal interconnect 6. The external connection terminal 7 may be disposed below the lower pad 5. The lower pad 5, the upper pad 3, and the interconnect may include a metal such as copper (Cu). The external connection terminal 7 may be configured as a conductive bump 855 (e.g., a solder bump).

[0068] The semiconductor device 100 may include an insulating structure 130, an upper conductive pattern 150, and a passivation structure P, which may be Figure 3A and Figure 3B The components of the semiconductor device 100 shown in FIG. 1 are the same or similar. The insulating structure 130 may be provided in the semiconductor device 100. The passivation structure P may be provided on the insulating structure 130 and may protect the insulating structure 130 from external physical impact. The upper conductive pattern 150 may be buried in the passivation structure P. The upper conductive pattern 150 may be connected to the upper pad 3 by the bonding wire 20.

[0069] The adhesive member 10 may be disposed between the substrate 2 and the semiconductor device 100. The adhesive member 10 may fix or attach the semiconductor device 100 to the substrate 2. The adhesive member 10 may be configured as a die attach film (DAF), but example embodiments thereof are not limited thereto. The sealant 30 may cover the substrate 2, the semiconductor device 100, and the bonding wire 20.

[0070] Figures 13 to 26 are cross-sectional views and enlarged cross-sectional views illustrating processes of a method of manufacturing a semiconductor device in sequence according to an example embodiment. Fig.13 , Fig.14A , Fig.16A and Figure 22 to Figure 26 is along Figure 2 A cross-sectional view taken along line II-II'. Fig. 14B , Fig.15 , Fig. 16B and Figures 17 to 21 Shows the corresponding Figure 3B area.

[0071] Reference Fig.13 , a device region 110 and an interconnection region 120 may be formed on a semiconductor substrate 102. The semiconductor substrate 102 may correspond to Figure 1 The semiconductor substrate or wafer W is shown in FIG.

[0072] The semiconductor substrate 102 may include a device region DR and a scribe line region SL between the device regions DR. The scribe line region SL may include an edge region ER and a cutting region CR between the edge regions ER. The edge region ER may surround the device region DR. The cutting region CR may refer to a portion separated during a dicing process described later. The semiconductor substrate 102 may include a semiconductor material.

[0073] The device region 110 may include an integrated circuit device 112, an internal interconnection 114, and a lower interlayer insulating layer 116. The integrated circuit device 112 may be disposed in the device region DR. The internal interconnection 114 may be disposed in the device region DR and the edge region ER, and in some example embodiments, the internal interconnection 114 may also be disposed in the dicing region CR. The lower interlayer insulating layer 116 may cover the semiconductor substrate 102, the integrated circuit device 112, and the internal interconnection 114.

[0074] The interconnection region 120 may be formed on the device region 110. The interconnection region 120 may include a lower insulating layer 122, a lower contact 124, and a lower interconnection 126.

[0075] Reference Fig.14A and Fig. 14B , an interlayer insulating layer 128 and a first via hole VH1 vertically penetrating the interlayer insulating layer 128 may be formed in the interconnection region 120 , and a first barrier layer 129 b may be formed in the first via hole VH1 .

[0076] The first via hole VH1 may be formed using a dry etching, wet etching, laser drilling, or mechanical drilling method. The first lower portion 129b1 of the first barrier layer 129b may be formed to have a uniform thickness on the lower surface and the side surface of the first via hole VH1. In an example embodiment, the second lower portion 129b2 of the first barrier layer 129b may cover the interlayer insulating layer 128. For example, the second lower portion 129b2 of the first barrier layer 129b may be formed on the upper surface of the interlayer insulating layer 128. However, example embodiments thereof are not limited thereto, and the first barrier layer 129b may not cover the upper surface of the interlayer insulating layer 128 or may be removed from the upper surface of the interlayer insulating layer 128, and may be formed in the first via hole VH1. The first barrier layer 129b may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0077] Reference Fig.15 , a first metal layer 129 a may be formed to fill the first via hole VH1 .

[0078] The first metal layer 129a may be configured to completely fill the first via hole VH1. For example, the lower vertical portion 129a1 of the first metal layer 129a may fill the first via hole VH1. In an example embodiment, the lower horizontal portion 129a2 of the first metal layer 129a may be formed to cover the first barrier layer 129b on the upper surface of the interlayer insulating layer 128. In this case, it is possible to manufacture Figure 8 The semiconductor device 100e in FIG. 1 and when the first metal layer 129a is formed to a greater thickness, the semiconductor device 100e in FIG. 1 can be manufactured. Fig. 9 100f in the semiconductor device 100f. However, example embodiments thereof are not limited thereto, and after removing the first barrier layer 129b on the upper surface of the interlayer insulating layer 128 by a planarization process, the lower horizontal portion 129a2 of the first metal layer 129a may be formed to cover the upper surface of the interlayer insulating layer 128, and the lower vertical portion 129a1 may completely fill the first via hole VH1. The first metal layer 129a may be formed by a PVD process, a CVD process, or an ALD process.

[0079] Reference Fig.16A and Fig. 16B , a first conductive via 129 may be formed, and a lower conductive pattern 137 may be formed on the first conductive via 129. Thereafter, an insulating structure 130 may be formed on the interconnection region 120.

[0080] The first conductive via 129 may be formed by removing the first metal layer 129a and the first barrier layer 129b from the upper surface of the interlayer insulating layer 128 by a planarization process, but example embodiments thereof are not limited thereto. Figure 8 The semiconductor device 100e or Fig. 9 The semiconductor device 100f in FIG. 1 may not be subjected to a planarization process.

[0081] The lower conductive pattern 137 may be formed by forming a lower metal layer 137a on the interlayer insulating layer 128, forming a lower anti-reflective layer 137b on the lower metal layer 137a, and performing a photolithography process and an etching process. Since the lower conductive pattern 137 may be formed by a process that is the same as or similar to a process for forming an upper conductive pattern 150 to be described later, the process for forming the upper conductive pattern 150 to be described later may be applied in the same or similar manner. The lower conductive pattern 137 may be disposed in the device region DR and the edge region ER, and at least one lower conductive pattern 137 may be electrically connected to the corresponding lower interconnect 126.

[0082] An insulating structure 130 may be formed on the interconnection region 120. The insulating structure 130 may include a first upper insulating layer 132, a second upper insulating layer 134, and a third upper insulating layer 136, and a lower conductive pattern 137 may be disposed in the insulating structure 130. The lower conductive pattern 137 may be covered by the first upper insulating layer 132. In an example embodiment, a portion of the second upper insulating layer 134 that overlaps the lower conductive pattern 137 in a vertical direction may protrude upward. The second upper insulating layer 134 may include a material having an etching selectivity relative to the first upper insulating layer 132. For example, the first upper insulating layer 132 may include a high density plasma (HDP) oxide. The second upper insulating layer 134 may include silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. In an example embodiment, the third upper insulating layer 136 may include silicon oxide. For example, the third upper insulating layer 136 may include tetraethyl orthosilicate (TEOS). The lower conductive pattern 137 may constitute an interconnection extending in a horizontal direction and a pad connected to the interconnection.

[0083] Reference Fig.17 , a second via hole VH2 vertically penetrating the insulating structure 130 may be formed, and a second barrier layer 138 b may be formed in the second via hole VH2 .

[0084] The second via hole VH2 may be formed using a dry etching, wet etching, laser drilling, or mechanical drilling method. The second barrier layer 138b may be formed to have a uniform thickness on the lower surface and side surfaces of the second via hole VH2. In an example embodiment, the second upper portion 138b2 of the second barrier layer 138b may be formed to cover the third upper insulating layer 136. For example, the second upper portion 138b2 of the second barrier layer 138b may be formed on the upper surface of the third upper insulating layer 136. However, example embodiments thereof are not limited thereto, and the second barrier layer 138b may not cover the upper surface of the third upper insulating layer 136 or may be removed from the upper surface of the third upper insulating layer 136, and may be formed in the second via hole VH2. The first upper portion 138b1 of the second barrier layer 138b may be formed to cover the lower surface and side surfaces of the second via hole VH2. In this case, it may be manufactured Figure 5 The second barrier layer 138b may be formed by a PVD process, a CVD process, or an ALD process.

[0085] Reference Fig.18 , a second metal layer 138a may be formed to fill the second via hole VH2.

[0086] The second metal layer 138a may be formed to completely fill the second via hole VH2. For example, the upper vertical portion 138a1 of the second metal layer 138a may fill the second via hole VH2. In an example embodiment, the upper horizontal portion 138a2 of the second metal layer 138a may be formed to cover the second barrier layer 138b on the third upper insulating layer 136. However, example embodiments thereof are not limited thereto, and after the second barrier layer 138b on the upper surface of the third upper insulating layer 136 is removed by a planarization process, the second metal layer 138a may be formed to cover the upper surface of the third upper insulating layer 136, and the second metal layer 138a may fill the second via hole VH2. In this case, the second metal layer 138a may be in contact with the upper surface of the third upper insulating layer 136, and may be manufactured. Figure 5 The second metal layer 138a can be formed by a PVD process, a CVD process, or an ALD process. When the second metal layer 138a is formed to have a greater thickness, a semiconductor device 100b can be manufactured. Figure 4 The semiconductor device 100a in FIG.

[0087] Thereafter, when the upper surface of the second metal layer 138a has a step difference, that is, when the upper surface of the upper horizontal portion 138a2 of the second metal layer 138a has a step difference, a planarization process may be optionally performed to remove the step difference from the upper surface of the second metal layer 138a. In example embodiments, a polishing CMP process may be performed.

[0088] Reference Fig.19 , an upper metal layer 150 a on the second metal layer 138 a and an upper anti-reflection layer 150 b on the upper metal layer 150 a may be formed.

[0089] The upper metal layer 150a and the upper anti-reflection layer 150b may be formed by a PVD process, a CVD process, or an ALD process. The thickness of the upper metal layer 150a may be greater than the thickness of the second metal layer 138a on the insulating structure 130 (particularly, greater than the thickness of the upper horizontal portion 138a2), ​​but example embodiments thereof are not limited thereto.

[0090] To manufacture Figure 6 In the semiconductor device 100c, before the upper metal layer 150a is formed on the second metal layer 138a, an upper barrier layer 151 may be formed on the second metal layer 138a. The upper barrier layer 151 may be disposed between the upper surface of the second metal layer 138a and the lower surface of the upper metal layer 150a. The upper barrier layer 151 may include Ti, TiN, Ta, TaN, WN, or a combination thereof.

[0091] To manufacture Figure 7 In the semiconductor device 100d, before the upper anti-reflective layer 150b is formed on the upper metal layer 150a, an oxide layer 152 may be formed. The oxide layer 152 may be formed to have a uniform thickness. The oxide layer 152 may include a conductive metal oxide, such as aluminum (Al) oxide. The oxide layer 152 may be formed by a PVD process, a CVD process, or an ALD process, but example embodiments thereof are not limited thereto.

[0092] Reference Fig. 20 , a photoresist pattern 200 may be formed on the upper anti-reflective layer 150 b.

[0093] In some embodiments, in order to form the photoresist pattern 200, a photoresist layer may be formed on the upper anti-reflection layer 150b. Thereafter, an exposure and development process may be performed on the photoresist layer by irradiating light, and a photomask may be used to form the photoresist pattern 200 to define an area in which a pattern may be formed. When light is irradiated, the upper metal layer 150a may be protected by the upper anti-reflection layer 150b.

[0094] Reference Fig.21 , the upper metal layer 150a, the upper anti-reflection layer 150b, the second metal layer 138a, and the second barrier layer 138b may be patterned using the photoresist pattern 200 as an etching mask. Thus, the upper conductive pattern 150 may be formed.

[0095] After the etching process, the photoresist pattern 200 may be removed through ashing and stripping processes. The upper anti-reflective layer 150b may include the same metal element as that of the upper metal layer 150a, but example embodiments thereof are not limited thereto.

[0096] Reference Fig. 22 , a protection layer 160 covering the second barrier layer 138b, the insulating structure 130, and the upper conductive pattern 150 may be formed. The protection layer 160 may be conformally formed along the second barrier layer 138b, the insulating structure 130, and the upper conductive pattern 150. The protection layer 160 may include the same material as that of the third upper insulating layer 136, and may include, for example, TEOS. In example embodiments, a boundary between the protection layer 160 and the third upper insulating layer 136 may not be obvious, and the protection layer 160 may be integrally connected to the third upper insulating layer 136.

[0097] After forming the protective layer 160, a trench T may be formed so that the interconnection region 120, the insulating structure 130, the second barrier layer 138b, and the protective layer 160 may be separated, and the upper surface of the device region 110 is exposed therebetween. The side surfaces of the interconnection region 120, the insulating structure 130, the second barrier layer 138b, and the protective layer 160, and the upper surface of the device region 110 may define the trench T. The trench T may extend in a horizontal direction to surround the device region DR and the edge region ER. According to another example embodiment, the trench T may not completely cut the interconnection region 120.

[0098] Reference Fig.23 , an insulating material layer 164p covering the protective layer 160 may be formed. The insulating material layer 164p may fill the space between the upper conductive patterns 150 and may completely cover the upper conductive patterns 150. The insulating material layer 164p may include silicon oxide, and in example embodiments, the insulating material layer 164p may include TEOS. In example embodiments, the upper surface of the insulating material layer 164p may be uneven, for example, a portion corresponding to the upper conductive pattern 150 may protrude.

[0099] Reference Fig.24 , a planarization process may be performed, and the first passivation layer 164 may be formed by etching the insulating material layer 164p. The planarization process may include a chemical mechanical polishing (CMP) process. For example, the CMP process may start from the upper portion of the insulating material layer 164p, and the insulating material layer 164p may be etched. Thus, the first passivation layer 164 may be formed, and the upper surface of the first passivation layer 164 may be flat.

[0100] Reference Fig.25, a second passivation layer 168 may be formed on the first passivation layer 164. The second passivation layer 168 may be conformally formed along the first passivation layer 164 and the trench T. The protective layer 160, the first passivation layer 164, and the second passivation layer 168 may form a passivation structure P. The passivation structure P may cover the inner wall of the trench T formed along the cutting region CR. The second passivation layer 168 may include silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. For example, the second passivation layer 168 may include silicon nitride.

[0101] Reference Fig.26 , an opening OP may be formed by partially etching the protection layer 160, the first passivation layer 164, and the second passivation layer 168. At least one of the upper conductive patterns 150 may be exposed through the opening OP. The term "exposing" may be used to describe the relationship between elements in certain intermediate processes in manufacturing a semiconductor device, but in the case of a completed device, it may not necessarily be necessary to expose a specific region, layer, structure, or other element.

[0102] Afterwards, refer to Figure 3A and Figure 3B , the semiconductor substrate 102, the lower interlayer insulating layer 116, the first passivation layer 164 and the second passivation layer 168 may be separated by a scribing process, so that the semiconductor device 100 may be formed. The laser beam may be irradiated to the back side of the semiconductor substrate 102. For example, a thin film tape (not shown) may be attached to the semiconductor substrate 102, and the laser beam may be irradiated to a portion of the semiconductor substrate 102 in the cutting region CR. The physical properties of the semiconductor substrate 102 may be changed at the laser point to which the laser beam is irradiated, and, for example, the physical strength of the semiconductor substrate 102 may be weakened. By extending the thin film tape attached to the semiconductor substrate 102 in the horizontal direction, the semiconductor substrate 102 may be separated along the cutting region CR. Alternatively, in example embodiments, the scribing process may include a process of cutting the semiconductor substrate 102 using a saw wheel.

[0103] According to the aforementioned example embodiments, the upper conductive pattern may include a metal layer disposed below the upper metal layer, and the metal layer may be configured to be connected to (or integrated with) a conductive path, so that an area in which the upper metal layer of the upper conductive pattern contacts the metal layer may be widened, thereby reducing the resistance of the semiconductor device. In addition, the electromigration characteristics of the upper conductive pattern may be improved by or based on the material of the metal layer.

[0104] Spatially relative terms, such as "above", "upper", "higher", "below", "under", "lower", etc., may be represented by reference numerals and refer to the accompanying drawings unless otherwise specified. It will be understood that such spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, elements described as being "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0105] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0106] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0116847 filed in the Korean Intellectual Property Office on September 4, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a device region on the semiconductor substrate; an interconnection region including a lower interconnection on the device region; an insulating structure on the interconnect region; a lower conductive pattern in the insulating structure; a first conductive path electrically connecting at least one of the lower conductive patterns to the lower interconnect of the interconnect region; an upper conductive pattern on the insulating structure; as well as a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to at least one of the lower conductive patterns, wherein the first conductive path comprises a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, wherein the second conductive path comprises a second metal layer in the insulating structure and a second barrier layer on the lower surface and the side surface of the second metal layer, respectively; and The upper conductive patterns respectively include: a third barrier layer extending from the second barrier layer and on a portion of the upper surface of the insulating structure; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; an upper metal layer on the third metal layer; and An upper anti-reflective layer is on the upper metal layer. 2 . The semiconductor device according to claim 1 , wherein a thickness of the upper metal layer is greater than a thickness of the third metal layer on the upper surface of the insulating structure. 3 . The semiconductor device according to claim 1 , wherein a thickness of the upper metal layer is substantially equal to or less than a thickness of the third metal layer on the upper surface of the insulating structure.

4. The semiconductor device according to claim 1, The insulating structure comprises: a first upper insulating layer on the side surfaces and the upper surface of the lower conductive pattern; a second upper insulating layer on the first upper insulating layer; as well as a third upper insulating layer on the second upper insulating layer, and The material of the second upper insulating layer is different from the material of the first upper insulating layer and the material of the third upper insulating layer. 5 . The semiconductor device according to claim 1 , wherein the upper conductive patterns further include an upper barrier layer between the upper metal layer and the third metal layer, respectively.

6. The semiconductor device according to claim 1, further comprising: an interlayer insulating layer between the interconnection region and the insulating structure, The lower conductive pattern respectively includes the first barrier layer on a portion of the upper surface of the interlayer insulating layer, the first metal layer on the first barrier layer on the portion of the upper surface of the interlayer insulating layer, a lower metal layer on the first metal layer, and a lower anti-reflective layer on the lower metal layer. 7 . The semiconductor device according to claim 6 , wherein a thickness of the lower metal layer is greater than a thickness of the first metal layer on the upper surface of the interlayer insulating layer. 8 . The semiconductor device according to claim 6 , wherein a thickness of the lower metal layer is substantially equal to or smaller than a thickness of the first metal layer on the upper surface of the interlayer insulating layer. 9 . The semiconductor device according to claim 1 , wherein the upper metal layer and the second metal layer comprise different materials.

10. The semiconductor device according to claim 9, wherein the upper metal layer comprises aluminum (Al), and The second metal layer includes tungsten (W). 11 . The semiconductor device according to claim 1 , wherein respective thicknesses of the upper conductive patterns are greater than respective thicknesses of the lower conductive patterns.

12. The semiconductor device according to claim 1, further comprising: a protective layer on the insulating structure and the upper conductive pattern; a first passivation layer on the protective layer; as well as A second passivation layer is on the first passivation layer.

13. The semiconductor device according to claim 1, further comprising: A via pad is under the semiconductor substrate and a through electrode is electrically connected to the via pad and penetrates the semiconductor substrate. 14 . The semiconductor device of claim 1 , wherein the upper metal layer is spaced apart from the upper surface of the insulating structure. 15 . The semiconductor device according to claim 1 , wherein the upper conductive patterns further include oxide layers between the upper metal layer and the upper anti-reflection layer, respectively.

16. A semiconductor package, comprising: A plurality of semiconductor devices sequentially stacked on a buffer chip; an adhesive layer between the plurality of semiconductor devices; as well as a sealant on the buffer chip and the plurality of semiconductor devices, The semiconductor devices respectively include: An insulating structure on a semiconductor substrate; a via pad beneath the semiconductor substrate; a through electrode electrically connected to the via pad and penetrating the semiconductor substrate; a lower conductive pattern in the insulating structure; a first conductive path on a lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to at least one of the lower conductive patterns; and a connection pad electrically connected to one of the upper conductive patterns, wherein the first conductive path comprises a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, respectively, wherein the second conductive path comprises a second metal layer in the insulating structure and a second barrier layer on the lower surface and the side surface of the second metal layer, respectively; and The upper conductive patterns respectively include: a third barrier layer extending from the second barrier layer and on a portion of the upper surface of the insulating structure; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; an upper metal layer on the third metal layer; and An upper anti-reflective layer is on the upper metal layer.

17. The semiconductor package according to claim 16, further comprising: an interlayer insulating layer between the semiconductor substrate and the insulating structure, The lower conductive pattern respectively includes the first barrier layer on a portion of the upper surface of the interlayer insulating layer, the first metal layer on the first barrier layer on the portion of the upper surface of the interlayer insulating layer, a lower metal layer on the first metal layer, and a lower anti-reflective layer on the lower metal layer.

18. A semiconductor device comprising: An insulating structure on a semiconductor substrate; a lower conductive pattern in the insulating structure; a first conductive path on a lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; as well as a second conductive path in the insulating structure and electrically connecting the upper conductive pattern to the lower conductive pattern, wherein the first conductive path comprises a first metal layer and a first barrier layer covering the lower surface and the side surface of the first metal layer, wherein the second conductive path comprises a second metal layer in the insulating structure and a second barrier layer on the lower surface and the side surface of the second metal layer, respectively; and The upper conductive pattern comprises: a first conductive layer extending from the second conductive path; a second conductive layer on the first conductive layer; and A third conductive layer is on the second conductive layer.

19. The semiconductor device according to claim 18, further comprising: a passivation structure on the insulating structure and the upper conductive pattern; an opening penetrating the passivation structure and exposing the upper conductive pattern; as well as A connection pad is in the opening and electrically connected to the upper conductive pattern. 20 . The semiconductor device according to claim 18 , wherein the first conductive layer includes a third metal layer continuously extending from the second metal layer and a third barrier layer continuously extending from the second barrier layer.

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