Method for phase locking and method for controlling delay-locked loop circuit

Abstract

The embodiment of the invention relates to a method for phase locking and a method for controlling a delay-locked loop circuit. Specifically, the method for phase locking includes: determining a first phase greater than or equal to 0 degrees and less than 180 degrees and a second phase determined based on a sum of the first phase and 180 degrees; and performing phase discrimination on the first phase and the second phase so as to perform phase locking based on the first phase and the second phase. According to the embodiment of the invention, the possibility of lock losing or harmonic locking can be obviously reduced.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of data computing, and more particularly to a method for phase locking and a method for controlling a delay locked loop circuit. Background Art

[0002] A delay loop (DLL) circuit can be used to generate multiple clock signals with precise phase relationships. Generally, the delay loop circuit may include a phase detector for phase detection, so that the delay loop circuit can perform phase lock according to the phase detection result of the phase detector. Generally speaking, in the existing related art, phase detection is performed only for the 0-degree phase and the 360-degree phase, and phase difference calibration and phase locking are performed only based on the phase detection result between the 0-degree phase and the 360-degree phase.

[0003] However, since the phase detection range of the phase detector is only 2π, and the phase difference between the 360-degree phase and the 0-degree phase is easily affected by factors such as process, voltage and temperature, the phase difference between the two fails to fall within the phase detection range of the phase detector, resulting in abnormal locking between phases (such as loss of lock or harmonic lock).

[0004] In summary, the disadvantage of the existing solution for phase locking is that since phase locking is performed only based on the phase detection results of the 0-degree phase and the 360-degree phase, abnormal locking phenomena such as loss of lock and harmonic lock are easily caused. Summary of the invention

[0005] In view of the above problems, the present invention provides a method for phase locking and a method for controlling a delay locked loop circuit, so that the phase detection range of the phase detector in the delay locked loop circuit can be expanded, while significantly reducing the possibility of loss of lock or harmonic lock.

[0006] According to a first aspect of the present invention, a method for phase locking is provided, comprising: determining a first phase and a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on the inversion of the sum of the first phase and 180 degrees; and performing phase discrimination on the first phase and the second phase so as to perform phase locking based on the first phase and the second phase.

[0007] In some embodiments, performing phase locking based on a first phase and a second phase includes: generating a delay control signal based on a phase detection result of the first phase and the second phase; adjusting a first delay amount between the first phase and the second phase based on the delay control signal; determining a second delay amount between a 360-degree phase and a 0-degree phase based on the adjusted first delay amount; and performing phase locking for the 360-degree phase and the 0-degree phase.

[0008] In some embodiments, the second delay amount is equal to twice the difference of the first delay amount minus π.

[0009] In some embodiments, the delay control signal is any one of the following: a voltage signal, a duty cycle signal, a digital code signal.

[0010] In some embodiments, the method according to the first aspect of the present invention further comprises: performing secondary phase detection on a 0 degree phase and a 360 degree phase to calibrate the second delay amount.

[0011] According to a second aspect of the present invention, a method for controlling a delay locked loop circuit is provided, comprising: receiving a first input signal and a second signal by a phase detector, the first input signal having a first phase, and the second input signal having a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on negating the sum of the first phase and 180 degrees; performing phase detection on the first phase and the second phase by the phase detector, and obtaining a first phase detection result; in response to obtaining the first phase detection result, generating a delay control signal by a digital control module, and transmitting the delay control signal to a delay module, so as to adjust the delay amount between phases in the delay module, so as to perform phase locking based on the delay amount.

[0012] In some embodiments, adjusting the delay amount between phases in a delay module so as to perform phase locking based on the delay amount includes: adjusting, by the delay module, a first delay amount between a first phase and a second phase based on a delay control signal; and determining, by the delay module, a second delay amount between a 360-degree phase and a 0-degree phase based on the adjusted first delay amount so as to lock the 0-degree phase and the 360-degree phase.

[0013] In some embodiments, locking the 0 degree phase and the 360 ​​degree phase further includes: receiving a third input signal and a fourth input signal by a phase detector, the third input signal has a 0 degree phase, and the fourth input signal has a 360 degree phase; performing phase detection on the 0 degree phase and the 360 ​​degree phase by the phase detector, and obtaining a second phase detection result; calibrating the second delay amount based on the second phase detection result by the delay module; and locking the 0 degree phase and the 360 ​​degree phase based on the calibrated second delay amount.

[0014] According to a third aspect of the present invention, there is provided a computing device comprising: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so that the at least one processor can execute the method of the second aspect of the present invention.

[0015] According to a fourth aspect of the present invention, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method of the second aspect of the present invention.

[0016] According to a fifth aspect of the present invention, there is provided a computer program product, wherein the computer program product is tangibly stored on a non-transitory computer readable medium and comprises machine executable instructions which, when executed, cause a machine to perform the steps in the method of the second aspect of the present invention.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features, advantages and aspects of the embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0019] Figure 1 The structural diagram of a delay locked loop circuit is exemplarily shown.

[0020] Figure 2A A schematic diagram showing the principle of normal locking is shown.

[0021] Figure 2B A schematic diagram showing the principle of loss of lock is shown.

[0022] Figure 2C A schematic diagram showing the principle of harmonic locking is shown.

[0023] Figure 3 A flow chart of a method for phase locking according to an embodiment of the present invention is shown.

[0024] Figure 4 A flow chart of a method for controlling a delay locked loop circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0026] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0027] Delay Loop Lock (DLL) circuits are increasingly used in system-on-chip (SoC) designs to generate multiple clock signals with precise phase relationships because they can be used to generate output signals with precise phase relationships.

[0028] Common delay phase-locked loop circuits mainly include: delay module, phase detector and digital control module. Figure 1 The structure diagram of the delay locked loop circuit 100 is exemplarily shown.

[0029] like Figure 1 As shown, the delay locked loop circuit 100 includes: a phase detector 110 , a digital control module 120 and a delay module 130 .

[0030] Regarding the phase detector 110, it can be configured to compare the phases of the signals (such as clock signals) input therein (also called "phase detection"). For example, two different clock signals can be transmitted to the phase detector 110 for comparison to determine whether the phase difference between the phases corresponding to the two clock signals respectively conforms to the specific phase relationship between the two clock signals.

[0031] Regarding the delay module 130, it may include at least one delay element so that a signal transmitted thereto (such as an input clock signal) can reach an output terminal after a predetermined time, and output an output clock signal having a specific phase relationship with the input clock signal. In some embodiments, the delay module 130 may output a plurality of output clock signals having different phases.

[0032] The digital control module 120 may be configured to generate a delay control signal for controlling the delay module 130 , for example, to adjust the delay between the input clock signal and the output clock signal of the delay module 130 so as to perform phase locking based on the adjusted delay.

[0033] Generally, the working principle of the delay locked loop circuit 100 includes: the phase detector 110 performs phase detection on the phase of the signal input therein, and the digital control module 120 generates a delay control signal for the delay module 130 based on the phase detection result to adjust the delay amount between the phases in the delay module 130 and perform phase locking.

[0034] In the existing related technologies, generally speaking, phase discrimination is performed only for the 0-degree phase and the 360-degree phase, and phase locking is performed only based on the phase discrimination result between the 0-degree phase and the 360-degree phase. Figure 1 In the delay locked loop circuit 100 shown, only the output clock signal with a 0-degree phase and the output clock signal with a 360-degree phase are transmitted to the phase detector 110, so that the phase detector 110 performs phase detection for the 0-degree phase (phase_0) and the 360-degree phase (phase_360). In response to the phase detection result obtained by the phase detector 110, the digital control module 120 generates a delay control signal and sends the generated delay control signal to the delay module 130, so that the delay module 130 can calibrate the phase relationship between the 0-degree phase and the 360-degree phase, and on this basis, lock the 0-degree phase and the 360-degree phase, thereby achieving phase locking. Further, the phase between the 0-degree phase and the 360-degree phase can be equally divided to achieve multi-phase signal output of the delay locked loop circuit 100.

[0035] As can be seen from the above, the existing solutions for phase locking may include: directly performing phase discrimination, phase difference calibration and phase locking on the 0-degree phase and the 360-degree phase.

[0036] However, considering that the phase detection range of the phase detector is only 2π, the normal phase locking can be achieved only when the phase difference between the 360-degree phase and the 0-degree phase falls within the phase detection range of the phase detector. Figure 2A A schematic diagram showing the principle of normal locking is shown.

[0037] like Figure 2A As shown, since the phase detection range of the phase detector is 2π, when the phase difference between the 360-degree phase and the 0-degree phase falls within the phase detection range of the phase detector, that is, when the phase difference between the 360-degree phase and the 0-degree phase is between π and 3π, the first rising edge of the 360-degree phase can be moved to the second rising edge of the 0-degree phase so that the first rising edge of the 360-degree phase is aligned with the second rising edge of the 0-degree phase, so as to achieve normal locking of the 360-degree phase and the 0-degree phase. Therefore, when the amplitude of the 0-degree phase corresponding to the first rising edge of the 360-degree phase is 0, the 360-degree phase will be adjusted to move to the right until the first rising edge of the 360-degree phase is aligned with the second rising edge of the 0-degree phase; similarly, until the first rising edge of the 360-degree phase is aligned with the second rising edge of the 0-degree phase.

[0038] In some cases, due to the influence of process, voltage and temperature, the phase difference between the 360-degree phase and the 0-degree phase may not fall within the phase detection range of the phase detector, which can easily cause abnormal locking between phases. Abnormal locking can be divided into: false lock and harmonic lock. Figure 2B and Figure 2C Describe the principles of loss of lock and harmonic lock.

[0039] Figure 2B The schematic diagram of the principle of loss of lock is shown; Figure 2C A schematic diagram showing the principle of harmonic locking is shown.

[0040] As described above, when the amplitude of the 0-degree phase corresponding to the first rising edge of the 360-degree phase is 1, the 360-degree phase will be adjusted to move to the left. Figure 2B In the case shown, when the phase difference between the 360-degree phase and the 0-degree phase is between 0 and π, the 360-degree phase will be adjusted to move to the left so that the first rising edge of the 360-degree phase is aligned with the first rising edge of the 0-degree phase. This situation is called "loss of lock".

[0041] Similarly, when the amplitude of the 0-degree phase corresponding to the first rising edge of the 360-degree phase is 0, the 360-degree phase will be adjusted to move to the right. Figure 2C In the case shown, when the phase difference between the 360-degree phase and the 0-degree phase is between 3π and 4π, the 360-degree phase will be adjusted to move to the right so that the first rising edge of the 360-degree phase is aligned with the third rising edge of the 0-degree phase. This situation is called "harmonic locking".

[0042] In summary, the existing solutions for phase locking perform phase locking based only on the phase detection results of the 0-degree phase and the 360-degree phase, which easily causes abnormal locking phenomena such as loss of lock and harmonic lock.

[0043] In order to at least partially solve one or more of the above problems and other potential problems, an exemplary embodiment of the present invention proposes a scheme for phase locking. In this scheme, by determining a first phase and a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on the inversion of the sum of the first phase and 180 degrees; and performing phase discrimination on the first phase and the second phase, so as to perform phase locking based on the first phase and the second phase, the possibility of loss of lock or harmonic lock occurring can be significantly reduced.

[0044] The following will be combined Figure 3 to Figure 4A scheme for phase locking according to an embodiment of the present invention is described in detail.

[0045] Figure 3 FIG. 3 is a flow chart of a method 300 for phase locking according to an embodiment of the present invention. The method 300 may be performed as follows: Figure 1 The delay locked loop circuit 100 shown in the figure performs. It should be understood that the method 300 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0046] In step 302 , the DLL circuit 100 determines a first phase and a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on negating the sum of the first phase and 180 degrees.

[0047] According to an embodiment of the present invention, the first phase may be determined by a phase detector 110 such as a delay locked loop circuit 100, and the first phase is greater than or equal to 0 degrees and less than 180 degrees. For example, the first phase is determined by a phase detector 110 such as a delay locked loop circuit 100 to be x degrees, where 0≤x<180. Here, the first phase may be recorded as phase_x.

[0048] According to an embodiment of the present invention, a phase detector 110 such as a delay locked loop circuit 100 can then determine a second phase based on the first phase. Specifically, the sum of the first phase and 180 degrees can be negated to determine the second phase. Taking the first phase phase_x as x degrees as an example, the second phase can be recorded as:

[0049] In step 304 , the delay locked loop circuit 100 performs phase discrimination on the first phase and the second phase, so as to perform phase locking based on the first phase and the second phase.

[0050] According to an embodiment of the present invention, a phase detector 110 such as a delay locked loop circuit 100 may perform phase detection on the first phase and the second phase determined in step 302. For example, the phase detector 110 may detect the first phase phase_x and the second phase Perform phase detection.

[0051] In this case, assume that the delay between the 0-degree phase and the 360-degree phase is T d1 , then the first phase phase_x and the second phase The delay between d2 ) is 1 / 2*T d1 As mentioned above, in order to achieve normal locking, the phase difference between the two phases detected by the phase detector 110 should be between π and 3π, that is, the first phase phase_x and the second phase The delay between 1 / 2*T d1 +π must satisfy the following formula:

[0052] π<1 / 2*T d1 +π<3π

[0053] From this we can infer that:

[0054] 0 <T d1 <4π

[0055] That is to say, based on the implementation scheme of the present invention, as long as the phase difference between the 360-degree phase and the 0-degree phase is between 0 and 4π, normal phase locking can be achieved.

[0056] In summary, according to the scheme for phase locking of the present invention, by performing phase detection on a first phase greater than or equal to 0 degrees and less than 180 degrees and a second phase determined based on the inversion of the sum of the first phase and 180 degrees, it is possible to phase lock a 360-degree phase with a phase difference between 0 and 4π with a 0-degree phase, thereby significantly expanding the phase detection range of the phase detector.

[0057] Regarding the phase locking based on the first phase and the second phase, according to an embodiment of the present invention, it may further include: based on the phase discrimination result of the first phase and the second phase, the digital control module 120 generates a delay control signal, and transmits the delay control signal to the delay module 130 to adjust the delay amount between the phases in the delay module 130, so as to perform phase locking based on the delay amount. Specifically, the delay module 130 may adjust the first delay amount between the first phase and the second phase based on the delay control signal; determine the second delay amount between the 360-degree phase and the 0-degree phase based on the adjusted first delay amount; and perform phase locking for the 360-degree phase and the 0-degree phase.

[0058] Regarding the delay control signal, it may be a voltage signal, a duty cycle signal or a digital code signal. According to an embodiment of the present invention, the adjustment of the phase relationship in the delay module 130 may be controlled by the delay control signal.

[0059] Regarding the first delay amount, taking the above embodiment as an example, it can be the first phase phase_x and the second phase The delay between d2 .

[0060] According to an embodiment of the present invention, the first delay amount can be changed according to the delay control signal. For example, if the delay control signal is a voltage signal, the delay module 130 can adjust the voltage based on the received voltage signal to adjust the first delay amount. Thus, the first phase phase_x and the second phase can be adjusted. The phase relationship between them can be adjusted, and the first phase phase_x and the second phase can be locked on a secondary basis.

[0061]

[0062] The second delay amount may refer to the delay amount between the 0 degree phase and the 360 ​​degree phase as T d1 .

[0063] As mentioned above, since the delay between the 0-degree phase and the 360-degree phase is T d1 The first phase phase_x and the second phase The delay between d2 With the following relationship: T d2 =1 / 2*T d1 +π, that is, T d1 =2*(T d2 -π). Therefore, the second delay amount between the 0-degree phase and the 360-degree phase can be calculated based on the first delay amount between the adjusted first phase and the second phase. Similarly, the second delay amount between the 0-degree phase and the 360-degree phase can be adjusted by adjusting the voltage, and on this basis, phase locking for the 0-degree phase and the 360-degree phase can be performed.

[0064] In summary, the present invention can first determine the delay between the first phase and the second phase by performing phase detection on a first phase greater than or equal to 0 degrees and less than 180 degrees and a second phase determined based on the inversion of the sum of the first phase and 180 degrees, and on this basis, further determine the delay between the 0 degree phase and the 360 ​​degree phase, so that for a 360 degree phase and a 0 degree phase with a phase difference between 0 and 4π, normal locking of the 0 degree phase and the 360 ​​degree phase can be achieved, which significantly reduces the possibility of loss of lock or harmonic locking.

[0065] According to the inventive concept of the present invention, since the delay amount between phases may be affected by factors such as process, voltage and temperature, in order to more accurately lock the 0-degree phase and the 360-degree phase, a phase detector may be used to perform secondary phase detection on the 0-degree phase and the 360-degree phase to calibrate the second delay amount between the 0-degree phase and the 360-degree phase determined by the previous step.

[0066] Specifically, according to an embodiment of the present invention, the method 300 may further include: performing secondary phase discrimination on the 0 degree phase and the 360 ​​degree phase, so as to calibrate a second delay amount (not shown) between the 360 ​​degree phase and the 0 degree phase.

[0067] For example, in response to determining a second delay amount between a 360-degree phase and a 0-degree phase based on the adjusted first delay amount, a phase detector 110 such as a delay-locked loop circuit 100 may perform secondary phase detection on the 0-degree phase and the 360-degree phase to calibrate the second delay amount between the 0-degree phase and the 360-degree phase, thereby enabling the 0-degree phase and the 360-degree phase to be locked more accurately.

[0068] In summary, the phase locking scheme provided by the present invention can improve the tolerance to deviations caused by factors such as process, voltage and temperature through secondary phase detection, achieve more accurate phase locking, and effectively avoid the occurrence of abnormal locking such as loss of lock or harmonic locking.

[0069] According to the inventive concept of the present invention, a scheme for controlling a delay locked loop circuit is also provided, so that the delay locked loop circuit can achieve phase locking according to the above-mentioned scheme for phase locking. Figure 1 and Figure 4 The invention provides a method for controlling a delay locked loop circuit.

[0070] Figure 4 FIG. 4 is a flow chart of a method 400 for controlling a delay locked loop circuit 100 according to an embodiment of the present invention. The method 400 may be performed as follows: Figure 1 The delay locked loop circuit 100 shown in the figure performs. It should be understood that the method 400 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0071] In step 401, the phase detector 110 of the delay locked loop circuit 100 receives a first input signal and a second input signal, wherein the first input signal has a first phase and the second input signal has a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on negating the sum of the first phase and 180 degrees.

[0072] For example, in some embodiments, the phase detector 110 of the phase-locked loop circuit 100 may receive a first signal and a second signal, wherein the first signal has a first phase phase_x (0≤x<180), and the second signal has a second phase Taking x=0 as an example, the phase detector 110 of the phase-locked loop circuit 100 may receive a first signal with a phase of 0 degrees and a second signal with a phase of 180 degrees.

[0073] In step 402, the phase detector 110 of the delay locked loop circuit 100 performs phase detection on the first phase and the second phase, and obtains a first phase detection result.

[0074] The first phase discrimination result refers to the result obtained by performing phase discrimination on the first phase and the second phase. According to an embodiment of the present invention, the first phase discrimination result may include information related to the phase difference between the first phase and the second phase, so that the positional relationship between the first phase and the second phase can be adjusted based on the information.

[0075] For example, in some embodiments, the phase detector 110 of the phase-locked loop circuit 100 can be used to detect the first phase phase_x and the second phase Phase discrimination is performed to obtain the first phase phase_x and the second phase The phase detection result is obtained, and the first phase phase_x and the second phase can be adjusted based on the phase detection result. Taking the above example of x=0 as an example, the phase detector 110 of the phase-locked loop circuit 100 can perform phase detection on the 0-degree phase and the 180-degree phase to obtain a phase detection result on the 0-degree phase and the 180-degree phase, and the phase detection result can include information related to the phase difference between the 0-degree phase and the 180-degree phase.

[0076] In step 403 , in response to obtaining the first phase detection result, the digital control module 120 of the delay locked loop circuit 100 generates a delay control signal and transmits the delay control signal to the delay module 130 of the delay locked loop circuit 100 .

[0077] As for the delay control signal, as mentioned above, it can be a voltage signal, a duty cycle signal or a digital code signal, etc., and the present invention is not limited to this.

[0078] In step 404 , the delay module 130 of the DLL circuit 100 adjusts a first delay amount between the first phase and the second phase based on the delay control signal.

[0079] Specifically, in some embodiments, based on the phase discrimination result about the first phase and the second phase obtained in step 402, the digital control module 120 of the phase-locked loop circuit 100 can generate a voltage signal such as a voltage signal that can be used for delay control, and transmit the voltage signal to the delay module 130 of the delay phase-locked loop circuit 100, so that the delay module 130 can then adjust the first phase phase_x and the second phase based on the voltage signal. The first delay between the first phase phase_x and the second phase The phase relationship between them.

[0080] Taking the above example of x=0 as an example, the first delay amount between the 0-degree phase and the 180-degree phase can be reduced by increasing the voltage, that is, the first rising edge of the 180-degree phase moves toward the direction close to the first rising edge of the 0-degree phase, so that the phase difference between the 0-degree phase and the 180-degree phase becomes smaller. Correspondingly, the first delay amount between the 0-degree phase and the 180-degree phase can be increased by decreasing the voltage, that is, the first rising edge of the 180-degree phase moves toward the direction away from the first rising edge of the 0-degree phase, so that the phase difference between the 0-degree phase and the 180-degree phase becomes larger. In some other embodiments, the first delay amount between the 0-degree phase and the 180-degree phase can also be changed by code.

[0081] In some embodiments, in response to adjusting the first delay amount between the first phase and the second phase, the phase-locked loop circuit 100 can be controlled to lock the first phase and the second phase. For example, the phase-locked loop circuit 100 can be controlled to lock the 0 degree phase and the 180 degree phase between which the first delay amount is adjusted.

[0082] In step 405 , the delay module 130 of the delay locked loop circuit 100 determines a second delay amount between the 360 ​​degree phase and the 0 degree phase based on the adjusted first delay amount, so as to lock the 0 degree phase and the 360 ​​degree phase.

[0083] According to an embodiment of the present invention, since the first phase phase_x and the second phase phase_x have been determined according to the above steps, , then the second delay amount between the 0-degree phase and the 360-degree phase can be obtained by referring to the description at the above step 302. On this basis, similar to step 404, the delay module 130 of the delay phase-locked loop circuit 100 can be controlled by adjusting the voltage to adjust the phase relationship between the 0-degree phase and the 360-degree phase, and then the phase-locked loop circuit 100 is controlled to lock the 0-degree phase and the 360-degree phase.

[0084] However, although the phase locking performed through the above steps can calibrate the deviation between the 0-degree phase and the 360-degree phase caused by the influence of process, voltage and temperature, in order to enable the delay locked loop circuit 100 to lock the 0-degree phase and the 360-degree phase more accurately, with respect to locking the 0-degree phase and the 360-degree phase, it can also include: receiving a third input signal and a fourth input signal by the phase detector 110 of the delay locked loop circuit 100, the third input signal has a 0-degree phase, and the fourth input signal has a 360-degree phase; performing phase detection on the 0-degree phase and the 360-degree phase by the phase detector 110 of the delay locked loop circuit 100, and obtaining a second phase detection result; calibrating the second delay amount by the delay module 130 of the delay locked loop circuit 100 based on the second phase detection result; and locking the 0-degree phase and the 360-degree phase based on the calibrated second delay amount.

[0085] That is, in some embodiments of the present invention, the phase detector 110 of the phase-locked loop circuit 100 can also receive a third signal with a 0-degree phase and a fourth signal with a 360-degree phase, and perform phase detection for the 0-degree phase and the 360-degree phase to obtain phase detection results for the 0-degree phase and the 360-degree phase. Then, based on the obtained phase detection results for the 0-degree phase and the 360-degree phase, the digital control module 120 of the phase-locked loop circuit 100 can generate a voltage signal such as one that can be used for delay control, and transmit the voltage signal to the delay module 130 of the delay phase-locked loop circuit 100, so that the delay module 130 can then calibrate the second delay amount between the 0-degree phase and the 360-degree phase based on the voltage signal, so that the phase relationship between the 0-degree phase and the 360-degree phase is more accurate. Thus, not only is it avoided that the delay phase-locked loop circuit 100 loses lock or harmonic locks when the phase is locked for the 0-degree phase and the 360-degree phase, but also the accuracy of the phase locking of the delay phase-locked loop circuit 100 is improved.

[0086] In addition, the various processes and processing described herein, such as method 400, may be performed at a computing device. The computing device includes, for example: at least one processor (at least one graphics processor and at least one central processing unit); and a memory connected to the at least one processor in communication; wherein the memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor. In some embodiments, method 400 may be implemented as a computer software program or program product, which is tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on a computing device via a read-only memory (ROM) and / or a communication unit. When the computer program is loaded into a random access memory (RAM) and executed by a processor, one or more actions of method 400 described above may be performed.

[0087] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions for executing various aspects of the present invention. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0088] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each square frame of the flow chart and / or block diagram and the combination of the square frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0089] These computer-readable program instructions can be provided to a central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the central processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0090] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the function involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0091] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0092] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0093] The above are only optional embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for phase locking, characterized in that: include: Determine a first phase and a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on negating a sum of the first phase and 180 degrees; as well as Phase discrimination is performed on the first phase and the second phase so as to perform phase locking based on the first phase and the second phase.

2. The method according to claim 1, characterized in that: Performing phase locking based on the first phase and the second phase includes: generating a delay control signal based on a phase detection result of the first phase and the second phase; adjusting a first delay amount between the first phase and the second phase based on the delay control signal; determining a second delay amount between a 360-degree phase and a 0-degree phase based on the adjusted first delay amount; and Phase locking is performed for a 360-degree phase and a 0-degree phase.

3. The method according to claim 2, characterized in that The second delay amount is equal to twice the difference of the first delay amount minus π.

4. The method according to claim 2, characterized in that: The delay control signal is any one of the following: a voltage signal, a duty cycle signal, and a digital code signal.

5. The method according to any one of claims 2 to 4, characterized in that: Also includes: Secondary phase detection is performed for a phase of 0 degree and a phase of 360 degrees to calibrate the second delay amount.

6. A method for controlling a delay locked loop circuit, the delay locked loop circuit comprising: A phase detector, a digital control module and a delay module, wherein the method comprises: The phase detector receives a first input signal and a second signal, wherein the first input signal has a first phase and the second input signal has a second phase, wherein the first phase is greater than or equal to 0 degrees and less than 180 degrees, and the second phase is determined based on negating a sum of the first phase and 180 degrees; The phase detector performs phase detection on the first phase and the second phase, and obtains a first phase detection result; In response to obtaining the first phase detection result, the digital control module generates a delay control signal and transmits the delay control signal to the delay module to adjust the delay amount between phases in the delay module so as to perform phase locking based on the delay amount.

7. The method according to claim 6, characterized in that Adjusting the delay amount between phases in the delay module so as to perform phase locking based on the delay amount includes: adjusting, by the delay module, a first delay amount between the first phase and the second phase based on the delay control signal; and The delay module determines a second delay amount between the 360-degree phase and the 0-degree phase based on the adjusted first delay amount, so as to lock the 0-degree phase and the 360-degree phase.

8. The method according to claim 7, characterized in that Locking the 0 degree phase and the 360 ​​degree phase further includes: The phase detector receives a third input signal and a fourth input signal, wherein the third input signal has a phase of 0 degrees and the fourth input signal has a phase of 360 degrees; The phase detector performs phase detection on a 0-degree phase and a 360-degree phase, and obtains a second phase detection result; Calibrate the second delay amount by the delay module based on the second phase detection result; and Based on the calibrated second delay amount, the 0 degree phase and the 360 ​​degree phase are locked.

9. A computing device, characterized in that include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 6 to 8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 6 to 8.

11. A computer program product, characterized in that The computer program product is tangibly stored on a non-transitory computer readable medium and comprises machine executable instructions which, when executed, cause a machine to perform the steps of the method according to any one of claims 6-8.

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