A high-speed and high-precision capacitor array for ADC

Abstract

The present invention discloses a high-speed and high-precision capacitor array applied to ADC, belonging to the field of capacitor technology of ADC, wherein the capacitor array is composed of a plurality of unit capacitors arranged in a regular pattern and side shielding capacitors added on both sides; wherein the capacitor array is a multi-row structure, the leftmost of each row is a side shielding capacitor, as the 0th capacitor, and the 1st to the jth are unit capacitors; the left top plate metal of the unit capacitor is connected and overlapped with the right top plate metal of the 0th capacitor; the right top plate metal of the first unit capacitor overlaps with the left top metal of the adjacent next unit capacitor; the j+1th is a side shielding capacitor flipped left and right. The present invention optimizes the arrangement of capacitor units, side shielding capacitors and capacitor arrays, reduces the parasitics of the capacitor top plate and the capacitor bottom plate, and improves the matching degree of the ADC, and is particularly suitable for high-speed and high-precision ADCs under advanced processes.

Description

Technical Field

[0001] The present invention belongs to the technical field of capacitors of ADC, and in particular relates to a high-speed and high-precision capacitor array applied to ADC. Background Art

[0002] ADC, as an analog-to-digital converter, connects analog signals and digital systems and is a key module in the system. As the core module of ADC, the capacitor array determines the accuracy of ADC. For example, in SAR ADC (successive approximation analog-to-digital converter), the accuracy of DAC forming a binary capacitor array directly determines the accuracy of ADC, especially DNL (differential nonlinearity) and INL (integral nonlinearity) performance. The parasitics of the top or bottom plates of traditional capacitor arrays are large, resulting in slower speed. At this resolution in 12-bit SAR ADC, a good capacitor array design can achieve good performance without relying on calibration, avoiding additional design complexity caused by calibration. Figure 1 For a traditional capacitor unit, after the metal layer of the capacitor is increased, only different metal layers of the same pattern are added. After forming a capacitor array, the parasitics on the bottom plate and the side wall are relatively large, which reduces the matching of the capacitor. Summary of the invention

[0003] The purpose of the present invention is to provide a high-speed and high-precision capacitor array for ADC, which can improve the ADC speed and reduce the parasitic capacitance to increase the speed by optimizing the pattern of unit capacitors and the arrangement of the capacitor array, and can effectively solve the problems raised in the above-mentioned background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions: a high-speed and high-precision capacitor array applied to ADC, the capacitor array is composed of a plurality of unit capacitors arranged in a regular pattern and side shielding capacitors added on both sides;

[0005] Among them, the capacitor array is a multi-row structure, the leftmost of each row is a side shielding capacitor, which is the 0th capacitor, and the 1st to jth are unit capacitors; the left top plate metal of the unit capacitor is connected and overlapped with the right top plate metal of the 0th capacitor; the right top plate metal of the first unit capacitor overlaps with the right top metal of the adjacent next unit capacitor; the j+1th is a side shielding capacitor flipped left and right, and the left top plate capacitor of the flipped side shielding capacitor overlaps with the right top plate metal of the jth unit capacitor;

[0006] The capacitor array is arranged in k+2 rows, with a spacing between two adjacent rows. The 0th row is used as an upper shielding capacitor, and the k+1th row is used as a lower shielding capacitor, thereby obtaining a capacitor array with k rows and j columns.

[0007] Preferably, the capacitor array connects the x+n layer metal lines of all the capacitors in all j columns from north to south and connects them northward, and then connects the j+1 northernmost top-level metal lines in the area without capacitors on the northernmost side with the x+n layer metal from east to west, as a common top plate connection VTOP for the capacitor array.

[0008] Preferably, the unit capacitor in the capacitor array has x+n layers of metal, including:

[0009] The xth layer is the two metal traces of the bottom plate, with the traces running north-south. There are two x-layer metal traces side by side, and only one of them has an upward through hole;

[0010] The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The central part of the layer has upward through holes.

[0011] The x+2 layer has a north-south routing in the middle with an upward through hole, and east-west comb metals are distributed on the left and right sides. Half of the comb metals are connected to the bottom plate capacitor in the middle, and the other half are connected to the top plate capacitors on both sides. The number of comb metals is an odd number, and the top and bottom comb metals on both sides are connected to the bottom plate of the capacitor. The top plate metal layer of the capacitor runs north-south and does not overlap with the x+1 layer.

[0012] The x+3 layer and the x+n-1 layer upwards can stack the same metal pattern as the x+2 layer to increase the capacitance value of the unit capacitor;

[0013] The x+nth layer is the level of the top plate routing. The top plate of the unit capacitor is routed from the north and south on both sides of the capacitor unit to other unit capacitors, connecting the top plates of the capacitor array. The position of the x+nth layer is the same as the top plate routing on both sides, and the width also overlaps with part of the top plate capacitor.

[0014] Preferably, the side shielding capacitor in the capacitor array has x+n layers of metal, including:

[0015] The xth layer is a metal trace of the bottom plate, with a north-south direction, and may or may not have an upward through hole depending on the position of the side shielding capacitor in the capacitor array;

[0016] The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The left part of the layer has upward through holes.

[0017] The left side of the x+2 layer is a north-south routing with an upward through hole, which is used as the metal for the bottom plate connection, and the right side is a north-south routing with an upward through hole, which is used as the top plate routing; y parallel east-west floating metal lines are distributed in the middle of the bottom plate routing and the top plate routing, and the line width and line spacing of the metal line are the same as the comb metal of the capacitor unit; the east-west comb metal is distributed on both the left and right sides, and half of the comb metal is connected to the bottom plate capacitor in the middle, and these floating metal lines are neither connected to the bottom plate routing on the left nor to the bottom plate routing on the right;

[0018] The x+3 layer and the x+n-1 layer above it are stacked with the same metal pattern as the x+2 layer;

[0019] The x+nth layer is the layer of the top plate routing. The top plate runs from the north-south route on the right side of the capacitor unit and is connected to other unit capacitors. According to the position of the side shielding capacitor in the capacitor array, the top plate connection of the x+nth layer can also be connected only to the position of the aforementioned side shielding capacitor without being connected to other capacitors. The position of the x+nth layer is the same as the top plate routing on the right side, and the width also overlaps with part of the top plate capacitor.

[0020] Preferably, the capacitor array is arranged in a capacitor array of k rows and j columns based on the principle of symmetry of the same capacitor center.

[0021] Preferably, when there are more than 2 different capacitors in each row of the capacitor array, the x-layer bottom plate metal of the unit capacitor is increased from 2 to 4 or more, while maintaining left-right symmetry and an even number, and the x-layer bottom plate metal is within the coverage of the x+1-layer shielding metal;

[0022] The x-th layer of metal is connected to the unit capacitor through selective upward vias and then leads out from the southernmost side;

[0023] The x-layer metal on the far left and far right is connected to the Vd port through upward vias and leads out at the southernmost end;

[0024] The two shielding capacitor rows in row 0 and row k+1 are also connected to the Vd port through the x-layer metal and are routed out at the southernmost end;

[0025] The unused portion of the capacitor array in row k and column j is used as redundant capacitor and is also connected to the Vd port through metal at the southernmost outlet.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention reduces the parasitics of the capacitor top plate and the capacitor bottom plate and improves the matching degree of ADC by optimizing the arrangement of the capacitor unit, the side shielding capacitor and the capacitor array, and is particularly suitable for high-speed and high-precision ADC under advanced technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the capacitor metal layer of a traditional capacitor unit.

[0029] Figure 2 The diagram is a capacitor layering diagram of a high-speed and high-precision capacitor array applied to ADC according to the present invention.

[0030] Figure 3 The figure is a schematic diagram of a 4-bit capacitor array of a high-speed and high-precision capacitor array applied to ADC according to the present invention. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] like Figure 2-3 As shown, this embodiment provides a high-speed and high-precision capacitor array applied to ADC, the capacitor array is composed of a plurality of unit capacitors arranged in a regular pattern and side shielding capacitors added on both sides;

[0033] Among them, the capacitor array is a multi-row structure, the leftmost of each row is a side shielding capacitor, which is the 0th capacitor, and the 1st to jth are unit capacitors; the left top plate metal of the unit capacitor is connected and overlapped with the right top plate metal of the 0th capacitor; the right top plate metal of the first unit capacitor overlaps with the left top metal of the adjacent next unit capacitor; the j+1th is a side shielding capacitor flipped left and right, and the left top plate capacitor of the flipped side shielding capacitor overlaps with the right top plate metal of the jth unit capacitor;

[0034] The capacitor array is arranged in k+2 rows, with a spacing between two adjacent rows. The 0th row is used as the upper shielding capacitor, and the k+1th row is used as the lower shielding capacitor, thereby obtaining a capacitor array with k rows and j columns.

[0035] In this embodiment, the capacitor array connects the x+n layer metal connection lines of all the capacitors in all j columns northward and upward, and then connects the j+1 northernmost top metal connection lines with the x+n layer metal east-west at the northernmost side without capacitors, as the common top plate connection VTOP of the capacitor array;

[0036] In this embodiment, the unit capacitor in the capacitor array has x+n layers of metal, including:

[0037] The xth layer is the two metal traces of the bottom plate, with the traces running north-south. There are two x-layer metal traces side by side, and only one of them has an upward through hole;

[0038] The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The central part of the layer has upward through holes.

[0039] The x+2 layer has a north-south routing in the middle with an upward through hole, and east-west comb metals are distributed on the left and right sides. Half of the comb metals are connected to the bottom plate capacitor in the middle, and the other half are connected to the top plate capacitors on both sides. The number of comb metals is an odd number, and the top and bottom comb metals on both sides are connected to the bottom plate of the capacitor. The top plate metal layer of the capacitor runs north-south and does not overlap with the x+1 layer.

[0040] The x+3 layer and the x+n-1 layer upwards can stack the same metal pattern as the x+2 layer to increase the capacitance value of the unit capacitor;

[0041] The x+nth layer is the level of the top plate routing. The top plate of the unit capacitor is routed from the north and south on both sides of the capacitor unit to other unit capacitors, connecting the top plates of the capacitor array. The position of the x+nth layer is the same as the top plate routing on both sides, and the width also overlaps with part of the top plate capacitor.

[0042] In this embodiment, the side shielding capacitor in the capacitor array has x+n layers of metal, including:

[0043] The xth layer is a metal trace of the bottom plate, with a north-south direction, and may or may not have an upward through hole depending on the position of the side shielding capacitor in the capacitor array;

[0044] The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The left part of the layer has upward through holes.

[0045] The left side of the x+2 layer is a north-south routing with an upward through hole, which is used as the metal for the bottom plate connection, and the right side is a north-south routing with an upward through hole, which is used as the top plate routing; y parallel east-west floating metal lines are distributed in the middle of the bottom plate routing and the top plate routing, and the line width and line spacing of the metal line are the same as the comb metal of the capacitor unit; the east-west comb metal is distributed on both the left and right sides, and half of the comb metal is connected to the bottom plate capacitor in the middle, and these floating metal lines are neither connected to the bottom plate routing on the left nor to the bottom plate routing on the right;

[0046] The x+3 layer and the x+n-1 layer above it are stacked with the same metal pattern as the x+2 layer;

[0047] The x+nth layer is the layer of the top plate routing. The top plate runs from the north-south route on the right side of the capacitor unit and is connected to other unit capacitors. Depending on the position of the redundant capacitor in the capacitor array, the top plate connection of the x+nth layer can also be connected only to the position of the aforementioned redundant capacitor without being connected to other capacitors. The position of the x+nth layer is the same as the top plate routing on the right side, and the width also overlaps with part of the top plate capacitor.

[0048] In this embodiment, the capacitor array is arranged in a capacitor array of k rows and j columns based on the principle of symmetry of the same capacitor center.

[0049] In this embodiment, when the number of different capacitors in each row of the capacitor array exceeds 2, the x-layer bottom plate metal of the unit capacitor is increased from 2 to 4 or more, while maintaining left-right symmetry and an even number, and the x-layer bottom plate metal is within the coverage of the x+1-layer shielding metal;

[0050] The x-th layer of metal is connected to the unit capacitor through selective upward vias and then leads out from the southernmost side;

[0051] The x-layer metal on the far left and far right is connected to the Vd port through upward vias and leads out at the southernmost end;

[0052] The two shielding capacitor rows in row 0 and row k+1 are also connected to the Vd port through the x-layer metal and are routed out at the southernmost end;

[0053] The unused portion of the capacitor array in row k and column j is used as redundant capacitor and is also connected to the Vd port through metal at the southernmost outlet.

[0054] like Figure 3For capacitor arrays, take a 4-bit binary capacitor array as an example. Capacitors C4, C3, C2, and C1 correspond to 8, 4, 2, and 1, respectively. The number of Cd is the number of unit capacitors remaining in the capacitor array layout. The top plates of the capacitors are statistically connected to VTOP, and the bottom plates of the capacitors are connected to V4, V3, V2, V1, and Vd, respectively. The leftmost side shielding capacitor in each row is called the 0th capacitor. From the 1st to the 5th are unit capacitors. The left top plate metal of the unit capacitor overlaps with the right top plate metal connection of the 0th capacitor. The rightmost top plate metal of the 1st overlaps with the top metal of the 2nd unit capacitor, and so on. The 5+1st is a side shielding capacitor that is flipped left and right, so the left top plate capacitor of the flipped side shielding capacitor overlaps with the right top plate metal of the 5th unit capacitor. Arrange the same number of rows in 4+2 rows, with a certain spacing between each row. The 0th row is used as the upper shielding capacitor, and the 4th+1st row is used as the lower shielding capacitor, to obtain a 4-row 5-column capacitor array. Connect the x+n-layer metal lines of all the capacitors in all 4 columns from north to south and connect them northward. Then, in the northernmost area without capacitors, connect the 5+1 northernmost top metal lines with the x+n-layer metal from east to west, as the common top plate of the capacitor array to connect VTOP. The capacitor array is arranged in a 4-row 5-column capacitor array based on the principle of central symmetry on the basis of keeping the same capacitor in the same column as much as possible. The x-layer metal is connected to the unit capacitor through a selective upward through hole, and then the line is connected from the southernmost side. The x-layer metal on the left and right is connected to the Vd port through the upward through hole and appears at the southernmost side. The two edge shielding capacitor rows of row 0 and row 4+1 are also connected to the Vd port through the x-layer metal and appear at the southernmost side. The unused part of the 4-row 5-column capacitor array is also connected to the Vd port through metal and appears at the southernmost side. C1 is placed in the 2nd row and 3rd column, located in the center of the capacitor array. Its bottom plate capacitor is punched upward at the position of the C1 capacitor through the x-layer metal on the left, and then the line is led out from the southernmost side. The port is VC1. C1 is placed in the 2nd row of the 3rd column, located in the center of the capacitor array. Its bottom plate capacitor is punched upward at the position of the C1 capacitor through the x-layer metal on the left, and then the line is led out from the southernmost side. The port is VC1. The other capacitors in the 3rd column are connected to the bottom plate by punching upward from the x-layer metal on the right, and then the line is led out from the southernmost side. The port is Vd. C2 is placed in the 2nd and 3rd rows of the 4th column, located on the right side of the C1 capacitor. Its bottom plate capacitor is punched upward at the position of the C2 capacitor through the x-layer metal on the left, and then the line is led out from the southernmost side. The port is VC2. The other capacitors in the 4th column are connected to the bottom plate by punching upward from the x-layer metal on the right, and then the line is led out from the southernmost side. The port is Vd.

[0055] C3 is placed from the 1st row to the 4th row of the 5th column. Its bottom plate capacitor is punched upward at the position of the C3 capacitor through the x-layer metal on the left, and then the wire is led out from the southernmost side, with the port being VC3. The other capacitors in the 5th column are connected to the bottom plate by punching upward from the x-layer metal on the right, and then the wire is led out from the southernmost side, with the port being Vd. C4 is placed from the 1st row to the 4th row of the 1st column and from the 1st row to the 4th row of the 5th column. Its bottom plate capacitor is punched upward at the position of the C4 capacitor through the x-layer metal on the left, and then the wire is led out from the southernmost side, with the port being VC4. The other capacitors in the 6th column are connected to the bottom plate by punching upward from the x-layer metal on the right, and then the wire is led out from the southernmost side, with the port being Vd.

[0056] The present invention reduces the parasitics of the capacitor top plate and the capacitor bottom plate and improves the matching degree of ADC by optimizing the arrangement of the capacitor unit, the side shielding capacitor and the capacitor array, and is particularly suitable for high-speed and high-precision ADC under advanced technology.

[0057] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0058] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high-speed and high-precision capacitor array applied to ADC, characterized in that: The capacitor array is composed of a plurality of unit capacitors arranged in a regular pattern and side shielding capacitors added on both sides; Among them, the capacitor array is a multi-row structure, the leftmost of each row is a side shielding capacitor, which is the 0th capacitor, and the 1st to jth are unit capacitors; the left top plate metal of the unit capacitor is connected and overlapped with the right top plate metal of the 0th capacitor; the right top plate metal of the first unit capacitor overlaps with the left top metal of the adjacent next unit capacitor; the j+1th is a side shielding capacitor flipped left and right, and the left top plate capacitor of the flipped side shielding capacitor overlaps with the right top plate metal of the jth unit capacitor; The capacitor array is arranged in k+2 rows, with a spacing between two adjacent rows, the 0th row is used as the upper shielding capacitor, and the k+1th row is used as the lower shielding capacitor, thereby obtaining a capacitor array with k rows and j columns; The capacitor array connects the x+n layer metal connections of all the unit capacitors in all j columns north-south and north-up, and then connects the j+1 northernmost top metal connections with the x+n layer metal east-west at the northernmost point where there is no capacitor, as the common top plate of the capacitor array connected to VTOP; The unit capacitor in the capacitor array has x+n layers of metal, including: The xth layer is the two metal traces of the bottom plate, with the traces running north-south. There are two x-layer metal traces side by side, and only one of them has an upward through hole; The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The central part of the layer has upward through holes. The x+2 layer has a north-south routing in the middle with an upward through hole, and east-west comb metals are distributed on the left and right sides. Half of the comb metals are connected to the bottom plate capacitor in the middle, and the other half are connected to the top plate capacitors on both sides. The number of comb metals is an odd number, and the top and bottom comb metals on both sides are connected to the bottom plate of the capacitor. The top plate metal layer of the capacitor runs north-south and does not overlap with the x+1 layer. The x+3 layer and the x+n-1 layer above are stacked with the same metal pattern as the x+2 layer to increase the capacitance value of the unit capacitor; The x+nth layer is the layer of the top plate routing. The top plate of the unit capacitor is routed from north to south on both sides of the capacitor unit, connected to other unit capacitors, and the top plate of the capacitor array is connected. The position of the x+nth layer is the same as the top plate routing on both sides, and the width also overlaps with part of the top plate capacitor. The side shielding capacitor in the capacitor array also has x+n layers of metal, including: The xth layer is a metal trace of the bottom plate, with a north-south direction, and may or may not have an upward through hole depending on the position of the side shielding capacitor in the capacitor array; The x+1th layer is the shielding metal layer of the bottom plate, which is a rectangle covering the x-layer metal. The left part of the layer has upward through holes. The left side of the x+2 layer is a north-south routing with an upward through hole, which is used as the metal for the bottom plate connection, and the right side is a north-south routing with an upward through hole, which is used as the top plate routing; y parallel east-west floating metal lines are distributed in the middle of the bottom plate routing and the top plate routing, and the line width and line spacing of the metal line are the same as the comb metal of the capacitor unit; the east-west comb metal is distributed on both the left and right sides, and half of the comb metal is connected to the bottom plate capacitor in the middle, and these floating metal lines are neither connected to the bottom plate routing on the left nor to the bottom plate routing on the right; The x+3 layer and the x+n-1 layer above it are stacked with the same metal pattern as the x+2 layer; The x+nth layer is the layer of the top plate routing. The top plate runs from the north-south route on the right side of the capacitor unit and is connected to other unit capacitors. Depending on the position of the redundant capacitor in the capacitor array, the top plate connection of the x+nth layer can also be connected only to the position of the aforementioned redundant capacitor without being connected to other capacitors. The position of the x+nth layer is the same as the top plate routing on the right side, and the width also overlaps with part of the top plate capacitor.

2. A high-speed and high-precision capacitor array applied to ADC according to any one of claim 1, characterized in that: The capacitor array is arranged in a capacitor array of k rows and j columns based on the principle of capacitor center symmetry.

3. The high-speed and high-precision capacitor array applied to ADC according to claim 1, characterized in that: When the number of different capacitors in each row of the capacitor array exceeds 2, the x-layer bottom plate metal of the unit capacitor is increased from 2 to 4 or more, while maintaining left-right symmetry and an even number, and the x-layer bottom plate metal is within the coverage of the x+1-layer shielding metal; The x-th layer of metal is connected to the unit capacitor through selective upward vias and then leads out from the southernmost side; The x-layer metal on the far left and far right is connected to the Vd port through upward vias and leads out at the southernmost end; The two shielding capacitor rows in row 0 and row k+1 are also connected to the Vd port through the x-layer metal and are routed out at the southernmost end; The unused portion of the capacitor array in row k and column j is used as redundant capacitor and is also connected to the Vd port through metal at the southernmost outlet.

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