Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure and having a tapered cross-section, a second portion having a tapered cross-section, and a third portion connecting the first portion with the second portion, where the third portion has a vertical profile, and where the second portion and the third portion extend through the second gate structure.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to an electronic device and a method for manufacturing the electronic device, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which memory cells are formed in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. In addition, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. Summary of the invention

[0003] In an embodiment of the present disclosure, a semiconductor device may include: a first gate structure; a second gate structure disposed above the first gate structure; and a channel structure including a first portion extending through the first gate structure and having a tapered cross-section, a second portion having a tapered cross-section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extend through the second gate structure.

[0004] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first stack; forming a first opening extending through the first stack and having a tapered cross-section; forming a second stack on the first stack; forming a second opening, the second opening extending through the second stack and including a first region and a second region, the first region having a tapered cross-section, the second region connecting the first region and the first opening to each other and having a vertical profile; and forming a channel structure in the first opening and the second opening.

[0005] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack; forming a mask pattern on the stack, the mask pattern including carbon; etching the stack by using the mask pattern as an etching barrier to form an opening having a tapered cross-section; forming a protective layer by allowing etching byproducts of the mask pattern to be adsorbed to an inner wall of the opening; and extending the opening with a vertical profile by etching the stack exposed through the protective layer.

[0006] These and other features and advantages of the present invention will become better understood from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3 is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] FIG. 4A to FIG. 4D is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 5A to FIG. 5C is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure are directed to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device has a stable structure and improved characteristics.

[0013] Therefore, according to the embodiments of the present disclosure, a semiconductor device having a stable structure and improved reliability can be provided.

[0014] Hereinafter, embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings.

[0015] Figure 1 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Now refer to Figure 1 The semiconductor device may include at least one of a first gate structure 110 , a second gate structure 120 disposed above the first gate structure 110 , and a channel structure 130 .

[0017] The first gate structure 110 may include a first insulating layer 110A and a first conductive layer 110B alternately stacked with each other in a first direction. The first direction may be, for example, a vertical direction. The first insulating layer 110A and the first conductive layer 110B may extend parallel to the second direction and the third direction. The second direction and the third direction may form a plane (e.g., a horizontal plane). For example, the first conductive layer 110B may be used as a word line, a bit line, or a selection line. The first insulating layer 110A may be made of any suitable insulating material (e.g., including an insulating material such as an oxide (e.g., silicon oxide)), and the first conductive layer 110B may each include a conductive material such as a metal (e.g., tungsten or molybdenum) or a polysilicon conductive material.

[0018] The second gate structure 120 may be disposed on the first gate structure 110. The second gate structure 120 may overlap the first gate structure 110 in the first direction. The second gate structure 120 may include a second insulating layer 120A and a second conductive layer 120B alternately stacked. For example, the second conductive layer 120B may be used as a word line, a bit line, or a selection line. The second insulating layer 120A may be made of any suitable insulating material (for example, including an insulating material such as an oxide (for example, silicon oxide)), and the second conductive layers 120B may each include a conductive material such as a metal (for example, tungsten or molybdenum) or a polysilicon conductive material.

[0019] The channel structure 130 may penetrate into the first gate structure 110 through the second gate structure 120. The channel structures 130 may be spaced apart from each other to form a regular pattern and may extend through the first gate structure and the second gate structure. Each channel structure 130 may include a channel layer 130A. Each channel structure 130 may also include at least one of a memory layer 130B surrounding the channel layer 130A and an insulating core 130C in the channel layer 130A. The channel structure 130 may include a first portion P1, a second portion P2, and a third portion P3 characterized by their relative positioning within the gate structures 110 and 120 and their geometric features. The first portion P1 may extend through the first gate structure 110, the second portion P2 may extend through the second gate structure 120, and the third portion P3 may be disposed between the first portion P1 and the second portion P2. For example, the third portion P3 may extend through the second gate structure 120.

[0020] The channel structure 130 may have a cross-section with a tapered shape. Forming each channel structure 130 includes first forming an opening. As the opening becomes deeper, the energy provided for the etching process for forming the opening gradually decreases, that is, the amount of energy becomes relatively small from the upper part of the opening toward the lower part of the opening. Therefore, an opening with a cross-section with a tapered shape whose width decreases from the upper part (e.g., the top surface) toward the lower part (e.g., the bottom surface) may be formed, and a channel structure 130 with a tapered cross-section may be formed in the opening. For example, the first portion P1 of the channel structure 130 may have a cross-section with a tapered shape, and the second portion P2 may have a cross-section with a tapered shape.

[0021] However, the present disclosure is not limited thereto, and in addition to the cross section of the tapered shape, the channel structure 130 may have a cross section of another shape. For example, in a variation of the illustrated embodiment, the channel structure 130 may have a vertical profile. For example, the channel structure 130 may have a vertical profile of a substantially constant cross section that does not change along the height of the channel structure 130. Etching byproducts may be formed in the process of forming the opening and may be adsorbed to the upper portion of the opening to form a protective layer. Because the protective layer is not formed at the lower portion of the opening, the lower portion of the opening may be expanded to have a vertical profile even with relatively small energy. For example, the third portion P3 of the channel structure 130 may have a vertical profile.

[0022] The first portion P1 may have a first width D1, the second portion P2 may have a second width D2 and a fourth width D4, and the third portion P3 may have a third width D3. For example, the first width D1 refers to the width of the top surface of the first portion P1. The second width D2 refers to the width of the top surface of the second portion P2, and the fourth width D4 refers to the width of the bottom surface of the second portion P2.

[0023] The third width D3 may be less than the width of the top surface of the first portion P1. For example, the third width D3 may be less than the first width D1. The third width D3 may be less than the width of the top surface of the second portion P2. For example, the third width D3 may be less than the second width D2. The third width D3 may be substantially the same as the width of the bottom surface of the second portion P2. For example, the third width D3 may be substantially the same as the fourth width D4. The width of the top surface of the third portion P3 and the width of the bottom surface may be substantially the same. This is because the third portion P3 may have a vertical profile. Therefore, the third width D3 of the third portion P3 may be uniform. Because the third portion P3 has an enlarged vertical profile, the connection between the first portion P1 and the second portion P2 may be improved compared to the case where the third portion P3 has a cross section with a tapered shape.

[0024] According to the above structure, the third portion P3 connecting the first and second portions P1 and P2 of the channel structure 130 has a vertical profile. Therefore, the connection between the first and second portions P1 and P2 can be improved compared to the case where the third portion P3 has a tapered cross section.

[0025] Figure 2 is a simplified diagram showing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any contents overlapping with the previously described contents may be omitted.

[0026] Reference Figure 2The semiconductor device may include at least one of a substrate 1, a first gate structure 210, a second gate structure 220, a channel structure 230, and a source structure 200. The semiconductor device may also include at least one of an isolation insulating layer ISO, a peripheral circuit PC, an interconnection structure 3, a bonding structure 4, a first interlayer insulating layer IL1, and a second interlayer insulating layer IL2.

[0027] The substrate 1 may be a semiconductor substrate such as a silicon wafer, a SiGe wafer, or a silicon-on-insulator (SOI) wafer. The peripheral circuit PC may be disposed on or above the substrate 1, and the isolation insulating layer ISO may be disposed in the substrate 1. The active region may be defined by the isolation insulating layer ISO. The peripheral circuit PC may include a transistor 2, a capacitor, a resistor, and the like. For example, the transistor 2 may include a first junction 2A, a second junction 2B, a gate insulating layer 2C, or a gate electrode 2D. The gate insulating layer 2C may be disposed between the gate electrode 2D and the substrate 1. The gate insulating layer 2C and the isolation insulating layer ISO may each include an insulating material such as an oxide or a nitride.

[0028] The interconnection structure 3 may be disposed on the substrate 1. For example, the interconnection structure 3 may include a first contact via 3A, a first wiring 3B, a second contact via 3C, and a second wiring 3D. The first contact via 3A and the first wiring 3B may be disposed in the first interlayer insulating layer IL1. For example, the first interlayer insulating layer IL1 may be disposed on the substrate 1. At least one first contact via 3A may be connected to the transistor 2. The first wirings 3B may be connected to the first contact vias 3A, respectively.

[0029] The first gate structure 210 and the second gate structure 220 may be disposed on the peripheral circuit PC. The first gate structure 210 may include a first insulating layer 210A and a first conductive layer 210B alternately stacked, and the second gate structure 220 may include a second insulating layer 220A and a second conductive layer 220B alternately stacked. The insulating layers 210A and 220A may each include an insulating material such as an oxide, and the conductive layers 210B and 220B may each include a conductive material such as tungsten, molybdenum, or polysilicon. The conductive layers 210B and 220B may be used as word lines, bit lines, or selection lines.

[0030] The source structure 200 may be disposed on the first gate structure 210 and the second gate structure 220. The channel structure 230 may extend into the source structure 200 through the first gate structure 210 and the second gate structure 220. The channel structure 230 may be connected to the source structure 200. The channel structure 230 may have a cross section of a tapered shape. In addition, the channel structure 230 may have a vertical profile. Each channel structure 230 may include at least one of a channel layer 230A, a memory layer 230B surrounding the channel layer 230A, and an insulating core 230C in the channel layer 230A. For example, the channel layer 230A may be connected to the source structure 200.

[0031] The second contact vias 3C and the second wirings 3D of the interconnect structure 3 may be disposed under the first gate structure 210 and the second gate structure 220. The second contact vias 3C may be connected to the channel structures 230, respectively. The second wirings 3D may be disposed under the second contact vias 3C, respectively. The second wirings 3D may be connected to the second contact vias 3C, respectively. The second contact vias 3C and the second wirings 3D may be disposed in the second interlayer insulating layer IL2.

[0032] The bonding structure 4 may be disposed between the second gate structure 220 and the peripheral circuit PC. The bonding structure 4 may include a first bonding pad 4A disposed in the first interlayer insulating layer IL1 and a second bonding pad 4B disposed in the second interlayer insulating layer IL2. The first bonding pad 4A may be connected to at least one first wiring 3B, and the second bonding pad 4B may be connected to at least one second wiring 3D. The first bonding pad 4A and the second bonding pad 4B may be bonded or coupled to each other. The first bonding pad 4A and the second bonding pad 4B may be in direct contact with each other.

[0033] According to the above structure, a wafer consisting of a memory cell array including the channel structure 230 and a peripheral circuit PC related to the operation of the memory cell array can be configured as separate wafers and then bonded or connected to each other. Configuring the peripheral circuit PC related to the operation of the memory cell array as a separate wafer is advantageous because it allows more memory cells to be provided on the wafer including the memory cell array, and thus more data can be stored.

[0034] Figure 3 1 is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0035] Reference Figure 3 , a stack 310 (also referred to as a multilayer structure 310 ) including a first material layer 310A and a second material layer 310B may be formed.

[0036] Subsequently, a mask pattern 320 may be formed on the stack 310. For example, the mask pattern 320 may include carbon. The mask pattern 320 may include an opening that exposes a location where a channel structure is to be formed.

[0037] Subsequently, the opening OP may be formed by etching the stack 310 using the mask pattern 320 as an etching barrier. The opening OP may be formed by a plasma treatment including fluorine (F). In the process of forming the opening OP, the energy for etching may reach the opening OP from the upper portion (or top) of the opening OP toward the lower portion of the opening OP in a relatively small amount. In this case, the width of the lower portion of the opening OP may be smaller than the width of the upper portion of the opening. Therefore, the opening OP may be formed to have a cross-section with a tapered shape.

[0038] When the mask pattern 320 including carbon is used as an etching barrier, an etching byproduct 330A of the mask pattern 320 may be formed. For example, the etching byproduct 330A refers to carbon fluoride (CF) formed by the reaction between carbon (C) and fluorine (F). The etching byproduct 330A may be adsorbed to the inner wall of the opening OP to form a protective layer 330B. Because the opening OP is formed under a low temperature environment, the adhesion coefficient of the etching byproduct 330A may increase. When the adhesion coefficient increases, the etching byproduct 330A may be less diffused. In this case, more etching byproducts 330A may be adsorbed to the upper portion of the opening OP compared to the lower portion of the opening OP. The etching byproduct 330A may be adsorbed to the upper portion of the opening OP to form a protective layer 330B.

[0039] The protective layer 330B may not be formed at the lower part of the opening OP, or may be formed at the lower part of the opening OP with a relatively small thickness. The lower part of the opening OP may maintain the state in which the stack 310 to be etched is exposed, and the stack 310 may be etched at the lower part of the opening OP even with a relatively small energy, so that the lower part of the opening OP may be expanded. Therefore, the opening OP may be extended with a vertical profile by etching the stack 310 exposed by the protective layer 330B. For example, the stack 310 may be etched by ion plasma collision.

[0040] In addition, the opening OP may be formed by etching the stack 310 in a low temperature environment of -15°C or lower. For example, the opening OP may be formed in a low temperature environment of -15°C or lower or -110°C or higher and -15°C or lower. This is because when the opening OP is formed in a low temperature environment of less than -110°C, the etching byproduct 330A may be excessively formed in the upper portion of the opening OP and may block the opening OP, or the lower portion of the opening OP may be excessively expanded so that bowing degradation may occur, or the opening OP may have a cross-section of a reverse tapered shape.

[0041] According to the above method, the protective layer 330B is formed at the upper portion of the opening OP, and is not formed at the lower portion of the opening OP. Therefore, the stack 310 to be etched can be etched at the lower portion of the opening OP even with a small etching energy, and the lower portion of the opening OP can be extended to have a vertical profile. For example, the lower portion of the opening OP where the protective layer 330B is not formed can extend at the lower 1 / 3 of the opening OP, the lower 1 / 4 of the opening OP, or the lower 1 / 5 of the opening OP.

[0042] FIG. 4A to FIG. 4D 1 is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0043] Reference Figure 4A , a first stack 410 may be formed. The first stack 410 may include first material layers 410A and second material layers 410B alternately stacked. For example, the first material layers 410A may each include an insulating material such as an oxide. The second material layers 410B may each include a sacrificial material such as, for example, a nitride. Alternatively, the second material layers 410B may each include a conductive material such as, for example, molybdenum or polysilicon.

[0044] Subsequently, a first opening OP1 extending through the first stack 410 may be formed before forming the second stack 430. The first opening OP1 may have a cross-section of a tapered shape. Subsequently, a sacrificial layer 420 may be formed in the first opening OP1. First, a first sacrificial layer 420A may be formed in the first opening OP1. Subsequently, a second sacrificial layer 420B may be formed within the first sacrificial layer 420A to fill the remaining space of the first opening OP1. For example, the first sacrificial layer 420A may include titanium nitride (TiN), and the second sacrificial layer 420B may include tungsten (W).

[0045] Subsequently, a second stack 430 may be formed on the first stack 410. The second stack 430 may include third material layers 430A and fourth material layers 430B alternately stacked. For example, the third material layers 430A may each include an insulating material such as an oxide, and the fourth material layers 430B may each include a sacrificial material such as a nitride. Alternatively, the fourth material layers 430B may each include a conductive material such as molybdenum or polysilicon.

[0046] Reference Figure 4B, a second opening OP2 extending through the second stack 430 may be formed. For example, the second opening OP2 may be formed to extend through the second stack 430 and include a first region OP2A having a cross section with a tapered shape and a second region OP2B connecting the first region OP2A and the first opening OP1 to each other and having a vertical profile. For example, the second opening OP2 may be formed by etching the second stack 430 in a low temperature environment of -15°C or lower or at a temperature between -110°C and -15°C.

[0047] First, a mask pattern (not shown) may be formed on the second stack 430. For example, the mask pattern may include carbon. Subsequently, the second stack 430 may be etched using the mask pattern as an etching barrier. In the process of forming the second opening OP2 by etching the second stack 430, the energy used for etching may be reduced from the upper portion of the second opening OP2 toward the lower portion of the second opening OP2. In this case, the width of the lower portion of the second opening OP2 may be less than the width of the upper portion of the second opening OP2. Therefore, the first region OP2A of the second opening OP2 may have a cross section of a tapered shape.

[0048] In the process of forming the second opening OP2, etching byproducts of the mask pattern may be adsorbed to the inner wall of the second opening OP2. For example, etching byproducts may be formed in the first region OP2A. For example, etching byproducts adsorbed to the first region OP2A may be used as a protective layer 440. Since the second stack 430 may be etched even with a small etching energy in the second region OP2B where the protective layer 440 is not formed, the second region OP2B may be expanded to have a vertical profile. Therefore, when the second opening OP2 is formed, the first region OP2A may be protected by the protective layer 440, and the second region OP2B may be expanded.

[0049] The sacrificial layer 420 may be exposed through the second opening OP2. For example, the second sacrificial layer 420B may be exposed. For example, the sacrificial layers 420 may each include a material that is selective to the third material layer 430A and the fourth material layer 430B of the second stack 430. For example, the second sacrificial layer 420B may each include tungsten that is selective to the third material layer 430A and the fourth material layer 430B. Therefore, in the process of enlarging the second region OP2B of the second opening OP2 by etching the second stack 430, the sacrificial layer 420 is not removed.

[0050] When the second sacrificial layer 420B includes tungsten, byproducts may be formed by a reaction between plasma ions and tungsten. Since the formed byproducts have low photocatalytic efficiency, deformation of the profile of the second opening OP2 due to a chemical reaction on the sidewall of the second opening OP2 may be prevented or minimized.

[0051] Reference Figure 4C , the first opening OP1 may be reopened by removing the sacrificial layer 420 exposed through the second opening OP2. Since the sacrificial layer 420 of the first opening OP1 is further exposed while the second region OP2B is enlarged, the sacrificial layer 420 may be more easily removed. Subsequently, the protective layer 440 may be removed. For example, a cleaning process may be performed, and the protective layer 440 may be removed in the cleaning process.

[0052] Reference Figure 4D , a channel structure 450 may be formed in the first opening OP1 and the second opening OP2. Each channel structure 450 may include a channel layer 450A and at least one of a memory layer 450B surrounding the channel layer 450A and an insulating core 450C in the channel layer 450A.

[0053] Each channel structure 450 may include a first portion P1 having a tapered cross-section, a second portion P2 having a tapered cross-section, and a third portion P3 disposed between the first portion P1 and the second portion P2 and having a vertical profile. The first portion P1 may have a first width D1, the second portion P2 may have a second width D2 and a fourth width D4, and the third portion P3 may have a third width D3. For example, the first width D1 refers to the width of the top surface of the first portion P1. The second width D2 refers to the width of the top surface of the second portion P2, and the fourth width D4 refers to the width of the bottom surface of the second portion P2. The third width D3 may be smaller than the first width D1. The third width D3 may be smaller than the second width D2. The third width D3 may be substantially the same as the fourth width D4. The width of the top surface and the width of the bottom surface of the third portion P3 may be substantially the same.

[0054] Subsequently, the second material layer 410B may be replaced by the fifth material layer 410C through a slit (not shown). The fourth material layer 430B may be replaced by the sixth material layer 430C through a slit. Thus, a first gate structure 410G and a second gate structure 420G may be formed. The first gate structure 410G may include a first material layer 410A and a fifth material layer 410C alternately stacked. The second gate structure 430G may include a third material layer 430A and a sixth material layer 430C alternately stacked. The fifth material layer 410C and the sixth material layer 430C may each include a conductive material such as tungsten, molybdenum or polysilicon. For example, the fifth material layer 410C and the sixth material layer 430C may be a word line, a bit line or a selection line. For reference, when the second material layer 410B and the fourth material layer 430B each include a conductive material, the replacement process may be omitted. In this case, the first stack 410 may be used as the first gate structure 410G, and the second stack 430 may be used as the second gate structure 430G. Subsequently, a slit structure (not shown) may be formed in the slit. For example, the slit structure may include an insulating material, a conductive material, a semiconductor material, or the like.

[0055] According to the above manufacturing method, in the process of forming the second opening OP2, the protective layer 440 may not be formed in the second region OP2B of the second opening OP2. Therefore, even if relatively small etching energy reaches the second region OP2B, the second region OP2B may be expanded.

[0056] In addition, the second region OP2B of the second opening OP2 may be expanded using the sacrificial layer 420 having selectivity with respect to the third material layer 430A and the fourth material layer 430B of the second stack 430. Therefore, as the second region OP2B is expanded, the sacrificial layer 420 may be more easily removed.

[0057] FIG. 5A to FIG. 5C 1 is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0058] Reference Figure 5A , a first stack 510 including first material layers 510A and second material layers 510B alternately stacked may be formed. For example, the first material layers 510A may each include an insulating material such as oxide, and the second material layers 510B may each include a sacrificial material such as nitride. Alternatively, the second material layers 510B may each include a conductive material such as molybdenum or polysilicon.

[0059] Subsequently, a sacrificial layer 520 may be formed in the first stack 510. First, a first sacrificial layer 520C may be formed in the first opening OP1. For example, the first sacrificial layer 520C may be formed to fill the first opening OP1. Subsequently, a trench T may be formed by partially etching the first sacrificial layer 520C. Subsequently, a second sacrificial layer 520B may be formed in the trench T. Before forming the second sacrificial layer 520B, a third sacrificial layer 520A may be formed in the trench T. For example, the first sacrificial layer 520C may include carbon, the second sacrificial layer 520B may include tungsten, and the third sacrificial layer 520A may include titanium nitride (TiN).

[0060] Reference Figure 5B , a second stack 530 may be formed on the first stack 510. The second stack 530 may include third material layers 530A and fourth material layers 530B alternately stacked. For example, the third material layers 530A may each include an insulating material such as an oxide, and the fourth material layers 530B may each include a sacrificial material such as a nitride. Alternatively, the fourth material layers 530B may each include a conductive material such as molybdenum or polysilicon.

[0061] Subsequently, a second opening OP2 may be formed, which extends through the second stack 530 and includes a first region OP2A having a cross section with a tapered shape and a second region OP2B connecting the first region OP2A and the first opening OP1 to each other and having a vertical profile. For example, the second opening OP2 may be formed by etching the second stack 530 in a low temperature environment of -15°C or lower or at a temperature between -110°C and -15°C.

[0062] First, a mask pattern (not shown) including carbon may be formed on the second stack 530. Subsequently, the mask pattern may be used as an etching barrier to etch the second stack 530. The first region OP2A of the second opening OP2 may have a cross section with a tapered shape. In the process of forming the second opening OP2, the etching byproducts of the mask pattern may be adsorbed to the inner wall of the first region OP2A, and the etching byproducts adsorbed to the first region OP2A may be used as a protective layer 540. Because the second stack 530 may be etched even with a small etching energy in the second region OP2B where the protective layer 540 is not formed, the second region OP2B may be expanded to have a vertical profile. Therefore, when the second opening OP2 is formed, the first region OP2A may be protected by the protective layer 540, and the second region OP2B may be expanded.

[0063] The second sacrificial layer 520B may be exposed through the second opening OP2. For example, the second sacrificial layers 520B may each include a material that is selective to the third material layer 530A and the fourth material layer 530B of the second stack 530. For example, the second sacrificial layers 520B may each include tungsten. Therefore, in the process of enlarging the second region OP2B of the second opening OP2 by etching the second stack 530, the second sacrificial layer 520B is not removed.

[0064] Reference Figure 5C , the first opening OP1 may be reopened by removing the sacrificial layer 520 exposed through the second opening OP2. Subsequently, the protective layer 540 may be removed, for example, by performing a cleaning process.

[0065] Subsequently, channel structures 550 may be formed in the first and second openings OP1 and OP2. Each channel structure 550 may include a channel layer 550A. The channel structure 550 may further include at least one of a memory layer 550B surrounding the channel layer 550A and an insulating core 550C in the channel layer 550A.

[0066] The channel structure 550 may include a first portion P1 having a tapered cross-section, a second portion P2 having a tapered cross-section, and a third portion P3 disposed between the first portion P1 and the second portion P2 and having a vertical profile. The first portion P1 may have a first width D1, the second portion P2 may have a second width D2 and a fourth width D4, and the third portion P3 may have a third width D3. For example, the first width D1 refers to the width of the top surface of the first portion P1. The second width D2 refers to the width of the top surface of the second portion P2, and the fourth width D4 refers to the width of the bottom surface of the second portion P2. The third width D3 may be smaller than the first width D1. The third width D3 may be smaller than the second width D2. The third width D3 may be substantially the same as the fourth width D4. The width of the top surface and the width of the bottom surface of the third portion P3 may be substantially the same.

[0067] Subsequently, the second material layer 510B may be replaced by the fifth material layer 510C through a slit (not shown). The fourth material layer 530B may be replaced by the sixth material layer 530C through a slit. Thus, a first gate structure 510G including the first material layer 510A and the fifth material layer 510C stacked alternately may be formed, and a second gate structure 530G including the third material layer 530A and the sixth material layer 530C stacked alternately may be formed. The fifth material layer 510C and the sixth material layer 530C may each include a conductive material such as tungsten, molybdenum, or polysilicon. For example, the fifth material layer 510C and the sixth material layer 530C may be a word line, a bit line, or a selection line. Subsequently, a slit structure (not shown) may be formed in the slit. For example, the slit structure may include an insulating material, a conductive material, a semiconductor material, and the like.

[0068] According to the above-described manufacturing method, the first sacrificial layer 520C including carbon may be formed in the first opening OP1. Subsequently, the trench T may be formed by partially etching the first sacrificial layer 520C, and then the second sacrificial layer 520B including tungsten may be formed in the trench T.

[0069] In addition, in the process of forming the second opening OP2, the protective layer 540 may not be formed in the second region OP2B of the second opening OP2. Therefore, even if relatively small etching energy may reach the second region OP2B, the second region OP2B may be expanded.

[0070] The second region OP2B of the second opening OP2 may be expanded using the second sacrificial layer 520B having selectivity with respect to the third material layer 530A and the fourth material layer 530B of the second stack 530. Therefore, as the second region OP2B is expanded, the sacrificial layer 520 may be more easily removed.

[0071] Although the embodiments according to the technical ideas of the present disclosure are described above with reference to the accompanying drawings, this is only to describe the exemplary embodiments according to the concept of the present disclosure, and the present invention is not limited to the above embodiments. Without departing from the present invention defined in the following claims, a person skilled in the art to which the present disclosure belongs may make various types of substitutions, modifications and changes to the embodiments, and it should be interpreted that these substitutions, modifications and changes belong to the scope of the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

[0072] CROSS-REFERENCE TO RELATED APPLICATIONS

[0073] This application claims priority to Korean Patent Application No. 10-2023-0117017, filed on September 4, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first gate structure; a second gate structure, the second gate structure being disposed above the first gate structure; as well as a channel structure including a first portion extending through the first gate structure and having a tapered cross-section, a second portion having a tapered cross-section, and a third portion connecting the first portion and the second portion, wherein the third portion has a vertical profile, and The second portion and the third portion extend through the second gate structure.

2. The semiconductor device according to claim 1, wherein The second portion extends from the top surface of the second gate structure to the third portion, and the third portion extends from the middle height of the second gate structure to the bottom surface of the second gate structure, where the third portion is connected to the top surface of the first portion of the channel structure.

3. The semiconductor device according to claim 1, wherein The first portion has a first width, the second portion has a second width, and the third portion has a third width that is smaller than the first width or the second width.

4. The semiconductor device according to claim 3, wherein: The third width is smaller than a width of a top surface of the first portion.

5. The semiconductor device according to claim 3, wherein: The third width is substantially the same as a width of a bottom surface of the second portion.

6. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first stack; forming a first opening extending through the first laminate and having a tapered cross-section; forming a second stack on the first stack; forming a second opening extending through the second laminate and including a first region having a cross-section of a tapered shape and a second region connecting the first region and the first opening to each other and having a vertical profile; as well as A channel structure is formed in the first opening and the second opening.

7. The manufacturing method according to claim 6, wherein: The step of forming the second opening comprises the following steps: forming a mask pattern on the second stack; and The second opening is formed by etching the second stack using the mask pattern as an etch barrier.

8. The manufacturing method according to claim 7, wherein: Etching byproducts of the mask pattern are adsorbed to an inner wall of the second opening to form a protection layer.

9. The manufacturing method according to claim 8, wherein: The protection layer is formed in the first region.

10. The manufacturing method according to claim 8, wherein: When the second opening is formed, the first region is protected by the protective layer, and the second region is expanded.

11. The manufacturing method according to claim 8, further comprising the following steps: The protective layer is removed.

12. The manufacturing method according to claim 7, wherein: The mask pattern includes carbon.

13. The manufacturing method according to claim 6, wherein: In the step of forming the second opening, the second stack is etched in a low temperature environment of -15°C or lower.

14. The manufacturing method according to claim 6, further comprising the following steps: A sacrificial layer is formed in the first opening.

15. The manufacturing method according to claim 14, wherein: The first stack includes first material layers and second material layers that are alternately stacked, and the second stack includes third material layers and fourth material layers that are alternately stacked.

16. The manufacturing method according to claim 15, wherein: The sacrificial layer includes a material having selectivity with respect to the third material layer and the fourth material layer.

17. The manufacturing method according to claim 16, wherein: The sacrificial layer includes tungsten.

18. The manufacturing method according to claim 14, wherein: The step of forming the sacrificial layer comprises the following steps: forming a first sacrificial layer in the first stack; forming a trench by partially etching the first sacrificial layer; and A second sacrificial layer is formed in the trench.

19. The manufacturing method according to claim 18, wherein: The first sacrificial layer includes carbon, and the second sacrificial layer includes tungsten.

20. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a stack; forming a mask pattern on the stack, the mask pattern comprising carbon; forming an opening having a cross-section of a tapered shape by etching the stack using the mask pattern as an etching barrier; forming a protective layer by causing etching byproducts of the mask pattern to be adsorbed onto inner walls of the opening; as well as The opening is extended with a vertical profile by etching the stack exposed by the protective layer.

21. The manufacturing method according to claim 20, further comprising the following steps: removing the protective layer; as well as A channel structure is formed in the opening.

22. The manufacturing method according to claim 20, wherein: In the step of forming the opening, the stack is etched in a low temperature environment of -15°C or lower.

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