Nonvolatile memory device

Abstract

A non-volatile memory device includes: a substrate; a first semiconductor layer including a memory cell array on the substrate; a second semiconductor layer including a peripheral circuit configured to write data to or read data from the memory cell array, in which the second semiconductor layer is on the first semiconductor layer; and a protruding structure including a wiring extending into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, in which the protruding structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and in which the protruding structure extends in a second direction perpendicular to the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0117231 filed on September 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including a plurality of semiconductor chips. Background Art

[0004] As information and communication equipment has become compact and multifunctional recently, it is expected that storage devices have high capacity and high integration density. As the size of storage cells is reduced for high integration density, the complexity of the operation circuits and / or wiring structures included in the storage device for its operation and electrical connection has increased. Therefore, the area of ​​semiconductor chips is reduced by reducing the size of storage cells. However, the multifunctionalization and compactness of information and communication equipment continue, and therefore, it is still necessary to reduce the size of semiconductor chips. Summary of the invention

[0005] The present disclosure provides a nonvolatile memory device having a high integration density by reducing the size of the nonvolatile memory device.

[0006] Various aspects of the present disclosure are not limited to those mentioned above, and other aspects not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of the present disclosure, a nonvolatile memory device is provided, comprising: a substrate; a first semiconductor layer comprising a memory cell array on the substrate, wherein the memory cell array comprises a plurality of gate conductive layers and defines a plurality of channel holes, wherein the plurality of gate conductive layers are spaced apart in a first direction perpendicular to a top surface of the substrate, and wherein each of the plurality of channel holes extends into the plurality of gate conductive layers; a second semiconductor layer comprising a peripheral circuit configured to write data to or read data from the memory cell array, wherein the second semiconductor layer is on the first semiconductor layer; and a protrusion structure comprising a wiring extending into at least a portion of the first semiconductor layer and into at least a portion of the second semiconductor layer, wherein the protrusion structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and wherein the protrusion structure extends in a second direction perpendicular to the first direction.

[0008] According to another aspect of the present disclosure, a memory package is provided, comprising: a package substrate configured to electrically connect an external device to the memory package; a first memory device extending in a first direction perpendicular to a top surface of the package substrate, wherein the first memory device comprises a first surface, a second surface, a third surface, and a fourth surface, wherein the first surface is spaced apart from the second surface in a second direction perpendicular to the first direction, and wherein the third surface and the fourth surface extend from the first surface to the second surface; and a second memory device comprising a fifth surface, a sixth surface, a seventh surface, and an eighth surface, wherein the fifth surface is spaced apart from the sixth surface in the second direction, and wherein the seventh surface and the eighth surface extend from the fifth surface to the sixth surface, wherein the first memory device comprises a first protruding structure extending from the first surface, wherein the second memory device comprises a second protruding structure extending from the fifth surface, wherein the second memory device is on the first memory device, and wherein a bottom surface of the second protruding structure overlaps with at least a portion of the first memory device in the first direction.

[0009] According to another aspect of the present disclosure, a memory package is provided, comprising: a package substrate configured to electrically connect an external device to the memory package; a first memory device extending in a first direction perpendicular to a top surface of the package substrate, wherein the first memory device comprises a first surface, a second surface, a third surface, and a fourth surface, wherein the first surface is spaced apart from the second surface in a second direction perpendicular to the first direction, and wherein the third surface and the fourth surface extend from the first surface to the second surface; and a second memory device comprising a fifth surface, a sixth surface, a seventh surface, and an eighth surface, wherein the fifth surface is spaced apart from the sixth surface in the second direction, and wherein the seventh surface and the eighth surface extend from the fifth surface to the sixth surface, wherein the first memory device comprises a first protruding structure extending from the first surface, wherein the second memory device comprises a second protruding structure extending from the fifth surface, wherein the second memory device at least partially overlaps with the first memory device in the first direction, and wherein the first protruding structure is spaced apart from the second protruding structure in a third direction perpendicular to the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram of a memory device according to some embodiments;

[0012] Figure 2 is a circuit diagram of a memory block according to some embodiments;

[0013] Figure 3 Shows Figure 1 Example structures of storage devices;

[0014] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a diagram showing an arrangement of memory devices on a wafer according to some embodiments;

[0015] Figure 5A and Figure 5B is a diagram of a memory device according to some embodiments;

[0016] Fig. 6A and Figure 6B is a cross-sectional view of a memory device according to some embodiments;

[0017] Fig. 7A and Figure 7B is a diagram illustrating a memory device according to some embodiments;

[0018] Fig. 8A and Figure 8B is a diagram illustrating a memory device according to some embodiments;

[0019] Fig. 9 is a cross-sectional view of a memory device having a bonded vertical NAND (BVNAND) structure according to some embodiments; and

[0020] Fig.10 is a block diagram of an example of applying a memory device to a solid state drive (SSD) system according to an embodiment. DETAILED DESCRIPTION

[0021] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0022] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on another element or there can also be an intermediate element. In contrast, when an element is referred to as being "directly" "on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms (e.g., "under", "below", "below", "above", "on", etc.) can be used in this article to describe the relationship between an element or feature and another element or feature as shown in the accompanying drawings. It will be understood that spatial relative terms, in addition to including the orientation shown in the accompanying drawings, are also intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the term "below ... below" can include both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used in this article can be interpreted accordingly.

[0023] In addition, unless explicitly described to the contrary, the word "include" and variants such as "contain" or "include" will be understood to mean including the elements described, but not excluding any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A "or" B "or" C) using non-exclusive logic OR, and should not be interpreted as indicating "at least one of A, at least one of B and at least one of C". As used herein, the singular forms "one", "one" and "said" are intended to also include plural forms, unless the context clearly gives the opposite indication. It should also be understood that the terms "include", "include", "include", and / or "include" are used in this article to indicate the presence of the features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or their combinations. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connection" can be used in this article to refer to physical connections and / or electrical connections, and can refer to direct or indirect physical connections and / or electrical connections. Components or layers described with reference to “overlapping” in a specific direction may be at least partially obscured by each other when viewed along a line extending in the specific direction or in a plane perpendicular to the specific direction.

[0024] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals denote the same elements, and redundant descriptions thereof will be omitted.

[0025] Figure 1 is a diagram of a memory device 10 according to some embodiments.

[0026] refer to Figure 1 , the memory device 10 may include a memory cell array 100 and a peripheral circuit 200. The peripheral circuit 200 may include a page buffer circuit 210, a control circuit 220, a voltage generator 230, and a row decoder 240. Figure 1 Although not shown, the peripheral circuit 200 may further include a data input / output circuit, an input / output interface, etc. The peripheral circuit 200 may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. In some embodiments, the memory device 10 herein may refer to a non-volatile memory device.

[0027] The memory cell array 100 may be connected to the page buffer circuit 210 through the bit lines BL and connected to the row decoder 240 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0028] The memory cell array 100 may include a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may have a planar structure or a three-dimensional (3D) structure. The memory cell array 100 may include at least one selected from the group consisting of a single-level cell (SLC) block including an SLC, a multi-level cell (MLC) block including an MLC, a triple-level cell (TLC) block including a TLC, and a quad-level cell (QLC) block including a QLC. For example, some of the memory blocks BLK1 to BLKz may correspond to SLC blocks, while other memory blocks may correspond to MLC blocks, TLC blocks, or QLC blocks.

[0029] Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the memory cell may include a flash memory cell. Hereinafter, the embodiment is described by taking the case where the memory cell is a NAND flash memory cell as an example. However, the embodiment is not limited thereto. In some embodiments, the memory cell may be a resistive memory cell, such as a resistive random access memory (ReRAM) cell, a phase change RAM (PRAM) cell, or a magnetic RAM (MRAM) cell.

[0030] In some embodiments, the memory cell array 100 may include a 3D memory cell array, which may include multiple NAND strings. However, embodiments are not limited thereto. In some embodiments, the memory cell array 100 may include a two-dimensional (2D) memory cell array, which may include multiple NAND strings in row and column directions.

[0031] Based on the command CMD, the address ADDR, and the control signal CTRL, the control circuit 220 may output various control signals, such as a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR, for programming data to the memory cell array 100, reading data from the memory cell array 100, or erasing data from the memory cell array 100. The control circuit 220 may thereby generally control various operations of the memory device 10.

[0032] The voltage generator 230 may generate various voltages for performing a program operation, a read operation, and an erase operation of the memory cell array 100 based on the voltage control signal CTRL_vol. Specifically, the voltage generator 230 may generate a word line voltage VWL, such as a program voltage, a read voltage, a pass voltage, an erase verification voltage, or a program verification voltage. The voltage generator 230 may also generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol.

[0033] In response to the row address X-ADDR, the row decoder 240 can select one of the memory blocks BLK1 to BLKz, one of the word lines WL of the selected memory block, and one of the string selection lines SSL. The page buffer circuit 210 can select some bit lines BL in response to the column address Y-ADDR. Specifically, the page buffer circuit 210 can operate as a write driver or a sense amplifier according to the operation mode.

[0034] The page buffer circuit 210 may include a plurality of page buffers PB respectively connected to the bit lines BL.

[0035] The memory cell array 100 and the peripheral circuit 200 may be respectively included in a first semiconductor layer and a second semiconductor layer stacked on each other. An external signal (e.g., CTRL, CMD, ADDR, etc.) from outside the memory device 10 may be received through an external signal pad formed outside the first semiconductor layer. The external signal may be provided to the peripheral circuit 200 through an external signal line that passes through the first semiconductor layer and at least a portion of the second semiconductor layer or extends into the first semiconductor layer and at least a portion of the second semiconductor layer.

[0036] According to some embodiments, the size of the memory device 10 may be reduced by limiting the position of a region where an external signal pad and an external signal line are formed in each of the first semiconductor layer and the second semiconductor layer.

[0037] Figure 2 is a circuit diagram of a memory block BLK according to some embodiments. A direction perpendicular to the substrate may be referred to as a first direction D1. A second direction D2 may be perpendicular to the first direction D1. A third direction D3 may be perpendicular to the first direction D1 and the second direction D2.

[0038] refer to Figure 2 , the memory block BLK may correspond to Figure 1 One of the memory blocks BLK1 to BLKz in the memory block BLK. The memory block BLK may include NAND strings NS11 to NS33, wherein each NAND string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST connected in series with each other. The transistors (e.g., string selection transistor SST and ground selection transistor GST) included in each NAND string and the memory cells MC may form a stacked structure in a vertical direction on a substrate.

[0039] The word lines WL1 to WL8 may extend in the second horizontal direction, and the first to third bit lines BL1 to BL3 may extend in the first horizontal direction. The NAND strings NS11, NS21, and NS31 may be between the first bit line BL1 and the common source line CSL. The NAND strings NS12, NS22, and NS32 may be between the second bit line BL2 and the common source line CSL. The NAND strings NS13, NS23, and NS33 may be between the third bit line BL3 and the common source line CSL. The string selection transistor SST may be connected to a corresponding string selection line among the string selection lines SSL1 to SSL3. Each of the memory cells MC may be connected to a corresponding word line among the word lines WL1 to WL8. The ground selection transistor GST may be connected to a corresponding ground selection line among the ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to a corresponding bit line among the first to third bit lines BL1 to BL3, and the ground selection transistor GST may be connected to the common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground selection lines, and string selection lines may vary according to embodiments.

[0040] Figure 3 Shows Figure 1 An example structure of the memory device 10 is shown.

[0041] Here, a direction perpendicular to the substrate may be referred to as a first direction D1. A second direction D2 may be perpendicular to the first direction D1. A third direction D3 may be perpendicular to the first direction D1 and the second direction D2.

[0042] refer to Figure 3 , the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 may be stacked on the second semiconductor layer L2 along a vertical direction (ie, a first direction D1). Specifically, the second semiconductor layer L2 may be below the first semiconductor layer L1 along the first direction D1.

[0043] In an embodiment, Figure 1 The memory cell array 100 may be formed in the first semiconductor layer L1, and Figure 1 The peripheral circuit 200 in the second semiconductor layer L2 may be formed in the second semiconductor layer L2. Therefore, the memory device 10 may have a cell-on-periphery (COP) structure in which the memory cell array 100 is above the peripheral circuit 200. According to the COP structure, the area in the horizontal direction (i.e., the second direction D2 and the third direction D3) may be effectively reduced, and the integration density of the memory device 10 may be increased.

[0044] In some embodiments, the second semiconductor layer L2 may include a substrate. The peripheral circuit 200 may be formed in the second semiconductor layer L2 by forming transistors and metal patterns interconnecting the transistors on the substrate. After the peripheral circuit 200 is formed in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100 may be formed. A metal pattern may be formed that electrically connects the word line WL and the bit line BL of the memory cell array 100 to the peripheral circuit 200 in the second semiconductor layer L2. For example, the word line WL may extend in the third direction D3 and the bit line BL may extend in the second direction D2.

[0045] As described above, the memory device 10 may have a COP structure, but the embodiment is not limited thereto. For example, the memory device 10 may have a chip-to-chip (C2C) structure. In this case, the first semiconductor layer L1 may correspond to an upper chip, and the second semiconductor layer L2 may correspond to a lower chip. In the C2C structure, the first semiconductor layer L1 may include a semiconductor layer formed on a first wafer. Figure 1 The memory cell array 100 in the embodiment of the present invention, and the second semiconductor layer L2 may include a semiconductor layer formed on the second wafer Figure 1 The first semiconductor layer L1 and the second semiconductor layer L2 may be connected to each other in a bonding manner. For example, a bonding metal (eg, Fig. 9 The upper bonding metal pattern 1370c in the second semiconductor layer L2 may be electrically connected to a bonding metal formed on the uppermost metal layer of the second semiconductor layer L2. For example, when the bonding metal includes copper (Cu), the bonding method may be Cu-Cu bonding. For example, the first semiconductor layer L1 and the second semiconductor layer L2 are stacked at a wafer level. For example, the first semiconductor layer L1 and the second semiconductor layer L2 are stacked at a chip level.

[0046] The memory device 10 may include a protrusion structure 300. The protrusion structure 300 may include a plurality of input / output pads 310. In some embodiments, the protrusion structure 300 may be referred to as an external connection unit, an external peripheral circuit unit, an outer periphery, or a pad region. Fig. 6A and Figure 6B The detailed configuration of the protrusion structure 300 is described.

[0047] The input / output pads 310 may be formed on or in an upper portion of the first semiconductor layer L1 and may electrically connect the memory device 10 to an external device through a bonding wire. For example, the external device may refer to a host, a memory controller, or the like.

[0048] In some embodiments, the memory device 10 may include a first surface and a second surface spaced apart from each other in a second direction D2 perpendicular to the first direction D1. The memory device 10 may include a third surface and a fourth surface extending from the first surface to the second surface, i.e., extending along the second direction D2. The protruding structure 300 may protrude or extend from the first surface of the memory device 10. One side of the protruding structure 300 (perpendicular to the third direction D3) may be coplanar with the third surface of the memory device 10.

[0049] In some embodiments, the first length LEN1 of the protrusion structure 300 in the third direction D3 may be less than half of the second length LEN2 of the memory device 10 in the third direction D3.

[0050] In some embodiments, a third length LEN3 of a third surface of the memory device 10 coplanar with one surface of the protrusion structure 300 in the second direction D2 may be greater than a fourth length LEN4 of a fourth surface facing the third surface of the memory device 10 in the second direction D2.

[0051] 4A to 4D is a diagram showing an arrangement of memory devices on a wafer according to some embodiments.

[0052] 4A to 4D The memory device 10 is formed on the wafer WF according to some embodiments. Herein, the memory device 10 may be referred to as a semiconductor chip or a chip. Photolithography may be performed on the wafer WF using an exposure device, and a plurality of exposure regions (shots) may be formed on the wafer WF. Here, each exposure region may be formed according to the pattern of a mask plate (reticle) used in the exposure device.

[0053] Figure 4A The first exposure area S1 of the exposure areas formed on the wafer WF is shown. The first exposure area S1 may include a plurality of chip groups CGa. Each of the chip groups CGa may include a first chip C1a and a second chip C2a. Each of the first chip C1a and the second chip C2a may be connected to Figure 3 The storage device 10 corresponds to the storage device 10. Figure 4A FIG. 4 shows that there are eight chip groups in the first exposure region S1 , but this is only an example. The first exposure region S1 may include fewer or more chip groups.

[0054] In some embodiments, the first chip C1a and the second chip C2a may be spaced apart from each other in the second direction D2. The first chip C1a and the second chip C2a may be arranged symmetrically along the scribe lane SCL with an origin. At this time, the scribe lane SCL between the first chip C1a and the second chip C2a may be divided into a first area AR1a, a second area AR2a, and a third area AR3a. The first area AR1a and the third area AR3a may be spaced apart from each other in the second direction D2, and the second area AR2a between the first area AR1a and the third area AR3a may be vertical. In other words, the second area AR2a of the scribe lane SCL may extend along the second direction D2.

[0055] In some embodiments, the line for division may be located in a scribe lane SCL. The semiconductor facility may focus the laser beam on the line for division, and may divide the wafer WF into a plurality of semiconductor chips along the line for division.

[0056] Figure 4B The second exposure region S2 is shown in the exposure region formed on the wafer WF. The second exposure region S2 may include a plurality of chip groups CGb. Each of the chip groups CGb may include a first chip C1b to a fourth chip C4b. Each of the first chip C1b to the fourth chip C4b may be connected to Figure 3 The storage device 10 corresponds to the storage device 10. Figure 4B FIG. 4 shows that there are four chip groups in the second exposure region S2, but this is only an example. The second exposure region S2 may include fewer or more chip groups.

[0057] In some embodiments, the first chip C1b to the fourth chip C4b may be spaced apart from each other in the second direction D2. The first chip C1b and the second chip C2b may be arranged symmetrically along the scribe lane SCL1b with an origin. The third chip C3b and the fourth chip C4b may be arranged symmetrically along the scribe lane SCL3b with an origin. The first chip C1b and the fourth chip C4b may be arranged symmetrically along the second scribe lane SCL2b. The second chip C2b and the third chip C3b may be arranged symmetrically along the second scribe lane SCL2b. At this time, the first scribe lane SCL1b between the first chip C1b and the second chip C2b may be divided into a first area AR1b, a second area AR2b, and a third area AR3b. The first area AR1b and the third area AR3b may be spaced apart from each other in the second direction D2, and the second area AR2b between the first area AR1b and the third area AR3b may be vertical. In other words, the second area AR2b of the first scribe lane SCL1b may extend along the second direction D2. Similar to the first scribe lane SCL1 b , the third scribe lane SCL3 b between the third chip C3 b and the fourth chip C4 b may be divided into three areas, and a redundant description thereof is omitted.

[0058] In some embodiments, the line for division may be located in each of the first to third scribe lanes SCL1b, SCL2b, and SCL3b. The semiconductor facility may focus the laser beam on the line for division and may divide the wafer WF into a plurality of semiconductor chips along the line for division.

[0059] Figure 4C The third exposure region S3 among the exposure regions formed on the wafer WF is shown. The third exposure region S3 may include a plurality of chip groups CGc. Each of the chip groups CGc may include a first chip C1c and a second chip C2c. In some embodiments, Figure 4C The third exposure area S3 in Figure 4A The first exposure area S1 in the embodiment is configured similarly. The scribe lane SCL between the first chip C1c and the second chip C2c may be divided into a first area AR1c, a second area AR2c, and a third area AR3c. The first area AR1c and the third area AR3c may be spaced apart from each other in the second direction D2, and the second area AR2c between the first area AR1c and the third area AR3c may be inclined.

[0060] In some embodiments, the line for division may be located in a scribe lane SCL. The semiconductor facility may focus the laser beam on the line for division, and may divide the wafer WF into a plurality of semiconductor chips along the line for division.

[0061] Figure 4DFIG. 4 shows a fourth exposure region S4 among the exposure regions formed on the wafer WF. The fourth exposure region S4 may include a plurality of chip groups CGd. Each of the chip groups CGd may include a first chip C1d to a fourth chip C4d. In some embodiments, Figure 4D The fourth exposure area S4 in Figure 4B The first scribe lane SCL1d between the first chip C1d and the second chip C2d may be divided into a first area AR1d, a second area AR2d, and a third area AR3d. The first area AR1d and the third area AR3d may be spaced apart from each other in the second direction D2, and the second area AR2d between the first area AR1d and the third area AR3d may be inclined. Similar to the first scribe lane SCL1d, the third scribe lane SCL3d between the third chip C3d and the fourth chip C4d may be divided into three areas, and a redundant description thereof is omitted.

[0062] In some embodiments, the line for division may be located in each of the first to third scribe lanes SCL1d, SCL2d, and SCL3d. The semiconductor facility may focus the laser beam on the line for division and may divide the wafer WF into a plurality of semiconductor chips along the line for division.

[0063] like 4A to 4D As shown, one side of each chip may protrude or extend, and the chips in the chipset may be arranged symmetrically or line-symmetrically with respect to each other. In this case, the chips may be arranged closer to each other in the second direction D2 than chips without protruding sides or extending sides (i.e., chips with rectangular top surfaces). In other words, assuming that the chipset includes the same number of chips, the length of each of the chipsets CGa and CGb in the second direction D2 may be reduced compared to the case where the chips do not have protruding sides or extending sides. Therefore, the length of each of the first exposure area S1 and the second exposure area S2 in the second direction D2 may be reduced compared to the case where the chips do not have protruding sides or extending sides. Therefore, according to some embodiments, when a pattern is formed on a wafer WF by using a mask having a pattern corresponding to the first exposure area S1 or the second exposure area S2, more semiconductor chips may be formed and the net die per wafer may be increased.

[0064] Figure 5A is a layout diagram of the first semiconductor layer L1 of the memory device 10 according to some embodiments. Figure 5B is a layout diagram of the second semiconductor layer L2 of the memory device 10 according to some embodiments.

[0065] refer to Figure 5A, the memory cell array 100 may be formed in the first semiconductor layer L1 of the memory device 10. The memory device 10 may include a protrusion structure 300. The protrusion structure 300 may be formed across the first semiconductor layer L1 and the second semiconductor layer L2. The protrusion structure 300 may include an input / output pad 310 formed in the first semiconductor layer L1.

[0066] The word lines in the memory cell array 100 may be activated independently of each other through a plurality of row decoders, and operations (e.g., write operations and read operations) of the memory cell array 100 may be controlled independently of each other through a plurality of page buffers. The memory cell array 100 may have a vertical stack structure. Specifically, the memory cell array 100 may have Figure 2 and Figure 3 The circuit configuration shown.

[0067] The memory device 10 may be electrically connected to an external device through the input / output pad 310. In some embodiments, the input / output pad 310 may be in an upper portion of at least a portion of the memory cell array 100. In other words, a portion of the memory cell array 100 vertically overlapping the input / output pad 310 may correspond to an upper portion of at least a portion of an outer region of the memory cell array 100 where a channel hole (not shown) is not arranged.

[0068] A plurality of input / output pad contacts (not shown) may be respectively under the input / output pads 310. The input / output pad contacts may respectively electrically connect the input / output pads 310 to the pad circuits 330 (at Figure 5B ). Refer to the following Fig. 6A and Figure 6B Describe the input / output pad contacts.

[0069] refer to Figure 5B , the peripheral circuit 200 and the pad circuit 330 may be formed in the second semiconductor layer L2. The peripheral circuit may be arranged according to the location of the memory cell array 100.

[0070] The page buffer PGBUF, the row decoder XDEC, and other peripheral circuits PERI may overlap the memory cell array 100 in a direction perpendicular to the substrate (e.g., the first direction D1). For example, the other peripheral circuits PERI may include a latch circuit, a cache circuit, or a sense amplifier. However, this is only one embodiment, and various modifications may be made therein.

[0071] The protrusion structure 300 may include a pad circuit 330 formed in the second semiconductor layer L2. In an embodiment, the pad circuit 330 may include an electrostatic discharge (ESD) circuit, a pull-up / pull-down driver, or a data input / output circuit.

[0072] Fig. 6A and Figure 6B is a cross-sectional view of a memory device 10 according to some embodiments. In detail, Fig. 6A is along Figure 3 1 is a cross-sectional view of the memory device 10 taken along line II′ in FIG. Figure 6B is along Figure 3 1 is a cross-sectional view of the memory device 10 taken along line II-II′ in FIG.

[0073] refer to Fig. 6A , the memory device 10 may include a memory cell array 100, a peripheral circuit 200, and a protruding structure 300. The memory cell array 100 may be formed on a first substrate SUB1. The protruding structure 300 may be formed across the first semiconductor layer L1 and the second semiconductor layer L2. The protruding structure 300 may include an input / output pad 310, a plurality of input / output pad contacts 320, and a pad circuit 330. The memory device 10 may be electrically connected to an external device through the input / output pad 310. The pad circuit 330 may be electrically connected to the input / output pad 310 through the input / output pad contact 320, and the input / output pad contact 320 passes through a portion of the first semiconductor layer L1 or extends into a portion of the first semiconductor layer L1.

[0074] The memory cell array 100 may include gate conductive layers GS spaced apart from each other. Fig. 6A and Figure 6B Only the first gate conductive layer GS1 to the sixth gate conductive layer GS6 are shown, but there may be fewer or more gate conductive layers. Each of the gate conductive layers GS may be divided by a word line cutting region 125, and the word line cutting region 125 has a width WLC. The second insulating film IL2 may be between the gate conductive layers GS. A plurality of channel structures CS may be insulated from each other by the first insulating film IL1. The channel holes CH may each extend through the gate conductive layer GS and the second insulating layer IL2 in a first direction perpendicular to the top surface of the first substrate SUB1. The bottom surface of each of the channel holes CH may contact the top surface of the first substrate SUB1. The channel holes CH may be spaced apart from each other in the second direction D2 and the third direction D3. A plurality of bit line contacts BC may electrically connect the channel structure CS to the bit line BL. The channel structure CS and the bit line BL may be covered with an upper insulating layer U_IL or overlap with the upper insulating layer U_IL.

[0075] In some embodiments, the channel holes CH may include polysilicon doped with impurities or polysilicon not doped with impurities. Each of the channel holes CH may have a cup shape (or a cylindrical shape having a closed bottom) extending in the first direction D1.

[0076] The peripheral circuit 200 and the pad circuit 330 may be formed on the second substrate SUB2. Each of the peripheral circuit 200 and the pad circuit 330 may include at least one transistor TR. The transistor TR, the lower contact portion 231, and the lower conductive line 233 may form the peripheral circuit 200 and the pad circuit 330. For example, the transistor TR may form Figure 1 The row decoder 240, the page buffer circuit 210, and the control circuit 220 in the second substrate SUB2 may be provided. Each of the transistors TR may include a gate insulating film 221, a gate electrode 223, a capping pattern 225, a gate spacer 227, and a source / drain region 229. The isolation film 211 may be in the second substrate SUB2. The isolation film 211 may define an active region in the second substrate SUB2. For example, the isolation film 211 may include silicon oxide.

[0077] The gate insulating film 221 may be between the gate electrode 223 and the second substrate SUB2. The capping pattern 225 may be on the gate electrode 223. The gate spacer 227 may cover the gate insulating film 221, the gate electrode 223, and the corresponding sidewalls of the capping pattern 225. The source / drain regions 229 may be in the second substrate SUB2 and adjacent to opposite sides of the gate electrode 223, respectively.

[0078] The lower wire 233 can be electrically connected to the transistor TR through the lower contact portion 231. For example, each of the transistors TR can correspond to an N-channel metal oxide semiconductor (NMOS) transistor or a P-channel MOS (PMOS) transistor. Each of the transistors TR can be a planar type or a full surround gate type. The lower contact portion 231 and the lower wire 233 can include a conductive material such as a metal. The peripheral circuit 200, the pad circuit 330, the lower contact portion 231 and the lower wire 233 can be covered by the lower insulating layer L_IL or overlapped with the lower insulating layer L_IL.

[0079] refer to Figure 6B , Figure 6B The memory device 10 may have Fig. 6A The memory device 10 has a similar structure. However, because Fig. 6A is a cross-sectional view of the memory device 10 taken along line II′ and Figure 6B is a cross-sectional view of the memory device 10 taken along line II-II', so the protruding structure 300 may not be Figure 6B Therefore, the third length LEN3 may be greater than the fourth length LEN4.

[0080] Fig. 7A and Figure 7B is a diagram showing a memory device according to an embodiment. In detail, Fig. 7A is a perspective view of memory package 2000a. Figure 7B is along Fig. 7A2 is a cross-sectional view of the memory package 2000 a taken along line III-III′ in FIG. Fig. 7A and Figure 7B You can refer to Figure 3 Description is made, and its redundant description may be omitted.

[0081] Fig. 7A and Figure 7B The memory package 2000a may include stacked along a first direction D1 Figure 3 A plurality of storage devices 10. Fig. 7A and Figure 7B The memory package 2000a may be an embodiment of a semiconductor package. Fig. 7A and Figure 7B Each of the first to fourth semiconductor chips 2200_1a to 2200_4a in the embodiment may be connected to Figure 3 Corresponding to the storage device 10.

[0082] refer to Fig. 7A , the memory package 2000a may include a package substrate 2100a. The package substrate 2100a may correspond to a printed circuit board (PCB). Figure 7B , the package substrate 2100a may include a package substrate body 2120a, a package upper pad 2130a, a package lower pad 2125a, and an internal wiring 2135a. The package upper pad 2130a may be exposed in the top surface of the package substrate body 2120a or by the top surface of the package substrate body 2120a. The package lower pad 2125a may be exposed in the bottom surface of the package substrate body 2120a or by the bottom surface of the package substrate body 2120a. The internal wiring 2135a may be in the package substrate body 2120a and may electrically connect the package upper pad 2130a to the package lower pad 2125a. The package upper pad 2130a may be electrically connected to the connection structure 2400a. The package lower pad 2125a may be connected to an external device through a conductive connector 2800a. In other words, the package substrate 2100a may be configured to electrically connect an external device to the memory package 2000a. The memory package 2000a may include adhesive layers 2300a on bottom surfaces of the first to fourth semiconductor chips 2200_1a to 2200_4a, respectively. The memory package 2000a may include a molding layer 2500a on a package substrate 2100a to cover or overlap the first to fourth semiconductor chips 2200_1a to 2200_4a and the connection structure 2400a.

[0083] Each of the first semiconductor chip 2200_1a to the fourth semiconductor chip 2200_4a may include a semiconductor substrate 3010a, a first structure 3100a and a second structure 3200a, wherein the first structure 3100a and the second structure 3200a are sequentially stacked on the semiconductor substrate 3010a. The first structure 3100a may include a peripheral circuit region, and the peripheral circuit region includes a peripheral wiring 3110a. The second structure 3200a may include a source structure 3205a, a stacked structure 3210a on the source structure 3205a, a vertical structure 3220a, an isolation structure 3230a, and a bit line 3240a electrically connected to the vertical structure 3220a, wherein the vertical structure 3220a and the isolation structure 3230a pass through the stacked structure 3210a. Although Fig. 7A and Figure 7B Only four semiconductor chips are shown in FIG. 2 , but this is merely an example, and the memory package 2000 a may include fewer or more semiconductor chips.

[0084] Each of the first semiconductor chip 2200_1a to the fourth semiconductor chip 2200_4a may include a through wiring 3245a, which is electrically connected to the peripheral wiring 3110a of the first structure 3100a and extends into the second structure 3200a. The through wiring 3245a may pass through the stacked structure 3210a or extend into the stacked structure 3210a. Although not shown, the through wiring 3245a may be outside the stacked structure 3210a. Each of the first semiconductor chip 2200_1a to the fourth semiconductor chip 2200_4a may also include an input / output pad electrically connected to the peripheral wiring 3110a of the first structure 3100a.

[0085] Each of the first to fourth semiconductor chips 2200_1a to 2200_4a may include an input / output pad 2210a. The input / output pad 2210a may be connected to Figure 3 Each of the first to fourth semiconductor chips 2200_1a to 2200_4a may include an input / output contact portion 3265a. The input / output contact portions 3265a may be connected to the respective Fig. 6A Corresponding to the input / output contact portion 320 in.

[0086] The first semiconductor chip 2200_1a may include a first protruding structure 2300_1a. The first semiconductor chip 2200_1a may be stacked on the package substrate 2100a along the first direction D1. The first semiconductor chip 2200_1a may include a first surface and a second surface spaced apart from each other in the second direction D2. The first semiconductor chip 2200_1a may include a third surface and a fourth surface extending from the first surface to the second surface. The first protruding structure 2300_1a may protrude or extend outward from the first surface of the first semiconductor chip 2200_1a. The first semiconductor chip 2200_1a may have a COP structure. Fig. 7A and Figure 7B , a layer in an upper portion of the first semiconductor chip 2200_1 a may be referred to as a first semiconductor layer, and a layer in a lower portion of the first semiconductor chip 2200_1 a may be referred to as a second semiconductor layer.

[0087] The second semiconductor chip 2200_2a may include a second protruding structure 2300_2a. The second semiconductor chip 2200_2a may be stacked on the first semiconductor chip 2200_1a along the first direction D1. The second semiconductor chip 2200_2a may include a fifth surface and a sixth surface spaced apart from each other in the second direction D2. The second semiconductor chip 2200_2a may include a seventh surface and an eighth surface extending from the fifth surface to the sixth surface. The second protruding structure 2300_2a may protrude or extend outward from the fifth surface of the second semiconductor chip 2200_2a. The second semiconductor chip 2200_2a may have a COP structure. Fig. 7A and Figure 7B , a layer in an upper portion of the second semiconductor chip 2200_2a may be referred to as a third semiconductor layer, and a layer in a lower portion of the second semiconductor chip 2200_2a may be referred to as a fourth semiconductor layer.

[0088] In some embodiments, one side surface of the first protrusion structure 2300_1a may be coplanar with the third surface. One side surface of the second protrusion structure 2300_2a may be coplanar with the seventh surface. The third surface may be coplanar with the seventh surface.

[0089] In some embodiments, the second semiconductor chip 2200_2a may be stacked on the first semiconductor chip 2200_1a such that the first surface of the first semiconductor chip 2200_1a is closer to the fifth surface of the second semiconductor chip 2200_2a than the second surface of the first semiconductor chip 2200_1a. In addition, the second semiconductor chip 2200_2a may be stacked on the first semiconductor chip 2200_1a such that the third surface of the first semiconductor chip 2200_1a is closer to the seventh surface of the second semiconductor chip 2200_2a than the fourth surface of the first semiconductor chip 2200_1a.

[0090] In some embodiments, the second semiconductor chip 2200_2a may be stacked on the first semiconductor chip 2200_1a in a step shape along the first direction D1. A bottom surface of the second protrusion structure 2300_2a may not overlap a top surface of the first protrusion structure 2300_1a.

[0091] In some embodiments, the length of the first protrusion structure 2300_1a in the third direction D3 may be less than half the length of the first semiconductor chip 2200_1a in the third direction D3. The length of the second protrusion structure 2300_2a in the third direction D3 may be less than half the length of the second semiconductor chip 2200_2a in the third direction D3.

[0092] In some embodiments, the length of the third surface coplanar with one side surface of the first protruding structure 2300_1a in the second direction D2 may be greater than the length of the fourth surface facing the third surface in the second direction D2. The length of the seventh surface coplanar with one side surface of the second protruding structure 2300_2a in the second direction D2 may be greater than the length of the eighth surface facing the seventh surface in the second direction D2.

[0093] The third semiconductor chip 2200_3a may include a third protrusion structure 2300_3a, and the fourth semiconductor chip 2200_4a may include a fourth protrusion structure 2300_4a. The third and fourth semiconductor chips 2200_3a and 2200_4a may be stacked in a manner similar to the first and second semiconductor chips 2200_1a and 2200_2a, and thus, redundant descriptions thereof are omitted.

[0094] Fig. 8A and Figure 8B is a diagram showing a memory device according to some embodiments. In detail, Fig. 8A is a perspective view of memory package 2000b. Figure 8B is along Fig. 8A 2 is a cross-sectional view of the memory package 2000 b taken along line IV-IV′ in FIG. Fig. 8A and Figure 8BYou can refer to Figure 3 , Fig. 7A and Figure 7B Description is made, and its redundant description may be omitted.

[0095] Fig. 8A and Figure 8B The memory package 2000b may have Fig. 7A and Figure 7B The memory package 2000a is similar in configuration. However, Fig. 8A and Figure 8B The first to fourth semiconductor chips 2200_1b to 2200_4b of the memory package 2000b may be connected to Fig. 7A and Figure 7B The first to fourth semiconductor chips 2200_1 a to 2200_4 a of the memory package 2000 a have different structures stacked on one another.

[0096] The first semiconductor chip 2200_1b may include a first protruding structure 2300_1b. The first semiconductor chip 2200_1b may be stacked on the package substrate 2100b along the first direction D1. The first semiconductor chip 2200_1b may include a first surface and a second surface spaced apart from each other in the second direction D2. The first semiconductor chip 2200_1b may include a third surface and a fourth surface extending from the first surface to the second surface. The first protruding structure 2300_1b may protrude or extend outward from the first surface of the first semiconductor chip 2200_1b. The first semiconductor chip 2200_1b may have a COP structure. Fig. 8A and Figure 8B , a layer in an upper portion of the first semiconductor chip 2200_1 b may be referred to as a first semiconductor layer, and a layer in a lower portion of the first semiconductor chip 2200_1 b may be referred to as a second semiconductor layer.

[0097] The second semiconductor chip 2200_2b may include a second protruding structure 2300_2b. The second semiconductor chip 2200_2b may be stacked on the first semiconductor chip 2200_1b along the first direction D1. The second semiconductor chip 2200_2b may include a fifth surface and a sixth surface spaced apart from each other in the second direction D2. The second semiconductor chip 2200_2b may include a seventh surface and an eighth surface extending from the fifth surface to the sixth surface. The second protruding structure 2300_2b may protrude or extend outward from the fifth surface of the second semiconductor chip 2200_2b. The second semiconductor chip 2200_2b may have a COP structure. Fig. 8A and Figure 8B, a layer in an upper portion of the second semiconductor chip 2200_2 b may be referred to as a third semiconductor layer, and a layer in a lower portion of the second semiconductor chip 2200_2 b may be referred to as a fourth semiconductor layer.

[0098] In some embodiments, one side surface of the first protruding structure 2300_1b may be coplanar with the third surface. One side surface of the second protruding structure 2300_2b may be coplanar with the eighth surface. The third surface may be spaced apart from the eighth surface in the third direction D3. In other words, the third surface may not be coplanar with the eighth surface.

[0099] In some embodiments, the length of the first protrusion structure 2300_1b in the third direction D3 may be less than half the length of the first semiconductor chip 2200_1b in the third direction D3. The length of the second protrusion structure 2300_2b in the third direction D3 may be less than half the length of the second semiconductor chip 2200_2b in the third direction D3.

[0100] In some embodiments, the length of the third surface coplanar with one side surface of the first protruding structure 2300_1b in the second direction D2 may be greater than the length of the fourth surface facing the third surface in the second direction D2. The length of the eighth surface coplanar with one side surface of the second protruding structure 2300_2b in the second direction D2 may be greater than the length of the seventh surface facing the eighth surface in the second direction D2.

[0101] The third semiconductor chip 2200_3b may include a third protruding structure 2300_3b. The third semiconductor chip 2200_3b may be stacked on the second semiconductor chip 2200_2b along the first direction D1. The third semiconductor chip 2200_3b may include a ninth surface and a tenth surface spaced apart from each other in the second direction D2. The third semiconductor chip 2200_3b may include an eleventh surface and a twelfth surface extending from the ninth surface to the tenth surface. The third protruding structure 2300_3b may protrude or extend outward from the ninth surface of the third semiconductor chip 2200_3b. The third semiconductor chip 2200_3b may have a COP structure. Fig. 8A and Figure 8B In some embodiments, the third protrusion structure 2300_3b may be spaced apart from the first protrusion structure 2300_1b in the second direction D2, and may be spaced apart from the second protrusion structure 2300_2b in the third direction D3.

[0102] The fourth semiconductor chip 2200_4b may include a fourth protrusion structure 2300_4b. The fourth semiconductor chip 2200_4b may be stacked on the third semiconductor chip 2200_3b in the same manner as the second semiconductor chip 2200_2b is stacked on the first semiconductor chip 2200_1b, and thus, a redundant description thereof is omitted.

[0103] When Fig. 8A and Figure 8B When the first to fourth semiconductor chips 2200_1 b to 2200_4 b are stacked as shown, the size of the memory package 2000 b in the second direction D2 may be reduced. Therefore, the memory package 2000 b may be miniaturized.

[0104] Fig. 9 is a diagram illustrating a memory device 1500 according to some embodiments of the present disclosure.

[0105] refer to Fig. 9 , the memory device 1500 may have a C2C structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, at least one upper chip and a lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0106] The memory device 1500 may include at least one upper chip including a cell region. Fig. 9 As shown, the memory device 1500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 1500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 1500. The first upper chip may be flipped or inverted, and then may be connected to the lower chip by a bonding method, and the second upper chip may also be flipped or inverted, and then may be connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped. In other words, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion defined based on the +Z axis direction. Fig. 9 The upper portion is defined in the -Z-axis direction. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0107] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 1500 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0108] The peripheral circuit region PERI may include a first substrate 1210 and a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210. An interlayer insulating layer 1215 including one or more insulating layers may be disposed on the plurality of circuit elements 1220a, 1220b, and 1220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 1220a, 1220b, and 1220c may be disposed in the interlayer insulating layer 1215. For example, the plurality of metal lines may include first metal lines 1230a, 1230b, and 1230c connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal lines 1240a, 1240b, and 1240c formed on the first metal lines 1230a, 1230b, and 1230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 1230 a , 1230 b , and 1230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 1240 a , 1240 b , and 1240 c may be formed of copper having a relatively low resistivity.

[0109] In the present embodiment, the first metal lines 1230a, 1230b and 1230c and the second metal lines 1240a, 1240b and 1240c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 1240a, 1240b and 1240c. In this case, the second metal lines 1240a, 1240b and 1240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 1240a, 1240b and 1240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 1240a, 1240b and 1240c.

[0110] The interlayer insulating layer 1215 may be disposed on the first substrate 1210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0111] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 1310 and a common source line 1320. A plurality of word lines 1330 (1331, 1332, ..., 1337, and 1338) may be stacked on the second substrate 1310 in a direction perpendicular to the top surface of the second substrate 1310 (i.e., the Z-axis direction). The string selection line and the ground selection line may be disposed above and below the word line 1330, and the plurality of word lines 1330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 1410 and a common source line 1420, and a plurality of word lines 1430 (1431, 1432, ..., 1437, and 1438) may be stacked on the third substrate 1410 in a direction perpendicular to the top surface of the third substrate 1410 (i.e., the Z-axis direction). Each of the second substrate 1310 and the third substrate 1410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0112] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 1310 to penetrate the word line 1330, the string selection line, and the ground selection line or extend into the word line 1330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 1350c and the second metal line 1360c in the bit line bonding region BLBA. For example, the second metal line 1360c may be a bit line and may be connected to the channel structure CH through the first metal line 1350c. The bit line 1360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 1310.

[0113] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming a lower channel LCH and a process of forming an upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 1310 to penetrate the common source line 1320 and the lower word lines 1331 and 1332 or extend into the common source line 1320 and the lower word lines 1331 and 1332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 1333 to 1338 or extend into the upper word lines 1333 to 1338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 1350c and the second metal line 1360c. As the length of the channel increases and due to the characteristics of the manufacturing process, it may be difficult to form a channel having a substantially uniform width. The memory device 1500 according to the present embodiment may include a channel having improved width uniformity due to the lower channel LCH and the upper channel UCH formed by sequentially performed processes.

[0114] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 1332 and 1333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in a memory cell connected to the dummy word line. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the general word line, and thus the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0115] At the same time, in the region "A2", the number of lower word lines 1331 and 1332 penetrated or extended to by the lower channel LCH is less than the number of upper word lines 1333 to 1338 penetrated or extended to by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated or extended to by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CELL1.

[0116] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Fig. 9 As shown, the first through electrode THV1 may penetrate the common source line 1320 and the plurality of word lines 1330 or extend into the common source line 1320 and the plurality of word lines 1330. In some embodiments, the first through electrode THV1 may also penetrate the second substrate 1310 or extend into the second substrate 1310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0117] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 1372d and the second through metal pattern 1472d. The first through metal pattern 1372d may be formed at the bottom end of the first upper chip including the first cell area CELL1, and the second through metal pattern 1472d may be formed at the top end of the second upper chip including the second cell area CELL2. The first through electrode THV1 may be electrically connected to the first metal line 1350c and the second metal line 1360c. The lower via 1371d may be formed between the first through electrode THV1 and the first through metal pattern 1372d, and the upper via 1471d may be formed between the second through electrode THV2 and the second through metal pattern 1472d. The first through metal pattern 1372d and the second through metal pattern 1472d may be connected to each other by a bonding method.

[0118] In addition, in the bit line bonding area BLBA, an upper metal pattern 1252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 1392 having the same shape as the upper metal pattern 1252 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 1392 of the first cell area CELL1 and the upper metal pattern 1252 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 1360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some circuit elements 1220c of the peripheral circuit area PERI may constitute a page buffer, and the bit line 1360c may be electrically connected to the circuit element 1220c constituting the page buffer through the upper bonding metal pattern 1370c of the first cell area CELL1 and the upper bonding metal pattern 1270c of the peripheral circuit area PERI.

[0119] Continue to refer Fig. 9In the word line bonding area WLBA, the word line 1330 of the first cell area CELL1 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the second substrate 1310 and may be connected to a plurality of cell contact plugs 1340 (1341, 1342, ..., 1346, and 1347). The first metal line 1350b and the second metal line 1360b may be sequentially connected to the cell contact plugs 1340 connected to the word line 1330. In the word line bonding area WLBA, the cell contact plugs 1340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 1370b of the first cell area CELL1 and the upper bonding metal pattern 1270b of the peripheral circuit area PERI.

[0120] The cell contact plug 1340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 1220b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 1340 may be electrically connected to the circuit element 1220b constituting the row decoder through the upper bonding metal pattern 1370b of the first cell region CELL1 and the upper bonding metal pattern 1270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 1220b constituting the row decoder may be different from the operating voltage of the circuit element 1220c constituting the page buffer. For example, the operating voltage of the circuit element 1220c constituting the page buffer may be greater than the operating voltage of the circuit element 1220b constituting the row decoder.

[0121] Likewise, in the word line bonding area WLBA, the word lines 1430 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 1410, and may be connected to a plurality of cell contact plugs 1440 (1441, 1442, ..., 1446, and 1447). The cell contact plugs 1440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower and upper metal patterns of the first cell area CELL1 and the cell contact plugs 1348.

[0122] In the word line bonding area WLBA, the upper bonding metal pattern 1370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 1270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 1370b of the first cell area CELL1 and the upper bonding metal pattern 1270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 1370b and the upper bonding metal pattern 1270b may be formed of aluminum, copper, or tungsten.

[0123] In the external pad bonding area PA, a lower metal pattern 1371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 1472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 1371e of the first cell area CELL1 and the upper metal pattern 1472a of the second cell area CELL2 may be connected to each other by a bonding method in the external pad bonding area PA. Similarly, an upper metal pattern 1372a may be formed in an upper portion of the first cell area CELL1, and an upper metal pattern 1272a may be formed in an upper portion of the peripheral circuit area PERI. The upper metal pattern 1372a of the first cell area CELL1 and the upper metal pattern 1272a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0124] Common source line contact plugs 1380 and 1480 may be disposed in the external pad bonding area PA. Common source line contact plugs 1380 and 1480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. Common source line contact plugs 1380 of the first cell area CELL1 may be electrically connected to the common source line 1320, and common source line contact plugs 1480 of the second cell area CELL2 may be electrically connected to the common source line 1420. First metal lines 1350a and second metal lines 1360a may be sequentially stacked on the common source line contact plugs 1380 of the first cell area CELL1, and first metal lines 1450a and second metal lines 1460a may be sequentially stacked on the common source line contact plugs 1480 of the second cell area CELL2.

[0125] The input / output pads 1205, 1405, and 1406 may be disposed in the external pad landing area PA. Fig. 9 , the lower insulating layer 1201 may cover or overlap the bottom surface of the first substrate 1210, and the first input / output pad 1205 may be formed on the lower insulating layer 1201. The first input / output pad 1205 may be connected to at least one of the plurality of circuit elements 1220a provided in the peripheral circuit region PERI through the first input / output contact plug 1203, and may be separated from the first substrate 1210 by the lower insulating layer 1201. In addition, a side insulating layer may be provided between the first input / output contact plug 1203 and the first substrate 1210 to electrically isolate the first input / output contact plug 1203 from the first substrate 1210.

[0126] An upper insulating layer 1401 covering or overlapping a top surface of the third substrate 1410 may be formed on the third substrate 1410. Second input / output pads 1405 and / or third input / output pads 1406 may be disposed on the upper insulating layer 1401. The second input / output pads 1405 may be connected to at least one of the plurality of circuit elements 1220a disposed in the peripheral circuit region PERI through second input / output contact plugs 1403 and 1303, and the third input / output pads 1406 may be connected to at least one of the plurality of circuit elements 1220a disposed in the peripheral circuit region PERI through third input / output contact plugs 1404 and 1304.

[0127] In some embodiments, the third substrate 1410 may not be disposed in a region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 1404 may be separated from the third substrate 1410 in a direction parallel to the top surface of the third substrate 1410, and may penetrate the interlayer insulating layer 1415 of the second cell region CELL2 or extend into the interlayer insulating layer 1415 of the second cell region CELL2 to be connected to the third input / output pad 1406. In this case, the third input / output contact plug 1404 may be formed by at least one of various processes.

[0128] In some embodiments, as shown in region “B1”, the third input / output contact plug 1404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 1404 may gradually increase toward the upper insulating layer 1401. In other words, the diameter of the channel structure CH described in region “A1” may gradually decrease toward the upper insulating layer 1401, but the diameter of the third input / output contact plug 1404 may gradually increase toward the upper insulating layer 1401. For example, the third input / output contact plug 1404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method.

[0129] In some embodiments, as shown in region "B2", the third input / output contact plug 1404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 1404 may gradually decrease toward the upper insulating layer 1401. In other words, similar to the channel structure CH, the diameter of the third input / output contact plug 1404 may gradually decrease toward the upper insulating layer 1401. For example, the third input / output contact plug 1404 may be formed together with the cell contact plug 1440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0130] In some embodiments, the input / output contact plug may overlap the third substrate 1410. For example, as shown in region "C", the second input / output contact plug 1403 may penetrate the interlayer insulating layer 1415 of the second cell region CELL2 in a third direction (e.g., Z-axis direction) and may be electrically connected to the second input / output pad 1405 through the third substrate 1410. In this case, the connection structure of the second input / output contact plug 1403 and the second input / output pad 1405 may be implemented by various methods.

[0131] In some embodiments, as shown in region “C1”, an opening 1408 may be formed to penetrate the third substrate 1410, and the second input / output contact plug 1403 may be directly connected to the second input / output pad 1405 through the opening 1408 formed in the third substrate 1410. In this case, as shown in region “C1”, the diameter of the second input / output contact plug 1403 may gradually increase toward the second input / output pad 1405. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 1403 may gradually decrease toward the second input / output pad 1405.

[0132] In some embodiments, as shown in region “C2”, an opening 1408 penetrating through the third substrate 1410 or extending into the third substrate 1410 may be formed, and a contact portion 1407 may be formed in the opening 1408. One end of the contact portion 1407 may be connected to the second input / output pad 1405, and the other end of the contact portion 1407 may be connected to the second input / output contact plug 1403. Therefore, the second input / output contact plug 1403 may be electrically connected to the second input / output pad 1405 through the contact portion 1407 in the opening 1408. In this case, as shown in region “C2”, the diameter of the contact portion 1407 may gradually increase toward the second input / output pad 1405, and the diameter of the second input / output contact plug 1403 may gradually decrease toward the second input / output pad 1405. For example, the second input / output contact plug 1403 may be formed together with the cell contact plug 1440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact portion 1407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0133] In some embodiments shown in region "C3", compared to the embodiment of region "C2", a blocking member 1409 may also be formed on the bottom end of the opening 1408 of the third substrate 1410. The blocking member 1409 may be a metal line formed in the same layer as the common source line 1420. Alternatively, the blocking member 1409 may be a metal line formed in the same layer as the at least one word line 430. The second input / output contact plug 1403 may be electrically connected to the second input / output pad 1405 through the contact portion 1407 and the blocking member 1409.

[0134] Similar to the second input / output contact plug 1403 and the third input / output contact plug 1404 of the second cell region CELL2, a diameter of each of the second input / output contact plug 1303 and the third input / output contact plug 1304 of the first cell region CELL1 may gradually decrease toward the lower metal pattern 1371e or may gradually increase toward the lower metal pattern 1371e.

[0135] Meanwhile, in some embodiments, the slit 1411 may be formed in the third substrate 1410. For example, the slit 1411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 1411 may be located between the second input / output pad 1405 and the cell contact plug 1440. Alternatively, when viewed in a plan view, the second input / output pad 1405 may be located between the slit 1411 and the cell contact plug 1440.

[0136] In some embodiments, as shown in region "D1", the slit 1411 may be formed to penetrate the third substrate 1410 or extend into the third substrate 1410. For example, the slit 1411 may be used to prevent or inhibit the occurrence of fine cracks in the third substrate 1410 when forming the opening 1408. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slit 1411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 1410.

[0137] In some embodiments, as shown in region "D2", a conductive material 1412 may be formed in the slit 1411. For example, the conductive material 1412 may be used to discharge leakage current occurring in driving of the circuit element in the external pad bonding region PA to the outside. In this case, the conductive material 1412 may be connected to an external ground line.

[0138] In some embodiments, as shown in the region "D3", the insulating material 1413 may be formed in the slit 1411. For example, the insulating material 1413 may be used to electrically isolate the second input / output pad 1405 and the second input / output contact plug 1403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 1413 is formed in the slit 1411, it is possible to prevent or inhibit a voltage provided through the second input / output pad 1405 from affecting a metal layer disposed on the third substrate 1410 in the word line bonding region WLBA.

[0139] Meanwhile, in some embodiments, the first to third input / output pads 1205, 1405, and 1406 may be selectively formed. For example, the memory device 1500 may be implemented to include only the first input / output pad 1205 disposed on the first substrate 1210, only the second input / output pad 1405 disposed on the third substrate 1410, or only the third input / output pad 1406 disposed on the upper insulating layer 1401.

[0140] In some embodiments, at least one of the second substrate 1310 of the first cell region CELL1 or the third substrate 1410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 1310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then an insulating layer covering or overlapping the top surface of the common source line 1320 or a conductive layer for connection may be formed. Similarly, the third substrate 1410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 1401 covering or overlapping the top surface of the common source line 1420 or a conductive layer for connection may be formed.

[0141] Fig.10 is a block diagram of an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system 4000 .

[0142] refer to Fig.10, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange a signal SIG with the host 4100 through a signal connector, and may receive power PWR through a power connector. The SSD 4200 may include an SSD controller 4210, an auxiliary power supply 4220, and storage devices 4230, 4240, and 4250. Each of the storage devices 4230, 4240, and 4250 may correspond to a vertically stacked NAND flash memory device. In some embodiments, each of the storage devices 4230, 4240, and 4250 may be configured by using the above reference Figures 1 to 9 The described embodiments are implemented.

[0143] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A nonvolatile memory device, comprising: substrate; a first semiconductor layer comprising a memory cell array on the substrate, wherein the memory cell array comprises a plurality of gate conductive layers and defines a plurality of channel holes, wherein the plurality of gate conductive layers are spaced apart in a first direction perpendicular to a top surface of the substrate, and wherein each of the plurality of channel holes extends into the plurality of gate conductive layers; a second semiconductor layer including a peripheral circuit configured to write data to or read data from the memory cell array, wherein the second semiconductor layer is on the first semiconductor layer; and A protruding structure comprising wiring extending into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, wherein the protruding structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and wherein the protruding structure extends along a second direction perpendicular to the first direction.

2. The nonvolatile memory device according to claim 1, wherein: The second surface of the first semiconductor layer is spaced apart from the first surface of the first semiconductor layer in the first direction; The second surface of the second semiconductor layer is spaced apart from the first surface of the second semiconductor layer in the first direction; A side surface of the protruding structure is perpendicular to the first surface of the first semiconductor layer and the first surface of the second semiconductor layer; The side surface of the protruding structure is coplanar with the third surface of the first semiconductor layer and the third surface of the second semiconductor layer; The third surface of the first semiconductor layer is perpendicular to the second surface of the first semiconductor layer; as well as The third surface of the second semiconductor layer is perpendicular to the second surface of the second semiconductor layer.

3. The nonvolatile memory device according to claim 2, wherein: The protruding structure comprises: a plurality of input / output pads on the first semiconductor layer and configured to electrically connect the nonvolatile memory device to an external device; a pad circuit in the second semiconductor layer and electrically connected to the peripheral circuit; and A plurality of input / output pad contacts extend into the first semiconductor layer and are configured to electrically connect the plurality of input / output pads to the pad circuit.

4. The nonvolatile memory device according to claim 3, wherein: The peripheral circuit and the pad circuit at least partially overlap each other in the second direction.

5. The nonvolatile memory device according to claim 2, wherein: The memory cell array further comprises: a plurality of cell strings, comprising a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, the plurality of word lines being electrically connected to the plurality of memory cells, the plurality of bit lines being electrically connected to first ends of corresponding cell strings among the plurality of cell strings, The plurality of word lines extend along a third direction perpendicular to the first direction and the second direction, and Wherein, the plurality of bit lines extend along the second direction.

6. The nonvolatile memory device according to claim 2, wherein: The fourth surface of the first semiconductor layer is opposite to the third surface of the first semiconductor layer; The fourth surface of the second semiconductor layer is opposite to the third surface of the second semiconductor layer; The length of the third surface of the first semiconductor layer in the second direction is greater than the length of the fourth surface of the first semiconductor layer in the second direction; as well as A length of the third surface of the second semiconductor layer in the second direction is greater than a length of the fourth surface of the second semiconductor layer in the second direction.

7. The nonvolatile memory device according to claim 1, wherein: A length of the protruding structure in a third direction perpendicular to the first direction and the second direction is smaller than half of a length of the first semiconductor layer in the third direction or smaller than half of a length of the second semiconductor layer in the third direction.

8. A memory package, comprising: a package substrate configured to electrically connect an external device to the memory package; a first memory device extending in a first direction perpendicular to a top surface of the package substrate, wherein the first memory device includes a first surface, a second surface, a third surface, and a fourth surface, wherein the first surface is spaced apart from the second surface in a second direction perpendicular to the first direction, and wherein the third surface and the fourth surface extend from the first surface to the second surface; and a second storage device comprising a fifth surface, a sixth surface, a seventh surface, and an eighth surface, wherein the fifth surface is spaced apart from the sixth surface in the second direction, and wherein the seventh surface and the eighth surface extend from the fifth surface to the sixth surface, wherein the first storage device comprises a first protruding structure extending from the first surface, wherein the second storage device comprises a second protruding structure extending from the fifth surface, wherein the second storage device is on the first storage device, and Wherein, a bottom surface of the second protrusion structure overlaps with at least a portion of the first storage device in the first direction.

9. The memory package of claim 8, wherein: The first memory device includes a first peripheral circuit; The second storage device includes a second peripheral circuit; The first protruding structure comprises: a first semiconductor layer; a second semiconductor layer; a plurality of first input / output pads on the first semiconductor layer and configured to electrically connect the first memory device to the external device; a first pad circuit in the second semiconductor layer and electrically connected to the first peripheral circuit; and a plurality of first input / output pad contacts extending into the first semiconductor layer and configured to electrically connect the plurality of first input / output pads to the first pad circuit, and The second protruding structure comprises: a third semiconductor layer; a fourth semiconductor layer; a plurality of second input / output pads on the third semiconductor layer and configured to electrically connect the second memory device to the external device; a second pad circuit in the fourth semiconductor layer and electrically connected to the second peripheral circuit; and A plurality of second input / output pad contacts extend into the third semiconductor layer and are configured to electrically connect the plurality of second input / output pads to the second pad circuit.

10. The memory package of claim 8, wherein: A side surface of the first protruding structure is coplanar with the third surface, a side surface of the second protruding structure is coplanar with the seventh surface, and the third surface is coplanar with the seventh surface.

11. The memory package of claim 8, wherein: The first surface of the first storage device is closer to the fifth surface of the second storage device than the second surface of the first storage device, and The third surface of the first storage device is closer to the seventh surface of the second storage device than the fourth surface of the first storage device.

12. The memory package of claim 10, wherein: The length of the first protruding structure in a third direction perpendicular to the first direction and the second direction is less than half of the length of the first storage device in the third direction, and The length of the second protrusion structure in the third direction is less than half of the length of the second storage device in the third direction.

13. The memory package of claim 10, wherein: The length of the third surface in the second direction is greater than the length of the fourth surface in the second direction, and A length of the seventh surface in the second direction is greater than a length of the eighth surface in the second direction.

14. The memory package of claim 8, wherein: The second storage device partially overlaps the first storage device in the first direction, and The bottom surface of the second protrusion structure does not overlap with the top surface of the first protrusion structure in the first direction.

15. A memory package, comprising: a package substrate configured to electrically connect an external device to the memory package; a first memory device extending in a first direction perpendicular to a top surface of the package substrate, wherein the first memory device includes a first surface, a second surface, a third surface, and a fourth surface, wherein the first surface is spaced apart from the second surface in a second direction perpendicular to the first direction, and wherein the third surface and the fourth surface extend from the first surface to the second surface; and a second storage device comprising a fifth surface, a sixth surface, a seventh surface, and an eighth surface, wherein the fifth surface is spaced apart from the sixth surface in the second direction, and wherein the seventh surface and the eighth surface extend from the fifth surface to the sixth surface, wherein the first storage device comprises a first protruding structure extending from the first surface, wherein the second storage device comprises a second protruding structure extending from the fifth surface, wherein the second storage device at least partially overlaps with the first storage device in the first direction, and The first protruding structure is spaced apart from the second protruding structure in a third direction perpendicular to the first direction and the second direction.

16. The memory package of claim 15, wherein: The first memory device includes a first peripheral circuit; The second storage device includes a second peripheral circuit; The first protruding structure comprises: a first semiconductor layer; a second semiconductor layer; a plurality of first input / output pads on the first semiconductor layer and configured to electrically connect the first memory device to the external device; a first pad circuit in the second semiconductor layer and electrically connected to the first peripheral circuit; and a plurality of first input / output pad contacts extending into the first semiconductor layer and configured to electrically connect the plurality of first input / output pads to the first pad circuit, and The second protruding structure comprises: a third semiconductor layer; a fourth semiconductor layer; a plurality of second input / output pads on the third semiconductor layer and configured to electrically connect the second memory device to the external device; a second pad circuit in the fourth semiconductor layer and electrically connected to the second peripheral circuit; and A plurality of second input / output pad contacts extend into the third semiconductor layer and are configured to electrically connect the plurality of second input / output pads to the second pad circuit.

17. The memory package of claim 15, wherein: A side surface of the first protruding structure is coplanar with the third surface, a side surface of the second protruding structure is coplanar with the eighth surface, and the third surface is spaced apart from the eighth surface in the third direction.

18. The memory package of claim 15, wherein: The length of the first protruding structure in the third direction is less than half of the length of the first storage device in the third direction, and The length of the second protrusion structure in the third direction is less than half of the length of the second storage device in the third direction.

19. The memory package of claim 15, wherein: The length of the third surface in the second direction is greater than the length of the fourth surface in the second direction, and A length of the eighth surface in the second direction is greater than a length of the seventh surface in the second direction.

20. The memory package of claim 15, further comprising: a third storage device comprising a ninth surface, a tenth surface, an eleventh surface, and a twelfth surface, wherein the ninth surface is spaced apart from the tenth surface in the second direction, and wherein the eleventh surface and the twelfth surface extend from the ninth surface to the tenth surface, Wherein, the third storage device further includes a third protruding structure extending from the ninth surface, wherein the third protruding structure overlaps with the first protruding structure in the second direction and is spaced apart from the second protruding structure in the third direction, and The third storage device at least partially overlaps with the second storage device in the first direction.

Images