Semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of suppressing current collapse. The semiconductor device includes: a barrier layer having a nitrogen polarity on an upper surface thereof; the channel layer is located on the barrier layer, and the upper surface of the channel layer has nitrogen polarity; the first cap layer is located on the channel layer, and the upper surface of the first cap layer has nitrogen polarity; and a dielectric film in contact with the upper surface of the first cap layer, the first cap layer being an aluminum nitride layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) has been proposed in which a channel layer is formed on a barrier layer.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2005 / 119787

[0006] In recent years, there has been an increasing demand for suppression of current collapse. Summary of the invention

[0007] An object of the present disclosure is to provide a semiconductor device capable of suppressing current collapse.

[0008] The semiconductor device disclosed in the present invention comprises: a barrier layer, the upper surface of which has nitrogen polarity; a channel layer, which is located on the barrier layer, the upper surface of which has nitrogen polarity; a first cap layer, which is located on the channel layer, the upper surface of which has nitrogen polarity; and a dielectric film, which is in contact with the upper surface of the first cap layer, and the first cap layer is an aluminum nitride layer.

[0009] Effects of the Invention

[0010] According to the present disclosure, current collapse can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0012] Figure 2 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 1).

[0013] Figure 3 This is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 2).

[0014] Figure 4 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 3).

[0015] Figure 5 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (Part 4).

[0016] Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 5).

[0017] Figure 7 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (the sixth).

[0018] Figure 8 This is a cross-sectional view showing the basic structure of an epitaxial substrate used in the experiment.

[0019] Fig. 9 This is a diagram showing an atomic force microscope image (part 1).

[0020] Fig.10 This is a diagram showing an atomic force microscope image (part 2).

[0021] Fig.11 This is a graph showing the relationship between aluminum composition and sheet resistance.

[0022] Fig.12 This is a graph showing the relationship between the aluminum composition and the number of protrusions.

[0023] Fig.13 This is a graph showing the relationship between the thickness of the aluminum nitride layer and the sheet resistance.

[0024] Description of Reference Numerals

[0025] 1: Semiconductor devices;

[0026] 10, 110: growth substrate;

[0027] 20, 120: nitride semiconductor layer;

[0028] 21, 121: buffer layer;

[0029] 22, 122: barrier layer;

[0030] 23, 123: spacer layer;

[0031] 24, 124: channel layer;

[0032] 24A: upper surface;

[0033] 25, 125: cap layer;

[0034] 25A, 125A: first cap layer;

[0035] 25B, 125B: second cap layer;

[0036] 26: channel area;

[0037] 29: upper surface;

[0038] 31: dielectric film;

[0039] 31D, 31S, 50D, 50G, 50S: open;

[0040] 40D, 40S: concave part;

[0041] 41D, 41S: regrowth layer;

[0042] 42D: drain electrode;

[0043] 42S: source electrode;

[0044] 43: gate electrode;

[0045] 50: passivation film;

[0046] 127: Nucleation layer. DETAILED DESCRIPTION

[0047] [Description of Embodiments of the Present Disclosure]

[0048] First, embodiments of the present disclosure will be described by way of examples.

[0049] [1] A semiconductor device of one embodiment of the present disclosure comprises: a barrier layer, the upper surface of which has nitrogen polarity; a channel layer, which is located on the barrier layer, the upper surface of which has nitrogen polarity; a first cap layer, which is located on the channel layer, the upper surface of which has nitrogen polarity; and a dielectric film, which is in contact with the upper surface of the first cap layer, and the first cap layer is an aluminum nitride layer.

[0050] [2] A semiconductor device according to another embodiment of the present invention comprises: a barrier layer, the upper surface of which has nitrogen polarity; a channel layer, which is located on the barrier layer, the upper surface of which has nitrogen polarity; a first cap layer, which is located on the channel layer, the upper surface of which has nitrogen polarity; and a dielectric film, which is in contact with the upper surface of the first cap layer, and at the upper surface of the first cap layer, the proportion of aluminum in the group III elements is greater than 52%.

[0051] The first cap layer is an aluminum nitride layer, or the ratio of aluminum in the group III element is 52% or more at the upper surface of the first cap layer, thereby obtaining an excellent surface morphology in the first cap layer. Therefore, electron traps existing on the surface of the first cap layer can be reduced, thereby suppressing current collapse.

[0052] [3] In [1] or [2], the thickness of the first cap layer may be greater than or equal to 0.2 nm and less than 2.0 nm. In this case, current collapse can be suppressed and an increase in sheet resistance can be suppressed.

[0053] [4] In any one of [1] to [3], a second cap layer may be provided between the channel layer and the first cap layer, the upper surface of the second cap layer having nitrogen polarity, and the proportion of aluminum in the group III element in the second cap layer is lower than the proportion of aluminum in the group III element in the first cap layer. In this case, even if the two-dimensional electron gas is reduced by the first cap layer, the two-dimensional electron gas can be supplemented by the second cap layer.

[0054] [5] In any one of [1] to [4], the semiconductor device may include a gate electrode on the dielectric film. In this case, gate leakage can be easily suppressed.

[0055] [Details of the embodiments of the present disclosure]

[0056] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited to these contents. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, repeated descriptions are sometimes omitted by marking the same figure numbers. In the present disclosure, "looking down" refers to observing an object from above.

[0057] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0058] like Figure 1 As shown, the semiconductor device 1 of the embodiment mainly includes a growth substrate 10 , a nitride semiconductor layer 20 , a dielectric film 31 , a passivation film 50 , a regrown layer 41S, a regrown layer 41D, a gate electrode 43 , a source electrode 42S, and a drain electrode 42D.

[0059] The growth substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the growth substrate 10 is a SiC substrate, the upper surface of the growth substrate 10 is a carbon (C) polar surface. When the surface of the growth substrate 10 is a C polar surface, the nitride semiconductor layer 20 can grow crystals with the nitrogen (N) polar surface as the growth surface.

[0060] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24, and a cap layer 25. The nitride semiconductor layer 20 may include a nucleation layer between the growth substrate 10 and the buffer layer 21.

[0061] The buffer layer 21 is located on the growth substrate 10. The buffer layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the AlN layer is, for example, not less than 1 nm and not more than 2000 nm. The buffer layer 21 may also include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer.

[0062] The barrier layer 22 is located on the buffer layer 21. The barrier layer 22 is, for example, an AlGaN layer. The band gap of the barrier layer 22 is greater than the band gap of the channel layer 24. The thickness of the barrier layer 22 is, for example, greater than 1 nm and less than 50 nm. The composition of the barrier layer 22 is, for example, Al Y Ga 1－Y N (0.15≤Y≤0.55). The conductivity type of the barrier layer 22 is, for example, n-type or non-doped (i-type). A scandium aluminum nitride (ScAlN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer. Y Ga 1－Y In the case of N, the ratio of Al in the group III element in the barrier layer 22 is Y×100%.

[0063] The spacer layer 23 is located on the barrier layer 22. The spacer layer 23 is, for example, an AlN layer. The thickness of the spacer layer 23 is, for example, in the range of 0.2 nm to 5 nm.

[0064] The channel layer 24 is located on the spacer layer 23. The channel layer 24 is, for example, a GaN layer. The band gap of the channel layer 24 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 24 is, for example, greater than 1 nm and less than 50 nm. Between the channel layer 24 and the barrier layer 22 and the spacer layer 23, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (two dimensional electron gas: 2DEG) is generated near the surface of the channel layer 24 that is opposite to the barrier layer 22, and a channel region 26 is formed. The conductivity type of the channel layer 24 is, for example, n-type or non-doped (i-type).

[0065] The cap layer 25 includes a second cap layer 25B and a first cap layer 25A. The second cap layer 25B is located on the channel layer 24. The first cap layer 25A is located on the second cap layer 25B. For example, the second cap layer 25B is an AlGaN layer, and the first cap layer 25A is an aluminum nitride (AlN) layer. The composition of the second cap layer 25B is, for example, Al X Ga 1－X N (0.15≤X≤0.55). For example, the thickness of the second cap layer 25B is greater than 0.2 nm and less than 10 nm, and the thickness of the first cap layer 25A is greater than 0.2 nm and less than 2.0 nm. The composition of the second cap layer 25B is Al XGa 1－X In the case of N, the ratio of Al in the group III element in the second cap layer 25B is X×100%.

[0066] On the C-polarity surface of the SiC substrate, the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, the second cap layer 25B, and the first cap layer 25A grow crystals with the N-polarity surface as the growth surface. Therefore, the upper surface of the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, the second cap layer 25B, and the first cap layer 25A each has N-polarity, and the lower surface of each has gallium (Ga) polarity or aluminum (Al) polarity.

[0067] A recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the recess 40D are formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0068] The dielectric film 31 is located on the nitride semiconductor layer 20. The dielectric film 31 is in contact with the upper surface 29 of the first cap layer 25A. For example, the relative dielectric constant of the dielectric film 31 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric film 31 may also be a high dielectric constant film. The dielectric film 31 is, for example, a silicon nitride (SiN) film. The dielectric film 31 may also be a dielectric oxide film or a dielectric nitride oxide film. The dielectric oxide film or the dielectric nitride oxide film may include at least one selected from the group consisting of hafnium (Hf), lanthanum (La) and zirconium (Zr). In addition, the dielectric oxide film or the dielectric nitride oxide film may include at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric film 31 may also be hafnium silicate (HfSiO x ) film, hafnium aluminate (HfAlO x ) film, hafnium silicon oxynitride (HfSiON) film or hafnium aluminum oxynitride (HfAlON) film. The thickness of the dielectric film 31 is, for example, not less than 1 nm and not more than 30 nm. An opening 31S for the source and an opening 31D for the drain are formed in the dielectric film 31. The opening 31S is connected to the recess 40S, and the opening 31D is connected to the recess 40D.

[0069] The regrown layer 41S is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40S. The regrown layer 41D is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as n-type impurities. The resistance of the regrown layer 41S and the regrown layer 41D is lower than the resistance of the channel layer 24. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowing the n-type GaN layer after the recess 40S and the recess 40D are formed in the nitride semiconductor layer 20.

[0070] The source electrode 42S is located on the regrown layer 41S, and the drain electrode 42D is located on the regrown layer 41D. The source electrode 42S is in contact with the regrown layer 41S, and the drain electrode 42D is in contact with the regrown layer 41D. The source electrode 42S is in ohmic contact with the regrown layer 41S, and the drain electrode 42D is in ohmic contact with the regrown layer 41D.

[0071] The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 is, for example, a SiN film. The thickness of the passivation film 50 is, for example, 5 nm or more and 50 nm or less in the portion where the thickness is uniform on the dielectric film 31. An opening 50S for the source electrode, an opening 50D for the drain electrode, and an opening 50G for the gate are formed in the passivation film 50. A portion of the source electrode 42S is exposed from the opening 50S, and a portion of the drain electrode 42D is exposed from the opening 50D. When viewed from above, the opening 50G is located between the opening 50S and the opening 50D. A portion of the dielectric film 31 is exposed from the opening 50G.

[0072] The gate electrode 43 is located between the source electrode 42S and the drain electrode 42D in a plan view. The gate electrode 43 is located on the passivation film 50 and the dielectric film 31 and is in contact with the dielectric film 31 via the opening 50G.

[0073] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 7 It is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0074] First, if Figure 2As shown, a nitride semiconductor layer 20 is formed on a growth substrate 10 by, for example, a metal organic chemical vapor deposition (MOCVD) method. In the formation of the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24, a second cap layer 25B, and a first cap layer 25A are formed in sequence. The first cap layer 25A is formed, for example, at a temperature of 700° C. or higher. The buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the second cap layer 25B may also be formed at the same temperature as the first cap layer 25A.

[0075] Then, if Figure 3 As shown, a dielectric film 31 is formed on the nitride semiconductor layer 20 .

[0076] Then, if Figure 4 As shown, an opening 31S for the source and an opening 31D for the drain are formed in the dielectric film 31, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the bottom of the recess 40D may be formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22. The opening 31S, the opening 31D, the recess 40S, and the recess 40D may be formed, for example, by reactive ion etching (RIE) using a mask (not shown).

[0077] Then, if Figure 5 As shown, a regrown layer 41S is formed in the recess 40S and on the channel layer 24, the spacer layer 23 or the barrier layer 22, and a regrown layer 41D is formed in the recess 40D and on the channel layer 24, the spacer layer 23 or the barrier layer 22. The regrown layer 41S and the regrown layer 41D can be formed by, for example, a physical vapor deposition (PVD) method such as an evaporation method, a sputtering method, a molecular beam epitaxy (MBE) method, or a metal organic vapor deposition (MOCVD) method.

[0078] Then, if Figure 6As shown, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in a region where the metal layer is to be formed is used to form a film, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0079] Then, if Figure 7 As shown, a passivation film 50 is formed on the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D.

[0080] Next, an opening 50G for a gate is formed in the passivation film 50 (see Figure 1 ). The opening 50G can be formed by, for example, RIE using a mask (not shown).

[0081] Next, a gate electrode 43 is formed on the passivation film 50 and the dielectric film 31 so as to be in contact with the dielectric film 31 via the opening 50G (see Figure 1 ). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) having an opening in a region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0082] Next, an opening 50S for the source and an opening 50D for the drain are formed in the passivation film 50 (see Figure 1 ). The opening 50S and the opening 50D can be formed by, for example, RIE using a mask (not shown).

[0083] In this way, the semiconductor device 1 can be manufactured.

[0084] In the semiconductor device 1 of the embodiment, the upper surfaces of the barrier layer 22 and the channel layer 24 have N polarity, thereby facilitating shortening the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D, and facilitating lowering of resistance.

[0085] Furthermore, since the first cap layer 25A, which is the layer in contact with the dielectric film 31 and is the last layer formed in the nitride semiconductor layer 20, is an AlN layer, an excellent surface morphology can be obtained in the nitride semiconductor layer 20. Therefore, electron traps existing on the surface of the nitride semiconductor layer 20 can be reduced, thereby suppressing current collapse.

[0086] Furthermore, the gate electrode 43 is provided on the dielectric film 31 to form a MIS (metal insulator semiconductor) structure, so that gate leakage can be easily suppressed.

[0087] It should be noted that the first cap layer 25A does not need to be an AlN layer. Even if the first cap layer 25A is an AlGaN layer, if the proportion of Al in the group III elements is 52% or more at the upper surface 29 of the first cap layer 25A, that is, if the Al composition is 0.52 or more, an excellent surface morphology can be obtained in the nitride semiconductor layer 20. At the upper surface 29, the proportion of Al in the group III elements can be 90% or more, that is, the Al composition can be 0.9 or more, and the proportion of Al in the group III elements can be 95% or more, that is, the Al composition can be 0.95 or more. The higher the Al composition, the easier it is to obtain high thermal decomposition resistance in the first cap layer 25A, and the easier it is to obtain excellent surface morphology. However, an AlGaN layer with a high Al composition is difficult to form stably, while an AlN layer has the advantage of being easy to form.

[0088] The Al composition of the nitride semiconductor layer can be measured by X-ray diffraction (XRD) or energy dispersive X-ray spectroscopy.

[0089] When the thickness of the first cap layer 25A is less than 0.2nm, it will be less than one molecular layer, and it may be difficult to obtain the effect of suppressing current collapse through the first cap layer 25A. When the thickness of the first cap layer 25A is greater than 2.0nm, the 2DEG in the channel region 26 is reduced and the sheet resistance becomes higher. If the thickness of the first cap layer 25A is less than 2.0nm, the sheet resistance can be suppressed to a low level. The thickness of the first cap layer 25A can be greater than 0.2nm and less than 1.0nm, or greater than 0.2nm and less than 0.9nm, or greater than 0.2nm and less than 0.8nm. In addition, the thickness of the first cap layer 25A can be greater than 0.3nm and less than 1.9nm, or greater than 0.4nm and less than 1.8nm.

[0090] Furthermore, the formation temperature of the first cap layer 25A is 700° C. or higher, thereby making it easy to obtain excellent surface morphology in the first cap layer 25A. The formation temperature of the first cap layer 25A may be 800° C. or higher, or 900° C. or higher.

[0091] Moreover, there is a second cap layer 25B having an Al composition lower than that of the first cap layer 25A between the channel layer 24 and the first cap layer 25A, thereby, the reduction of 2DEG caused by the first cap layer 25A can be supplemented by the second cap layer 25B. Therefore, the increase of sheet resistance can be suppressed. Even if the first cap layer 25A is an AlGaN layer, if the Al composition at the second cap layer 25B is lower than the Al composition at the first cap layer 25A, the reduction of 2DEG can be supplemented by the second cap layer 25B. However, it is also possible that the nitride semiconductor layer 20 does not include the second cap layer 25B, and the first cap layer 25A is in contact with the upper surface of the channel layer 24.

[0092] Here, the results of experiments conducted by the inventors of the present application are described. Figure 8 is a cross-sectional view showing the basic structure of the epitaxial substrate used in the experiment. Figure 8 As shown, the basic structure of the epitaxial substrate used for the experiment has a growth substrate 110 and a nitride semiconductor layer 120. The growth substrate 110 is a SiC substrate whose upper surface is a C polar plane. The nitride semiconductor layer 120 has a nucleation layer 127, a buffer layer 121, a barrier layer 122, a spacer layer 123, a channel layer 124 and a cap layer 125. The nucleation layer 127 is located on the growth substrate 110. The buffer layer 121 is located on the nucleation layer 127. The barrier layer 122 is located on the buffer layer 121. The spacer layer 123 is located on the barrier layer 122. The channel layer 124 is located on the spacer layer 123. The cap layer 125 has a second cap layer 125B and a first cap layer 125A. The second cap layer 125B is located on the channel layer 124. The first cap layer 125A is located on the second cap layer 125B. The nucleation layer 127 , the buffer layer 121 , the barrier layer 122 , the spacer layer 123 , the channel layer 124 , the second cap layer 125B, and the first cap layer 125A each have an upper surface with N polarity, and each have a lower surface with Ga polarity or Al polarity.

[0093] (First Experiment)

[0094] In the first experiment, an epitaxial substrate in which the cap layer 125 does not include the second cap layer 125B and the first cap layer 125A is in contact with the upper surface of the channel layer 124 was used, and the difference in surface morphology associated with the difference in Al composition at the first cap layer 125A was confirmed. Specifically, two epitaxial substrates (samples No. 1 and No. 2) were produced. In sample No. 1, an AlGaN layer with an Al composition of 0.2 was formed as the first cap layer 125A, and in sample No. 2, an AlN layer with an Al composition of 1.0 was formed as the first cap layer 125A. The other structures are the same between samples No. 1 and No. 2.

[0095] Then, the surface morphology of samples No. 1 and No. 2 was observed using an atomic force microscope (AFM). The results are shown in Fig. 9 and Fig.10 . Fig. 9 This is a diagram showing an AFM image of sample No. 1. Fig.10 is a diagram showing the AFM image of sample No. 2. Fig. 9 and Fig.10 As shown, sample No. 2 obtained a surface morphology more excellent than that of sample No. 1.

[0096] (Second experiment)

[0097] In the second experiment, epitaxial substrates with different compositions of the cap layer 125 were used. The first cap layer 125A used an AlN layer with a thickness of 0.25 nm, and the second cap layer 125B used an AlGaN layer or an AlN layer with a thickness of 2 nm. In condition A, the cap layer 125 does not include the first cap layer 125A, but only includes the second cap layer 125B. In condition B, the cap layer 125 does not include the second cap layer 125B, but only includes the first cap layer 125A, and the first cap layer 125A is in contact with the upper surface of the channel layer 124. In condition C, the cap layer 125 includes the first cap layer 125A and the second cap layer 125B. The Al composition of the second cap layer 125B in condition C is 0.2.

[0098] Then, the sheet resistance of each epitaxial substrate was measured. The results are shown in Fig.11 . Fig.11 It is a graph showing the relationship between Al composition and sheet resistance. Fig.11 The Al composition on the horizontal axis in φ represents the Al composition at the upper surface of the nitride semiconductor layer 120 .

[0099] like Fig.11 As shown, in condition A, the higher the Al composition of the second cap layer 125B, the higher the sheet resistance. This is because the thickness of the second cap layer 125B is 2 nm, and the higher the Al composition, the easier it is to reduce 2DEG. In conditions B and C, even if the Al composition of the first cap layer 125A is 1.0, the sheet resistance is low. This is because the thickness of the first cap layer 125A is 0.25 nm, and 2DEG is not easy to reduce.

[0100] (Third Experiment)

[0101] In the third experiment, the change in sheet resistance caused by ultraviolet irradiation was measured. In the third experiment, two types of epitaxial substrates (samples No. 3 and No. 4) were produced. In sample No. 3, the cap layer 125 does not include the first cap layer 125A, and in sample No. 4, the cap layer 125 includes the first cap layer 125A and the second cap layer 125B. The first cap layer 125A is an AlN layer with a thickness of 0.25 nm. The second cap layer 125B is an AlGaN layer with a thickness of 2 nm, and the Al composition of the second cap layer 125B is 0.2. The other structures are the same between samples No. 3 and No. 4.

[0102] Then, the sheet resistance of each epitaxial substrate was measured under two conditions, condition D without ultraviolet irradiation and condition E with ultraviolet irradiation. In addition, the ratio R of the sheet resistance measured under condition D to the sheet resistance measured under condition E was calculated. The results are shown in Table 1.

[0103] [Table 1]

[0104]

[0105] As shown in Table 1, in Sample No. 4, the ratio R is smaller than that in Sample No. 3. When ultraviolet rays are irradiated to the surface of the nitride semiconductor layer, the electrons captured by the electron traps present on the surface of the nitride semiconductor layer are released. Therefore, a smaller ratio R means that there are fewer electron traps on the surface of the nitride semiconductor layer. Based on the results shown in Table 1, it can be said that in Sample No. 4 having the first cap layer 125A, there are fewer electron traps than in Sample No. 3 not having the first cap layer 125A. Therefore, according to Sample No. 4, current collapse can be suppressed compared to Sample No. 3.

[0106] (Fourth Experiment)

[0107] In the fourth experiment, the change in sheet resistance caused by ultraviolet irradiation was also measured. In the fourth experiment, two epitaxial substrates (samples No. 5 and No. 6) were produced. In sample No. 5, no cap layer 125 was provided, and in sample No. 6, the cap layer 125 did not include a second cap layer 125B. The first cap layer 125A is an AlN layer with a thickness of 0.25 nm. The other structures are the same between samples No. 5 and No. 6. It should be noted that the structure of the barrier layer 122 is different between samples No. 3 and No. 4 and samples No. 5 and No. 6.

[0108] Then, the sheet resistance of each epitaxial substrate was measured under the same two conditions as in Experiment 3. In addition, the ratio R of the sheet resistance measured under Condition D to the sheet resistance measured under Condition E was calculated. The results are shown in Table 2.

[0109] [Table 2]

[0110]

[0111] As shown in Table 2, in Sample No. 6, the ratio R is smaller than that in Sample No. 5. Based on the results shown in Table 2, it can be said that in Sample No. 6 having the first cap layer 125A, the number of electron traps is smaller than that in Sample No. 5 not having the first cap layer 125A. Therefore, according to Sample No. 6, the current collapse can be suppressed compared with Sample No. 5.

[0112] (Fifth Experiment)

[0113] In the fifth experiment, multiple samples with different Al compositions on the upper surface of the nitride semiconductor layer 120 were prepared, and the number of protrusions on the upper surface was measured from the AFM image of the upper surface. In the measurement of the number of protrusions, the AFM image was binarized using an appropriate threshold in the range of -2nm to +2nm based on the average plane of the upper surface. Then, the number of protrusions per 1μm was calculated. 2 The results are shown in Fig.12 . Fig.12 This is a graph showing the relationship between the Al composition and the number of protrusions.

[0114] like Fig.12 As shown in the figure, the higher the Al composition, the fewer the protrusions. That is, the higher the Al composition, the better the surface morphology. In particular, when the Al composition is 0.6 or more, the number of protrusions per 1 μm 2 The number of protrusions is 0. In addition, as mentioned above, the higher the Al composition, the less electron traps there are. In summary, it can be said that the improvement of surface morphology contributes to the reduction of electron traps. In addition, Fig.12 In the figure, the intercept of the horizontal axis is 0.52. Therefore, it can be said that when the Al composition is 0.52 or more, the effects of improving the surface morphology and reducing the electron traps are excellent.

[0115] (Sixth Experiment)

[0116] In the sixth experiment, an epitaxial substrate was used in which an AlGaN layer with an Al composition of 0.2 and a thickness of 3 nm was used as the second cap layer 125B and an AlN layer was used as the first cap layer 125A. Then, the thickness of the first cap layer 125A was changed and the sheet resistance was measured. The results are shown in Fig.13 . Fig.13 It is a graph showing the relationship between the thickness of the first cap layer 125A and the sheet resistance.

[0117] like Fig.13As shown in FIG. 1 , the thicker the first cap layer 125A, the higher the sheet resistance. This is because the first cap layer 125A is an AlN layer, and therefore, the thicker the first cap layer 125A, the less 2DEG. However, within the range where the thickness of the first cap layer 125A is 1 nm or less, the sheet resistance increases more slowly than when the thickness of the first cap layer 125A exceeds 1 nm.

[0118] As mentioned above, although embodiment is described in detail, this disclosure is not limited to a specific embodiment, Various deformation|transformation and change are possible within the range described in a claim.

Claims

1. A semiconductor device comprising: a barrier layer, the upper surface of which has nitrogen polarity; A channel layer, located on the barrier layer, wherein the upper surface of the channel layer has nitrogen polarity; A first cap layer, located on the channel layer, wherein an upper surface of the first cap layer has nitrogen polarity; and a dielectric film in contact with the upper surface of the first cap layer, The first cap layer is an aluminum nitride layer.

2. A semiconductor device comprising: a barrier layer, the upper surface of which has nitrogen polarity; A channel layer, located on the barrier layer, wherein the upper surface of the channel layer has nitrogen polarity; A first cap layer, located on the channel layer, wherein an upper surface of the first cap layer has nitrogen polarity; and a dielectric film in contact with the upper surface of the first cap layer, At the upper surface of the first cap layer, a ratio of aluminum among group III elements is greater than 52%.

3. The semiconductor device according to claim 1 or 2, wherein: The thickness of the first cap layer is greater than or equal to 0.2 nm and less than 2.0 nm.

4. The semiconductor device according to claim 1 or 2, wherein: A second cap layer is provided between the channel layer and the first cap layer, and an upper surface of the second cap layer has nitrogen polarity. The ratio of aluminum in the group III elements at the second cap layer is lower than the ratio of aluminum in the group III elements at the first cap layer.

5. The semiconductor device according to claim 1 or 2, comprising: A gate electrode is formed on the dielectric film.

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