Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel, and solves the problem of poor display uniformity in the prior art. The array substrate comprises a fan-out region, a first electrode and a second electrode, the array substrate comprises a substrate; the conductive layers are stacked on the same side of the substrate; wherein the plurality of conducting layers comprise a plurality of conducting wires, the plurality of conducting wires comprise a plurality of fan-out wires and at least one redundant wire, the fan-out wires and the redundant wire are located in the fan-out area, the fan-out wires and the redundant wire are arranged in sequence, and two fan-out wires adjacent to the redundant wire are located in the same conducting layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the continuous development of smart terminal technology, consumers' requirements for display effects are constantly increasing. How to ensure uniform display brightness of smart terminal products has always been one of the research topics for those skilled in the art. Summary of the invention

[0003] In view of this, the embodiments of the present application provide an array substrate and a method for preparing the same, and a display panel, which solve the problem of poor display uniformity in the prior art.

[0004] In a first aspect, the present application provides an array substrate, comprising a fan-out area; the array substrate comprises: a substrate; and a plurality of conductive layers stacked on the same side of the substrate; wherein the plurality of conductive layers comprise a plurality of conductive wires, the plurality of conductive wires comprise a plurality of fan-out lines located in the fan-out area and at least one redundant line, the fan-out lines and the redundant lines are arranged sequentially, and two fan-out lines adjacent to the redundant lines are located in the same conductive layer.

[0005] In combination with the first aspect, in some possible implementations, the multiple conductive layers include a first conductive layer and a second conductive layer, and the multiple conductive wires are alternately arranged in the first conductive layer and the second conductive layer.

[0006] In combination with the first aspect, in some possible implementations, the line widths of the wires in the first conductive layer and the wires in the second conductive layer are different; or, the line widths of the wires in the first conductive layer and the wires in the second conductive layer are equal.

[0007] In combination with the first aspect, in some possible implementations, at least one redundant line includes a first redundant line, and two conductive wires adjacent to the first redundant line are used to transmit the same electrical signal; preferably, the two conductive wires adjacent to the first redundant line include a first power signal line; preferably, the first power signal line includes a first conductive portion and a second conductive portion that are connected to each other, a first spacing is provided between an end of the first conductive portion away from the second conductive portion and the first redundant line, a second spacing is provided between an end of the first conductive portion connected to the second conductive portion and the first redundant line, a third spacing is provided between an end of the second conductive portion away from the first conductive portion and the first redundant line, the first spacing is greater than the second spacing, and the second spacing is equal to the third spacing.

[0008] In combination with the first aspect, in some possible implementations, at least one redundant line includes a second redundant line, and two conductors adjacent to the second redundant line are used to transmit different electrical signals; preferably, the two conductors adjacent to the second redundant line include a first power signal line and a second power signal line; preferably, the distance between the first power signal line and the second redundant line is equal to the distance between the second power signal line and the second redundant line.

[0009] In combination with the first aspect, in some possible implementations, at least one redundant line includes a first redundant line, a second redundant line and a third redundant line, the first redundant line is located between the second redundant line and the third redundant line; the multiple fan-out lines include multiple first power signal lines and multiple second power signal lines, the first redundant line is located between the multiple first power signal lines, part of the second power signal lines are located on a side of the second redundant line away from the first redundant line, and the remaining part of the second power signal lines are located on a side of the third redundant line away from the first redundant line; preferably, part of the second power signal lines and the remaining part of the second power signal lines are axially symmetrical about the first redundant line; preferably, the multiple first power signal lines are symmetrical about the first redundant line.

[0010] In combination with the first aspect, in some possible implementations, at least one redundant line includes a first redundant line and a second redundant line, and the first redundant line and the second redundant line are located in different conductive layers; preferably, at least one redundant line also includes a third redundant line, and the third redundant line and the second redundant line are located in the same conductive layer.

[0011] In combination with the first aspect, in some possible implementations, the array substrate also includes a pixel circuit area located on one side of the fan-out area; the fan-out area includes a first sub-area and a second sub-area that are adjacent to each other, the first sub-area is located on a side of the second sub-area close to the pixel circuit area, and at least part of the redundant lines are located in the first sub-area; preferably, at least part of the redundant lines extend from the first sub-area to the second sub-area; preferably, the fan-out lines are located in the first sub-area and extend to the second sub-area.

[0012] A second aspect of the present application provides a method for preparing an array substrate, comprising: alternately preparing multiple conductive layers and multiple insulating layers on a substrate to obtain an array substrate; wherein the multiple conductive layers include multiple conductive wires, the multiple conductive wires include multiple fan-out lines and at least one redundant line, and the redundant lines and the fan-out lines are both at least located in the fan-out area; the fan-out lines and the redundant lines are arranged along a first direction, and two fan-out lines adjacent to the redundant lines are located in the same conductive layer.

[0013] A third aspect of the present application provides a display panel, comprising the array substrate provided by any of the above embodiments.

[0014] According to the array substrate and its preparation method, and the display panel provided by the embodiments of the present application, a redundant line is added between two adjacent fan-out lines, and the two adjacent fan-out lines are set in the same conductive layer. In this case, compared with the conventional technical solution in which two adjacent fan-out lines are alternately set in different conductive layers, since they are set in the same conductive layer, it can be ensured that the two fan-out lines are obtained by the same process step, and then the width of the two fan-out lines is ensured to be consistent, thereby avoiding the resistance difference caused by inconsistent width and improving the display unevenness problem caused by resistance loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a top view structure of an array substrate in the related art.

[0016] Figure 2 A partially enlarged schematic diagram of a fan-out area of ​​an array substrate provided in the first embodiment of the present application.

[0017] Figure 3 for Figure 2 The cross-sectional structure diagram of the array substrate along line A1A2 is shown.

[0018] Figure 4 A partially enlarged schematic diagram of a fan-out area of ​​an array substrate provided in the second embodiment of the present application.

[0019] Figure 5 A partially enlarged schematic diagram of a fan-out area of ​​an array substrate provided in the third embodiment of the present application.

[0020] Figure 6 An embodiment of the present application provides Figure 5 The cross-sectional structure diagram of the array substrate along line B1B2 is shown.

[0021] Figure 7 A schematic top view of the fan-out region of an array substrate provided in the fourth embodiment of the present application.

[0022] Figure 8 for Figure 7 The cross-sectional structure diagram of the array substrate along line C1C2 is shown.

[0023] Fig. 9 The present invention provides a flowchart of a method for preparing an array substrate according to an embodiment of the present invention.

[0024] Fig.10 A schematic diagram of the top structure of a display panel provided in one embodiment of the present application.

[0025] Fig.11 A schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The display panel generally includes an array substrate and a light emitting device stacked on one side of the array substrate. The array substrate includes a pixel circuit and a plurality of signal lines, and an external electrical signal is transmitted to the pixel circuit and the light emitting device through the signal line to drive the light emitting device to emit light.

[0027] Figure 1 FIG. 1 is a schematic diagram of a top view structure of an array substrate in the related art. Figure 1 As shown, the array substrate includes a pixel circuit area PA and a fan-out area SA located on one side of the pixel circuit area PA. A variety of signal lines are arranged in the pixel circuit area PA, and at least some of the signal lines extend to the fan-out area SA to form fan-out lines 121, thereby forming lead-out terminals at the edge of the array substrate. In the fan-out area SA, a plurality of fan-out lines 121 are arranged sequentially in the horizontal direction. On the one hand, in order to achieve a narrow frame, the lengths of the plurality of fan-out lines 121 in the fan-out area SA are not equal; on the other hand, the plurality of fan-out lines 121 are usually alternately arranged in two metal layers, and due to process reasons, there are differences in the line widths of different metal layers. The above two reasons lead to differences in the resistance of the signal lines, which in turn leads to uneven display when the array substrate is subsequently applied to a display panel.

[0028] In view of this, the present application provides an array substrate and a method for manufacturing the same, and a display panel. By adding redundant lines in the fan-out area, the resistance difference between adjacent fan-out lines 121 is reduced, thereby improving the display unevenness problem.

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is understood that when a structure is referred to as being "on or under" another structure, the structure may be directly on or under the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. The structures mentioned herein include any of a film layer, an element, a device, a component, and an assembly.

[0031] When a structure is referred to as being “connected” to another structure, the structure may be directly connected to the other structure or indirectly connected to the other structure with one or more intervening structures interposed therebetween.

[0032] Figure 2 A partially enlarged schematic diagram of a fan-out area of ​​an array substrate provided in the first embodiment of the present application. Figure 3 for Figure 2The cross-sectional structure diagram of the array substrate along the A1A2 line is shown. Figure 2 and Figure 3 As shown, the array substrate includes: a substrate 11 and a plurality of conductive layers 12 stacked on the same side of the substrate 11. The conductive layer 12 is, for example, a metal layer. It should be understood that an insulating layer 13 is also provided between adjacent conductive layers 12.

[0033] The substrate 11 is a base substrate.

[0034] In some embodiments, the base substrate may be a glass-based substrate.

[0035] In some embodiments, the substrate substrate may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. For example, the substrate substrate may be a FR4 type printed circuit board PCB, or may be a flexible PCB that is easily deformed.

[0036] In some embodiments, the substrate substrate may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or include a metal or a metal compound. For example, the substrate substrate may be a metal core printed circuit board (MCPCB) or a metal copper clad laminate (MCCL).

[0037] The array substrate may be divided into a plurality of regions in a direction parallel to the substrate 11. The plurality of regions include a fan-out region SA and may also include a pixel circuit region PA located on one side of the fan-out region SA. A pixel circuit is disposed in the pixel circuit region PA, and the pixel circuit is, for example, a 7T1C pixel circuit.

[0038] The multiple conductive layers 12 include multiple conductive lines 120, and the multiple conductive lines 120 include multiple fan-out lines 121 and at least one redundant line 122 located in the fan-out area SA. The fan-out lines 121 and the redundant lines 122 are arranged in sequence, and two fan-out lines 121 adjacent to the redundant lines 122 are located in the same conductive layer 12. The redundant lines 122 are located in a conductive layer 12 other than the conductive layer 12 where the two fan-out lines 121 are located, that is, the redundant lines 122 and the two fan-out lines 121 are located in different conductive layers 12. For example, the multiple conductive layers 12 include four conductive layers stacked on the substrate 11 in sequence, the redundant lines 122 are located in a first conductive layer M1 close to the substrate 11, and the two fan-out lines 121 adjacent to the redundant lines 122 are located in a second conductive layer M2, and the second conductive layer M2 is located on a side of the first conductive layer M1 away from the substrate 11 and is adjacent to the first conductive layer M1.

[0039] The redundant line 122 refers to the conductive line 120 in a suspended state, that is, the redundant line 122 is not connected to an electrical signal.

[0040] According to the array substrate provided in this embodiment, a redundant line 122 is added between two adjacent fan-out lines 121, and the two adjacent fan-out lines 121 are arranged in the same conductive layer 12. In this case, compared with the conventional technical solution in which two adjacent fan-out lines 121 are alternately arranged in different conductive layers 12, since the two fan-out lines 121 are arranged in the same conductive layer 12, it can be ensured that the two fan-out lines 121 are obtained by the same process step, and then the widths of the two fan-out lines are ensured to be consistent, thereby avoiding the resistance difference caused by inconsistent widths and improving the display unevenness problem caused by resistance loss.

[0041] In one embodiment, see Figure 2 As can be seen from the array substrate shown, at least one redundant line 122 includes a first redundant line L1, and two wires 120 adjacent to the first redundant line L1 are used to transmit the same electrical signal. Exemplarily, the two wires 120 adjacent to the first redundant line L1 include a first power signal line ELVDD, that is, both sides of the first redundant line L1 are first power signal lines ELVDD.

[0042] In this case, in one embodiment, the first power signal lines ELVDD on both sides of the first redundant line L1 are fanned out in a direction close to the first redundant line L1. Specifically, the first power signal line ELVDD includes a first conductive part ab and a second conductive part bc, and the first conductive part ab is located on a side of the second conductive part bc close to the pixel circuit area PA. An end of the first conductive part ab close to the second conductive part bc is connected to an end of the second conductive part bc close to the first conductive part ab. There is a first spacing S1 between an end of the first conductive part ab away from the second conductive part bc and the first redundant line L1, a second spacing S2 between an end of the first conductive part ab close to the second conductive part bc and the first redundant line L1, and a second spacing S2 between an end of the second conductive part bc close to the first conductive part ab and the first redundant line L1. There is a third spacing S3 between an end of the second conductive part bc away from the first conductive part ab and the first redundant line L1, S1>S2=S3. Exemplarily, the first power signal line ELVDD can be a fold line, and the first redundant line L1 can be a straight line. In this case, the length difference of the first power signal lines ELVDD on both sides of the first redundant line L1 is relatively large. By setting the first redundant line ELVDD between the two signal lines with relatively large length difference, the two signal lines can be set in the same conductive layer 12, thereby avoiding the resistance difference caused by process difference, so that the resistance difference between the two signal lines only comes from the length difference, thereby reducing the resistance difference between the two signal lines and improving the display unevenness problem caused by resistance loss.

[0043] Figure 4 This is a partial enlarged schematic diagram of the fan-out area of ​​the array substrate provided in the second embodiment of the present application. Figure 4 and Figure 2 The array substrate shown in the figure is different in that, in the present embodiment, at least one redundant line 122 includes a second redundant line L2, and two wires 120 adjacent to the second redundant line L2 are used to transmit different electrical signals. Exemplarily, the two wires 120 adjacent to the second redundant line L2 include a first power signal line ELVDD and a second power signal line ELVSS, that is, one side of the second redundant line L2 is the first power signal line ELVDD, and the other side is the second power signal line ELVSS. Since the length difference between the adjacent first power signal line ELVDD and the second power signal line ELVSS is large, by setting the second redundant line L2 between the adjacent first power signal line ELVDD and the second power signal line ELVSS, the adjacent first power signal line ELVDD and the second power signal line ELVSS can be set in the same conductive layer 12, thereby avoiding the resistance difference caused by the process difference, so that the resistance difference between the two signal lines only comes from the length difference, thereby reducing the resistance difference between the two signal lines and improving the display unevenness problem caused by resistance loss.

[0044] In this case, in one embodiment, any one of the first power signal line ELVDD and the second power signal line ELVSS includes a first conductive portion ab and a second conductive portion bc that are connected. The first conductive portion ab of the first power signal line ELVDD is parallel to the first conductive portion ab of the second power signal line ELVSS, and the second conductive portion bc of the first power signal line ELVDD is parallel to the second conductive portion bc of the second power signal line ELVSS. The distance between the first power signal line ELVDD and the second redundant line L2 is equal to the distance between the second power signal line ELVSS and the second redundant line L2.

[0045] It should be noted that, in this embodiment, the array substrate may include the first redundant line L1 and the second redundant line L2, or may only include the second redundant line L2.

[0046] Figure 5 This is a partial enlarged schematic diagram of the fan-out area of ​​the array substrate provided in the third embodiment of the present application. Figure 5As shown, the difference between the array substrate provided in this embodiment and the array substrate provided in any of the above embodiments is that, in this embodiment, at least one redundant line 122 includes a first redundant line L1, a second redundant line L2 and a third redundant line L3, and the first redundant line L1 is located between the second redundant line L2 and the third redundant line L3. The plurality of fan-out lines 121 include a plurality of first power signal lines ELVDD and a plurality of second power signal lines ELVSS, the first redundant line L1 is located between the plurality of first power signal lines ELVDD, a portion of the second power signal lines ELVSS is located on the side of the second redundant line L2 away from the first redundant line L1, and the remaining portion of the second power signal lines ELVSS is located on the side of the third redundant line L3 away from the first redundant line L1.

[0047] In one embodiment, the plurality of first power signal lines ELVDD are symmetrical about the first redundant line L1. The positional relationship between the first redundant line L1 and the two first power signal lines ELVDD adjacent to the first redundant line L1 is shown in FIG. Figure 2 The embodiments shown will not be described in detail here.

[0048] In one embodiment, part of the second power signal line ELVSS and the rest of the second power signal line ELVSS are axially symmetrical about the first redundant line L1. The positional relationship between the second redundant line L2 and a first power signal line ELVDD and a second power signal line ELVSS adjacent to the second redundant line L2 is shown in FIG. Figure 4 The embodiments shown will not be described in detail here.

[0049] In one embodiment, see Figure 5 As can be seen from the array substrate shown, the fan-out area SA includes a first sub-area SA1 and a second sub-area SA2 that are adjacently arranged, the first sub-area SA1 is located on a side of the second sub-area SA2 close to the pixel circuit area PA, and at least part of the redundant line 122 is located in the first sub-area SA1. For example, the second redundant line L2 and the third redundant line L3 are located in the first sub-area SA1.

[0050] In further embodiments, at least a portion of the redundant line 122 extends from the first sub-area SA1 to the second sub-area SA2. For example, the first redundant line L1 extends from the first sub-area SA1 to the second sub-area SA2.

[0051] In a further embodiment, the fan-out line 121 is located in the first sub-area SA1 and extends to the second sub-area SA2 .

[0052] In one embodiment, see Figure 5, at least one redundant line 122 includes a first redundant line L1 and a second redundant line L2, and the first redundant line L1 and the second redundant line L2 are located in different conductive layers 12. In a further embodiment, at least one redundant line 122 further includes a third redundant line L3, and the third redundant line L3 and the second redundant line L2 are located in the same conductive layer 12.

[0053] Figure 6 An embodiment of the present application provides Figure 5 The cross-sectional structure diagram of the array substrate along the B1B2 line is shown. Figure 6 and Figure 5 It can be seen that in this embodiment, the plurality of conductive layers 12 include a first conductive layer M1 and a second conductive layer M2 , and the plurality of conductive lines 120 are alternately disposed in the first conductive layer M1 and the second conductive layer M2 .

[0054] In this embodiment, the film layer positions of the first conductive layer M1 and the second conductive layer M2 in the array substrate can be reasonably set according to actual needs. In one embodiment, the first conductive layer M1 and the second conductive layer M2 are sequentially stacked on one side of the substrate 11, and the first conductive layer M1 and the second conductive layer M2 are two adjacent conductive layers 12 among the multiple conductive layers 12.

[0055] In one embodiment, the line widths of the conductive lines 120 in the first conductive layer M1 and the conductive lines 120 in the second conductive layer M2 are equal.

[0056] According to the array substrate provided in this embodiment, by arranging multiple conductive wires 120 alternately arranged in two conductive layers, namely the first conductive layer M1 and the second conductive layer M2, instead of more conductive layers 12, the resistance difference caused by process difference can be avoided as much as possible, and the display unevenness problem caused by resistance loss can be improved.

[0057] Figure 7 A schematic top view of the fan-out region of an array substrate provided in the fourth embodiment of the present application. Figure 8 for Figure 7 The cross-sectional structure diagram of the array substrate along the C1C2 line is shown. Figure 7 , Figure 8 The array substrate and Figure 6 The difference of the array substrate shown is that, in this embodiment, the line widths of the conductive wires 120 in the first conductive layer M1 and the conductive wires 120 in the second conductive layer M2 are different.

[0058] Since two adjacent fan-out lines 121 with a large length difference are arranged in the same conductive layer 12, the resistance difference caused by the process difference is basically eliminated. In this case, when the array substrate is subsequently used to prepare a display panel, if the display panel still has the problem of uneven brightness, the problem of uneven brightness can be improved by adjusting the line width of the single-layer conductive line 120.

[0059] The present application also provides a method for preparing an array substrate. Fig. 9 The flowchart of the method for preparing an array substrate provided in one embodiment of the present application is shown in FIG. Fig. 9 As shown, the method 900 for preparing the array substrate includes:

[0060] Step S910, see Figure 3 In the array substrate shown, a plurality of conductive layers 12 and a plurality of insulating layers 13 are alternately prepared on a substrate 11 to obtain the array substrate.

[0061] The plurality of conductive layers 12 include a plurality of conductive lines 120, the plurality of conductive lines 120 include a plurality of fan-out lines 121 and at least one redundant line 122, and the redundant line 122 and the fan-out line 121 are at least located in the fan-out area. The fan-out lines 121 and the redundant line 122 are sequentially arranged along the first direction x, and the two fan-out lines 121 adjacent to the redundant line 122 are located in the same conductive layer 12.

[0062] The preparation method of the array substrate provided in the present application and the array substrate provided in the embodiment of the present application belong to the same inventive concept. For structural details not described in the preparation method embodiment, please refer to the array substrate embodiment, and the preparation method embodiment will not be repeated here.

[0063] The present application also provides a display panel. Fig.10 FIG. 1 is a schematic diagram of a top view of a display panel provided in an embodiment of the present application. Fig.10 As shown, the display panel includes an array substrate 10 and a light emitting device layer provided in any of the above embodiments, and the light emitting device layer is stacked on one side of the array substrate 10. The area where the light emitting device is located is called the display area AA.

[0064] The present application also provides a display device. Fig.11 This is a schematic diagram of the structure of a display device provided in one embodiment of the present application. Fig.11 As shown, the display device includes Fig.10 The display panel 20 provided in the illustrated embodiment. The display device is a product having an image display function. For example, the display device can be used to display static images, such as pictures or photos. The display device can also be used to display dynamic images, such as videos.

[0065] The display device can be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted intelligent central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0066] In addition, the display device may also have functions such as taking photos, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device also includes at least one functional module for realizing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0067] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0068] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: Including a fan-out area; the array substrate includes: substrate; and A plurality of conductive layers stacked on the same side of the substrate; Among them, the multiple conductive layers include multiple conductive wires, the multiple conductive wires include multiple fan-out lines and at least one redundant line located in the fan-out area, the fan-out lines and the redundant lines are arranged sequentially, and the two fan-out lines adjacent to the redundant lines are located in the same conductive layer.

2. The array substrate according to claim 1, characterized in that: The plurality of conductive layers include a first conductive layer and a second conductive layer, and the plurality of conductive wires are alternately arranged in the first conductive layer and the second conductive layer.

3. The array substrate according to claim 2, characterized in that: The line widths of the conductive lines in the first conductive layer and the conductive lines in the second conductive layer are different; or The line widths of the conductive lines in the first conductive layer and the conductive lines in the second conductive layer are equal.

4. The array substrate according to claim 1, characterized in that: The at least one redundant line includes a first redundant line, and the two conductive wires adjacent to the first redundant line are used to transmit the same type of electrical signals; Preferably, the two wires adjacent to the first redundant line include first power signal lines; Preferably, the first power signal line includes a first conductive part and a second conductive part which are connected to each other, a first distance is provided between an end of the first conductive part away from the second conductive part and the first redundant line, a second distance is provided between an end of the first conductive part connected to the second conductive part and the first redundant line, a third distance is provided between an end of the second conductive part away from the first conductive part and the first redundant line, the first distance is greater than the second distance, and the second distance is equal to the third distance.

5. The array substrate according to claim 1, characterized in that: The at least one redundant line includes a second redundant line, and the two conductive wires adjacent to the second redundant line are used to transmit different electrical signals; Preferably, the two wires adjacent to the second redundant line include a first power signal line and a second power signal line; Preferably, a distance between the first power signal line and the second redundant line is equal to a distance between the second power signal line and the second redundant line.

6. The array substrate according to claim 1, characterized in that: At least one of the redundant lines includes a first redundant line, a second redundant line, and a third redundant line, the first redundant line is located between the second redundant line and the third redundant line; the plurality of fan-out lines include a plurality of first power signal lines and a plurality of second power signal lines, the first redundant line is located between the plurality of first power signal lines, a portion of the second power signal lines is located on a side of the second redundant line away from the first redundant line, and the remaining portion of the second power signal lines is located on a side of the third redundant line away from the first redundant line; Preferably, part of the second power signal line and the rest of the second power signal line are axially symmetrical about the first redundant line; Preferably, the plurality of first power signal lines are symmetrical about the first redundant line.

7. The array substrate according to claim 1, characterized in that: At least one of the redundant lines includes a first redundant line and a second redundant line, wherein the first redundant line and the second redundant line are located in different conductive layers; Preferably, the at least one redundant line further includes a third redundant line, and the third redundant line and the second redundant line are located in the same conductive layer.

8. The array substrate according to claim 1, characterized in that: It also includes a pixel circuit area located on one side of the fan-out area; the fan-out area includes a first sub-area and a second sub-area that are adjacently arranged, the first sub-area is located on a side of the second sub-area close to the pixel circuit area, and at least part of the redundant lines are located in the first sub-area; Preferably, at least part of the redundant lines extend from the first sub-region to the second sub-region; Preferably, the fan-out line is located in the first sub-area and extends to the second sub-area.

9. A method for preparing an array substrate, characterized in that: include: Alternately preparing a plurality of conductive layers and a plurality of insulating layers on a substrate to obtain the array substrate; Among them, the multiple conductive layers include multiple conductive wires, the multiple conductive wires include multiple fan-out lines and at least one redundant line, the redundant line and the fan-out line are both located at least in the fan-out area; the fan-out line and the redundant line are arranged along a first direction, and the two fan-out lines adjacent to the redundant line are located in the same conductive layer.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

Images