Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, a display area, a transition area and a hole area, the transition area surrounds the hole area, and the display area surrounds the transition area. The first signal lines and the second signal lines are located on one side of the substrate. Part of the first signal line comprises a first section, a first connecting section and a second section which are connected in sequence, the first section and the second section are located in the display area and extend in the first direction, and the first connecting section is located in the transition area. The first sections and the first connecting sections of part of the first signal lines are located on different film layers, and the first sections and the second sections are located on the same film layer. Part of the second signal line comprises a third section, a second connecting section and a fourth section which are connected in sequence, the third section and the fourth section are located in the display area and extend in the second direction, and the second connecting section is located in the transition area. The first direction intersects the second direction. The first signal line and the second signal line receive driving signals at the same time in a partial driving period of a frame of picture.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the development of mobile smart terminal devices such as mobile phones and tablet computers, users have higher and higher requirements for screen-to-body ratio. In order to improve the screen-to-body ratio of display devices, a hole is usually set on the display device, and a camera or sensor is placed under the hole.

[0003] However, one of the problems with this design is that the display device located near the opening will produce display Mura (the phenomenon of uneven brightness of the display and various traces). Summary of the invention

[0004] The purpose of the present application is to provide a display substrate and a display device with uniform display brightness.

[0005] The present application discloses a display substrate, which comprises a display area, a transition area and a hole area, wherein the transition area surrounds the hole area, and the display area surrounds the transition area;

[0006] The display substrate comprises:

[0007] substrate;

[0008] a plurality of first signal lines located on one side of the substrate; part of the first signal lines comprises a first section, a first connecting section and a second section connected in sequence, the first section and the second section are located in the display area and both extend along a first direction, and the first connecting section is located in the transition area; the first section and the first connecting section of part of the first signal lines are located in different film layers, and the first section and the second section are located in the same film layer;

[0009] A plurality of second signal lines are located on the same side of the substrate as the first signal lines; part of the second signal lines comprises a third section, a second connecting section and a fourth section connected in sequence, the third section and the fourth section are located in the display area and extend along a second direction, the second connecting section is located in the transition area; the first direction intersects the second direction;

[0010] In a partial driving period of a frame, the first signal line receives a first driving signal and the second signal line receives a second driving signal at the same time.

[0011] Optionally, the first signal line includes a data signal line; and the second signal line includes a light emitting control signal line.

[0012] Optionally, the display substrate includes a base, a first source-drain metal layer located on one side of the base, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the base; the first source-drain metal layer and the second source-drain metal layer are insulated;

[0013] In some of the first signal lines, the first section and the second section are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; or, in some of the first signal lines, the first section and the second section are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer;

[0014] The second signal line is disposed between the substrate and the first source-drain metal layer.

[0015] Optionally, the first signal line includes a data signal line; the second signal line includes a light-emitting control signal line; two adjacent data signal lines control the same column of pixels, one of which is connected to pixels located in odd rows, and the other is connected to pixels located in even rows;

[0016] The first section and the second section of the data signal lines connected to at least some of the odd-numbered rows of pixels among all the data signal lines are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; the first section and the second section of the data signal lines connected to at least some of the even-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; or

[0017] The first section and the second section of the data signal lines that are at least partially connected to the odd-numbered rows of pixels among all the data signal lines are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; the first section and the second section of the data signal lines that are at least partially connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer.

[0018] Optionally, among all the data signal lines, the first section and the second section of the data signal lines connected to the odd-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; the first section and the second section of the data signal lines connected to the even-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; or

[0019] The first section and the second section of the data signal lines connected to the odd-numbered rows of pixels among all the data signal lines are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; the first section and the second section of the data signal lines connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer.

[0020] Optionally, the data signal lines of the display substrate are divided into a plurality of data signal line groups, each data signal line group includes eight data signal lines, the same data signal line group includes 8k-7 to 8k data signal lines, and the 8k-7 to 8k data signal lines are sequentially arranged along the second direction in the display area; in the same data signal line group, the 8k-7 data signal line and the 8k-6 data signal line are connected to the same column of pixels, the 8k-5 data signal line and the 8k-4 data signal line are connected to the same column of pixels, the 8k-3 data signal line and the 8k-2 data signal line are connected to the same column of pixels, and the 8k-1 data signal line and the 8k data signal line are connected to the same column of pixels; the 8k-7, 8k-5, 8k-2, and 8k data signal lines are connected to odd-numbered rows of pixels, and the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are connected to even-numbered rows of pixels;

[0021] In the display area, the first section and the second section of the data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are arranged on the first source-drain metal layer; the first section and the second section of the data signal lines 8k-6, 8k-4, 8k-2, and 8k are arranged on the second source-drain metal layer;

[0022] In the transition zone, the first connection segments of the data signal lines 8k-7, 8k-5, 8k-2, and 8k are set on the first source-drain metal layer, and the first connection segments of the data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are placed in the second source-drain metal layer; k is an integer greater than 0.

[0023] Optionally, the display substrate further includes:

[0024] A source driving circuit, wherein the source driving circuit comprises a plurality of source driving transistors;

[0025] A plurality of source signal lines are divided into a plurality of source signal line groups, each source signal line group includes a first source signal line and a second source signal line; in the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line, and the first source signal line and the second source signal line connected to the data signal lines of the same data signal line group belong to the same source signal line group; each of the data signal lines is connected to the source signal line through a source driving transistor;

[0026] The first multiplexed signal line to the fourth multiplexed signal line; in the same data signal line group, the source driving transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first to fourth multiplexed signal lines, and the gates of the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines; the gates of the source driving transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first to fourth multiplexed signal lines, and the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines.

[0027] Optionally, in the same data signal line group, the 8k-7th data signal line is connected to the first source signal line under the control of the first multiplexing signal line; the 8k-6th data signal line is connected to the first source signal line under the control of the third multiplexing signal line; the 8k-5th data signal line is connected to the first source signal line under the control of the second multiplexing signal line; the 8k-4th data signal line is connected to the first source signal line under the control of the fourth multiplexing signal line;

[0028] The 8k-3 data signal line is connected to the second source signal line under the control of the third multiplexing signal line; the 8k-2 data signal line is connected to the second source signal line under the control of the first multiplexing signal line; the 8k-1 data signal line is connected to the second source signal line under the control of the fourth multiplexing signal line; the 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexing signal line.

[0029] Optionally, in the transition region, the orthographic projections of the first connecting segment disposed on the first source-drain metal layer and the first connecting segment disposed on the second source-drain metal layer on the substrate have no overlapping area.

[0030] Optionally, in the transition region, the orthographic projections of the first connecting segment disposed on the first source-drain metal layer and the first connecting segment disposed on the second source-drain metal layer on the substrate at least partially overlap.

[0031] Optionally, the display substrate further includes a second conductive layer located between the base and the first source-drain metal layer;

[0032] The display substrate further comprises a plurality of scanning signal lines; part of the scanning signal lines comprises a fifth section, a third connecting section and a sixth section connected in sequence, the fifth section and the sixth section are located in the display area and both extend along the second direction, the third connecting section is located in the transition area; the scanning signal lines are arranged in the second conductive layer;

[0033] In the transition region, orthographic projections of a plurality of the third connecting segments and a plurality of the first connecting segments disposed on the first source-drain metal layer on the substrate have no overlapping areas.

[0034] Optionally, the display substrate further includes a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer;

[0035] The light-emitting control signal line is arranged on the first conductive layer; in the transition region, the second connecting segment at least partially overlaps with the orthographic projection of the first connecting segment arranged on the first source-drain metal layer on the substrate.

[0036] Optionally, the display substrate further includes a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer;

[0037] Part of the light-emitting control signal lines are arranged on the first conductive layer; part of the light-emitting control signal lines are arranged on the second conductive layer;

[0038] In the transition zone, the second connecting segment arranged in the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment on the substrate; the second connecting segment arranged in the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment on the substrate.

[0039] Optionally, the display substrate further includes a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer;

[0040] The display substrate further comprises a plurality of scanning signal lines; part of the scanning signal lines comprises a fifth section, a third connecting section and a sixth section connected in sequence, the fifth section and the sixth section are located in the display area and both extend along the second direction, and the third connecting section is located in the transition area;

[0041] Part of the scanning signal lines is arranged on the first conductive layer; part of the scanning signal lines is arranged on the second conductive layer;

[0042] In the transition zone, the third connecting segment arranged in the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment on the substrate; the third connecting segment arranged in the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment on the substrate.

[0043] The present application also provides a display device, which includes the above-mentioned display substrate.

[0044] Compared with the related art, the present application arranges the first signal line in different film layers in the display area and the transition area to regulate the interference of the second signal line on the first signal line, thereby improving the display effect of the display panel.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0047] Figure 1 This is a schematic plan view of a substrate for this application.

[0048] Figure 2 A schematic diagram showing the layers of a substrate for this application.

[0049] Figure 3 This is a timing diagram showing the operation of the substrate in this application.

[0050] Figure 4 This is a schematic diagram showing partial circuit connections of a substrate for this application.

[0051] Figure 5 For related technologies Figure 1 Schematic diagram of the cross section along line AA.

[0052] Figure 6 For related technologies Figure 1 Schematic diagram of the cross section along line AA.

[0053] Figure 7 It is a circuit diagram showing the junction between the second section and the first connecting section of the substrate in one embodiment of the present application.

[0054] Figure 8 It is a schematic diagram showing a circuit at the junction of the first section and the first connecting section of the substrate in one embodiment of the present application.

[0055] Fig. 9 In one embodiment of the present application, Figure 1 Schematic diagram of the cross section along line AA.

[0056] Fig.10 In one embodiment of the present application, Figure 1 Schematic diagram of the cross section along line AA.

[0057] Fig.11 In one embodiment of the present application, Figure 1 Schematic diagram of the cross section along line AA.

[0058] Fig.12 In one embodiment of the present application, Figure 1 Schematic diagram of the cross section along line AA. DETAILED DESCRIPTION

[0059] Here, the technical solutions in the embodiments (or "implementations") of the present application will be described clearly and completely in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0060] If there are terms involving directional indications or positional relationships in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings); if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance.

[0061] like Figure 1 As shown, the display substrate generally includes a display area 1000 and a frame area 4000. Some display substrates are dug in the display area 1000 to form a hole area 3000, and the hole area 3000 can be used to set a front camera or some sensors, etc. The display panel also includes a transition area 2000 between the display area 1000 and the hole area. The wiring part of the display substrate is located in the transition area 2000 surrounding the hole area 3000 to avoid the hole area 3000.

[0062] like Figure 2As shown, the display substrate may include, in the third direction F3 thereof, a substrate 10, an active layer 11 located on a side of the substrate 10 close to the display side, a first gate insulating layer 12 located on a side of the active layer 11 away from the substrate 10, a first conductive layer 20 (GT1) located on a side of the first gate insulating layer 12 away from the active layer 11, a second gate insulating layer 21 located on a side of the first conductive layer 20 away from the first gate insulating layer 12, a second conductive layer 30 (GT2) located on a side of the second gate insulating layer 21 away from the first conductive layer 20, and an interlayer insulating layer 30 located on a side of the second conductive layer 30 away from the second gate insulating layer 21. 1. A first source-drain metal layer 40 (SD1) located on a side of the interlayer insulating layer 31 away from the second conductive layer 30, a passivation layer 41 located on a side of the first source-drain metal layer 40 away from the interlayer insulating layer 31, a first flat layer 42 located on a side of the passivation layer 41 away from the first source-drain metal layer 40, a second source-drain metal layer 50 (SD2) located on a side of the first flat layer 42 away from the passivation layer 41, a second flat layer 51 located on a side of the second source-drain metal layer 50 away from the first flat layer 42, a light-emitting device located on a side of the second flat layer 51 away from the second source-drain metal layer 50, and a packaging structure 60. The third direction F3 may be the thickness direction of the display substrate.

[0063] like Figure 1 as well as Figure 2 As shown, the display substrate includes a plurality of first signal lines 100 extending along a first direction F1. Part of the first signal lines 100 includes a first segment 110, a first connecting segment 120, and a second segment 130 connected in sequence, the first segment 110 and the second segment 130 are both located in the display area 1000 and extend along the first direction F1, the first connecting segment 120 is located in the transition area 2000 and is arranged around the hole area 3000, and its shape matches the shape of a portion of the edge of the hole area 3000.

[0064] The display substrate further includes a plurality of second signal lines 200 extending along the second direction F2. Part of the second signal lines 200 includes a third section 210, a second connecting section 220 and a fourth section 230 connected in sequence, the third section 210 and the fourth section 230 are both located in the display area 1000 and extend along the second direction F2, the second connecting section 220 is located in the transition area 2000 and is arranged around the hole area 3000, and its shape matches the shape of a portion of the edge of the hole area 3000.

[0065] Optionally, the display substrate further includes a plurality of scan signal lines 300 (Scan) extending along the second direction F2. Part of the scan signal lines 300 includes a fifth section 310, a third connecting section 320 and a sixth section 330 connected in sequence, the fifth section 310 and the sixth section 330 are both located in the display area 1000 and extend along the second direction F2, and the third connecting section 320 is located in the transition area 2000 and is arranged around the hole area 3000.

[0066] The first direction F1 intersects with the second direction F2 . The first direction F1 may be a length direction of the display substrate, and the second direction may be a width direction of the display substrate.

[0067] In one embodiment, the first signal line 100 may be a data signal line, and the second signal line 200 may be a light emitting control signal line. The first signal line 100 may be disposed in the first source-drain metal layer 40 and the second source-drain metal layer 50. The second signal line 200 may be disposed in the first conductive layer 20 and / or the second conductive layer 30. The scanning signal line 300 may be disposed in the first conductive layer 20 and / or the second conductive layer 30.

[0068] like Figure 3 As shown, Figure 3 Schematic diagram of the timing of the data signal Data, the light-emitting control signal EM and the gate drive signal GT of the display substrate. The data signal Data is transmitted by the data signal line, the light-emitting control signal EM is transmitted by the light-emitting control signal line, and the gate drive signal GT is transmitted by the scanning signal line 300. In the pixel driving circuit, the gate drive signal GT is used to control whether the data signal Data is written into the control electrode of the driving transistor, the data signal Data is used to control the conduction of the driving transistor, and the light-emitting control signal EM is used to control the conduction between the power supply and the light-emitting element.

[0069] In the transition area 2000, the first connection section 120 and the second connection section 220 are both arranged around the hole area 3000, and the first connection section 120 and the second connection section 220 will partially overlap in the third direction F3, resulting in parasitic capacitance between the first signal line 100 and the second signal line 200. Specifically, when the first signal line 100 is a data signal line and the second signal line 200 is a light-emitting control signal line. The light-emitting control signal EM will have a potential change in the ①, ②, ③, ④, ⑤, and ⑥ time periods. At this time, the light-emitting control signal EM will interfere with the data signals on some data signal lines, causing some data signals to fluctuate. Specifically, Figure 3 In the figure, from Dataj-1 to Dataj+2, the solid line timing part represents the original timing, and the dotted line part represents the timing after being disturbed. The disturbed data signal Data will cause the screen of the display substrate to be abnormal after being written into the control electrode of the driving transistor.

[0070] During the periods ①, ②, and ③, the gate drive signal GT of the display area 1000 controls the data signal Data not to be written into the control electrode of the driving transistor, while the gate drive signal GT of the transition area 2000 controls the data signal Data to be written into the control electrode of the driving transistor. When there are no pixels in the transition area 2000, the data signal Data disturbed during the periods ①, ②, and ③ will not cause the image of the display substrate to be abnormal. During the periods ④, ⑤, and ⑥, the gate drive signal GT of the display area 1000 controls the data signal Data to be written into the control electrode of the driving transistor. Therefore, the data signal Data disturbed during the periods ④, ⑤, and ⑥ will cause the image of the display substrate to be abnormal.

[0071] like Figure 4 As shown, the data signal lines of the display substrate are divided into a plurality of data signal line groups, each data signal line group includes eight data signal lines, and the same data signal line group includes the 8k-7th to 8kth data signal lines, and the 8k-7th to 8kth data signal lines are sequentially arranged along the second direction F2 in the display area. In the same data signal line group, the 8k-7th data signal line and the 8k-6th data signal line are connected to the same column of pixels, the 8k-5th data signal line and the 8k-4th data signal line are connected to the same column of pixels, the 8k-3th data signal line and the 8k-2th data signal line are connected to the same column of pixels, and the 8k-1st data signal line and the 8kth data signal line are connected to the same column of pixels. The 8k-7th, 8k-5th, 8k-2nd, and 8kth data signal lines are connected to the odd-numbered rows of pixels, and the 8k-6th, 8k-4th, 8k-3rd, and 8k-1st data signal lines are connected to the even-numbered rows of pixels, and k is an integer greater than 0.

[0072] The display substrate also includes a plurality of source signal lines, which are divided into a plurality of source signal line groups, each of which includes a first source signal line and a second source signal line. In the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line, and the first source signal line and the second source signal line connected to the data signal lines of the same data signal line group belong to the same source signal line group. Each data signal line is connected to the source signal line through a source driver transistor.

[0073] The display substrate also includes first to fourth multiplexing signal lines MUX1 to MUX4. In the same data signal line group, source driver transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first to fourth multiplexing signal lines MUX1 to MUX4, and the gates of source driver transistors corresponding to different data signal lines are connected to different multiplexing signal lines. The gates of source driver transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first to fourth multiplexing signal lines MUX1 to MUX4, and the source driver transistors corresponding to different data signal lines are connected to different multiplexing signal lines.

[0074] In the same data signal line group, the 8k-7th data signal line is connected to the first source signal line under the control of the first multiplexing signal line MUX1. The 8k-6th data signal line is connected to the first source signal line under the control of the third multiplexing signal line MUX3. The 8k-5th data signal line is connected to the first source signal line under the control of the second multiplexing signal line MUX2. The 8k-4th data signal line is connected to the first source signal line under the control of the fourth multiplexing signal line MUX4.

[0075] The 8k-3 data signal line is connected to the second source signal line under the control of the third multiplexing signal line MUX3. The 8k-2 data signal line is connected to the second source signal line under the control of the first multiplexing signal line MUX1. The 8k-1 data signal line is connected to the second source signal line under the control of the fourth multiplexing signal line MUX4. The 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexing signal line MUX2.

[0076] Specifically, Figure 4 As shown, the multiplexing signal line MUX is connected to the control electrode of the source driving transistor, the source signal line is connected to the first electrode of the source driving transistor, and the data signal line is connected to the second electrode of the source driving transistor. One source signal line is connected to the first electrodes of four source driving transistors respectively, the control electrodes of the four source driving transistors are connected to MUX1, MUX2, MUX3, and MUX4 respectively, and the second electrodes of the four source driving transistors are connected to four different data signal lines respectively. For example, a group of data signal lines includes D1 to D8, a group of source signal lines includes S1 and S2, and the multiplexing signal line MUX includes the first multiplexing signal line MUX1 to the fourth multiplexing signal line MUX4.

[0077] The source signal line S1 is connected to the data signal lines D1 to D4 through four source driving transistors, and the gates of the four source driving transistors are connected to MUX1, MUX3, MUX2, and MUX4 in sequence, that is, MUX1 controls the conduction between the source signal line S1 and the data signal line D1, MUX3 controls the conduction between the source signal line S1 and the data signal line D2, MUX2 controls the conduction between the source signal line S1 and the data signal line D3, and MUX4 controls the conduction between the source signal line S1 and the data signal line D4. The source signal line S2 is connected to the data signal lines D5 to D8 through four source drive transistors, and the gates of the four source drive transistors are connected to MUX3, MUX1, MUX4, and MUX2 in sequence, that is, MUX3 controls the conduction between the source signal line S2 and the data signal line D5, MUX1 controls the conduction between the source signal line S2 and the data signal line D6, MUX4 controls the conduction between the source signal line S2 and the data signal line D7, and MUX2 controls the conduction between the source signal line S2 and the data signal line D8. The subsequent source signal lines, data signal lines, and multiplexed signal lines are also connected according to this rule. Among them, D1 and D2 are connected to the first column of pixels, D3 and D4 are connected to the second column of pixels, D5 and D6 are connected to the third column of pixels, and D7 and D8 are connected to the fourth column of pixels. D1, D3, D6, and D8 are connected to the odd-numbered rows of pixels, and D2, D4, D5, and D7 are connected to the even-numbered rows of pixels.

[0078] like Figure 5 As shown, Figure 5 For along Figure 1 A cross-sectional schematic diagram of the AA line in the figure. In the related art, the first section, the first connecting section and the second section of the data signal line are located in the same film layer. The specific connection method of the signal line is the same as the above method and will not be repeated here. In a group of data signal lines, the 8k-7th, 8k-5th, 8k-3th, and 8k-1th data signal lines are arranged in the first source and drain metal layer SD1, and the 8k-6th, 8k-4th, 8k-2nd, and 8kth data signal lines are arranged in the second source and drain metal layer SD2. The data signal lines are arranged in order from small to large according to the serial number, and the data signal lines in the first source and drain metal layer SD1 and the second source and drain metal layer SD2 have no overlapping area in their orthographic projection on the substrate. Figure 5The number on the data signal line indicates which multiplexing signal line MUX controls it to be turned on. For example, the number 1 indicates that it is turned on with the source signal line through the first multiplexing signal line MUX1, and the number 3 indicates that it is turned on with the source signal line through the third multiplexing signal line MUX3. The first conductive layer GT1 and the second conductive layer GT2 are sequentially provided with scanning signal lines and light-emitting control signal lines, wherein one light-emitting control signal line is provided for every three signal lines, and the remaining positions are scanning signal lines. The orthographic projections of the signal lines in the first conductive layer GT1 and the second conductive layer GT2 on the substrate have no overlapping areas. The orthographic projections of the signal lines in the first conductive layer GT1 and the second source and drain metal layer SD2 on the substrate have no overlapping areas. The orthographic projections of the signal lines in the second conductive layer GT2 and the first source and drain metal layer SD1 on the substrate have no overlapping areas.

[0079] Table 1

[0080]

[0081] The following table combines Figure 5 For explanation. The Data wiring layer row in the table indicates at which layer the data signal line is located. MUX indicates which multiplexed signal line controls the data signal line. For example, in the second column, MUX is 1, and the Data wiring layer is SD1, indicating that the data signal line controlled by the first multiplexed signal line is located in the first source and drain metal layer SD1. The GOA signal wiring layer row in the table indicates at which layer the scan signal line and the light-emitting control signal line are located, and the GOA signal row indicates that the position is a scan signal line or a light-emitting control signal line. For example, in the second column, the GOA signal wiring layer is GT1, and the GOA signal is Scan, indicating that this is a scan signal line and the scan signal line is located in the first conductive layer GT1.

[0082] The light control signal EM on the light control signal line will interfere with the data signal on the data signal line located closer to the first source-drain metal layer SD1. Due to the shielding effect of the first source-drain metal layer SD1, the light control signal EM on the light control signal line will not interfere with the data signal line located on the second source-drain metal layer SD2. Figure 5 As shown in Table 1, the light control signal EM will interfere with the data signals on the data signal lines controlled by MUX1, MUX2, MUX3, and MUX4. That is, display abnormalities will appear unevenly in pixels of odd and even rows, so that serious X-shaped Mura (unevenness) defects will occur in the area where display abnormalities are stacked.

[0083] like Figure 6 As shown, Figure 6 For along Figure 1Schematic diagram of a cross section along line AA in FIG. In the related art, the first section, the first connecting section and the second section of the data signal line are located in the same film layer. The specific connection method of the signal line is the same as the aforementioned method and will not be described in detail here. The setting of the data signal line and the meaning of the numbers in the figure are the same as those in the above embodiment and will not be described in detail here. The first conductive layer GT1 is sequentially provided with scanning signal lines and light-emitting control signal lines, wherein one light-emitting control signal line is provided for every three signal lines, and the remaining positions are scanning signal lines. There is no overlapping area in the orthographic projection of the signal line of the first conductive layer GT1 and the signal line of the first source and drain metal layer SD1 on the substrate.

[0084] Table 2

[0085]

[0086] Combination Figure 6 As shown in Table 2, the light control signal EM will interfere with the data signals on the data signal lines controlled by MUX1, MUX2, MUX3, and MUX4. That is, display abnormalities will appear unevenly in pixels of odd and even rows, so that serious X-shaped Mura (unevenness) defects will occur in the area where display abnormalities are stacked.

[0087] like Figures 7 to 9 As shown, the interference between the first signal line 100 and the second signal line 200 is related to the distance between the two lines. The present application adjusts the distance between the first signal line 100 and the second signal line 200 in the transition area 2000 by setting the first signal line 100 in different film layers in the display area 1000 and the transition area 2000, thereby adjusting the interference of the second signal line 200 on the first signal line 100, thereby improving the display effect of the display panel. That is, the first segment 110 and the second segment 130 of the first signal line 100 of the present application are located in the same film layer, and the first connecting segment 120 and the first segment 110 and the second segment 130 are located in different film layers. Optionally, the first segment 110 and the second segment 130 can be located in the first source-drain metal layer SD1, and the first connecting segment 120 can be located in the second source-drain metal layer SD2. Alternatively, the first segment 110 and the second segment 130 can be located in the second source-drain metal layer SD2, and the first connecting segment 120 can be located in the first source-drain metal layer SD1. Specifically, take the first signal line 100 as a data signal line as an example.

[0088] The first section 110 and the second section 130 of the data signal lines at least partially connected to the pixels in odd rows among all the data signal lines are located in the first source-drain metal layer SD1, and the first connection section 120 is located in the second source-drain metal layer SD2. The first section 110 and the second section 130 of the data signal lines at least partially connected to the pixels in even rows are located in the second source-drain metal layer SD2, and the first connection section 120 is located in the first source-drain metal layer SD1. Alternatively, the first section 110 and the second section 130 of the data signal lines at least partially connected to the pixels in odd rows among all the data signal lines are located in the second source-drain metal layer SD2, and the first connection section 120 is located in the first source-drain metal layer SD1. The first section 110 and the second section 130 of the data signal lines at least partially connected to the pixels in even rows are located in the first source-drain metal layer SD1, and the first connection section 120 is located in the second source-drain metal layer SD2. At least some of the data signal lines among all the data signal lines may be data signal lines passing through the transition region 2000.

[0089] like Figures 7 to 9 As shown, Figure 7 Schematic diagram of the data signal line at the junction of the second section 130 and the first connecting section 120 . Figure 8 FIG. 1 is a schematic diagram of a data signal line at the junction of the first section 110 and the first connecting section 120 . Fig. 9 For along Figure 1 Schematic diagram of the cross section along line AA.

[0090] In a group of data signal lines, in the display area 1000, the first section 110 and the second section 130 of the 8k-7th, 8k-5th, 8k-3rd, and 8k-1st data signal lines are disposed on the first source-drain metal layer SD1. The first section 110 and the second section 130 of the 8k-6th, 8k-4th, 8k-2nd, and 8kth data signal lines are disposed on the second source-drain metal layer SD2. In the transition area 2000, the first connection section 120 of the 8k-7th, 8k-5th, 8k-2nd, and 8kth data signal lines are disposed on the first source-drain metal layer SD1, and the first connection section 120 of the 8k-6th, 8k-4th, 8k-3rd, and 8k-1st data signal lines are disposed on the second source-drain metal layer SD2. The data signal lines controlled by the third multiplexing signal line MUX3 and the fourth multiplexing signal line MUX4 are set in the second source-drain metal layer SD2 in the transition area 2000, and the data signal lines controlled by the first multiplexing signal line MUX1 and the second multiplexing signal line MUX2 are set in the second source-drain metal layer SD2 in the transition area 2000. In this way, in the transition area 2000, only the data signal lines controlled by the first multiplexing signal line MUX1 and the second multiplexing signal line MUX2 will be disturbed, that is, only the pixels in the odd-numbered rows will be disturbed, and the display abnormalities will appear uniformly in the odd-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (uneven) defects.

[0091] like Figure 7 , Figure 8 and Fig. 9 As shown, Fig. 9 For along Figure 1 Schematic diagram of the cross section of the AA line. In an optional embodiment, the connection method of a group of data signal lines, source signal lines and multiplexed signal lines is the same as the above embodiment, and no further description is given here. In the display area 1000, the first segment 110 and the second segment 130 of the 8k-7th, 8k-5th, 8k-3rd, and 8k-1st data signal lines are sequentially arranged in the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of the 8k-6th, 8k-4th, 8k-2nd, and 8kth data signal lines are sequentially arranged in the second source-drain metal layer SD2. In the transition area 2000, the first connection segments 120 of the 8k-7, 8k-5, 8k-2, and 8k data signal lines are sequentially arranged in the first source-drain metal layer SD1, and the first connection segments 120 of the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are sequentially placed in the second source-drain metal layer SD2.

[0092] The data signal lines in the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are arranged in sequence at intervals, that is, the data signal lines arranged in the first source-drain metal layer SD1 and the data signal lines arranged in the second source-drain metal layer SD2 have no overlapping area in their orthographic projections on the substrate, and the orthographic projection of the data signal line arranged in the first source-drain metal layer SD1 on the substrate falls between the orthographic projections of the two data signal lines arranged in the second source-drain metal layer SD2 on the substrate.

[0093] The first conductive layer GT1 and the second conductive layer GT2 are respectively provided with a light-emitting control signal line and a scanning signal line. The orthographic projection of the light-emitting control signal line in the first conductive layer GT1 on the substrate has no overlapping area with the orthographic projection of the data signal line of the second source-drain metal layer SD2 on the substrate, and at least partially overlaps with the orthographic projection of the data signal line of the first source-drain metal layer SD1 on the substrate. The orthographic projection of the scanning signal line in the second conductive layer GT2 on the substrate has no overlapping area with the orthographic projection of the data signal line of the first source-drain metal layer SD1 on the substrate, and at least partially overlaps with the orthographic projection of the data signal line of the second source-drain metal layer SD2 on the substrate.

[0094] Table 3

[0095]

[0096] Combination Fig. 9 As shown in Table 3, the light emitting control signal EM will only interfere with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (unevenness) defects.

[0097] like Figure 7 , Figure 8 Right now Fig.10 As shown, Fig.10 For along Figure 1Schematic diagram of the cross section of the AA line. In an optional embodiment, the connection method of a group of data signal lines, source signal lines and multiplexed signal lines is the same as the above embodiment, and no further description is given here. In the display area 1000, the first segment 110 and the second segment 130 of the 8k-7th, 8k-5th, 8k-3rd, and 8k-1st data signal lines are sequentially arranged in the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of the 8k-6th, 8k-4th, 8k-2nd, and 8kth data signal lines are sequentially arranged in the second source-drain metal layer SD2. In the transition area 2000, the first connection segments 120 of the 8k-7, 8k-5, 8k-2, and 8k data signal lines are sequentially arranged in the first source-drain metal layer SD1, and the first connection segments 120 of the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are sequentially placed in the second source-drain metal layer SD2.

[0098] The data signal lines in the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are stacked, that is, the orthographic projections of the data signal lines in the first source-drain metal layer SD1 and the data signal lines in the second source-drain metal layer SD2 on the substrate at least partially overlap.

[0099] The first conductive layer GT1 and the second conductive layer GT2 are sequentially provided with scanning signal lines and light-emitting control signal lines, wherein one light-emitting control signal line is provided for every three signal lines, and the remaining positions are scanning signal lines. The orthographic projections of the signal lines in the first conductive layer GT1 and the second conductive layer GT2 on the substrate have no overlapping areas. The orthographic projections of the signal lines in the first conductive layer GT1, the first source-drain metal layer SD1, and the second source-drain metal layer SD2 on the substrate at least partially overlap. The orthographic projections of the signal lines in the second conductive layer GT2, the first source-drain metal layer SD1, and the second source-drain metal layer SD2 on the substrate have no overlapping areas.

[0100] Table 4

[0101]

[0102] Combination Fig.10 As shown in Table 4, the light emitting control signal EM will only interfere with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (unevenness) defects.

[0103] like Figure 7 , Figure 8 Right now Fig.11 As shown, Fig.11 For along Figure 1In an optional embodiment, the connection method of a group of data signal lines, source signal lines and multiplexed signal lines is the same as that of the above embodiment, and will not be described in detail here. Fig.10 The configuration of the corresponding embodiment is the same and will not be described in detail here.

[0104] In this embodiment, the first conductive layer GT1 and the second conductive layer GT2 are respectively provided with a light-emitting control signal line and a scanning signal line. The orthographic projection of the light-emitting control signal line in the first conductive layer GT1 on the substrate overlaps at least partially with the orthographic projection of the data signal line of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 on the substrate. The orthographic projection of the light-emitting control signal line in the second conductive layer GT2 on the substrate overlaps with the orthographic projection of the data signal line of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 on the substrate.

[0105] Table 5

[0106]

[0107] Combination Fig.11 As shown in Table 5, the light emitting control signal EM will only interfere with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (unevenness) defects.

[0108] like Figure 7 , Figure 8 Right now Fig.12 As shown, Fig.12 For along Figure 1 In an optional embodiment, the connection method of a group of data signal lines, source signal lines and multiplexed signal lines is the same as that of the above embodiment, and will not be described in detail here. Fig.11 The configuration of the corresponding embodiment is the same and will not be described in detail here. Fig.11 The position of the scanning signal line in the corresponding embodiment is that the scanning signal line in this embodiment is arranged at Fig.11 Corresponding to the position of the light emission control signal line in the embodiment.

[0109] Table 6

[0110]

[0111] Combination Fig.12As shown in Table 6, the light emitting control signal EM will only interfere with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (unevenness) defects.

[0112] In an alternative embodiment, Figure 9-12 In the embodiment shown, the positions of the data signal line of the first source-drain metal layer SD1 and the data signal line of the second source-drain metal layer SD2 can be interchanged. In this way, the light-emitting control signal EM will only interfere with the data signals on the data signal lines controlled by MUX3 and MUX4. That is, only the pixels in the even-numbered rows will be interfered, and the display abnormalities will appear evenly in the even-numbered rows. In this way, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce serious X-shaped Mura (uneven) defects.

[0113] The present application also provides a display device, which includes the above-mentioned display substrate.

[0114] In one embodiment, the display device further includes a housing, and the display panel is disposed in the housing.

[0115] The display device provided in the embodiment of the present application may be, for example, a mobile phone, a tablet computer, a television, a laptop computer, a vehicle-mounted device, or any other device with a display function.

[0116] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without causing conflicts. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A display substrate, characterized in that: The display substrate comprises a display area, a transition area and a hole area, wherein the transition area surrounds the hole area, and the display area surrounds the transition area; The display substrate comprises: substrate; a plurality of first signal lines located on one side of the substrate; part of the first signal lines comprises a first section, a first connecting section and a second section connected in sequence, the first section and the second section are located in the display area and both extend along a first direction, and the first connecting section is located in the transition area; the first section and the first connecting section of part of the first signal lines are located in different film layers, and the first section and the second section are located in the same film layer; A plurality of second signal lines are located on the same side of the substrate as the first signal lines; part of the second signal lines comprises a third section, a second connecting section and a fourth section connected in sequence, the third section and the fourth section are located in the display area and extend along a second direction, the second connecting section is located in the transition area; the first direction intersects the second direction; In a partial driving period of a frame, the first signal line receives a first driving signal and the second signal line receives a second driving signal at the same time.

2. The display substrate according to claim 1, characterized in that: The first signal line includes a data signal line; the second signal line includes a light emitting control signal line.

3. The display substrate according to claim 1, characterized in that: The display substrate comprises a base, a first source-drain metal layer located at one side of the base, and a second source-drain metal layer located at a side of the first source-drain metal layer away from the base; the first source-drain metal layer and the second source-drain metal layer are insulated from each other; In some of the first signal lines, the first section and the second section are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; or, in some of the first signal lines, the first section and the second section are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; The second signal line is disposed between the substrate and the first source-drain metal layer.

4. The display substrate according to claim 3, characterized in that: The first signal line includes a data signal line; the second signal line includes a light-emitting control signal line; two adjacent data signal lines control the same column of pixels, one of which is connected to pixels located in odd rows, and the other is connected to pixels located in even rows; The first section and the second section of the data signal lines at least partially connected to the pixels in odd rows among all the data signal lines are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; the first section and the second section of the data signal lines at least partially connected to the pixels in even rows are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; or The first section and the second section of the data signal lines that are at least partially connected to the odd-numbered rows of pixels among all the data signal lines are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; the first section and the second section of the data signal lines that are at least partially connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer.

5. The display substrate according to claim 4, characterized in that: The first section and the second section of the data signal lines connected to the odd-numbered rows of pixels among all the data signal lines are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer; the first section and the second section of the data signal lines connected to the even-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; or The first section and the second section of the data signal lines connected to the odd-numbered rows of pixels among all the data signal lines are located in the second source-drain metal layer, and the first connecting section is located in the first source-drain metal layer; the first section and the second section of the data signal lines connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting section is located in the second source-drain metal layer.

6. The display substrate according to claim 5, characterized in that: The data signal lines of the display substrate are divided into a plurality of data signal line groups, each data signal line group includes eight data signal lines, and the same data signal line group includes 8k-7 to 8k data signal lines, which are sequentially arranged along the second direction in the display area; the 8k-7 data signal line and the 8k-6 data signal line in the same data signal line group are connected to the same column of pixels, the 8k-5 data signal line and the 8k-4 data signal line are connected to the same column of pixels, the 8k-3 data signal line and the 8k-2 data signal line are connected to the same column of pixels, and the 8k-1 data signal line and the 8k data signal line are connected to the same column of pixels; the 8k-7, 8k-5, 8k-2, and 8k data signal lines are connected to odd-numbered rows of pixels, and the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are connected to even-numbered rows of pixels; In the display area, the first section and the second section of the data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are arranged on the first source-drain metal layer; the first section and the second section of the data signal lines 8k-6, 8k-4, 8k-2, and 8k are arranged on the second source-drain metal layer; In the transition zone, the first connection segments of the data signal lines 8k-7, 8k-5, 8k-2, and 8k are set on the first source-drain metal layer, and the first connection segments of the data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are placed in the second source-drain metal layer; k is an integer greater than 0.

7. The display substrate according to claim 6, characterized in that: The display substrate further comprises: A source driving circuit, wherein the source driving circuit comprises a plurality of source driving transistors; A plurality of source signal lines are divided into a plurality of source signal line groups, each source signal line group includes a first source signal line and a second source signal line; in the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line, and the first source signal line and the second source signal line connected to the data signal lines of the same data signal line group belong to the same source signal line group; each of the data signal lines is connected to the source signal line through a source driving transistor; The first multiplexed signal line to the fourth multiplexed signal line; in the same data signal line group, the source driving transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first to fourth multiplexed signal lines, and the gates of the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines; the gates of the source driving transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first to fourth multiplexed signal lines, and the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines.

8. The display substrate according to claim 7, characterized in that: In the same data signal line group, the 8k-7th data signal line is connected to the first source signal line under the control of the first multiplexing signal line; the 8k-6th data signal line is connected to the first source signal line under the control of the third multiplexing signal line; the 8k-5th data signal line is connected to the first source signal line under the control of the second multiplexing signal line; the 8k-4th data signal line is connected to the first source signal line under the control of the fourth multiplexing signal line; The 8k-3 data signal line is connected to the second source signal line under the control of the third multiplexing signal line; the 8k-2 data signal line is connected to the second source signal line under the control of the first multiplexing signal line; the 8k-1 data signal line is connected to the second source signal line under the control of the fourth multiplexing signal line; the 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexing signal line.

9. The display substrate according to claim 5, characterized in that: In the transition region, the orthographic projections of the first connecting segment disposed on the first source-drain metal layer and the first connecting segment disposed on the second source-drain metal layer on the substrate have no overlapping area.

10. The display substrate according to claim 5, characterized in that: In the transition region, the first connection segment disposed on the first source-drain metal layer and the first connection segment disposed on the second source-drain metal layer have orthographic projections on the substrate that at least partially overlap.

11. The display substrate according to claim 9 or 10, characterized in that: The display substrate further comprises a second conductive layer located between the base and the first source-drain metal layer; The display substrate further comprises a plurality of scanning signal lines; part of the scanning signal lines comprises a fifth section, a third connecting section and a sixth section connected in sequence, the fifth section and the sixth section are located in the display area and both extend along the second direction, the third connecting section is located in the transition area; the scanning signal lines are arranged in the second conductive layer; In the transition region, orthographic projections of a plurality of the third connecting segments and a plurality of the first connecting segments disposed on the first source-drain metal layer on the substrate have no overlapping areas.

12. The display substrate according to claim 9 or 10, characterized in that: The display substrate further comprises a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer; The light-emitting control signal line is arranged on the first conductive layer; in the transition region, the second connecting segment at least partially overlaps with the orthographic projection of the first connecting segment arranged on the first source-drain metal layer on the substrate.

13. The display substrate according to claim 10, characterized in that: The display substrate further comprises a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer; Part of the light emitting control signal lines are arranged on the first conductive layer; Part of the light emitting control signal lines are arranged on the second conductive layer; In the transition region, the second connecting segment disposed on the first conductive layer at least partially overlaps with an orthographic projection of the first connecting segment on the substrate; The orthographic projections of the second connecting segment disposed on the second conductive layer and the first connecting segment on the substrate have no overlapping area.

14. The display substrate according to claim 10, characterized in that: The display substrate further comprises a first conductive layer located on a side of the base close to the first source-drain metal layer and a second conductive layer located on a side of the first conductive layer close to the first source-drain metal layer; The display substrate further comprises a plurality of scanning signal lines; part of the scanning signal lines comprises a fifth section, a third connecting section and a sixth section connected in sequence, the fifth section and the sixth section are located in the display area and both extend along the second direction, and the third connecting section is located in the transition area; Part of the scanning signal lines is arranged on the first conductive layer; part of the scanning signal lines is arranged on the second conductive layer; In the transition region, the third connecting segment disposed on the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment on the substrate; The third connecting segment disposed on the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment on the substrate.

15. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 14.

Images