Vertical germanium-silicon avalanche photodetector and preparation method thereof

Abstract

The invention relates to the field of photoelectric detectors, in particular to a vertical germanium-silicon avalanche photoelectric detector and a preparation method thereof. The silicon-on-insulator structure sequentially comprises a silicon-on-insulator substrate, an intrinsic silicon layer, an intrinsic germanium layer and a P-type germanium layer from bottom to top, the intrinsic silicon layer comprises an intrinsic multiplication layer; a P-type silicon charge layer is arranged at the top of the upper surface of the intrinsic multiplication layer; the P-type silicon charge layer is provided with a P-type silicon shielding ring layer along the circumferential direction; the aluminum oxide layer coats the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer, the intrinsic germanium layer and the P-type germanium layer; a spin-coating dielectric layer is arranged on the outer surface of the aluminum oxide layer; first metal electrodes are respectively arranged at two ends of the upper surface of the silicon-on-insulator substrate; according to the invention, the dark current is reduced to nanoampere magnitude, the diffusion effect of doped elements is reduced, the production cost is reduced, and the large-scale array layout of the device is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detectors, and in particular to a vertical silicon-germanium avalanche photoelectric detector and a preparation method thereof. Background Art

[0002] The rapid development of unmanned technologies such as autonomous driving has put forward new requirements for the performance of short-wave infrared detectors. Avalanche photodetectors have been widely used in weak light detection, laser radar, etc. due to their advantages such as high gain and signal-to-noise ratio. At present, commercial avalanche photodetectors used for short-wave infrared detection generally use indium phosphide (InP) and indium gallium arsenide (InGaAs) materials.

[0003] Affected by the k value of indium phosphide (InP) and indium gallium arsenide (InGaAs) materials, the device's excess noise and gain-bandwidth product are limited and difficult to further improve. In addition, since it is incompatible with silicon-based complementary metal oxide semiconductor (CMOS) technology, new process lines need to be developed, and the product yield is low. Since the material itself is expensive, its cost is high.

[0004] Germanium (Ge) avalanche photodetectors have solved the problems of compatibility with Si processes and price due to the material's own characteristics. However, due to the material's own characteristics, low multiplication and signal-to-noise ratio make it difficult to detect weak light. Therefore, a single germanium (Ge) avalanche photodetector is not a mainstream solution.

[0005] The current mainstream germanium (Ge) avalanche photodetector solution is the avalanche multiplication separation (SCAM) structure, which uses germanium as the short-wave infrared absorption region and silicon as the electron multiplication region. Taking advantage of the small (0.09) ratio of the hole-electron ionization rate (k value) of silicon as the multiplication layer, lower noise and higher gain-bandwidth product are achieved.

[0006] Due to the characteristics of germanium materials, epitaxial germanium is easily oxidized and corroded in the air, which leads to high leakage on the germanium sidewalls in vertical germanium-silicon avalanche photodetectors. Existing germanium-silicon avalanche photodetectors lack improvements in device structure and manufacturing process in this regard. As a result, existing germanium-silicon avalanche photodetectors still lag behind indium phosphide (InP) and indium gallium arsenide (InGaAs) avalanche photodetectors in performance, and it is difficult to achieve a high product yield, resulting in their failure to become the current mainstream short-wave infrared photodetectors.

[0007] Some avalanche multiplication and separation devices use molecular beam epitaxy to grow silicon and germanium. Not only does the high temperature during substrate processing cause the diffusion of doping elements to affect device performance, but the epitaxy speed is also slow, which is not conducive to industrial production. In addition, most of the known step-structured avalanche multiplication and separation type germanium silicon avalanche photodetectors do not have their surfaces flattened, and are only suitable for preparing single devices or small-scale arrays, which is not conducive to large-area array layouts. Summary of the invention

[0008] The object of the present invention is to provide a vertical silicon-germanium avalanche photodetector and a preparation method thereof, so as to solve the problems in the prior art.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a vertical silicon-germanium avalanche photodetector, which comprises, from bottom to top, a silicon-on-insulator substrate, an intrinsic silicon layer, an intrinsic germanium layer and a P-type germanium layer; the intrinsic silicon layer comprises an intrinsic multiplication layer; a P-type silicon charge layer is arranged on the top of the upper surface of the intrinsic multiplication layer; the P-type silicon charge layer is provided with a P-type silicon shielding ring layer along the circumferential direction; It also includes an aluminum oxide layer, which covers the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer, the intrinsic germanium layer and the P-type germanium layer; a spin-coated dielectric layer is provided on the outer surface of the aluminum oxide layer; first metal electrodes are provided at both ends of the upper surface of the silicon-on-insulator substrate; the first metal electrode penetrates the aluminum oxide layer and the spin-coated dielectric layer; a second metal electrode is provided on the top of the P-type germanium layer; the second metal electrode penetrates the aluminum oxide layer and the spin-coated dielectric layer.

[0010] Preferably, the silicon-on-insulator substrate comprises, from bottom to top, a bottom silicon layer, a silicon dioxide layer and an N-type silicon layer.

[0011] Preferably, boron element is injected into the P-type silicon charge layer.

[0012] Preferably, boron element is implanted into the P-type silicon shielding ring layer.

[0013] Preferably, the upper surfaces of the first metal electrode and the second metal electrode are flush with the upper surface of the spin-on dielectric layer.

[0014] Preferably, the silicon-on-insulator substrate is N-type doped, wherein the doping element is phosphorus, arsenic or antimony.

[0015] Preferably, the first metal electrode is a metal tungsten electrode.

[0016] Preferably, the second metal electrode is a metal tungsten electrode.

[0017] In a second aspect, the present invention provides a method for preparing a vertical silicon-germanium avalanche photodetector, which specifically comprises the following steps: The silicon-on-insulator substrate is cleaned, and an intrinsic silicon layer is grown on the top of the silicon-on-insulator substrate; a P-type charge layer is formed on the upper surface of the intrinsic silicon layer by ion implantation, and a P-type silicon shielding ring layer is formed along the circumference of the P-type charge layer by ion implantation; an intrinsic germanium layer and a P-type germanium layer are grown in sequence on the top of the intrinsic silicon layer; an aluminum oxide layer is generated on the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer, the intrinsic germanium layer, and the outer surface of the P-type germanium layer; A layer of dielectric is spin-coated on the outer surface of the aluminum oxide layer to form a spin-coated dielectric layer; the spin-coated dielectric layer is etched to the silicon substrate on the insulator to form a first through hole, and a first electrode is set in the first through hole; the spin-coated dielectric layer is then etched to the P-type germanium layer to form a second through hole, and a second electrode is set in the second through hole.

[0018] Preferably, the specific method of forming a P-type charge layer on the upper surface of the intrinsic silicon layer by ion implantation is: using plasma enhanced chemical vapor deposition to grow a layer of silicon dioxide on the upper surface of the intrinsic silicon layer, and then using photoresist and a mask to form a charge layer pattern to be injected on the silicon dioxide, the photoresist is used as a mask for ion implantation, and boron is selectively implanted into the epitaxial intrinsic silicon to form a P-type charge layer.

[0019] Compared with the prior art, the present invention has the following beneficial effects: Through simulation results and post-tapeout test results, it can be seen that compared with the structure without a shielding layer, the present invention adds a P-type silicon shielding ring layer, which effectively curbs the leakage of the germanium side wall. At the same time, through the sidewall passivation process, the sidewall leakage caused by surface defects is further suppressed, and the dark current is further reduced to the nanoampere level.

[0020] Furthermore, compared with molecular beam epitaxy, reduced pressure chemical vapor deposition can grow high-quality silicon and germanium at a lower temperature and at a faster rate, which is beneficial to reducing the diffusion effect of doping elements, reducing production costs, and facilitating industrial production; the present invention uses spin-coated dielectrics and chemical mechanical polishing to flatten the device surface, which is beneficial to large-scale array layout of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0022] Figure 1A cross-sectional view of a vertical silicon-germanium avalanche photodetector structure of the present invention; Figure 2 It is a schematic diagram of the simulation results and test data after tape-out of the photoelectric detector of the present invention.

[0023] In the figure, 1-bottom silicon layer; 2-silicon dioxide layer; 3-N-type silicon; 4-intrinsic silicon layer; 41-intrinsic multiplication layer; 42-P-type silicon charge layer; 43-P-type silicon shielding ring layer; 5-intrinsic germanium layer; 6-P-type germanium layer; 7-aluminum oxide layer; 8-spin-coated dielectric layer; 9-first metal electrode; 10-second metal electrode. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to understand the characteristics and effects of the present invention, the following is a general description and definition of the terms and expressions mentioned in the specification and claims. Unless otherwise specified, all technical and scientific terms used in the text are the common meanings understood by those skilled in the art for the present invention. In the event of a conflict, the definition in this specification shall prevail.

[0025] The theories or mechanisms described and disclosed herein, whether correct or incorrect, should not limit the scope of the present invention in any way, that is, the present invention can be implemented without being limited by any specific theory or mechanism.

[0026] In this article, all features such as values, quantities, contents and concentrations defined in the form of numerical ranges or percentage ranges are for simplicity and convenience only. Accordingly, the description of numerical ranges or percentage ranges should be considered to have included and specifically disclosed all possible secondary ranges and individual values ​​within the range (including integers and fractions).

[0027] In this document, unless otherwise specified, “includes,” “including,” “contains,” “has,” or similar terms cover the meanings of “consisting of” and “mainly consisting of,” for example, “A includes a” covers the meanings of “A includes a and other” and “A only includes a.”

[0028] In this document, in order to make the description concise, not all possible combinations of various technical features in various embodiments or examples are described. Therefore, as long as there is no contradiction in the combination of these technical features, the various technical features in various embodiments or examples can be combined arbitrarily, and all possible combinations should be considered to be within the scope of this specification.

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings: like Figure 1As shown, the present invention provides a vertical silicon-germanium avalanche photodetector, which comprises, from bottom to top, a silicon-on-insulator substrate, an intrinsic silicon layer 4, an intrinsic germanium layer 5 and a P-type germanium layer 6; the intrinsic silicon layer 4 comprises an intrinsic multiplication layer 41; a P-type silicon charge layer 42 is arranged on the top of the upper surface of the intrinsic multiplication layer 41; the P-type silicon charge layer 42 is circumferentially provided with a P-type silicon shielding ring layer 43; It also includes an aluminum oxide layer 7, which covers the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer 4, the intrinsic germanium layer 5 and the P-type germanium layer 6; a spin-coated dielectric layer 8 is provided on the outer surface of the aluminum oxide layer 7; first metal electrodes 9 are respectively provided at both ends of the upper surface of the silicon-on-insulator substrate; the first metal electrode 9 penetrates the aluminum oxide layer 7 and the spin-coated dielectric layer 8; a second metal electrode 10 is provided on the top of the P-type germanium layer 6; the second metal electrode 10 penetrates the aluminum oxide layer 7 and the spin-coated dielectric layer 8.

[0030] The silicon-on-insulator substrate serves as the base of the detector and can provide stable mechanical support and electrical isolation. The insulator helps to reduce the impact of the substrate on the device performance and improve the integration and compatibility of the device. The spin-coated dielectric layer 8 serves as an isolation and protection layer to prevent the intrinsic silicon layer 4, the intrinsic germanium layer 5 and the P-type germanium layer 6 from direct contact with the external environment, thereby reducing pollution and damage. The intrinsic germanium layer 5 can absorb photons and generate photogenerated carriers. The design of germanium-silicon absorption multiplication separation can optimize light absorption and carrier transmission performance and improve the sensitivity of the detector. The aluminum oxide layer 7 serves as an isolation layer to prevent direct contact and mutual interference between the layers, and can provide good electrical performance and thermal stability, ensuring the long-term stable operation of the device. The first metal electrode 9 and the second metal electrode 10 serve as electrical contact points to achieve connection with the external circuit.

[0031] The silicon-on-insulator substrate includes, from bottom to top, a bottom silicon layer 1, a silicon dioxide layer 2, and an N-type silicon layer 3. The bottom silicon layer 1 provides stable mechanical support to ensure the reliability of the device during long-term operation. The silicon dioxide layer 2, as an insulating layer, effectively prevents electrical interference and impurity diffusion, further improving the stability of the device. The N-type silicon layer 3 provides free electrons through doping, and forms a PIN junction with the subsequent P-type silicon charge layer and the intrinsic silicon layer, which helps to optimize the electrical performance and improve the sensitivity and response speed of the detector.

[0032] The P-type silicon charge layer 42 is implanted with boron. The P-type silicon shielding ring layer 43 is implanted with boron. Boron has fewer valence electrons than silicon, so it forms holes when it replaces silicon atoms in the silicon lattice. The P-type silicon shielding ring layer 43 is formed into a P-type semiconductor by doping boron, which can shield the edge electric field and prevent the electric field from leaking or generating unnecessary distribution. This helps to optimize the electric field distribution of the detector and improve the detection efficiency.

[0033] The upper surfaces of the first metal electrode 9 and the second metal electrode 10 are flush with the upper surface of the spin-coated dielectric layer 8. The first metal electrode 9 and the second metal electrode 10 are both metal tungsten electrodes.

[0034] The silicon-on-insulator substrate is N-type doped, wherein the doping element is phosphorus, arsenic or antimony.

[0035] The second object of the present invention is to provide a method for preparing a vertical silicon-germanium avalanche photodetector, which specifically comprises the following steps: The silicon-on-insulator substrate is cleaned, and an intrinsic silicon layer 4 is grown on the top of the silicon-on-insulator substrate; a P-type charge layer 42 is formed on the upper surface of the intrinsic silicon layer 4 by ion implantation, and a P-type silicon shielding ring layer 43 is formed along the circumference of the P-type charge layer 42 by ion implantation; an intrinsic germanium layer 5 and a P-type germanium layer 6 are grown in sequence on the top of the intrinsic silicon layer 4; an aluminum oxide layer 7 is formed on the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer 4, the intrinsic germanium layer 5, and the outer surface of the P-type germanium layer 6; A layer of dielectric is spin-coated on the outer surface of the aluminum oxide layer 7 to form a spin-coated dielectric layer 8; the spin-coated dielectric layer 8 is etched to the silicon substrate on the insulator to form a first through hole, and a first electrode 9 is set in the first through hole; the spin-coated dielectric layer 8 is then etched to the P-type germanium layer 6 to form a second through hole, and a second electrode 10 is set in the second through hole.

[0036] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0037] The following examples use conventional instruments and equipment in the art. The experimental methods in the following examples where specific conditions are not specified are usually carried out under conventional conditions or under conditions recommended by the manufacturer. The various raw materials used in the following examples are conventional commercial products unless otherwise specified, and their specifications are conventional specifications in the art. In the specification of the present invention and the following examples, unless otherwise specified, "%" means weight percentage, "part" means weight part, and ratio means weight ratio.

[0038] The concentration is about 10 18 -10 20 cm -3The N-type doped (doping elements include but are not limited to phosphorus (P), arsenic (As), antimony (Sb), etc.) silicon-on-insulator (SOI) substrate is cleaned by standard process, and a layer of intrinsic silicon layer 4 with a thickness of 600-1000 nanometers is grown on the top of the silicon-on-insulator substrate using reduced pressure chemical vapor deposition (RPCVD) equipment.

[0039] Then, a 50-nanometer silicon dioxide (SiO2) layer is grown on the upper surface of the intrinsic silicon layer 4 by plasma enhanced chemical vapor deposition (PECVD) as a protective layer for the silicon surface during ion implantation to reduce the damage to the silicon surface caused by high-energy particles. The charge layer pattern to be implanted is formed on the silicon oxide using photoresist and mask. The photoresist is used as a mask for ion implantation to selectively implant boron (B) elements into the epitaxial intrinsic silicon (implantation depth is about 150-200 nanometers, doping concentration is 10 17 -10 19 cm -3 ), forming a P-type charge layer 42.

[0040] After the injection is completed, the photoresist is removed, and the photoresist and mask are used again to form the shielding layer pattern to be injected on the intrinsic silicon layer 4. The photoresist and silicon dioxide are still used as masks and protective layers for P-type shielding ring injection. The injected element is B, the injection depth is 50 nanometers shallower than the charge layer (corresponding to 100-150 nanometers), and the doping concentration is one to two orders of magnitude lower than the charge layer (corresponding to a doping concentration of 10 16 -10 18 cm -3 ), forming a P-type silicon shielding ring layer 43.

[0041] The remaining intrinsic silicon layer 4 without implanted elements is the intrinsic multiplication layer 41 .

[0042] The substrate wafer after two ion implantations is cleaned again using a standard process to remove surface contaminants such as photoresist, SiO2, organic matter, and metal ions.

[0043] A layer of high-quality intrinsic germanium (Ge) with a thickness of 500-700 nanometers is grown on top of the intrinsic silicon layer 4 using reduced pressure chemical vapor deposition (RPCVD) to form an intrinsic germanium layer 5. Borane is then added to the gas to grow a layer of high-quality P-type germanium with a thickness of 150-250 nanometers (doping concentration is about 10 18 -10 20 cm -3 ), and utilize the temperature during the growth of Ge (500-800 degrees Celsius) to activate the previously implanted boron ions, thereby forming a P-type germanium layer 6.

[0044] A 20-nanometer aluminum oxide (Al2O3) film is formed on the surface by atomic layer deposition (ALD) to form an aluminum oxide layer 7, which can not only isolate germanium from direct contact with air, avoiding oxidation and corrosion of germanium in the air, but also be used as a hard mask during the etching process.

[0045] The pattern to be etched is formed on aluminum oxide using photoresist and mask, and the area to be etched is etched using inductively coupled plasma (ICP) equipment: first, the hard mask (aluminum oxide) is etched using an aluminum oxide etching procedure. The pattern of the photoresist is transferred to the hard mask. Then, the germanium is etched using an optimized germanium and silicon etching procedure, and the etching is carried out to the P-type silicon shielding ring layer 43 to achieve a good suppression effect on the germanium sidewall current, and the corresponding etching depth is 500-700 nanometers. The etching depth and effect are characterized using an atomic force microscope and a scanning electron microscope.

[0046] Removing the etched aluminum oxide by wet etching: Using the atomic layer deposition equipment again to grow a 20-nanometer layer of aluminum oxide, the aluminum oxide layer 7 is used as a hard mask for the next etching and also as a protection for the etching sidewalls to prevent the plasma from corroding the sidewalls (after the previous etching) during the next etching process. Using photoresist and mask, a second step pattern to be etched is formed on the aluminum oxide layer 7.

[0047] First, the hard mask (aluminum oxide) is etched using an aluminum oxide etching procedure. The pattern of the photoresist is transferred to the hard mask. Then, the epitaxial intrinsic silicon is etched using an optimized germanium and silicon etching procedure to the N-type silicon substrate layer, with a corresponding etching depth of about 600-1000 nanometers. The etching depth and effect are characterized using an atomic force microscope and a scanning electron microscope.

[0048] Wet etching is used to remove aluminum oxide after etching: the device after photoresist removal is treated in an oxygen plasma atmosphere for 15-30 seconds to remove the macromolecular polymer formed on the side wall due to etching by oxidation. Wet etching (hydrofluoric acid: deionized water = 1:50, soaking for 30 seconds) is used to remove silicon oxides and germanium oxides of different valence states on the side wall.

[0049] Immediately place the device in an ozone or oxygen plasma atmosphere to fully oxidize the sidewalls, forming relatively stable silicon dioxide (SiO2) and germanium monoxide (Ge2O) on the silicon and germanium surfaces, respectively. Use a vacuum transfer cavity to transfer the device to an atomic layer deposition (ALD) chamber under vacuum conditions to grow 10-20 nanometers of high-quality and dense aluminum oxide (Al2O3). Isolate the outside air from the contact between silicon dioxide and germanium monoxide on the device surface, thereby protecting the sidewalls. Effectively reduce the dark current on the sidewalls.

[0050] A layer of dielectric (including but not limited to Fox-15) is spin-coated to form a spin-coated dielectric layer 8, which is then denatured into silicon dioxide by heating or exposure to fill the device surface. The surface is flattened by chemical mechanical polishing, and the spin-coated dielectric layer 8 is thinned to 100-300 nanometers above the top interface.

[0051] The etching pattern of the through hole of the silicon substrate on the insulator is formed by using photoresist: the first through hole contacting the N-type silicon layer 3 is etched by using the Bosch process. The above two steps are repeated to etch the second through hole contacting the top P-type germanium layer 6. Metal tungsten is deposited in the through hole by chemical vapor deposition, and a metal tungsten electrode with a flat top is obtained by chemical mechanical polishing.

[0052] like Figure 2 As shown, through the simulation results and the test results after tape-out, it can be known that compared with the structure without a shielding layer, the present invention adds a P-type shielding ring 43, and accurately controls the etching of the first layer of steps to the P-type shielding ring 43, and the P-type shielding ring 43 effectively curbs the leakage of the germanium side wall. At the same time, the present invention adopts a sidewall passivation process to further suppress the sidewall leakage caused by surface defects, etc., so that the dark current is further reduced to the nanoampere level. Compared with molecular beam epitaxy, reduced pressure chemical vapor deposition can grow high-quality silicon and germanium at a faster rate at a lower temperature, which is beneficial to reduce the diffusion effect of doping elements, reduce production costs, and is beneficial to industrial production. In addition, the present invention uses spin-coated dielectrics and chemical mechanical polishing to flatten the device surface, which is beneficial to the large-scale array layout of the device.

[0053] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A vertical silicon-germanium avalanche photodetector, characterized in that: The invention comprises, from bottom to top, a silicon substrate on an insulator, an intrinsic silicon layer (4), an intrinsic germanium layer (5) and a P-type germanium layer (6); the intrinsic silicon layer (4) comprises an intrinsic multiplication layer (41); a P-type silicon charge layer (42) is arranged on the top of the upper surface of the intrinsic multiplication layer (41); and a P-type silicon shielding ring layer (43) is arranged along the circumference of the P-type silicon charge layer (42); It also comprises an aluminum oxide layer (7), the aluminum oxide layer (7) covers the upper surface of the silicon-on-insulator substrate, the intrinsic silicon layer (4), the intrinsic germanium layer (5) and the P-type germanium layer (6); a spin-coated dielectric layer (8) is provided on the outer surface of the aluminum oxide layer (7); first metal electrodes (9) are provided at both ends of the upper surface of the silicon-on-insulator substrate; the first metal electrode (9) penetrates the aluminum oxide layer (7) and the spin-coated dielectric layer (8); a second metal electrode (10) is provided on the top of the P-type germanium layer (6); the second metal electrode (10) penetrates the aluminum oxide layer (7) and the spin-coated dielectric layer (8).

2. A vertical SiGe avalanche photodetector according to claim 1, characterized in that: The silicon-on-insulator substrate comprises, from bottom to top, a bottom silicon layer (1), a silicon dioxide layer (2) and an N-type silicon layer (3).

3. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: Boron element is injected into the P-type silicon charge layer (42).

4. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: Boron element is implanted into the P-type silicon shielding ring layer (43).

5. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: The upper surfaces of the first metal electrode (9) and the second metal electrode (10) are flush with the upper surface of the spin-coated dielectric layer (8).

6. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: The silicon-on-insulator substrate is N-type doped, wherein the doping element is phosphorus, arsenic or antimony.

7. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: The first metal electrode (9) is a metal tungsten electrode.

8. The vertical SiGe avalanche photodetector according to claim 1, characterized in that: The second metal electrode (10) is a metal tungsten electrode.

9. A method for preparing a vertical SiGe avalanche photodetector according to any one of claims 1 to 8, characterized in that: The specific steps include: The silicon-on-insulator substrate is cleaned, and an intrinsic silicon layer (4) is grown on the top of the silicon-on-insulator substrate; a P-type charge layer (42) is formed on the top surface of the intrinsic silicon layer (4) by ion implantation, and a P-type silicon shielding ring layer (43) is formed along the circumference of the P-type charge layer (42) by ion implantation; an intrinsic germanium layer (5) and a P-type germanium layer (6) are grown in sequence on the top of the intrinsic silicon layer (4); and an aluminum oxide layer (7) is formed on the top surface of the silicon-on-insulator substrate, the intrinsic silicon layer (4), the intrinsic germanium layer (5), and the outer surface of the P-type germanium layer (6); A layer of dielectric is spin-coated on the outer surface of the aluminum oxide layer (7) to form a spin-coated dielectric layer (8); the spin-coated dielectric layer (8) is etched to the silicon substrate on the insulator to form a first through hole, and a first electrode (9) is arranged in the first through hole; the spin-coated dielectric layer (8) is then etched to the P-type germanium layer (6) to form a second through hole, and a second electrode (10) is arranged in the second through hole.

10. The method for preparing a vertical SiGe avalanche photodetector according to claim 9, characterized in that: The specific method for forming the P-type charge layer (42) on the upper surface of the intrinsic silicon layer (4) by ion implantation is as follows: a layer of silicon dioxide is grown on the upper surface of the intrinsic silicon layer (4) by plasma enhanced chemical vapor deposition, and a pattern of the charge layer to be implanted is formed on the silicon dioxide by using a photoresist and a mask. The photoresist is used as a mask for ion implantation to selectively implant boron elements into the epitaxial intrinsic silicon to form the P-type charge layer (42).

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