Imaging device, imaging method and electronic equipment

Abstract

The image forming apparatus includes a controller and a generator. The controller controls the imaging unit based on a command and data received from the host according to an I2C / I3C communication protocol. The generator generates a second control signal indicating whether to apply Intra Dynamic Frequency Scaling (DFS) or Intra Dynamic Voltage Frequency Scaling (DVFS) based on a first control signal received from the host via a first route different from the I2C / I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C / I3C communication protocol.

Description

Background Art

[0001] The present disclosure relates to an imaging device, an imaging method, and an electronic device.

[0002] Recently, imaging devices have been developed in metal oxide semiconductor (MOS) image sensors such as complementary metal oxide semiconductor (CMOS). For example, Japanese Unexamined Patent Application Publication No. 2010-245506 discloses an imaging device in which a semiconductor wafer having a pixel array portion and a semiconductor wafer having a logic circuit are laminated. Summary of the invention

[0003] It has been desired to save power consumption of imaging devices.

[0004] It is desirable to provide an imaging device, an imaging method, and an electronic device, which are capable of saving power consumption.

[0005] An imaging device according to a first aspect of the present disclosure includes a controller and a generator. The controller controls an imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol. The generator generates a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from the host via a first route different from the I2C / I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C / I3C communication protocol.

[0006] The imaging method according to the first aspect of the present disclosure comprises:

[0007] generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal transmitted from a host transmitting commands and data according to the I2C / I3C communication protocol via a first route different from the I2C / I3C communication protocol; and

[0008] The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

[0009] An electronic device according to a first aspect of the present disclosure includes a host, a controller and a generator. The host is configured to communicate according to an I2C / I3C communication protocol. The controller controls an imaging unit based on commands and data received from the host according to the I2C / I3C communication protocol. The generator generates a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from the host via a first route different from the I2C / I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C / I3C communication protocol.

[0010] An imaging device according to a second aspect of the present disclosure includes a controller and a generator. The controller controls an imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol. The generator decodes a slave address included in a command received from the host, and generates a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by decoding, and outputs the control signal to the host via a route different from the I2C / I3C communication protocol.

[0011] The imaging method according to the second aspect of the present disclosure comprises:

[0012] decoding a slave address included in a virtual command transmitted from a host transmitting commands and data according to an I2C / I3C communication protocol;

[0013] generating a control signal based on the slave address obtained by decoding, the control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS); and

[0014] The control signal is output to the host via a route different from the I2C / I3C communication protocol.

[0015] An electronic device according to a second aspect of the present disclosure includes a host, a controller, and a generator. The host is configured to communicate according to an I2C / I3C communication protocol. The controller controls an imaging unit based on commands and data received from the host according to the I2C / I3C communication protocol. The generator decodes a slave address included in a virtual command received from the host, generates a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by decoding, and outputs the control signal to the host via a route different from the I2C / I3C communication protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and together with the description serve to explain the principles of the disclosure.

[0017] Figure 1A is a diagram illustrating an exemplary temporal variation of a clock frequency observed when dynamic frequency scaling (DFS) is performed in a CMOS image sensor.

[0018] Figure 1B is a diagram illustrating an exemplary temporal variation of a clock frequency observed when dynamic frequency scaling (DFS) is performed in a CMOS image sensor.

[0019] Figure 1C is a diagram illustrating an exemplary temporal variation of a clock frequency observed when dynamic frequency scaling (DFS) is performed in a CMOS image sensor.

[0020] Figure 2 It is a summary Figures 1A to 1C Clock control table shown.

[0021] Figure 3A is a diagram illustrating an exemplary temporal variation of a clock voltage observed when dynamic voltage scaling (DVS) is performed in a CMOS image sensor.

[0022] Figure 3B is a diagram illustrating exemplary temporal variations of a clock voltage observed when dynamic voltage scaling (DVS) is performed in a CMOS image sensor.

[0023] Figure 3C is a diagram illustrating exemplary temporal variations of a clock voltage observed when dynamic voltage scaling (DVS) is performed in a CMOS image sensor.

[0024] Figure 4 is a table summarizing the power control shown in FIG. 3 .

[0025] Figure 5 : is a block diagram showing an exemplary configuration of an imaging device according to an embodiment of the present disclosure.

[0026] Figure 6 It is shown in Figure 5 Schematic diagram of an exemplary method of controlling DFS in an imaging device shown in FIG.

[0027] Figure 7 It is shown in Figure 5 Schematic diagram of a modified example of a method of controlling DFS in an imaging device shown in FIG.

[0028] Figure 8 It is shown in Figure 5 0 is a block diagram of a modified example of the configuration of the imaging device shown in FIG.

[0029] Fig. 9 It is shown Figure 8 0048 is a block diagram of an exemplary configuration of an I2C / I3C block shown in FIG.

[0030] Fig.10 : is a schematic block diagram showing an exemplary configuration of an imaging system including an imaging device according to any of the above-described embodiments and modifications. DETAILED DESCRIPTION

[0031] Some embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the following description relates to illustrative examples of the present disclosure and is not to be construed as limiting the present disclosure. Factors including but not limited to numerical values, shapes, materials, components, the positions of components, and how components are coupled to each other are merely illustrative and should not be construed as limiting the present disclosure. In addition, the elements not stated in the most general independent claims of the present disclosure in the following exemplary embodiments are optional and may be provided as required. The accompanying drawings are schematic and are not intended to be drawn to scale. Throughout this specification and the accompanying drawings, elements having substantially the same function and configuration are represented by the same reference numerals without any redundant description.

[0032] 1. Intra-frame DFS and intra-frame DVS

[0033] Dynamic frequency scaling (DFS) is a technique for saving power consumption by dynamically changing the clock frequency according to the operation mode to prevent the circuit from operating at an unnecessary high clock frequency. Unlike clock gating, which involves clock on / off operations, DFS involves raising or lowering the clock frequency.

[0034] Dynamic voltage scaling (DVS) is a technique that can be combined with DFS to achieve high power voltage operation when the clock frequency is high, and low power voltage operation when the clock frequency is low. The combined use of DFS and DVS enables greater power consumption savings than a single use of DFS. The combination of DFS and DVS is sometimes referred to as dynamic voltage and frequency scaling (DVFS). Unlike power gating, which involves power on / off operations, DVS involves changing the power supply voltage.

[0035] According to an embodiment of the present disclosure, power consumption of a CMOS image sensor (CIS) in a normally-on mode is saved by using DFS within a frame operation (hereinafter referred to as "intra-frame DFS"). In addition, in the viewing mode, only the intra-frame DFS is applied to a mode with an image of VGA size or smaller to save power consumption by the CIS according to an embodiment of the present disclosure. The normally-on mode of the CIS according to an embodiment of the present disclosure refers to a mode in which motion detection is performed on an image of a size of 32×10 (monochrome), and the viewing mode of the CIS according to an embodiment of the present disclosure refers to a mode in which image data of a size of 320×120 (color) or larger is output from a mobile industry processor interface (MIPI) block.

[0036] One frame of CIS operation consists of the repetition of the following cycles (1) to (4):

[0037] (1) Shutter cycle: Reset the photodiode in the pixel

[0038] (2) Integration (or exposure) period: Photoelectric conversion of photodiodes

[0039] (3) Read cycle: A / D conversion of the photodiode charge

[0040] (4) V blanking period: waiting time until the next frame starts

[0041] In the case of using a small size image or a low frame rate, such as in the always-on mode or the viewing mode with a VGA image size or smaller, the shutter period (1) and the read period (3) are relatively short, and the V blanking period (4) occupies most of the time of one frame. Thus, by saving power consumption in the V blanking period (4), the average power of the CIS is reduced.

[0042] The necessary function to be implemented in the V blanking period (4) is to simply wait for the start timing of the next frame. Therefore, in order to meet the necessary function in the V blanking period (4), it is sufficient to operate the selective block by supplying a low-frequency clock signal to the selective block. In the case of a rolling shutter CIS with a short exposure time, in some cases, the reading operation of the first row may be started before the shutter operation of the last row is completed. Thus, the integration period (2) may not exist in some cases. Here, the integration period (2) refers to a period about the operating state of the sensor as a simple waiting time from the completion of the shutter operation to the start of the reading operation for all pixels, rather than the exposure time of each pixel.

[0043] In the case of allowing a small size image and a low accuracy ADC, such as in the normally open mode, the shutter period (1) and the read period (3) are short. Thus, in many cases, the integration period (2) is retained. In the integration period (2), the time until the start of the read operation is simply counted. Therefore, the selective block can be operated by supplying a low frequency clock. This also effectively saves the power consumption of the CIS in the integration period (2) such as in the V blanking period (4).

[0044] According to the CIS of the embodiment of the present disclosure, the V blanking period (4) and the integration period (2) are the time to wait until the start of the next frame or the start of reading while applying only the clock with a frequency of 422kHz to the circuit. In the V blanking period (4) and the integration period (2), the clock is stopped in the CPU and the bus coupled to the CPU. Figures 1A to 1C Each conceptually represents the change in clock frequency within a frame. Figures 1A to 1C In each of the figures, the CIS according to the embodiment of the present disclosure is shown in comparison with the existing CIS. These conceptual diagrams show a case in which there is no remaining integration period (2). According to the existing CIS, intra-frame clock gating is performed in the SIF block described below, and inter-frame mode DFS is performed in the CU block, PM / CK block, and SYS block described below. In contrast, according to the CIS of the embodiment of the present disclosure, intra-frame clock gating is performed in the SIF block and SYS block described below, and intra-frame DFS is performed in the CU block and PM / CK block. The CIS according to the embodiment of the present invention is characterized in that the newly introduced technology involves inter-frame mode DFS in the CU block and PM / CK block and intra-frame DFS.

[0045] Figure 2 The clock control for the CIS according to the embodiment of the present disclosure is summarized. The clock control of the CIS according to the embodiment of the present invention is characterized by the newly introduced intra-frame DFS.

[0046] By operating only with a 422 kHz clock during the V blanking period and the integration period, the circuit can operate with a power supply voltage much lower than the standard power supply voltage of 1.05 V. The operating specification of the CIS according to the embodiment of the present disclosure has been modified to allow the following use: For the SYSTOP block that accommodates the SRAM, all clocks are stopped, and during the V blanking period and the integration period, the SYSTOP block is provided with only the power supply voltage required to maintain the latest state until the next operation is started.

[0047] FIG. 3A to FIG. 3CEach conceptually represents a change in the power supply voltage within a frame. According to the existing CIS, inter-frame mode power gating is performed in the DU block and the IFD block, intra-frame power gating is performed in the SIF block, and the standard voltage of 1.05V is constantly supplied to the CU block, the PM / CK block, and the SYS block. In contrast, according to the CIS of the embodiment of the present disclosure, inter-frame mode DVS and intra-frame DVS are performed in the CU block, the PM / CK block, and the SYS block, instead of constantly supplying the standard voltage. The CIS of the embodiment of the present disclosure is characterized by a newly introduced technology involving inter-frame mode DVS and intra-frame DVS in the CU block, the PM / CK block, and the SYS block, instead of constantly supplying the standard voltage.

[0048] Figure 4 The power control adopted in the embodiment of the present disclosure is summarized. According to the embodiment of the present disclosure, the technology related to the inter-mode DVS and intra-mode DVS can be newly introduced into the power control of CIS.

[0049] 2. Questions about the introduction of intra-frame DFS

[0050] Specifications for using host-based DFS control

[0051] According to the specification of DFS of the CIS applied to the embodiment of the present disclosure, the clock supply to the SYS block is stopped in the V blanking period. Another conceivable option for using intra-frame DFS to save power consumption is to operate the SYS block with a clock of 422kHz, as in the case of the CU block and the PM / CK block. However, even if the SYS block is designed to operate with a clock of 422kHz, some peripheral blocks in the SYS block may not be able to operate with a clock of 422kHz alone. The peripheral blocks in the SYS block may include an I2C block and an I3C block. Thus, there is a small functional difference between the case in which the clock is completely stopped and the case in which the SYS block operates with a clock of 422kHz. Thus, the clock for the SYS block is stopped in the CIS according to the embodiment of the present disclosure.

[0052] At the same time, the use of DFS raises concerns that communication from a host (which may be an external controller such as an application processor) to a CIS according to an embodiment of the present disclosure is disabled. When the SYS block is operating, the host is able to control the SYS block using an I2C block or an I3C block. However, once the SYS block is switched to a DFS-application mode in which DFS is applied under the control of the host, it is difficult for the host to control the SYS block, making it difficult to switch from the DFS-application mode back to a DFS-unapplication mode in which DFS is not applied. A detailed examination of the operation of the CIS according to an embodiment of the present disclosure demonstrates that DFS is performed within a frame. The SYS block therefore operates constantly in a shutter cycle and a read cycle. Thus, the host is able to communicate with the SYS block only in a shutter cycle and a read cycle. However, the host cannot recognize when the SYS block is operating. This places a restriction on the specification of the CIS: regardless of the operating state of the CIS according to an embodiment of the present disclosure, when the DFS-application mode is selected, the I2C block and the I3C block should not be used to perform communication from the host to the SYS block.

[0053] As described above, once switched to DFS application mode, the host finds it difficult to control the SYS block. A conceivable measure to solve this problem is to change the specification of the I2C block or the I3C block so that the host can control the CIS even in DFS-application mode. However, it is difficult to change the basic block design within a limited time period. Here, two methods are proposed to address this concern about CIS. The first method includes extending the function of the existing GPO pin (output from the CIS) and changing the specification of the existing GPI pin (input to the CIS) to enable the host to control DFS. The second method includes separating the specific functions of the I2C or I3C block that can operate in a clockless manner from the functions that can operate with a clock, and using a front-end unit with a specific function that can operate in a clockless manner to enable the host to control DFS. In the following, the first method is described in the embodiment described below, and the second method is described in a modified example of the embodiment described below.

[0054] 3. Example

[0055] Figure 5 1 is a block diagram showing an exemplary configuration of an imaging device 100 according to an embodiment of the present disclosure. The imaging device 100 includes a controller (DGTOP) 110 and an imaging unit 120. The imaging unit 120 acquires image data through imaging and outputs the acquired image data to the controller 110. The controller 110 controls imaging in the imaging unit 120 and outputs image data obtained by imaging in the imaging unit 120 to an application processor 200 serving as a host.

[0056] The controller 110 includes a SYS block 10 , a CU block 20 , a PM / CK block 30 , a SIF block 40 , a DU block 50 , and a mipi block 60 .

[0057] The SIF block 40 is an interface for receiving image data obtained by the imaging unit 120. The SIF block 40 outputs the image data received from the imaging unit 120 to the DU block 50. The DU block 50 performs predetermined image processing on the image data received from the imaging unit 120 via the SIF block 40, and outputs the obtained image data to the mipi block 60. The mipi block 60 communicates with the application processor 200 according to the mipi protocol. For example, the mipi block 60 transmits the image data received from the DU block 50 to the application processor 200 according to the mipi protocol.

[0058] The SYS block 10 communicates with the application processor 200. The SYS block 10 controls the imaging unit 120 based on an I2C / I3C signal received from the application processor 200 according to the I2C / I3C communication protocol. In this document, the term "I2C / I3C" refers to I2C or I3C. The I2C / I3C communication protocol is a protocol for communication between the imaging unit 120 and the application processor 200 that controls the imaging unit 120. The SYS block 10 includes, for example, a CPU 11 and an I2C / I3C block 12. The CPU 11 controls the imaging unit 120 based on commands and data received from the application processor 200 via the I2C / I3C block 12. The I2C / I3C block 12 communicates with the application processor 200 via a terminal t3 according to the I2C / I3C communication protocol. For example, the I2C / I3C block 12 retrieves commands and data from I2C / I3C signals received from the application processor 200, and outputs the retrieved commands and data to the CPU 11. The CPU 11 and the I2C / I3C block 12 operate based on several clock signals transmitted from the PM / CK block 30. The SYS block 10, the CU block 20, and the PM / CK block 30 perform mutual data communication, for example, via a bus.

[0059] The CU block 20 generates an imaging unit control signal based on the control signal received from the SYS block 10, and outputs the imaging unit control signal to the imaging unit 120. The CU block 20 and the PM / CK block 30 control the start timing and end timing of each operating state by operating in cooperation with each other. Examples of the operating states controlled by the CU block 20 and the PM / CK block 30 may include a shutter period, an integration period, a read period, and a V blanking period.

[0060] The PM / CK block 30 sets the frequency of a clock signal for operating the SYS block 10 (hereinafter, referred to as "clock frequency") based on the GPI signal received from the application processor 200 via the GPI terminal t1. For example, the PM / CK block 30 determines the polarity of the GPI signal received from the application processor 200 via the GPI terminal t1. For example, the PM / CK block 30 determines the polarity of the GPI signal at the start timing of a predetermined operation state (e.g., an integration period or a V blanking period). The PM / CK block 30 sets the clock frequency for operating the SYS block 10 based on the determination result. For example, the PM / CK block 30 sets the clock frequency for a predetermined operation state (e.g., an integration period or a V blanking period) based on the determination result. For example, when the GPI signal has a high polarity, the PM / CK block 30 sets the clock frequency to a relatively high frequency. For example, when the GPI signal has a low polarity, the PM / CK block 30 sets the clock frequency to a relatively low frequency.

[0061] The PM / CK block 30 holds a control signal corresponding to a clock frequency set therein. The PM / CK block 30 includes, for example, a control register storing control data corresponding to the set clock frequency. For example, when the GPI signal has a low polarity, the PM / CK block 30 may generate a control signal for stopping the clock signal and hold the control signal therein. In this case, the PM / CK block 30 may include, for example, a control register storing control data for stopping the clock signal. The PM / CK block 30 may hold therein a control signal corresponding to a voltage set for each operating state. In this case, the PM / CK block 30 may include, for example, an operating state register storing control data corresponding to a voltage set for each operating state.

[0062] The PM / CK block 30 generates a control signal indicating whether to apply intra-frame DFS based on a GPI signal received via a route (GPI terminal t1) different from the I2C / I3C communication protocol. For example, the SYS block 10 determines the polarity of a control signal generated by the PM / CK block 30 and indicating whether to apply intra-frame DFS at the start timing of a predetermined operation state (e.g., an integration period or a V blanking period). When the determination result indicates that intra-frame DFS is not applied, the SYS block 10 generates a low polarity control signal. The SYS block 10 outputs the low polarity control signal as a GPO signal to the application processor 200 via a route (GPO terminal t2) different from the I2C / I3C communication protocol.

[0063] Figure 6 An exemplary method of controlling intra-frame DFS using GPI and GPO is shown. Figure 6 Part (A) shows the input value of the GPI signal input to the GPI terminal t1. Figure 6 Part (B) shows the operating status of the CIS. Figure 6 In part (B), “V” and “V-Blanking” represent the V-blanking period, “S” represents the shutter period, “I” represents the integration period, and “R” represents the reading period. Figure 6 Part (C) shows the clock frequency. Figure 6 Part (D) shows the output value of the GPO signal output from the GPO terminal t2. Figure 6 The portion (E) indicates whether the DFS-application mode is selected. Figure 6 The portion (F) of indicates whether communication from the application processor 200 via the I2C / I3C block 12 is permitted. Figure 6 In the illustrated exemplary method of controlling DFS, the DFS-not-applied mode is switched to the DFS-applied mode, and then the DFS-applied mode is switched back to the DFS-not-applied mode.

[0064] When the operation state is a shutter cycle or a read cycle, the SYS block 10 operates regardless of whether DFS is applied, for example, Figure 6 As shown in part (C) of Figure 6 As shown in part (A) of FIG. 1 , for example, the application processor 200 instructs the PM / CK block 30 to apply DFS by setting the polarity of the GPI signal to low (#1). At this time, the PM / CK block 30 does not immediately apply DFS. However, the application processor 200 cannot recognize when the DFS-application mode starts. Therefore, when the GPI signal is set to the negative (low) polarity, the application processor 200 avoids communicating via the I2C / I3C block 12.

[0065] The PM / CK block 30 reads a GPI signal (e.g., #2) at a predetermined timing. When the read GPI signal has a low polarity, the PM / CK block 30 switches to the DFS-application mode. At this time, the PM / CK block 30 sets the clock frequency to a relatively low frequency and generates a control signal corresponding to the clock frequency set therein. Thereafter, the PM / CK block 30 outputs a clock having a low frequency based on the control signal. Alternatively, the PM / CK block 30 generates a control signal for stopping the clock signal, and stops timing based on the control signal.

[0066] like Figure 6 As shown in part (A) of FIG. 1 , for example, application processor 200 instructs PM / CK block 30 not to apply DFS by setting the polarity of the GPI signal to high (#3). At this time, PM / CK block 30 does not immediately make DFS inapplicable. Therefore, application processor 200 has not yet started communicating through I2C / I3C block 12 at this moment.

[0067] The PM / CK block 30 reads a GPI signal (e.g., #4) at a predetermined timing. When the read GPI signal has a high polarity, the PM / CK block 30 switches to the DFS-not applied mode. At this time, the PM / CK block 30 sets the clock frequency to a relatively high frequency and generates a control signal corresponding to the clock frequency set therein. Thereafter, the PM / CK block 30 outputs a clock having a high frequency based on the control signal.

[0068] The SYS block 10 outputs a signal to the application processor 200 via a route (GPO terminal t2) different from the I2C / I3C communication protocol based on a control signal generated by the PM / CK block 30 and indicating whether to apply intra-frame DFS. For example, the SYS block 10 generates a low polarity signal and outputs the generated low polarity signal as a GPO signal to the application processor 200 via the GPO terminal t2 (#5). That is, the SYS block 10 switches the GPO signal at the timing when the DFS-applied mode is switched to the DFS-not-applied mode. The application processor 200 recognizes that DFS has become unapplicable based on the switching of the GPO signal acquired via the GPO terminal t2, and starts communicating via the I2C / I3C block 12.

[0069] In an embodiment of the present disclosure, the application processor 200 can control the DFS using the GPO and GPI signals. Therefore, power consumption can be effectively saved by using the DFS.

[0070] 4. Modifications

[0071] Modification A

[0072] Figure 7 A variation of the method of controlling intra-frame DFS using GPI and GPO is shown. Figure 7 Part (A) shows the input value of the GPI signal input to the GPI terminal t1. Figure 7 Part (B) shows the operating status of the CIS. Figure 7 Part (C) shows the clock frequency. Figure 7 Part (D) shows the output value of the GPO signal output from the GPO terminal t2. Figure 7 The portion (E) indicates whether the DFS-application mode is selected. Figure 7 Part (F) of shows whether communication from the application processor 200 via the I2C / I3C block 12 is allowed. Figure 7 In the illustrated exemplary method of controlling DFS, the DFS-not applied mode is switched to the DFS-applied mode, and the DFS-applied mode is then switched back to the DFS-not applied mode.

[0073] In modification A, the PM / CK block 30 detects the switching (toggling) of the polarity of the GPI signal input to the GPI terminal t1. For example, the PM / CK block 30 detects the switching of the polarity of the GPI signal from the low polarity to the high polarity (#4). At this time, the PM / CK block 30 switches to the DFS-not applied mode, for example, Figure 7 The PM / CK block 30 also sets the clock frequency to Figure 7 (C) and outputs a control signal corresponding to the set clock frequency to the CU block 20.

[0074] After the CU block 20 outputs a clock having a relatively high frequency, the SYS block 10 starts operating, generates a low polarity signal, and outputs the generated low polarity signal as a GPO signal to the application processor 200 through the GPO terminal t2 (#5). That is, the SYS block 10 switches the GPO signal at the timing when the DFS-applied mode is switched to the DFS-not-applied mode. The application processor 200 recognizes that DFS has become unapplied based on the switching of the GPO signal acquired via the GPO terminal t2, and starts communicating via the I2C / I3C block 12.

[0075] In the above-described embodiment, in some cases, it may take a long time from the time when the GPI signal is switched from the application processor 200 to the time when communication via the I2C / I3C block 12 is enabled. Therefore, in Modification A, switching to the DFS-Not Applied mode is performed using the switching of the GPI signal as a trigger, and the GPO signal is switched at the timing of switching to the DFS-Not Applied mode. This configuration allows communication via the I2C / I3C block 12 to start earlier than the configuration of the above-described embodiment.

[0076] Modification B

[0077] In the above-described embodiments and variations, in addition to the I2C or I3C control lines, the GPI and GPO control lines are provided between the application processor 200 and the controller 110. Figure 8 As shown, a configuration without GPI and GPO can be used.

[0078] Figure 8 1 is a block diagram showing an exemplary configuration of an imaging device 100 according to a modification (modification B) of the above-described embodiment. The imaging device 100 according to modification B includes a controller (DGTOP) 110A and an imaging unit 120. The imaging unit 120 acquires image data by imaging and outputs the acquired image data to the controller 110A. The controller 110A controls imaging in the imaging unit 120, and outputs image data obtained by imaging in the imaging unit 120 to the application processor 200 serving as a host.

[0079] The controller 110A includes a SYS block 10A, a CU block 20 , a PM / CK block 30A, a SIF block 40 , a DU block 50 , and a mipi block 60 .

[0080] The SYS block 10A controls the imaging unit 120 based on the I2C / I3C signal received from the application processor 200 when communicating with the application processor 200. The SYS block 10A includes, for example, a CPU 11A and an I2C / I3C block 12A. The CPU 11A controls the imaging unit 120 based on the command and data received from the application processor 200 through the I2C / I3C block 12A. The I2C / I3C block 12A communicates with the application processor 200 according to the I2C / I3C communication protocol. For example, the I2C / I3C block 12A retrieves the command and data from the I2C / I3C signal received from the application processor 200, and outputs the retrieved command and data to the CPU 11A. The CPU 11A and the I2C / I3C block 12A operate based on various clock signals transmitted from the PM / CK block 30A. The SYS block 10A, the CU block 20, and the PM / CK block 30A perform mutual data communication, for example, via a bus.

[0081] The CU block 20 generates an imaging unit control signal based on the control signal received from the SYS block 10A, and outputs the imaging unit control signal to the imaging unit 120. The CU block 20 and the PM / CK block 30A control the start timing and end timing of each operating state by operating in cooperation with each other. Examples of the operating states controlled by the CU block 20 and the PM / CK block 30A may include a shutter period, an integration period, a read period, and a V blanking period.

[0082] The PM / CK block 30A sets the frequency of a clock signal (hereinafter referred to as "clock frequency") based on the DFS signal received from the CPU 11A. For example, the PM / CK block 30A determines the polarity of the DFS signal received from the CPU 11A. For example, the PM / CK block 30A determines the polarity of the DFS signal at the start timing of a predetermined operating state (e.g., an integration period or a V blanking period). The PM / CK block 30A sets the clock frequency based on the result of the determination. For example, the PM / CK block 30A sets the clock frequency for a predetermined operating state (e.g., an integration period or a V blanking period) based on the result of the determination. For example, when the DFS signal has a high polarity, the PM / CK block 30A sets the clock frequency to a relatively high frequency. For example, when the DFS signal has a low polarity, the PM / CK block 30 sets the clock frequency to a relatively low frequency.

[0083] The PM / CK block 30A holds a control signal corresponding to a clock frequency set therein. For example, when the DFS signal has a low polarity, the PM / CK block 30A may generate a control signal for stopping the clock signal and hold the control signal therein. The PM / CK block 30A may hold a control signal corresponding to a voltage set for each operation state therein.

[0084] Fig. 9 is a block diagram showing an exemplary configuration of the I2C / I3C block 12A. Fig. 9 As shown, for example, the I2C / I3C block 12A includes a front end unit (I2C / I3C IF front end) 12a and a back end unit 12b.

[0085] The front end unit 12a is a block for implementing only a specific function of the I2C / I3C communication protocol, which can operate in a clockless manner (executable without a clock signal provided from the PM / CK block 30A). The front end unit 12a uses the signal SCL or data SDA received from the application processor 200 as a clock. The signal SCL is a clock signal for synchronizing data transmission via the control data bus according to the I2C / I3C communication protocol. The data SDA is image data transmitted from the I2C / I3C block 12A to the application processor 200, or includes various data items for transmitting image data.

[0086] For example, the front end unit 12a decodes the slave address included in the virtual write command or virtual read command received from the application processor 200 in a clockless manner. For example, the front end unit 12a determines whether the slave address decoded in the DFS-applied mode matches the slave address assigned to the CIS. For example, when the decoded slave address matches the slave address assigned to the CIS, the front end unit 12a generates a signal (e.g., a low polarity signal) for making DFS inapplicable as a DFS control signal for making DFS applicable or inapplicable, and transmits the signal to the PM / CK block 30A. In this case, the front end unit 12a can access a control register or an operation status register in the PM / CK block 30A to make DFS inapplicable. The front end unit 12a, for example, determines whether the slave address decoded in the DFS-unapplied mode matches the slave address assigned to the CIS. For example, when the decoded slave address matches the slave address assigned to the CIS, the front end unit 12a generates a signal (e.g., a high polarity signal) for making DFS applicable as a DFS control signal to make DFS applicable or not applicable, and transmits the signal to the PM / CK block 30A. In this case, the front end unit 12a may access a control register or an operation status register in the PM / CK block 30A to make DFS applicable.

[0087] like Fig. 9 As shown, for example, the back-end unit 12b includes a block (I2C / I3C IF back-end) 12-1 and a bus IF block 12-2. The block 12-1 implements the function of the I2C / I3C communication protocol executable using a clock signal (clock signal ck1 provided from the PM / CK block 30A). The bus IF block 12-2 is a block that requires the clock signal ck2 provided from the PM / CK block 30A, and serves as an interface for the above-mentioned bus. For example, the front-end unit 12a and the back-end unit 12b can access a control register or an operation status register in the PM / CK block 30A to apply DFS based on a DFS application request command received from the application processor 200 in the DFS-unapplied mode.

[0088] In variant B, a virtual write command or a virtual read command transmitted from the application processor 200 is used instead of the GPI terminal t1 and the GPO terminal t2 to switch the DFS-applied mode to the DFS-unapplied mode. This allows the application processor 200 to control the switch to the DFS-unapplied mode. In addition, a virtual write command or a virtual read command transmitted by the application processor 200 is used instead of the GPI terminal t1 and the GPO terminal t2 to switch the DFS-unapplied mode to the DFS-applied mode. This allows the application processor 200 to control the switch to the DFS-applied mode. Alternatively, a DFS application request command is used instead of the virtual write command and the virtual read command transmitted by the application processor 200, and the DFS-unapplied mode is switched to the DFS-applied mode without using the GPI terminal t1 and the GPO terminal t2. Therefore, power consumption can be effectively saved by using DFS.

[0089] Modification C

[0090] In the above modification B, front end unit 12a decodes the slave address included in the dummy write command or the dummy read command transmitted from application processor 200 in a clockless manner, and controls whether DFS is applied based on the result of the decoding, for example. Alternatively, in the above modification B, front end unit 12a may decode a specific non-dummy write command or a specific non-dummy read command in a clockless manner, and control whether DFS is applied based on the result of the decoding.

[0091] Modification D

[0092] In the above-described embodiments and modifications, DFS is performed to save power consumption. However, in the above-described embodiments and modifications, DVFS may be performed instead of DFS.

[0093] Modification E

[0094] In the above-described embodiments and modifications, the application processor 200 controls the CIS using communication according to the I2C / I3C communication protocol. However, a control method using communication according to a communication protocol other than the I2C / I3C communication protocol may be applied to the above-described embodiments and modifications.

[0095] 5. Application Examples

[0096] The imaging device 1 according to the above-mentioned embodiments and modified examples can be applied to imaging devices (such as digital still cameras or cameras), portable devices with imaging functions, and various electronic devices including imaging elements in their image capture units (such as copiers including imaging elements in their image reading units). In addition, the embodiments of the present disclosure are also applicable to robots, drones, automobiles, medical equipment (endoscopes), etc. that include the imaging device 1. It should be noted that the imaging device 1 according to the above-mentioned embodiments and modified examples can be formed into a chip or a single package module including an imaging unit and a signal processor or an optical system with an imaging function. In the following, reference is made to Fig.10 An exemplary imaging system including the imaging device 1 according to any of the above-described embodiments and modifications is described. Fig.10 1 is a block diagram showing an exemplary configuration of an imaging system 2 including the imaging device 1 according to any of the above-described embodiments and modifications.

[0097] like Fig.10 As shown, the imaging system 2 includes, for example, the imaging device 1 according to any of the above-described embodiments and modifications, an optical system 310, a shutter device 320, a control circuit 330, a DSP circuit 340, a frame memory 350, a display unit 360, a storage body 370, an operation unit 380, and a power supply unit 390. In the imaging system 2, the imaging device 1 according to any of the above-described embodiments and modifications, the DSP circuit 340, the frame memory 350, the display unit 360, the storage body 370, the operation unit 380, and the power supply unit 390 are coupled to each other via a bus 400. The DSP circuit 340 corresponds to a specific example of the application processor 200 according to any of the above-described embodiments and modifications.

[0098] The optical system 310 includes one or more lenses. The optical system 310 guides the light (incident light) received from the object to the imaging device 1 to focus the light on the light receiving surface of the imaging device 1. The shutter device 320 is arranged between the optical system 310 and the imaging device 1. The shutter device 320 controls the light irradiation period and the light shielding time for the imaging device 1 under the control of the control circuit 330. The imaging device 1 accumulates signal charges of a certain period according to the light focused on the light receiving surface through the optical system 310 and the shutter device 320. Based on the driving signal (timing signal) provided from the control circuit 330, the signal charge accumulated in the imaging device 1 is transmitted to the DSP circuit 340 as a pixel signal (image data). That is, the imaging device 1 receives the image light (incident light) through the optical system 310 and the shutter device 320, and outputs the pixel signal corresponding to the received image light (incident light) to the DSP circuit 340. The control circuit 330 outputs a drive signal for controlling the transfer operation of the imaging device 1 and the shutter operation of the shutter device 320 to drive the imaging device 1 and the shutter device 320 .

[0099] The DSP circuit 340 is a signal processing circuit that processes a pixel signal (image data) output from the imaging device 1. The frame memory 350 temporarily holds the image data processed by the DSP circuit 340 in units of frames. The display unit 360 is, for example, a display panel such as a liquid crystal panel or an organic electroluminescent (EL) panel. The display unit 360 displays a moving image or a still image captured by the imaging device 1. The storage body 370 records the image data of the moving image or the still image captured by the imaging device 1 on a recording medium (for example, a semiconductor memory or a hard disk). The operation unit 380 issues operation commands for various functions of the imaging system 2 according to operations performed by a user. The power supply unit 390 supplies the imaging device 1, the DSP circuit 340, the frame memory 350, the display unit 360, the storage body 370, and the operation unit 380 with power for appropriately operating these components.

[0100] In the application example, the imaging device 1 according to any of the embodiments and the modified examples is applied to an imaging system 2. Using such a power saving imaging device 1, it is possible to provide an imaging system 2 that enables saving of power consumption.

[0101] Although the present disclosure has been described with reference to the embodiments and their variations, application examples, and application examples, the present disclosure should not be limited to the above-described embodiments, etc., and various modifications may be made. It should be noted that the effects described herein are merely illustrative. The effects of the present disclosure should not be limited to the effects described herein. The present disclosure may have other effects in addition to the effects described herein.

[0102] The present disclosure may also have the following configurations.

[0103] (1) An imaging device comprising:

[0104] a controller that controls the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; and

[0105] generator

[0106] generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from a host via a first route different from an I2C / I3C communication protocol, and

[0107] The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

[0108] (2) The imaging device according to (1), wherein the generator sets a frequency and an operation state of a clock signal used in the controller based on the first control signal.

[0109] (3) The imaging device according to (2), wherein the generator sets a frequency and an operation state of the clock signal based on a polarity of the first control signal, and generates the second control signal based on the polarity of the first control signal.

[0110] (4) The imaging device according to (2), wherein the generator sets a frequency and an operation state of the clock signal based on switching of the first control signal, and generates the second control signal based on switching of the first control signal.

[0111] (5) An imaging device comprising:

[0112] a controller that controls the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; and

[0113] generator

[0114] Decode the slave address included in the command received from the host,

[0115] generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding, and

[0116] The control signal is output to the host via a route different from the I2C / I3C communication protocol.

[0117] (6) The imaging device according to (5), wherein the generator determines whether the slave address obtained by decoding matches a slave address assigned to the imaging device, and generates the control signal based on a result of the determination.

[0118] (7) The imaging device according to (6), wherein

[0119] When the slave address obtained by the decoding matches the slave address assigned to the imaging device in the DFS-applying mode, the generator generates a signal for disapplying intra-frame DFS as the control signal, and

[0120] When the slave address obtained by the decoding in a DFS-unapplied mode matches a slave address assigned to the imaging device, the generator generates a signal for applying the intra-frame DFS as the control signal.

[0121] (8) The imaging device according to any one of (5) to (7), wherein the generator decodes a slave address included in a dummy write command or a dummy read command received from a host, and generates a control signal based on the slave address obtained by decoding.

[0122] (9) An imaging device according to any one of (5) to (7), wherein the generator generates the control signal based on a DFS application command received from the host in a DFS-unapplied mode or a specific write command or a specific read command received from the host in a DFS-applied mode.

[0123] (10) The imaging device according to any one of (5) to (7), further comprising:

[0124] A block that implements the functionality of the I2C / I3C communication protocol that can be operated with a clock, wherein

[0125] The generator is a block that implements only the functions of the I2C / I3C communication protocol that can operate in a clockless manner.

[0126] (11) An imaging method comprising:

[0127] generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal transmitted from a host via a first route different from an I2C / I3C communication protocol, the host transmitting commands and data according to the I2C / I3C communication protocol; and

[0128] The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

[0129] (12) An imaging method comprising:

[0130] decoding a slave address included in a virtual command transmitted from a host transmitting commands and data according to an I2C / I3C communication protocol;

[0131] generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding; and

[0132] The control signal is output to the host via a route different from the I2C / I3C communication protocol.

[0133] (13) An electronic device comprising:

[0134] A host, configured to communicate according to an I2C / I3C communication protocol;

[0135] a controller that controls the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; and

[0136] generator

[0137] generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from a host via a first route different from an I2C / I3C communication protocol, and

[0138] The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

[0139] (14) An electronic device comprising:

[0140] A host, configured to communicate according to an I2C / I3C communication protocol;

[0141] a controller that controls the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; and

[0142] generator

[0143] decoding a slave address included in a virtual command received from the host,

[0144] generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding, and

[0145] The control signal is output to the host via a route different from the I2C / I3C communication protocol.

[0146] In an imaging device, an imaging method, and an electronic device according to the first aspect of the present disclosure, a second control signal indicating whether to apply intra-frame DFS or intra-frame DVFS is generated based on a first control signal received from a host via a first path different from a communication protocol. The second control signal is output to the host via a second route different from the communication protocol. Therefore, power consumption can be effectively saved by using DFS.

[0147] In an imaging device, an imaging method, and an electronic device according to a second aspect of the present disclosure, a slave address included in a virtual command received from a host is decoded. Based on the decoded slave address, a second control signal indicating whether intra-frame DFS or intra-frame DVFS is applied is generated. The second control signal is output to the host via a second route different from the communication protocol. Therefore, power consumption can be effectively saved by using DFS.

Claims

1. An imaging device, comprising: a controller to control the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; as well as generator generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from the host via a first route different from the I2C / I3C communication protocol, and The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

2. The imaging device according to claim 1, wherein: The generator sets an operating state and a frequency of a clock signal used in the controller based on the first control signal.

3. The imaging device according to claim 2, wherein: The generator sets the operating state and the frequency of the clock signal based on a polarity of the first control signal, and generates the second control signal based on the polarity of the first control signal.

4. The imaging device according to claim 2, wherein: The generator sets the operation state and the frequency of the clock signal based on switching of the first control signal, and generates the second control signal based on the switching of the first control signal.

5. An imaging device comprising: a controller to control the imaging unit based on commands and data received from a host according to an I2C / I3C communication protocol; as well as generator decoding a slave address included in said command received from said host, generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding, and The control signal is output to the host via a route different from the I2C / I3C communication protocol.

6. The imaging device according to claim 5, wherein: The generator determines whether the slave address obtained by the decoding matches a slave address assigned to the imaging device, and generates the control signal based on a result of the determination.

7. The imaging device according to claim 6, wherein When the slave address obtained by the decoding matches the slave address assigned to the imaging device in the DFS-applying mode, the generator generates a signal for disapplying intra-frame DFS as the control signal, and When the slave address obtained by the decoding in a DFS-unapplied mode matches a slave address assigned to the imaging device, the generator generates a signal for applying the intra-frame DFS as the control signal.

8. The imaging device according to claim 5, wherein: The generator decodes the slave address included in a dummy write command or a dummy read command received from the host, and generates the control signal based on the slave address obtained by the decoding.

9. The imaging device according to claim 5, wherein: The generator generates the control signal based on a DFS applied command received from the host in a DFS-unapplied mode or a specific write command or a specific read command received from the host in a DFS-applied mode.

10. The imaging device according to claim 5, further comprising: A block implementing the functionality of the I2C / I3C communication protocol capable of being operated by a clock, wherein The generator includes blocks that implement only the functions of the I2C / I3C communication protocol that can operate in a clockless manner.

11. An imaging method comprising: generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal transmitted from a host via a first route different from an I2C / I3C communication protocol according to which the host transmits commands and data; as well as The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

12. An imaging method comprising: decoding a slave address included in a virtual command transmitted from a host transmitting commands and data according to an I2C / I3C communication protocol; generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding; as well as The control signal is output to the host via a route different from the I2C / I3C communication protocol.

13. An electronic device, comprising: A host, configured to communicate according to an I2C / I3C communication protocol; a controller to control an imaging unit based on commands and data received from the host according to the I2C / I3C communication protocol; as well as generator generating a second control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on a first control signal received from the host via a first route different from the I2C / I3C communication protocol, and The second control signal is output to the host via a second route different from the I2C / I3C communication protocol.

14. An electronic device comprising: A host, configured to communicate according to an I2C / I3C communication protocol; a controller to control an imaging unit based on commands and data received from the host according to the I2C / I3C communication protocol; as well as generator decoding a slave address included in a virtual command received from the host, generating a control signal indicating whether to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) based on the slave address obtained by the decoding, and The control signal is output to the host via a route different from the I2C / I3C communication protocol.

Images