Electronic component

Abstract

An electronic component (101) is provided with: a substrate (1); an insulator layer (2) extending along the surface of the substrate (1); a planar conductor (4), which is formed on the substrate (1) or inside the insulator layer (2), and which extends in a planar shape parallel to the surface of the substrate (1); and an inductor conductor pattern (5) formed on or in the insulator layer (2). When viewed from a direction perpendicular to the surface of the substrate (1), the length in the longitudinal direction of the region where the inductor conductor pattern (5) is formed and the planar conductor (4) overlap is represented by Ls, and the interval between the inductor conductor pattern (5) and the planar conductor (4) is represented by d, the value of Ls / d is 1-60.

Description

Technical Field

[0001] The present invention relates to an electronic component including a substrate provided with a conductor pattern constituting a capacitor or an inductor. Background Art

[0002] An electronic component including a conductor pattern constituting a capacitor or an inductor on a substrate is used as, for example, an LC composite component.

[0003] Patent Document 1 discloses an LC composite component in which capacitor electrodes are arranged outside a hollow core portion of a coil formed of a spiral conductor pattern.

[0004] Patent Document 2 discloses an LC composite component in which electrodes for capacitors are arranged so as not to overlap with the central axis of a coil conductor formed by a spiral conductor pattern.

[0005] Patent Document 3 discloses an LC composite component in which a capacitor formed of comb-teeth electrodes is arranged in an upper layer or a lower layer outside the central region of a coil conductor formed of a spiral conductor pattern, and the comb-teeth electrodes are formed perpendicularly to an inductor conductor wiring.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2004-079973

[0009] Patent Document 2: Japanese Patent Application Publication No. 2012-178717

[0010] Patent Document 3: Japanese Patent Application Publication No. 2019-091847 Summary of the invention

[0011] Problem that the invention aims to solve

[0012] In the LC composite elements disclosed in Patent Documents 1, 2, and 3, the magnetic field generated by the coil does not pass through the electrode of the capacitor portion, so the Q value of the inductor does not deteriorate. However, in the LC composite components of the structures disclosed in Patent Documents 1, 2, and 3, it is necessary to arrange the capacitor electrodes away from the center of the coil, so the plane area of ​​the LC composite component becomes large. That is, if the capacitor electrodes are arranged away from the center of the coil, the desired capacitance cannot be ensured, and if the coil conductor is arranged away from the capacitor electrodes, the desired inductance cannot be ensured, so the LC composite component cannot be miniaturized.

[0013] The above-mentioned problem is not limited to an LC composite component formed by combining an inductor and a capacitor, but also occurs in an electronic component including a planar conductor and a conductor pattern for an inductor.

[0014] Therefore, an object of the present invention is to provide an electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor having a desired size and that is miniaturized.

[0015] Technical solutions to solve problems

[0016] An electronic component as an example of the present disclosure is characterized in that it comprises: a substrate; an insulating layer extending along the surface of the substrate; a single or multiple planar conductors formed on the substrate or in the insulating layer and extending in a planar manner parallel to the surface of the substrate; and a conductor pattern for an inductor formed on or in the insulating layer, wherein, as viewed from a direction perpendicular to the surface of the substrate, the length in the long dimension direction of a single region where the formation region of the conductor pattern for the inductor overlaps with the planar conductor, or the length in the long dimension direction of multiple regions where the formation region of the conductor pattern for the inductor overlaps with the planar conductor added in a given direction is represented by Ls, and the interval between the conductor pattern for the inductor and the planar conductor closest to the conductor pattern for the inductor is represented by d, and in this case, the value of Ls / d is greater than 1 and less than 60.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to obtain an electronic component which includes an inductor conductor pattern which generates a desired inductance and a planar conductor having a desired size and is miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a perspective view and a front view of the electronic component 101 according to the first embodiment.

[0020] Figure 2 These are a plan view and a cross-sectional view of a main portion of the electronic component 101 .

[0021] Figure 3 It is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the planar conductor 4 .

[0022] Figure 4 It is a diagram showing the tendency of Ls / d and Q / Q0 found from a plurality of combinations of Ls and d.

[0023] Figure 5 (A) Figure 5 (B) Figure 5 (C) and Figure 5(D) is a diagram showing an example of the shape of a region where the inductor conductor pattern 5 is formed and a region where the planar conductor 4 overlaps.

[0024] Figure 6 It is a top view and a cross-sectional view of the electronic component 102 according to the second embodiment.

[0025] Figure 7 is an equivalent circuit diagram of the electronic component 102 .

[0026] Figure 8 1 is a diagram showing the structure of each layer of the electronic component 102 .

[0027] Fig. 9 (A) Fig. 9 (B) Fig. 9 (C) and Fig. 9 (D) is a cross-sectional view of the electronic component 102 in each manufacturing step.

[0028] Fig.10 (A) Fig.10 (B) Fig.10 (C) and Fig.10 (D) is a cross-sectional view of the electronic component 102 in each manufacturing step.

[0029] Fig.11 It is a top view and a cross-sectional view of the electronic component 103 according to the third embodiment.

[0030] Fig.12 1 is a diagram showing the structure of each layer of the electronic component 103 .

[0031] Fig.13 (A) Fig.13 (B) Fig.13 (C) and Fig.13 (D) is a cross-sectional view of the electronic component 103 in each manufacturing step.

[0032] Fig.14 (A) Fig.14 (B) and Fig.14 (C) is a cross-sectional view of the electronic component 103 in each manufacturing step.

[0033] Fig.15 It is a top view and a cross-sectional view of the electronic component 104 according to the fourth embodiment.

[0034] Fig.16 It is a top view and a cross-sectional view of the electronic component 105 according to the fifth embodiment.

[0035] Fig.17 is an equivalent circuit diagram of the electronic component 105 .

[0036] Fig.18 1 is a diagram showing the structure of each layer of the electronic component 105 .

[0037] Fig.19 (A) Fig.19 (B) Fig.19 (C) and Fig.19 (D) is a cross-sectional view of the electronic component 105 in each manufacturing step.

[0038] Fig. 20 (A) Fig. 20 (B) and Fig. 20 (C) is a cross-sectional view of the electronic component 105 in each manufacturing step.

[0039] Fig.21 It is a cross-sectional view of an electronic component 106 according to the sixth embodiment. DETAILED DESCRIPTION

[0040] Hereinafter, several specific examples are cited with reference to the drawings to illustrate a plurality of ways for implementing the present invention. The same reference numerals are used to mark the same parts in the respective figures. In consideration of the ease of explanation or understanding of the key points, the embodiments are illustrated in a plurality of embodiments for the convenience of explaining the embodiments, but partial replacement or combination of the structures illustrated in different embodiments is possible. After the second embodiment, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects brought about by the same structure will not be mentioned one by one in each embodiment.

[0041] 《First Implementation Method》

[0042] Figure 1 The upper part of FIG. 1 is a perspective view of the electronic component 101 according to the first embodiment. In this perspective view, the outer shape is indicated by two-dot chain lines. Figure 1 The lower part is a front view of the electronic component 101 observed in the Y-axis direction.

[0043] The electronic component 101 comprises: an electrically insulating substrate 1; an insulating layer 2 extending along the surface of the substrate 1; a planar conductor 4 formed on the substrate 1 or in the insulating layer 2 and extending in a planar manner parallel to the surface of the substrate 1; and a conductor pattern 5 for a rectangular spiral coil type inductor formed on the substrate 1 or in the insulating layer 2.

[0044] Figure 2 The upper part in FIG. 1 is a top view of the main part of the electronic component 101. Figure 2 The lower part is a cross-sectional view of the XX portion in the top view. Figure 31 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the planar conductor 4. However, for convenience of explanation, the distance between the inductor conductor pattern 5 and the planar conductor 4 is intentionally enlarged and drawn.

[0045] The inductor conductor pattern 5 has an opening MH of magnetic flux φ where magnetic flux concentrates. Eddy current EC flows through the planar conductor 4 according to the magnetic flux (high-frequency magnetic flux) φ. The larger the magnetic flux φ, the larger the eddy current EC.

[0046] exist Figure 2 In the figure, W represents the width of the planar conductor 4. When d represents the interval between the inductor conductor pattern 5 and the planar conductor 4, the smaller the interval d between the inductor conductor pattern 5 and the planar conductor 4, the larger the eddy current EC becomes. In addition, if Ls represents the length in the long dimension direction of the area where the inductor conductor pattern 5 is formed and the area where the planar conductor 4 overlaps when the surface of the substrate 1 is observed from a direction perpendicular to the surface of the substrate 1, the larger Ls is, the larger the eddy current EC becomes. Therefore, the larger the value of Ls / d is, the larger the eddy current EC becomes.

[0047] Table 1 shows the relationship between the length Ls in the longitudinal direction of the region where the inductor conductor pattern 5 is formed and overlaps the planar conductor 4 , the distance d between the inductor conductor pattern 5 and the planar conductor 4 , and the degradation of the Q value of the inductor.

[0048] [Table 1]

[0049]

[0050] In Table 1, S[μm 2 ] is the area of ​​the overlapping area of ​​the inductor conductor pattern 5 and the planar conductor 4 when the overlapping area is a square. In Table 1, Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 without the planar conductor 4, and Q / Q0 is the area S[μm 2 The ratio of the Q value to Q0 when the planar conductor 4 is arranged at a distance d [μm] from the inductor conductor pattern 5. In addition, L0 is the inductance of the inductor conductor pattern 5 without the planar conductor 4, and L / L0 is the ratio of the area S [μm 2 ] is a ratio of the L value when the planar conductor is arranged at a distance d [μm] from the inductor conductor pattern 5 to L0.

[0051] Figure 4 : is a graph showing the tendency of Ls / d and Q / Q0 found from the above-mentioned multiple combinations of Ls and d. Figure 4 In the figure, the horizontal axis is Ls / d and the vertical axis is Q / Q0. Figure 4It is clear that when the value of Ls / d (the value of √(S) / d) is greater than or equal to 1 and less than or equal to 60, Q / Q0 is greater than or equal to 0.3, so the decrease in the Q value of the inductor due to the presence of the planar conductor 4 is small. Furthermore, when the value of Ls / d is greater than or equal to 1 and less than or equal to 55, the decrease in Q / Q0 can be further suppressed.

[0052] In Table 1, Figure 4 The example is an example in which the overlapping area of ​​the inductor conductor pattern 5 and the planar conductor 4 is a square, that is, it is the worst case. Therefore, when the formation area of ​​the inductor conductor pattern 5 and the overlapping area of ​​the planar conductor 4 are not square, it is sufficient to treat the length of the overlapping area in the long dimension direction as Ls.

[0053] exist Figure 1 In the example shown, the area where the formation area of ​​the inductor conductor pattern 5 overlaps with the planar conductor 4 is single when viewed from a direction perpendicular to the surface of the substrate 1. However, when there are multiple such areas, the length of the long dimension direction of the multiple areas where the formation area of ​​the inductor conductor pattern 5 overlaps with the planar conductor 4 added in a given direction may be treated as Ls.

[0054] Figure 5 (A) Figure 5 (B) Figure 5 (C) and Figure 5 (D) is a diagram showing an example of the shape of the region where the inductor conductor pattern 5 is formed and the region where the planar conductor 4 overlaps. Figure 5 As shown in (A), if the area of ​​the planar conductor 4 overlapping the area where the inductor conductor pattern 5 is formed is L-shaped, the dimension of the long dimension in this area is Ls. Figure 5 As shown in (B), if the area of ​​the planar conductor 4 overlapping the area where the inductor conductor pattern 5 is formed is circular or elliptical, the dimension in the long dimension direction of the area is Ls. Figure 5 As shown in (C), if the region of the planar conductor 4 overlapping the region where the inductor conductor pattern 5 is formed is T-shaped, the dimension in the longitudinal direction of the width Lx and height Ly of the region is defined as Ls.

[0055] In addition, if Figure 5 As shown in (D), when there are multiple areas of the planar conductor overlapping the area where the inductor conductor pattern 5 is formed, the length of the long dimension direction of these overlapping areas added in a given direction is Ls. Figure 5In the example shown in (D), one of the two planar conductor regions overlapping the formation region of the inductor conductor pattern 5 has an X-axis dimension of Lx1 and a Y-axis dimension of Ly1, and the other region has an X-axis dimension of Lx2 and a Y-axis dimension of Ly2. In this example, the sum of Ly1+Ly2 is greater than the sum of Lx1+Lx2, so the value of Ly1+Ly2 is the length Ls in the long dimension direction.

[0056] <<Second Implementation Method>>

[0057] In the second embodiment, an LC composite electronic component is exemplified. Figure 6 The upper part is a plan view of the electronic component 102 according to the second embodiment. Figure 6 The lower part is Figure 6 A cross-sectional view of the upper XX portion.

[0058] The electronic component 102 comprises: a substrate 1; an insulating layer 2 extending along the surface of the substrate 1; an inductor formed in the insulating layer 2; planar conductors 3 and 4 formed on the substrate 1 and extending along the substrate 1; planar conductor connecting conductors 7A, 7B, 7C conductively connected to the planar conductor 3; and a planar conductor connecting conductor 8 conductively connected to the planar conductor 4.

[0059] Terminal electrodes 10A and 10B are formed on the surface of the insulating layer 2. The terminal electrodes 10A and 10B are electrically connected to the terminal electrodes 9A and 9B.

[0060] The inductor is a spiral coil type inductor formed by an inductor conductor pattern 5 along the surface of the substrate 1 .

[0061] The planar conductors 3 and 4 are capacitor electrodes. That is, a capacitor is formed by the planar conductors 3 and 4 and the dielectric layer 11 sandwiched between the planar conductors 3 and 4. That is, the planar conductors 3 and 4 are capacitor electrodes that form a capacitor together with the dielectric layer 11.

[0062] When viewed from a direction perpendicular to the surface of the substrate 1, the formation area of ​​the inductor conductor pattern 5 overlaps with the planar conductor 3 and also overlaps with the planar conductor 4. Of these planar conductors 3 and 4, the planar conductor 4 is closer to the inductor conductor pattern 5, so d represents the interval between the inductor conductor pattern 5 and the planar conductor 4. In addition, Ls represents the length of the largest area in the long dimension direction of the area where the inductor conductor pattern 5 and the planar conductor 4 overlap.

[0063] exist Figure 6 In the example, the value of Ls is 190 μm, and the interval d between the inductor conductor pattern 5 and the planar conductor 4 is 20 μm. Therefore, Ls / d is 9.5, which is less than 60 and even less than 55. Figure 6The structural model shown was simulated, and the result was that according to this embodiment, the ratio Q / Q0 of the Q value Q0 when there is no planar conductor 4 to the Q value when there is a planar conductor 4 is 0.48. Although the Q value decreases, it is not an extreme decrease, and an electronic component of an inductor with an effective Q value can be obtained.

[0064] Figure 7 : is an equivalent circuit diagram of the electronic component 102. As described above, the electronic component 102 forms a series circuit of the inductor L1 and the capacitor C1. The electronic component 102 can be used as a frequency filter or an impedance matching circuit.

[0065] Figure 8 is a diagram showing the structure of each layer of the electronic component 102. Figure 8 In the figure, layer La is a layer of substrate 1, layer Lb is a layer for forming planar conductor 3, layer Lc is a layer for forming dielectric layer 11 and planar conductor connection conductor 7A, layer Ld is a layer for forming planar conductor 4 and planar conductor connection conductor 7B. Layer Le is a layer for forming planar conductor connection conductors 7C and 8, layer Lf is a layer for forming inductor conductor pattern 5 and terminal electrodes 9A and 9B. Moreover, layer Lg is a layer for forming terminal electrodes 10A and 10B.

[0066] Next, Figure 8 The manufacturing method of the electronic component 102 having each layer structure shown is exemplified. Fig. 9 (A) is a cross-sectional view of the substrate. As the substrate 1, not only a semiconductor substrate such as a Si substrate or a GaAs substrate but also a glass substrate or a ceramic substrate can be used. Fig. 9 (B) is a cross-sectional view of a state where a planar conductor 3 is formed. In this process, the following semiconductor processes are used to form the planar conductor 3: an Al film or a Cu film is deposited on the surface of the substrate 1 and then peeled off; an Al film or a Cu film is formed by sputtering or CVD, and then photolithography and etching are performed; etc.

[0067] Fig. 9 (C) is a cross-sectional view of a state where the dielectric layer 11 is formed. In this process, the dielectric layer 11 such as SiO2 film or SiN film is formed on the surface of the planar conductor 3 by a semiconductor process such as sputtering or CVD. Then, as shown in FIG. Fig. 9 As shown in (D), an opening is formed in the portion where the planar conductor connection conductor 7A is formed, and the planar conductor connection conductors 7A, 7B and the planar conductor 4 are formed. In this step, the opening is formed by photolithography and etching, and the pattern of the planar conductor 4 is formed by the following semiconductor processes: Al film or Cu film is evaporated and peeled off; Al film or Cu film is formed by sputtering or CVD, and photolithography and etching are performed; etc.

[0068] Fig.10 (A) is a cross-sectional view of a state where an insulator layer 2 is formed and an opening AP is formed. In this structure, an inorganic film such as a resin (organic) film, a SiO2 film, or a SiN film is formed by a method such as spin coating, CVD, or sputtering, and then an opening AP is formed at a given location by photolithography and etching.

[0069] Fig.10 (B) is a cross-sectional view of a state where the planar conductor connection conductors 7C and 8 are formed. Fig.10 The planar conductor connection conductors 7C and 8 are formed in the opening AP shown in (A). For example, the conductors are formed by forming a Cu film, performing photolithography, and plating; or sputtering Cu, performing photolithography, and etching; or performing photolithography on a Cu film, performing vapor deposition, and performing lift-off.

[0070] Fig.10 (C) is a cross-sectional view in a state where the inductor conductor pattern 5 and the terminal electrodes 9A and 9B are formed. In this process, the inductor conductor pattern 5 and the terminal electrodes 9A and 9B are formed on the surface of the insulating layer 2. For example, they are formed by the following methods: forming a Cu film, performing photolithography, and plating; or sputtering Cu, performing photolithography, and etching; or performing photolithography on a Cu film, performing vapor deposition, and peeling.

[0071] Fig.10 (D) is a cross-sectional view in a state where the terminal electrodes 10A and 10B are formed. In this process, the terminal electrodes 10A and 10B are electrodes for mounting, and are formed by applying Ni plating, Au plating, etc. to the surface of the terminal electrodes 9A and 9B. Then, a protective film is formed, and the terminal electrodes 10A and 10B are partially opened to expose the terminal electrodes 10A and 10B.

[0072] 《Third Implementation Method》

[0073] In the third embodiment, an electronic component is exemplified in which the structure of the planar conductor is different from the examples described in the first and second embodiments.

[0074] Fig.11 It is a diagram showing the structure of an electronic component 103 according to the third embodiment. Fig.11 The <top view> in FIG. 1 is a top view of the electronic component 103 . Fig.11 The <cross-sectional view> in FIG. 1 is a cross-sectional view of a portion XX in the plan view of the electronic component 103 .

[0075] The electronic component 103 comprises: a substrate 1; an insulating layer 2 extending along the surface of the substrate 1; a conductor pattern 5 for an inductor formed in the insulating layer 2; a dielectric layer 11 and a planar conductor 4 formed on the substrate 1 and extending along the substrate 1; a conductor 8 for connecting planar conductors, which is electrically connected to the planar conductor 4; and conductors 7A, 7B, 7C for connecting planar conductors, which are electrically connected to the substrate 1.

[0076] A dielectric layer 11 is formed on the surface of the substrate 1, and a planar conductor 4 is formed on the surface of the dielectric layer 11. In addition, a planar conductor connection conductor 7A is formed at a predetermined position on the surface of the substrate 1. The substrate 1 is a semiconductor substrate with high conductivity. The other structures are as shown in the second embodiment.

[0077] exist Fig.11 In the embodiment, the value of Ls is 210 μm, and the interval d between the inductor conductor pattern 5 and the planar conductor 4 is 30 μm. Therefore, Ls / d is 7, and Ls / d is less than 60 and less than 55. According to the present embodiment, the ratio Q / Q0 of the Q value Q0 when there is no planar conductor 4 to the Q value when there is a planar conductor 4 is 0.61, and an electronic component of an inductor having an effective Q value can be obtained.

[0078] Fig.12 is a diagram showing the structure of each layer of the electronic component 103. Fig.12 In the figure, layer La is a layer of substrate 1, layer Lb is a layer for forming planar conductor connection conductor 7A and dielectric layer 11, layer Lc is a layer for forming dielectric layer 11 and planar conductor 4, and layer Ld is a layer for forming planar conductor connection conductor 7C and 8. Layer Le is a layer for forming inductor conductor pattern 5 and terminal electrodes 9A and 9B. Furthermore, layer Lf is a layer for forming terminal electrodes 10A and 10B.

[0079] Next, Fig.11 The manufacturing method of the electronic component 103 having each layer structure shown is exemplified. Fig.13 (A) is a cross-sectional view of the substrate. As the substrate 1, not only a semiconductor substrate such as a Si substrate or a GaAs substrate but also a glass substrate or a ceramic substrate can be used. Fig.13 (B) is a cross-sectional view in a state where the dielectric layer 11 is formed and the opening AP is formed at a given position. Fig.13 (C) is a cross-sectional view in a state where the planar conductor connecting conductor 7A is formed in the opening AP, and the planar conductor connecting conductor 7B and the planar conductor 4 are formed on the upper surface of the dielectric layer 11 . Fig.13(D) is a cross-sectional view of a state where the insulating layer 2 is formed and the opening AP is formed. In this structure, an inorganic film such as a resin (organic) film, a SiO2 film, or a SiN film is formed by a method such as spin coating, CVD, or sputtering, and then an opening AP is formed at a given location by photolithography and etching.

[0080] Fig.14 (A) is a cross-sectional view of a state where the planar conductor connection conductors 7C and 8 are formed. Fig.13 The planar conductor connection conductors 7C and 8 are formed in the opening AP shown in (D). For example, the conductors are formed by forming a Cu film, performing photolithography, and plating; or sputtering Cu, performing photolithography, and etching; or performing photolithography on a Cu film, performing vapor deposition, and performing lift-off.

[0081] Fig.14 (B) is a cross-sectional view in a state where the inductor conductor pattern 5 and the terminal electrodes 9A, 9B are formed. In this process, the inductor conductor pattern 5 and the terminal electrodes 9A, 9B are formed on the surface of the insulating layer 2. For example, they are formed by forming a Cu film, performing photolithography, and plating; or sputtering Cu, performing photolithography, and etching; or performing photolithography on a Cu film, performing vapor deposition, and peeling.

[0082] Fig.14 (C) is a cross-sectional view in a state where the terminal electrodes 10A and 10B are formed. In this process, the terminal electrodes 10A and 10B are electrodes for mounting, and are formed by applying Ni plating, Au plating, etc. to the surface of the terminal electrodes 9A and 9B. Then, a protective film is formed, and the terminal electrodes 10A and 10B are partially opened to expose the terminal electrodes 10A and 10B.

[0083] 《Fourth Implementation Method》

[0084] In the fourth embodiment, an electronic component having a planar conductor on the rear surface of a substrate is exemplified. Fig.15 The <top view> in FIG. 1 is a top view of the electronic component 104 . Fig.15 The <cross-sectional view> in FIG. 1 is a cross-sectional view of a portion XX in the plan view of the electronic component 104 .

[0085] The electronic component 104 includes: a substrate 1; a dielectric layer 11 formed on the upper surface of the substrate 1; a terminal electrode 9A formed on the lower surface of the substrate 1; an insulating layer 2; a conductor pattern 5 for an inductor formed in the insulating layer 2; a planar conductor 4 extending along the substrate 1; and a conductor 8 for connecting the planar conductors, which is electrically connected to the planar conductor 4.

[0086] The electronic component 104 of the present embodiment uses the capacitance generated between the planar conductor 4 and the terminal electrode 9A as a capacitor. In addition, the terminal electrodes 9A and 9B on the upper and lower surfaces are used.

[0087] The value of Ls in this embodiment is 210 μm, and the value of d is 30 μm. Except for the back electrode, it is the same as the electronic component 103 shown in the third embodiment. Therefore, the value of Ls / d is the same as the result shown in the third embodiment.

[0088] 《Fifth Implementation Method》

[0089] In the fifth embodiment, an electronic component having three terminal electrodes and an electronic component including a resistor element are exemplified.

[0090] Fig.16 It is a diagram showing the structure of an electronic component 105 according to the fifth embodiment. Fig.16 The <top view> in FIG. 1 is a top view of the electronic component 105 . Fig.16 The <cross-sectional view> in FIG. 1 is a cross-sectional view of a portion XX in the plan view of the electronic component 105 .

[0091] The electronic component 105 includes: a substrate 1; an insulating film 20 extending along the surface of the substrate 1; an inductor conductor pattern 5 formed in the insulating layer 2; a resistor film 21 formed on the insulating film 20 and extending along the insulating film 20; a planar conductor connection conductor 7 conducting with the resistor film 21 and the terminal electrode 9A; and a planar conductor connection conductor 8 conducting with the resistor film 21 and the terminal electrode 9B. In the present embodiment, the resistor film 21 corresponds to the planar conductor according to the present invention.

[0092] Fig.17 : is an equivalent circuit diagram of the electronic component 105. As described above, the electronic component 105 is a composite component of the inductor L1 and the resistor R1.

[0093] Fig.18 is a diagram showing the structure of each layer of the electronic component 105. Fig.18 In the figure, layer La is a layer for forming the insulating film 20 and the resistor film 21, layer Lb is a layer for forming the planar conductor connection conductors 7 and 8, layer Lc is a layer for forming the inductor conductor pattern 5 and the terminal electrodes 9A, 9B, and 9C. Furthermore, layer Ld is a layer for forming the terminal electrodes 10A, 10B, and 10C.

[0094] Next, Fig.18 The manufacturing method of the electronic component 105 having each layer structure shown is exemplified. Fig.19 (A) is a cross-sectional view of the substrate. Fig.19 (B) is a cross-sectional view in a state where the insulating film 20 is formed. Fig.19 (C) is a cross-sectional view showing a state where the resistor film 21 is formed on the insulating film 20 . Fig.19 (D) is a cross-sectional view in a state where the insulating layer 2 is formed and the opening AP is formed.

[0095] The resistor film 21 is formed of a material having an electrical conductivity between that of the insulator layer and that of the conductor forming the terminal electrode and the inductor conductor pattern. The resistor film 21 may be, for example, a film of a laminated insulator and a conductor other than NiCr or impure Si.

[0096] Fig. 20 (A) is a cross-sectional view of a state where the planar conductor connection conductors 7 and 8 are formed. Fig.19 The planar conductor connection conductors 7 and 8 are formed in the opening AP shown in (D).

[0097] Fig. 20 (B) is a cross-sectional view in a state where the inductor conductor pattern 5 and the terminal electrodes 9A, 9B, 9C are formed. In this step, the inductor conductor pattern 5 and the terminal electrodes 9A, 9B, 9C are formed on the surface of the insulating layer 2 .

[0098] Fig. 20 (C) is a cross-sectional view of the state where the terminal electrodes 10A, 10B, and 10C for mounting are formed. In this process, Ni plating, Au plating, etc. are applied to the surface of the terminal electrodes 9A, 9B, and 9C. Then, a protective film is formed, and the terminal electrodes 10A, 10B, and 10C are partially opened to expose the terminal electrodes 10A, 10B, and 10C.

[0099] In this embodiment, the value of Ls is 250 μm, the value of d is 30 μm, and Ls / d is about 8.3. In this example, Ls / d is also less than 55, and Q / Q0 is 0.52, so an electronic component with a sufficiently large Q value of the inductor can be obtained.

[0100] 《Sixth Implementation Method》

[0101] In the sixth embodiment, an electronic component having capacitor electrodes inside a dielectric layer is exemplified.

[0102] Fig.21This is a cross-sectional view of an electronic component 106 according to the sixth embodiment. The electronic component 106 includes: a substrate 1; a dielectric layer 11 extending along the surface of the substrate 1; planar conductors 3 and 4 formed in the dielectric layer 11; a spiral coil type inductor conductor pattern 5 formed in the insulating layer 2; and terminal electrodes 9A, 9B, 10A, and 10B. One end of the inductor conductor pattern 5 is electrically connected to the planar conductor 4 and the terminal electrode 9A, and the other end of the inductor conductor pattern 5 is electrically connected to the planar conductor 3 and the terminal electrode 9B. The electronic component 106 forms a parallel circuit of an inductor and a capacitor.

[0103] In this embodiment, when Ls represents the length in the longitudinal direction of the region where the inductor conductor pattern 5 is formed and overlaps with the planar conductor 4 and d represents the interval between the inductor conductor pattern and the planar conductor, Ls / d is also a value of 1 to 60.

[0104] In addition, in each of the embodiments shown above, an example is shown in which a conductor pattern for an inductor has an opening MH of a magnetic flux φ where the magnetic flux is concentrated, and a planar conductor is arranged in the entire or a part of the opening MH. It is not necessarily explicitly shown that the planar conductor covers the entire opening MH of the magnetic flux φ, but the planar conductor may also cover the entire opening MH of the magnetic flux φ.

[0105] In addition, in each of the above-described embodiments, an electronic component including a capacitor or a resistor as a passive component in addition to an inductor is shown, but an electronic component including a passive component including both a capacitor and a resistor can also be configured in the same manner. In addition, an electronic component including a passive component including a plurality of capacitors or a plurality of inductors can also be configured in the same manner.

[0106] Furthermore, the present invention can also be similarly applied to electronic components used as LC parallel resonant circuits, bandpass filters including a plurality of inductors and capacitors, duplexers, and the like.

[0107] Furthermore, the present invention can also be similarly applied to electronic components in which the substrate is a semiconductor substrate and the planar conductor and the semiconductor substrate together constitute a semiconductor active element. For example, the present invention can also be similarly applied to a high-frequency power amplifier in which an active element is provided on a semiconductor substrate.

[0108] Finally, the present invention is not limited to the above-mentioned embodiments. It can be appropriately modified and changed by those skilled in the art. The scope of the present invention is not shown by the above-mentioned embodiments, but by the claims. Furthermore, within the scope of the present invention, modifications and changes from the embodiments within the scope equivalent to the claims are included.

[0109] The structures of the electronic components of the present invention are listed below.

[0110] <1>

[0111] The invention comprises: a substrate; an insulating layer extending along the surface of the substrate; a single or multiple planar conductors formed on the substrate or in the insulating layer and extending in a planar manner parallel to the surface of the substrate; and a conductor pattern for an inductor formed on or in the insulating layer, wherein, as viewed from a direction perpendicular to the surface of the substrate, the length in the long dimension direction of a single region where the formation region of the conductor pattern for the inductor overlaps with the planar conductor, or the length in the long dimension direction of a plurality of regions where the formation region of the conductor pattern for the inductor overlaps with the planar conductor added in a given direction is represented by Ls, and the interval between the conductor pattern for the inductor and the planar conductor closest to the conductor pattern for the inductor is represented by d, and in this case, the value of Ls / d is greater than 1 and less than 60.

[0112] <2>

[0113] according to <1> The electronic component, wherein

[0114] The value of Ls / d is 1 or more and 55 or less.

[0115] <3>

[0116] according to <1> or <2> The electronic component, wherein

[0117] The invention comprises: a dielectric layer formed between the substrate and the insulating layer;

[0118] The planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer.

[0119] <4>

[0120] according to <1> or <2> The electronic component, wherein

[0121] The substrate is a low-resistance semiconductor substrate,

[0122] The planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate.

[0123] <5>

[0124] according to <1> or <2> The electronic component, wherein

[0125] The substrate is a semiconductor substrate,

[0126] The planar conductor and the semiconductor substrate together constitute a semiconductor active element.

[0127] <6>

[0128] according to <1> to <5> The electronic component according to any one of claims , wherein

[0129] The planar conductor is a resistive film.

[0130] <7>

[0131] according to <1> to <6> The electronic component according to any one of claims , wherein

[0132] The inductor conductor pattern has an opening where magnetic flux concentrates, and the planar conductor is arranged in the opening.

[0133] <8>

[0134] according to <7> The electronic component, wherein

[0135] The planar conductor covers the entire opening.

[0136] Description of Reference Numerals

[0137] AP: Open mouth;

[0138] C1: capacitor;

[0139] d: interval;

[0140] EC: eddy current;

[0141] Ls: length in the long dimension direction;

[0142] L1: inductor;

[0143] Lx: width;

[0144] Ly: height;

[0145] La, Lb, Lc, Ld, Le, Lf, Lg: layers;

[0146] MH: opening of magnetic flux;

[0147] R1: resistance element;

[0148] φ: magnetic flux;

[0149] 1: Substrate;

[0150] 2: Insulator layer;

[0151] 3, 4: Planar conductor;

[0152] 5: Conductor pattern for inductor;

[0153] 7, 8: conductors for connecting planar conductors;

[0154] 7A, 7B, 7C, 8: conductors for connecting planar conductors;

[0155] 9A, 9B, 9C, 10A, 10B, 10C: terminal electrodes;

[0156] 11: dielectric layer;

[0157] 20: insulator film;

[0158] 21: resistor body film;

[0159] 101~106: Electronic components.

Claims

1. An electronic component comprising: substrate; an insulator layer extending along a surface of the substrate; A single or a plurality of planar conductors are formed on the substrate or in the insulator layer and extend in a planar shape parallel to the surface of the substrate; as well as an inductor conductor pattern formed on or in the insulating layer, When observed from a direction perpendicular to the surface of the substrate, the length in the long dimension direction of a single area where the formation area of ​​the inductor conductor pattern overlaps with the planar conductor, or the lengths in the long dimension direction of multiple areas where the formation area of ​​the inductor conductor pattern overlaps with the planar conductor added in a given direction are represented by Ls, and the interval between the inductor conductor pattern and the planar conductor closest to the inductor conductor pattern is represented by d. In this case, the value of Ls / d is greater than 1 and less than 60.

2. The electronic component according to claim 1, wherein The value of Ls / d is 1 or more and 55 or less.

3. The electronic component according to claim 1 or 2, wherein: The invention comprises: a dielectric layer formed between the substrate and the insulating layer; The planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer.

4. The electronic component according to claim 1 or 2, wherein: The substrate is a low-resistance semiconductor substrate, The planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate.

5. The electronic component according to claim 1 or 2, wherein: The substrate is a semiconductor substrate, The planar conductor and the semiconductor substrate together constitute a semiconductor active element.

6. The electronic component according to any one of claims 1 to 5, wherein The planar conductor is a resistive film.

7. The electronic component according to any one of claims 1 to 6, wherein: The inductor conductor pattern has an opening where magnetic flux concentrates, and the planar conductor is arranged in the opening.

8. The electronic component according to claim 7, wherein The planar conductor covers the entire opening.

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