Dynamic body biasing for radio frequency (RF) switches

Abstract

A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switching field effect transistor (FET). The switching FET includes a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled between a body region and a gate region of the switching FET.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 892,800, filed on August 22, 2022, entitled “DYNAMIC BODY BIASING FOR RADIOFREQUENCY (RF) SWITCH,” the disclosure of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to integrated circuits (ICs). More specifically, the present disclosure relates to dynamic body biasing for radio frequency (RF) switches. Background Art

[0004] The design complexity of mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is complicated by the addition of circuit functions to support communication enhancement. Designing mobile RF transceivers can include the use of semiconductor-on-insulator technology. Semiconductor-on-insulator (SOI) technology replaces conventional semiconductor (such as silicon) substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices are different from conventional silicon-made devices because the silicon junction is above an electrical insulator (usually a buried oxide (BOX) layer). However, the reduced thickness of the BOX layer may not be able to fully reduce the artificial harmonics caused by the proximity of the active devices on the SOI layer and the SOI substrate supporting the BOX layer.

[0005] For example, high performance complementary metal oxide semiconductor (CMOS) radio frequency (RF) switch technology is currently manufactured using SOI substrates. Although SOI substrates can provide some protection against out-of-band harmonics in RF transceivers, there is a need to increase device isolation and reduce RF losses. In addition, transistors manufactured using SOI technology may be affected by the floating body effect, in which the body of the transistor collects the charge generated at the junction of the transistor device. Summary of the invention

[0006] A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switching field effect transistor (FET). The switching FET includes a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled between the body region and the gate region of the switching FET.

[0007] A method of constructing a radio frequency integrated circuit (RFIC) having a switching field effect transistor (FET) is described. The method includes bonding a gate region to a body region of the switching FET. The method also includes forming a dynamic bias control circuit between the gate region and the body region of the switching FET. The dynamic bias control circuit includes at least one transistor between the gate region and the body region of the switching FET.

[0008] This is a rather broad overview of the features and technical advantages of the present disclosure, so that the following detailed description is better understood. Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures for achieving the same purpose of the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the teachings of the present disclosure as set forth in the appended claims. When considered in conjunction with the accompanying drawings, the novel features that are considered to be features of the present disclosure, including their organization and methods of operation, and additional purposes and advantages, will be better understood from the following description. However, it should be expressly understood that each of the accompanying drawings is provided for the purpose of illustration and description only, and is not intended to be a definition of the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a schematic diagram of a wireless device having a wireless local area network module and a radio frequency (RF) front-end module for a chipset;

[0011] Figure 2 A cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) is shown, including an RF silicon-on-insulator (SOI) device;

[0012] Figure 3A is a schematic diagram showing a switching field effect transistor (FET) including a body current bypass resistor for improving breakdown voltage and harmonic performance;

[0013] Figure 3B is a schematic diagram showing a switching field effect transistor (FET) including a body current bypass resistor for further improving breakdown voltage and harmonic performance;

[0014] Figure 4 is a schematic diagram showing a switch stack including a switching field effect transistor (FET) with a dynamic bias control circuit according to aspects of the present disclosure;

[0015] Figure 5is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0016] Figure 6 is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0017] Figure 7 is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0018] Figure 8 is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0019] Fig. 9 is a schematic diagram showing a radio frequency integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0020] Fig. 10A and Fig. 10B is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET;

[0021] Fig.11 is a process flow diagram illustrating a method for constructing a radio frequency (RF) integrated circuit (RFIC) having a dynamic bias control circuit according to one aspect of the present disclosure;

[0022] Fig.12 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed; and

[0023] Fig.13 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION

[0024] The detailed description presented below in conjunction with the accompanying drawings is intended to describe various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it is clear to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusing such concepts.

[0025] As described herein, the use of the term "and / or" is intended to mean "inclusive or", while the use of the term "or" is intended to mean "exclusive or", and the term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration", and should not necessarily be interpreted as being preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used throughout this specification means "connected directly or indirectly through an intervening connection (e.g., a switch), the intervening connection being electrical, mechanical, or otherwise", and is not necessarily limited to physical connections. In addition, a connection may cause an object to be permanently connected or releasably connected. The connection may be made by a switch. As described herein, the term "close to" as used throughout this specification means "adjacent, very close, immediately adjacent, or near". As described herein, the term "on..." as used throughout this specification means "directly on..." in some configurations and "indirectly on..." in other configurations.

[0026] Due to cost and power consumption considerations, mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep submicron process nodes. Designing mobile RF transceivers can include using semiconductor-on-insulator technology. Semiconductor-on-insulator (SOI) technology replaces conventional silicon substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices are different from conventional silicon-made devices because the silicon junction is above an electrical insulator (usually a buried oxide (BOX) layer). However, the reduced thickness of the BOX layer may not be able to fully reduce the artificial harmonics caused by the proximity of the active devices on the SOI layer and the SOI substrate supporting the BOX layer.

[0027] For example, the thickness of the BOX layer determines the distance between the active device and the SOI substrate separated from the active device by the BOX layer. Sufficient distance between the active device and the SOI substrate is important for improving the performance of the active device. However, reducing the device footprint to meet the specifications of future process nodes will reduce the thickness of the BOX layer, which defines the distance between the active device and the SOI substrate. Reducing the thickness of the BOX layer in future process nodes may significantly reduce device performance due to artificial harmonics. That is, increasing the proximity of the active device and the SOI substrate in future process nodes will reduce device performance.

[0028] Active devices on the SOI layer may include high performance complementary metal oxide semiconductor (CMOS) transistors. For example, high performance CMOS RF switch technologies are currently manufactured using SOI substrates. The RF front end (RFFE) can rely on these high performance CMOS RF switch technologies to operate successfully. Therefore, the process used to manufacture the RFFE involves expensive integration of SOI wafers to support these high performance CMOS RF switch technologies. In addition, support for future RF performance enhancements involves increasing device isolation while reducing RF losses.

[0029] One technique to increase device isolation and reduce RF losses is to use SOI wafers to manufacture RFFE. For example, an RF device (e.g., an RF switching device) may include a transistor manufactured using an SOI wafer. Unfortunately, transistors manufactured using SOI technology may be affected by the floating body effect. The floating body effect is a phenomenon in which the body of the transistor collects the charge generated at the junction of the transistor device. In this case, the charge accumulated in the body can cause adverse effects such as parasitic transistors in the structure and OFF state leakage. In addition, the accumulated charge also causes the threshold voltage of the transistor to depend on its previous state. The floating body effect may also generate out-of-band harmonic frequencies, which is harmful to future communication enhancements.

[0030] Various aspects of the present disclosure provide techniques for dynamic bias control circuits for improving the breakdown voltage and harmonic performance of RF switching devices. The process flow of semiconductor manufacturing of integrated RF circuits with RF switching devices may include front-end line (FEOL) processes, middle line (MOL) processes, and back-end line (BEOL) processes. It should be understood that the term "layer" includes a film and shall not be interpreted as indicating vertical or horizontal thickness unless otherwise specified. As described herein, the term "substrate" may refer to a substrate of a cut wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0031] Various aspects of the present disclosure relate to a dynamic bias control circuit for improving the performance of an RF switching device. That is, various aspects of the present disclosure employ dynamic control of at least one transistor of a dynamic bias control circuit to dynamically bias the body bias of an RF switching device. According to this aspect of the present disclosure, an RF integrated circuit (RFIC) includes a switching field effect transistor (FET) having a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit, which includes at least one transistor coupled between the body region and the gate region of the switching FET.

[0032] Figure 11 is a schematic diagram of a wireless device 100 (e.g., a cellular phone or smartphone) according to various aspects of the present disclosure, the wireless device 100 including a dynamic bias control circuit for improving the performance of a radio frequency (RF) switch device. The wireless device 100 has a wireless local area network (WLAN) (e.g., WiFi) module 150 and an RF front-end module 170 for a chipset 110. The WiFi module 150 includes a first duplexer 160 that communicatively couples an antenna 162 to a wireless local area network module (e.g., WLAN module 152). The RF front-end module 170 includes a second duplexer 190 that communicatively couples an antenna 192 to a wireless transceiver 120 (WTR) through a duplexer 180 (DUP). The RF switch 172 communicatively couples the second duplexer 190 to the duplexer 180. The wireless transceiver 120 and the WLAN module 152 of the WiFi module 150 are coupled to a modem (MSM, e.g., a baseband modem) 130, which is powered by the power supply 102 through a power management integrated circuit (PMIC) 140. The chipset 110 also includes capacitors 112 and 114, and (multiple) inductors 116 to provide signal integrity. The PMIC 140, the modem 130, the wireless transceiver 120, and the WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to the clock 118. The geometry and arrangement of the various inductor and capacitor components in the chipset 110 can reduce electromagnetic coupling between the components.

[0033] The wireless transceiver 120 of the wireless device generally includes a mobile RF transceiver for transmitting and receiving data for two-way communication. The mobile RF transceiver may include a transmission part for data transmission and a reception part for data reception. For data transmission, the transmission part may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal with an appropriate output power level, and transmit the amplified RF signal to a base station via an antenna 192. For data reception, the reception part may obtain a received RF signal via an antenna, and may amplify the received RF signal using a low noise amplifier (LNA), and process the received RF signal to recover the data sent by the base station in the communication signal.

[0034] The wireless transceiver 120 may include one or more circuits for amplifying these communication signals. The amplifier circuit (e.g., LNA / PA) may include one or more amplifier stages, which may have one or more driver stages and one or more amplifier output stages. Each amplifier stage includes one or more transistors configured in various ways to amplify the communication signals. There are various options for manufacturing transistors configured to amplify the communication signals transmitted and received by the wireless transceiver 120.

[0035] The wireless transceiver 120 and the RF front-end module 170 may be implemented using semiconductor-on-insulator (SOI) technology for manufacturing transistors of the wireless transceiver 120, which helps reduce high-order harmonics in the RF front-end module 170. SOI technology replaces conventional semiconductor substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional silicon-made devices because the silicon junction is above an electrical insulator, typically a buried oxide (BOX) layer. However, the reduced thickness of the BOX layer may not adequately reduce artificial harmonics caused by the proximity of active devices on the SOI layer and the SOI substrate supporting the BOX layer. Active devices such as the SOI substrate fabricated using SOI technology may not be able to sufficiently reduce the harmonics caused by the proximity of active devices on the SOI layer and the SOI substrate supporting the BOX layer. Figure 2 shown.

[0036] Figure 2 2 shows a cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) 200. Figure 2 As shown, the RF silicon-on-insulator (SOI) device includes an active device 210 on a buried oxide (BOX) layer 220 supported by an SOI substrate 202 (e.g., a silicon wafer). The RF SOI device can be manufactured as a complementary metal oxide semiconductor (CMOS) transistor using a CMOS process. The RF SOI device also includes an interconnect 250 coupled to the active device 210 within a first dielectric layer 206. In this configuration, the parasitic capacitance of the RF SOI device is proportional to the thickness of the BOX layer 220, which determines the distance between the active device 210 and the SOI substrate 202.

[0037] The active device 210 on the BOX layer 220 may be a CMOS transistor. For example, high performance CMOS RF switch technology is currently manufactured using SOI substrates. Figure 1 ) can rely on these high-performance CMOS RF technologies to operate successfully. Therefore, the process used to manufacture RFFE 170 involves the integration of SOI wafers to support these high-performance CMOS RF technologies. In addition, support for future RF performance enhancements involves increasing device isolation while reducing RF losses. RF integrated circuit 200 can be used to implement Figure 1 For example, the active device 210 may be a switching field effect transistor (FET) of the RF switch 172 of the RFFE 170.

[0038] By using SOI wafers to implement RFFE 170, the configuration of RF integrated circuit 200 increases device isolation and reduces RF losses. Unfortunately, because RF integrated circuit 200 is manufactured using SOI technology, active devices 210 may be affected by floating body effect. The floating body effect is a phenomenon in which the body of the transistor collects the charge generated at the junction of the transistor device. The charge accumulated in the body can cause adverse effects such as parasitic transistors in the structure and OFF state leakage (e.g., gate induced drain leakage (GIDL) current). In addition, the accumulated charge also causes the threshold voltage of the transistor to depend on its previous state. The floating body effect may also produce undesirable out-of-band harmonic frequencies, which are harmful to the communication enhancement integrated within RFFE 170.

[0039] During the OFF state, the active device 210 (e.g., a switching field effect transistor (FET)) isolates the RF integrated circuit from the input power supply (Pin). The isolation of the active device 210 from the input power supply Pin is increased by negatively biasing the gate of the active device 210 for hard shutdown of the active device 210. Unfortunately, negatively biasing the gate of the active device 210 may significantly increase the gate-to-drain voltage (Vgd) of the active device 210. The high gate-to-drain voltage Vgd triggers a gate-induced drain leakage (GIDL) current, resulting in positive charge accumulation in the body of the active device 210. That is, the high potential difference between the gate and drain of the switching FET causes the GIDL current.

[0040] Furthermore, when an RF signal is received at the drain of the active device 210, i.e., in a bias OFF state, the transmission of the RF signal may be corrupted along the intended path if the active device 210 is not fully isolated. For example, if the gate of the active device 210 fails to isolate the RF signal from, for example, a power supply coupled to the active device 210, the RF signal is severely corrupted. Isolating the RF signal (e.g., gate) from the power supply may be referred to as RF isolation.

[0041] The current switching product may include a body contact for extracting the charge accumulated in the body of the switching transistor by biasing the body contact of the switching FET (e.g., active device 210) independently of the gate of the switching FET. In addition, a resistor may be used to RF isolate the gate of the switching FET from the power supply. Although these techniques provide RF isolation, biasing the body independently of the bias to the gate of the switching FET may cause the body to move independently of the gate. This independent movement of the body may generate undesirable out-of-band harmonics. In addition, biasing the gate and body separately may involve a separate charge pump for providing external gate and body voltages. However, using a separate charge pump consumes a large amount of chip area of ​​the RF integrated circuit 200.

[0042] One technique for preventing independent movement of the body involves binding the body contact to the gate of the switching FET using a diode. In addition, an external resistor can be coupled to the node where the gate is bound to the body to provide RF isolation of the gate from the power supply to protect the RF signal. When the external resistor provides RF isolation, the voltage drop across the external resistor (e.g., due to the body current Ib) can reduce the voltage at the gate of the switching FET. This reduced gate voltage (Vg) reduces the negative bias of the gate, resulting in gate debiasing of the switching FET. Gate debiasing of the switching FET prevents the gate from isolating the switching FET from the input power supply Pin.

[0043] Lowering the gate voltage Vg also lowers the breakdown voltage of the switch FET because the breakdown voltage is a function of the gate voltage Vg. That is, the gate voltage Vg is negatively affected by the body current Ib of the switch FET due to the voltage drop across the external resistor. As described above, the body current Ib is based on the magnitude of the input power supply Pin at the gate of the switch FET. As a result, the maximum breakdown voltage of the switch FET is limited by the body current Ib of the switch FET because the body current substantially reduces the gate voltage Vg.

[0044] Figure 3A 300 . Schematic diagram of a switching field effect transistor (FET) including a body current bypass resistor for improving breakdown voltage and harmonic performance. In this configuration, an isolation diode is used to bind the body of the switching FET 300 to the gate. In this example, the switching FET 300 does not include an external resistor for isolating the switching FET 300 from a power supply that can be electrically coupled to an external voltage (Vext) node. Eliminating the external resistor can prevent de-biasing of the gate of the switching FET 300. Eliminating the external resistor makes the internal gate voltage (Vgint) node equal to the external voltage (Vext) of the switching FET 300.

[0045] In this configuration, a body bypass resistor (Rb) is coupled between the body and the gate of the switching FET 300. In this example, an isolation diode is electrically coupled between the body bypass resistor Rb and the body of the switching FET 300. The resistance of the body bypass resistor Rb can be reduced to allow charge to escape from the body of the switching FET 300. As the body voltage (Vb) increases, a small body bypass resistor Rb can provide RF isolation of the body by allowing charge to escape from the body through the isolation diode without de-biasing the gate. In addition, gate de-biasing can be further prevented by electrically coupling a gate isolation resistor (Rg) between the body bypass resistor Rb and the gate of the switching FET 300.

[0046] Figure 3Bis a schematic diagram showing a switching field effect transistor (FET) 350 including a body current bypass resistor for further improving breakdown voltage and harmonic performance. In this example, a gate isolation resistor (Rg) is electrically coupled between an internal voltage (Vint) node and the gate of the switching FET 350. In addition, a body bypass resistor (Rb) is electrically coupled between an isolation diode and the body of the switching FET 350. In this example, both the isolation diode and the gate isolation resistor Rg are electrically coupled to the Vint node of the switching FET 350.

[0047] exist Figure 4 In the configuration shown, the resistance of the gate isolation resistor Rg is greater than or equal to the resistance of the body bypass resistor Rb. In addition, the size of the gate isolation resistor Rg is selected to tune the switching time of the switch FET 350. In addition, the resistance of the body bypass resistor Rb can be reduced to allow charge to escape from the body of the switch FET 350. The small body bypass resistor Rb provides RF isolation of the body and simultaneously allows the regulated GIDL current to flow through the isolation diode and out to the external voltage (Vext) node without de-biasing the gate.

[0048] In operation, the isolation diode electrically couples the gate and body nodes of the switch FET 350 to ensure high linearity. In addition, the internal voltage Vint and the external voltage Vext are determined according to the voltage drop (Vdrop) across the body bypass resistor Rb (Vdrop = Ib*Rb). The switching time of the switch FET 350 is tuned according to the gate isolation resistor Rg, which is independent of the body bypass resistor Rb and does not affect the gate voltage Vg. In addition, this configuration of the switch FET 350 supports a single charge pump, which saves a lot of semiconductor chip area.

[0049] Figure 3A The switch FET 300 and Figure 3B The configuration of switch FET 350 shown solves some of the problems previously associated with gate de-biasing and provides area optimization for the level shifter and charge pump. However, these configurations of switch FET 300 and switch FET 350 suffer from the effect of the internal body voltage (Vbint) being lower than the external voltage (Vext) (e.g., Vext-diode voltage (Vdiode)-Vdrop~0.7V). Having the internal body voltage Vbint lower than the external voltage Vext has a negative impact on the breakdown of short channel devices. In addition, these configurations of switch FET 300 and switch FET 350 also suffer from higher actual losses (represented by Rp), especially when implemented in a switch product, such as, for example, Figure 4 shown.

[0050] Figure 4is a schematic diagram showing a switch stack 400 including switching field effect transistors (FETs) with dynamic bias control circuitry according to aspects of the present disclosure. In this example, the switch stack 400 is coupled to an input RF voltage source (V rf ), impedance (Z0). Gate voltage source (V g ) is coupled to the gate resistor (R g ), gate resistor (R g ) is coupled to each gate of the switch FETs of the switch stack 400. In the parallel condition (when the switches are open), the gates of the switch FETs of the switch stack 400 are negatively biased. The negative bias results in a hard turn-off condition for preventing an input RF signal (e.g., an input power supply Pin) from passing between the drain and source of the switch FETs. Although described with reference to a semiconductor on insulator (SOI) wafer, it should be appreciated that the switch stack 400 is not limited to SOI wafers and can be manufactured using bulk semiconductor wafers.

[0051] Unfortunately, when the switch stack 400 is used e.g. Figure 3A The switching FET 300 or Figure 3B When the switch FET 350 is implemented with a switch stack 400, the switch stack 400 suffers from higher real losses (represented by the parameter Rp). As previously described, the net effect from the parasitic losses to ground is represented by the real losses Rp. For example, the real losses Rp are calculated based on measured antenna parameters (e.g., S parameters Y(11)), where the real losses Rp are equal to 1 / real[Y(11)]. At low frequencies, the real losses Rp are equal to the resistance value (Rb) of all bias resistors (N) in parallel (e.g., Rg / N).

[0052] Figure 3A The switching FET 300 and Figure 3B The switch FET 350 has resistors in both the body region and the gate region. At low frequencies, the actual loss Rp of this configuration is equal to the resistance value Rb of all bias resistors N and the resistance value Rb of the bias resistors in parallel (e.g., (Rg||Rb) / N), resulting in an increase in the actual loss Rp. In practice, an RF switch with reduced actual loss Rp is important for achieving antenna efficiency, for example, Figure 5-10B shown.

[0053] Figure 5is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) 500 according to aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) 510 and a dynamic bias control circuit 520 for improving the performance of the switching FET 510. In this configuration, the dynamic bias control circuit 520 is used for dynamic biasing of the body of the switching FET 510. In this example, the switching FET 510 includes an external gate resistor (Rg,ext) for providing power to the switching FET 510, which can be electrically coupled to an external gate voltage (Vg,ext) node. The gate of the switching FET 510 is coupled to the gate resistor Rg,ext to provide an internal gate voltage (Vg,int).

[0054] In this configuration, the dynamic bias control circuit 520 is electrically coupled between the body and gate of the switch FET 510. In this example, the dynamic bias control circuit 520 includes an N-channel metal oxide semiconductor (NMOS) transistor 530 and a P-channel metal oxide semiconductor (PMOS) transistor 540. In these aspects of the present disclosure, the NMOS transistor 530 includes an NMOS source terminal (S), an NMOS drain terminal (D), an NMOS body terminal (B), and an NMOS gate terminal (G) coupled to the gate region of the switch FET 510. In addition, the PMOS transistor 540 includes a PMOS source terminal (S) coupled to the body region of the switch FET 510 and a PMOS drain terminal (D) coupled to the NMOS drain terminal. The PMOS transistor 540 also includes a PMOS body terminal (B) coupled to the NMOS body terminal, and a PMOS gate terminal (G) coupled to the NMOS source terminal and the gate region of the switch FET 510.

[0055] In this configuration, the NMOS gate terminal is coupled to the PMOS source terminal and the body region of the switch FET 510. In addition, the NMOS drain terminal is coupled to the PMOS body terminal. Figure 5 As shown, the external gate resistor Rg,ext is coupled to the NMOS source terminal, the PMOS body terminal, and the gate region of the switch FET 510. In some aspects of the present disclosure, the dynamic bias control circuit 520 significantly improves the ON state and OFF state performance of the switch FET 510, such as the on-resistance (Ron), the breakdown voltage (BVD), and the actual loss Rp, which are important figures of merit (FOM). The dynamic bias control circuit 520 also significantly eliminates the leakage problem that may be caused by the de-biasing of the switch FET 510.

[0056] Figure 6is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to aspects of the present disclosure, the RFIC including a switch FET 610 and a dynamic bias control circuit 620 for improving the performance of the switch FET 610. Figure 6 As shown, the RFIC 600 including the dynamic bias control circuit 620 is implemented using a transistor for dynamically biasing the body of the switch FET 610 to improve the performance of the switch FET 610. In this example, the switch FET 610 also includes an external resistor Rg,ext (e.g., a first gate resistor) for providing power to the switch FET 610, which can be electrically coupled to the external gate voltage node Vg,ext.

[0057] like Figure 6 As shown, the dynamic bias control circuit 620 is electrically coupled between the body and gate of the switch FET 610. In these examples, the dynamic bias control circuit 620 is implemented with an N-channel metal oxide semiconductor field effect transistor (MOSFET). In some aspects of the present disclosure, the N-channel MOSFET includes a MOSFET source terminal coupled to the gate region of the switch FET 610 and a MOSFET drain terminal coupled to the body region of the switch FET 610. In addition, the N-channel MOSFET includes a MOSFET body terminal electrically coupled to the MOSFET gate terminal.

[0058] Implementing the dynamic bias control circuit 620 with a dynamically controlled N-channel MOSFET significantly improves the performance of the switch FET 610. In some aspects of the present disclosure, connecting the MOSFET gate terminal and the MOSFET body terminal of the N-channel MOSFET together and dynamically changing the gate potential of the N-channel MOSFET and the switch FET 610 improves the body bias of the switch FET 610. In operation, during the ON state of the switch FET 610 (e.g., switch gate voltage (Vgswitch) = positive control voltage), biasing of the dynamic bias control circuit 620 (e.g., gate voltage control (Vgcntrl) = body voltage control (Vbcntrl) = 0V) is performed.

[0059] The biasing of the dynamic bias control circuit 620 improves the body voltage of the switch FET 610 (e.g., Vbswitch=100 millivolts (mV)). Beneficially, the improved body voltage of the switch FET 610 (e.g., Vbswitch=100 mV) exceeds the performance of a simple diode (approximately 0 V) ​​and also exceeds the independent body switch FET biasing configuration (e.g., Vbody=0). The biasing of the dynamic bias control circuit 620 (e.g., Vgcntrl=Vbcntrl=negative control voltage) is performed in the OFF state of the switch FET 610 (e.g., Vgswitch=negative control voltage).

[0060] The biasing of the dynamic bias control circuit 620 improves the body voltage of the switch FET 610 (e.g., Vbswitch ~ negative control voltage). Beneficially, the improved body voltage of the switch FET 610 (e.g., Vbswitch ~ negative control voltage) exceeds the performance of a simple diode (e.g., Vbint ~ negative control voltage + Vdiode). Although similar to an independent body switch FET biasing configuration (e.g., Vbody = negative control voltage), this configuration provides significantly higher actual losses Rp, which is similar to a diode-connected body switch FET biasing configuration. In some aspects of the present disclosure, the dynamic bias control circuit 620 significantly improves the ON state and OFF state performance of the switch FET 610, such as on-resistance (Ron), breakdown voltage (BVD), and actual losses Rp, which are important figures of merit. The dynamic bias control circuit 620 provides significant overall improvements (e.g., approximately 15%-25%) in area reduction and / or performance improvement.

[0061] Figure 7 is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) 700 according to aspects of the present disclosure, the RFIC including a switch FET 710 and a dynamic bias control circuit 720 for improving the performance of the switch FET 710. Figure 7 As shown, RFIC 700 includes a dynamic bias control circuit 720, which is also implemented using transistors to dynamically bias the body of the switch FET 710 to improve the performance of the switch FET 710. In this example, the switch FET 710 also includes an external resistor Rg,ext for providing power to the switch FET 710, which can be electrically coupled to the external gate voltage node Vg,ext.

[0062] like Figure 7As shown, the dynamic bias control circuit 720 is electrically coupled between the body and gate of the switch FET 710. In this example, the dynamic bias control circuit 720 is implemented using a low threshold voltage (Vt) N-channel metal oxide semiconductor (NMOS) transistor. In some aspects of the present disclosure, the low Vt NMOS transistor includes an NMOS source terminal coupled to the gate region of the switch FET 710 and an NMOS drain terminal coupled to the body region of the switch FET 710. In addition, the low Vt NMOS transistor includes an NMOS body terminal electrically coupled to the NMOS gate terminal and the body region of the switch FET 710.

[0063] Implementing the dynamic bias control circuit 720 using a dynamically controlled low Vt NMOS transistor significantly improves the performance of the switch FET 710. In some aspects of the present disclosure, connecting the NMOS gate terminal and the NMOS body terminal of the low Vt NMOS transistor to the body region of the switch FET 710 eliminates additional bias specifications for the switch FET 710. For example, connecting the NMOS gate terminal and the NMOS body terminal of the low Vt NMOS transistor to the body region of the switch FET 710 eliminates additional bias specifications for the switch FET 710. Figure 6 The body of RFIC 600 is shown with an additional level shifter controlling transistors.

[0064] In operation, during the ON state of the switch FET 710 (e.g., Vgswitch = positive control voltage), an improved body voltage of the switch FET 710 (e.g., Vbswitch = 260 mV) is achieved. Beneficially, the improved body voltage of the switch FET 710 (e.g., Vbswitch = 200 mV) exceeds the performance of a simple diode (~7 mV) and also exceeds the performance of a stand-alone body switch FET biasing configuration (e.g., Vbody = 0). In the OFF state of the switch FET 710 (e.g., Vgswitch = negative control voltage), biasing of the dynamic bias control circuit 720 is performed (e.g., Vgcntrl = Vbcntrl = negative control voltage). The biasing of the dynamic bias control circuit 720 improves the body voltage of the switch FET 710 (e.g., Vbswitch ~ negative control voltage).

[0065] Beneficially, the improved body voltage of the switch FET 710 (e.g., Vbswitch ~ negative control voltage) exceeds the performance of a single diode (e.g., Vbint ~ negative control voltage + Vdiode) configuration. While similar to the independent body switch FET bias configuration (e.g., Vbody = ~ negative control voltage), this configuration provides significantly higher actual losses Rp, similar to Figure 3A and Figure 3BIn some aspects of the present disclosure, the dynamic bias control circuit 720 significantly improves the ON-state and OFF-state performance of the switch FET 710, such as on-resistance (Ron), breakdown voltage (BVD), and real loss Rp, which are important figures of merit.

[0066] Figure 8 is a schematic diagram showing a radio frequency integrated circuit (RFIC) according to various aspects of the present disclosure, the RFIC including a switch FET 810 and a dynamic bias control circuit 820 for improving the performance of the switch FET 810. Figure 8 As shown, the RFIC 800 includes a dynamic bias control circuit 820, which is implemented using transistors to dynamically bias the body of the switch FET 810 to improve the performance of the switch FET 810. In this example, the switch FET 810 also includes an external resistor Rg,ext for providing power to the switch FET 810, which can be electrically coupled to the external gate voltage node Vg,ext. In some aspects of the present disclosure, the dynamic bias control circuit 820 is implemented using transistors to dynamically bias the body of the switch FET 810 to improve the performance of the switch FET 810. In this example, the switch FET 810 also includes an external resistor Rg,ext for providing power to the switch FET 810, and the power can be electrically coupled to the external gate voltage node Vg,ext. Figure 6 The N-channel metal oxide semiconductor field effect transistor (MOSFET) is replaced by Figure 8 This is achieved by using the P-channel MOSFET in the circuit.

[0067] Fig. 9 is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) 900 according to aspects of the present disclosure, the RFIC including a switch FET 910 and a dynamic bias control circuit 920 for improving the performance of the switch FET 810. Fig. 9 As shown, the RFIC 900 includes a dynamic bias control circuit 920, which is also implemented using a low threshold voltage (Vt) transistor to dynamically bias the body of the switch FET 910 to improve the performance of the switch FET 910. In this example, the switch FET 910 also includes an external resistor Rg,ext for providing power to the switch FET 910, which can be electrically coupled to the external gate voltage node Vg,ext. In some aspects of the present disclosure, the dynamic bias control circuit 920 is implemented by using a low voltage threshold (Vt) P-channel metal oxide semiconductor (PMOS) transistor. In this example, the low Vt PMOS transistor includes a PMOS source terminal coupled to the gate region of the switch FET 910 and a PMOS drain terminal coupled to the body region of the switch FET 910. In addition, the low Vt PMOS transistor includes a PMOS body terminal electrically coupled to the PMOS gate terminal, the PMOS source terminal, and the body region of the switch FET 910.

[0068] Fig. 10Aand Fig. 10B is a schematic diagram showing a radio frequency (RF) integrated circuit (RFIC) according to various aspects of the present disclosure, the RFIC including a switching field effect transistor (FET) and a dynamic bias control circuit for improving the performance of the switching FET. Fig. 10A As shown, RFIC 1000 includes Figure 8 The switching FET 810 and the dynamic bias control circuit 820, and the resistor 860 electrically coupled to the gate terminal of the MOSFET. Fig. 10B As shown, RFIC 1050 includes Figure 6 A switching FET 610 and a dynamic bias control circuit 620, and a resistor 660 (eg, a second gate resistor) electrically coupled to the MOSFET gate terminal.

[0069] Reference again Figure 5 This configuration of the dynamic bias control circuit 520 as a combined NMOS / PMOS transistor control circuit eliminates the challenges associated with higher currents in the ON state associated with conventional switch FET bias configurations. In operation, during the ON state of the switch FET 510, the internal body voltage (Vb,int) is approximately equal to 82 mV (e.g., Vb,int ~ 82 mV), similar to a control transistor biased with a low threshold voltage gate, such as Figure 6 , Figure 8 , Fig. 10A and Fig. 10B shown. Figure 5 The configuration of the dynamic bias control circuit 520 shown exceeds the performance of both diode-connected and independent body switch FET bias configurations. In operation, during the OFF state, the internal body voltage (Vb,int) of the switch FET 510 is approximately equal to the negative control voltage (e.g., Vbint ~ negative control voltage). This OFF state operation is similar to the independent body switch FET bias configuration, but with twice the actual loss value (e.g., ~2xRp), and exceeds the performance of the diode-connected body switch FET bias configuration (e.g., Vbint = ~ negative control voltage + Vdiode).

[0070] Various aspects of the present disclosure provide techniques for dynamic body biasing to improve the performance of a switching FET by using a dynamic bias control circuit, such as Figure 5-10B Some aspects of the present disclosure provide a NMOS / PMOS transistor combination control circuit for performing dynamic body biasing of a switch FET, for example, Figure 5 In other aspects of the present disclosure, the NMOS / PMOS transistor combination control circuit can be replaced with a dynamically controlled MOSFET (e.g., Figure 6 , Figure 8 , Fig. 10A and Fig. 10B ) and low threshold voltage transistors (e.g. Figure 7 and Fig. 9 ). Fig.11 A method of constructing an RFIC with a dynamic body bias control circuit according to aspects of the present disclosure is shown in FIG.

[0071] Fig.11 1 is a process flow diagram illustrating a method for constructing a radio frequency (RF) integrated circuit (RFIC) with a dynamic bias control circuit according to one aspect of the present disclosure. The method 1100 begins at block 1102, where a gate region is bonded to a body region of a switching field effect transistor (FET). For example, Figure 5-10B As shown, the gate region is tied to the body region of the switch FET 510 / 610 / 710 / 810 / 910. In block 1004, a dynamic bias control circuit is formed between the gate region and the body region of the switch FET. Figure 5-Figure 1 In B, the dynamic bias control circuit 520 / 620 / 720 / 820 / 920 is formed between the gate region and the body region of the switch FET 510 / 610 / 710 / 810 / 910.

[0072] like Fig.11 As shown, in block 1104, the dynamic bias control circuit includes at least one transistor between the gate region and the body region of the switch FET. Figure 5 As shown, the dynamic bias control circuit 520 includes an N-channel metal oxide semiconductor (NMOS) transistor 530 and a P-channel metal oxide semiconductor (PMOS) transistor 540. In this example, the NMOS source terminal is coupled to the gate region of the switch FET 510, and the PMOS drain terminal is coupled to the NMOS drain terminal. In addition, the PMOS source terminal is coupled to the body region of the switch FET 510 to perform dynamic body biasing of the switch FET 510. In other aspects of the present disclosure, the NMOS / PMOS transistor 530 / 540 combination control circuit of the dynamic bias control circuit 520 can be replaced with a dynamically controlled metal oxide semiconductor field effect transistor (MOSFET) (e.g., Figure 6 , Figure 8 , Fig. 10A and Fig. 10B ) or low threshold voltage transistors (e.g. Figure 7 and Fig. 9 ).

[0073] Various aspects of the present disclosure relate to a dynamic bias control circuit for improving the performance of an RF switching device. That is, various aspects of the present disclosure employ dynamic control of at least one transistor of the dynamic bias control circuit to dynamically bias the body bias of the RF switching device. According to these aspects of the present disclosure, an RFIC includes a switch FET having a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit, which includes at least one transistor coupled between the body region and the gate region of the switch FET.

[0074] According to another aspect of the present disclosure, an RF integrated circuit including a switch FET is described. The switch FET includes means for dynamically biasing a body region of the switch FET. The dynamic bias means may be such as Figure 5-10B The dynamic body bias control circuit shown. In another aspect, the above means may be any module or any device configured to perform the functions recited by the above means.

[0075] Fig.12 1 is a block diagram illustrating an exemplary wireless communication system 1200 in which one aspect of the present disclosure may be advantageously employed. For purposes of illustration, Fig.12 Three remote units 1220, 1230, and 1250 and two base stations 1240 are shown. It will be appreciated that the wireless communication system can have more remote units and base stations. The remote units 1220, 1230, and 1250 include IC devices 1225A, 1225C, and 1225B, which include the disclosed switching field effect transistors (FETs) and dynamic bias control circuits. It will be appreciated that other devices may also include the disclosed switching field effect transistors (FETs) and dynamic bias control circuits, such as base stations, switching devices, and network equipment. Fig.12 Forward link signals 1280 from base station 1240 to remote units 1220, 1230, and 1250 and reverse link signals 1290 from remote units 1220, 1230, 1250 to base station 1240 are shown.

[0076] exist Fig.12 , remote unit 1220 is shown as a mobile phone, remote unit 1230 is shown as a portable computer, and remote unit 1250 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading device, or other communication devices that store or retrieve data or computer instructions, or a combination thereof. Although Fig.12Remote units are shown, but according to aspects of the present disclosure, the present disclosure is not limited to these exemplary shown units.Aspects of the present disclosure may be suitably applied in many devices including the disclosed switching field effect transistors (FETs) and dynamic bias control circuits.

[0077] Fig.13 13 is a block diagram of a design workstation for circuit, layout, and logic design of semiconductor components, such as the switching field effect transistor (FET) and dynamic bias control circuits described above. The design workstation 1300 includes a hard disk 1301, which contains operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 1300 also includes a display 1302 to facilitate the circuit design 1310 or RFIC 1312. A storage medium 1304 is provided for tangibly storing the circuit design 1310 or RFIC 1312. The circuit design 1310 or RFIC 1312 can be stored on the storage medium 1304 in a file format such as GDSII or GERBER. The storage medium 1304 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. In addition, the design workstation 1300 includes a drive 1303, which is used to accept input from the storage medium 1304 or write output to the storage medium 1304.

[0078] The data recorded on the storage medium 1304 may specify a logic circuit configuration, pattern data for a lithography mask, or mask pattern data for a serial write tool such as electron beam lithography. The data may also include logic verification data such as a timing diagram or network circuit associated with a logic simulation. Providing data on the storage medium 1304 facilitates the design of the circuit design 1310 or the RFIC 1312 by reducing the number of processes used to design a semiconductor wafer.

[0079] Implementation examples are described in the following numbered clauses:

[0080] 1. A radio frequency integrated circuit (RFIC), comprising:

[0081] a switching field effect transistor (FET), including a source region, a drain region, a body region, and a gate region; and

[0082] A dynamic bias control circuit includes at least one transistor coupled between a body region and a gate region of a switching FET.

[0083] 2. The RFIC of clause 1, wherein the dynamic bias control circuit comprises:

[0084] an N-channel metal oxide semiconductor (NMOS) transistor including an NMOS source terminal, an NMOS drain terminal, an NMOS body terminal, and an NMOS gate terminal, the NMOS source terminal being coupled to a gate region of the switch FET; and

[0085] A P-channel metal oxide semiconductor (PMOS) transistor includes a PMOS source terminal coupled to a body region of a switch FET, a PMOS drain terminal coupled to an NMOS drain terminal, a PMOS body terminal coupled to an NMOS body terminal, and a PMOS gate terminal coupled to the NMOS source terminal and a gate region of the switch FET.

[0086] 3. An RFIC according to clause 2, wherein the NMOS gate terminal is coupled to the PMOS source terminal and the body region of the switch FET.

[0087] 4. An RFIC according to clause 2 or 3, wherein the NMOS drain terminal is coupled to the PMOS body terminal.

[0088] 5. The RFIC according to any one of clauses 2 to 4, further comprising a gate resistor coupled to the NMOS source terminal, the PMOS gate terminal and the gate region of the switch FET.

[0089] 6. An RFIC according to claim 1, wherein at least one transistor includes an N-channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor including an NMOS source terminal coupled to a gate region of a switch FET, an NMOS drain terminal coupled to a body region of the switch FET, an NMOS body terminal, and an NMOS gate terminal coupled to the NMOS body terminal.

[0090] 7. The RFIC of clause 6, further comprising a first gate resistor coupled to the NMOS source terminal and the gate region of the switch FET.

[0091] 8. The RFIC according to clause 6 or 7, further comprising a second gate resistor coupled to the NMOS gate terminal and the NMOS body terminal.

[0092] 9. An RFIC according to claim 1, wherein at least one transistor includes an N-channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor including an NMOS source terminal coupled to a gate region of a switch FET, an NMOS drain terminal coupled to a body region of the switch FET, an NMOS body terminal coupled to the NMOS drain terminal, and an NMOS gate terminal coupled to the NMOS drain terminal.

[0093] 10. The RFIC of clause 9, further comprising a gate resistor coupled to the NMOS source terminal and the gate region of the switch FET.

[0094] 11. An RFIC according to claim 1, wherein at least one transistor includes a P-channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor including a PMOS source terminal coupled to a gate region of a switching FET, a PMOS drain terminal coupled to a body region of the switching FET, a PMOS body terminal, and a PMOS gate terminal coupled to the PMOS body terminal.

[0095] 12. The RFIC of clause 11, further comprising a first gate resistor coupled to the PMOS source terminal and the gate region of the switch FET.

[0096] 13. The RFIC according to clause 11 or 12, further comprising a second gate resistor coupled to the PMOS gate terminal and the PMOS body terminal.

[0097] 14. An RFIC according to claim 1, wherein at least one transistor includes a P-channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor including a PMOS source terminal coupled to a gate region of a switching FET, a PMOS drain terminal coupled to a body region of the switching FET, a PMOS body terminal coupled to the PMOS source terminal, and a PMOS gate terminal coupled to the PMOS source terminal.

[0098] 15. The RFIC of clause 14, further comprising a gate resistor coupled to the PMOS source terminal and the gate region of the switch FET.

[0099] 16. An RFIC according to any one of clauses 1 to 15, integrated into an RF front-end module, the RF front-end module being incorporated into at least one of the following items: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed position data unit, a mobile phone and a portable computer.

[0100] 17. A method of constructing a radio frequency integrated circuit (RFIC) having a switching field effect transistor (FET), comprising:

[0101] bonding the gate region to the body region of the switch FET; and

[0102] A dynamic bias control circuit is formed between the gate region and the body region of the switch FET, wherein the dynamic bias control circuit includes at least one transistor between the gate region and the body region of the switch FET.

[0103] 18. The method of clause 17, wherein the dynamic bias control circuit comprises:

[0104] an N-channel metal oxide semiconductor (NMOS) transistor including an NMOS source terminal, an NMOS drain terminal, an NMOS body terminal, and an NMOS gate terminal, the NMOS source terminal being coupled to a gate region of the switch FET; and

[0105] A P-channel metal oxide semiconductor (PMOS) transistor includes a PMOS source terminal coupled to a body region of a switch FET, a PMOS drain terminal coupled to an NMOS drain terminal, a PMOS body terminal coupled to an NMOS body terminal, and a PMOS gate terminal coupled to the NMOS source terminal and a gate region of the switch FET.

[0106] 19. The method of clause 18, wherein the dynamic bias control circuit further comprises a gate resistor coupled to the NMOS source terminal, the PMOS gate terminal, and a gate region of the switch FET.

[0107] 20. The method of any one of clauses 17 to 19 further comprises integrating the RFIC into an RF front-end module, the RF front-end module being incorporated into at least one of the following items: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0108] For firmware and / or software implementations, the methods can be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium that tangibly embodies instructions can be used to implement the methods described herein. For example, software codes can be stored in a memory and executed by a processor unit. The memory can be implemented within a processor unit or outside a processor unit. As used herein, the term "memory" refers to long-term, short-term, volatile, non-volatile, or other memory types, and is not limited to a specific memory type or number of memories, or the type of medium on which the memory is stored.

[0109] If implemented in firmware and / or software, these functions can be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. Storage media can be available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or other media that can be used to store desired program codes in the form of instructions or data structures and can be accessed by a computer; disks and optical disks as used herein include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVDs), floppy disks, and blue-ray disks, wherein disks generally reproduce data magnetically, and optical disks reproduce data optically with lasers. Combinations of the above items should also be included within the scope of computer-readable media.

[0110] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals on a transmission medium included in a communication device. For example, a communication device may include a transceiver with signals indicating instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0111] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure defined by the attached claims. For example, relational terms such as "above" and "below" are used relative to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, the above becomes the below, and vice versa. In addition, if facing the side, the above and the below can refer to the side of the substrate or electronic device. In addition, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures and material compositions, means, methods and steps described in the specification. As will be readily understood by those of ordinary skill in the art from the present disclosure, according to the present disclosure, processes, machines, manufactures, material compositions, means, methods or steps that currently exist or will be developed later to perform functions substantially the same as the corresponding configurations described herein or to achieve substantially the same results can be utilized. Therefore, the attached claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

Claims

1. A radio frequency integrated circuit (RFIC), comprising: a switching field effect transistor (FET), including a source region, a drain region, a body region, and a gate region; as well as A dynamic bias control circuit includes at least one transistor coupled between the body region and the gate region of the switch FET.

2. The RFIC of claim 1 , wherein the dynamic bias control circuit comprises: an N-channel metal oxide semiconductor (NMOS) transistor including an NMOS source terminal, an NMOS drain terminal, an NMOS body terminal, and an NMOS gate terminal, the NMOS source terminal being coupled to the gate region of the switch FET; as well as a P-channel metal oxide semiconductor (PMOS) transistor comprising a PMOS source terminal coupled to the body region of the switch FET, a PMOS drain terminal coupled to the NMOS drain terminal, a PMOS body terminal coupled to the NMOS body terminal, and a PMOS gate terminal coupled to the NMOS source terminal and the gate region of the switch FET.

3. The RFIC of claim 2, wherein the NMOS gate terminal is coupled to the PMOS source terminal and the body region of the switch FET.

4. The RFIC of claim 2, wherein the NMOS drain terminal is coupled to the PMOS body terminal.

5. The RFIC of claim 2, further comprising a gate resistor coupled to the NMOS source terminal, the PMOS gate terminal, and the gate region of the switch FET.

6. The RFIC of claim 1 , wherein the at least one transistor comprises an N-channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor comprising an NMOS body terminal, an NMOS source terminal coupled to the gate region of the switch FET, an NMOS drain terminal coupled to the body region of the switch FET, and an NMOS gate terminal coupled to the NMOS body terminal.

7. The RFIC of claim 6, further comprising a first gate resistor coupled to the NMOS source terminal and the gate region of the switch FET.

8. The RFIC of claim 6, further comprising a second gate resistor coupled to the NMOS gate terminal and the NMOS body terminal.

9. The RFIC of claim 1 , wherein the at least one transistor comprises an N-channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor comprising an NMOS source terminal coupled to the gate region of the switch FET, an NMOS drain terminal coupled to the body region of the switch FET, an NMOS body terminal coupled to the NMOS drain terminal, and an NMOS gate terminal coupled to the NMOS drain terminal.

10. The RFIC of claim 9, further comprising a gate resistor coupled to the NMOS source terminal and the gate region of the switch FET.

11. The RFIC of claim 1 , wherein the at least one transistor comprises a P-channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor comprising a PMOS body terminal, a PMOS source terminal coupled to the gate region of the switch FET, a PMOS drain terminal coupled to the body region of the switch FET, and a PMOS gate terminal coupled to the PMOS body terminal.

12. The RFIC of claim 11, further comprising a first gate resistor coupled to the PMOS source terminal and the gate region of the switch FET.

13. The RFIC of claim 11, further comprising a second gate resistor coupled to the PMOS gate terminal and the PMOS body terminal.

14. The RFIC of claim 1 , wherein the at least one transistor comprises a P-channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor comprising a PMOS source terminal coupled to the gate region of the switch FET, a PMOS drain terminal coupled to the body region of the switch FET, a PMOS body terminal coupled to the PMOS source terminal, and a PMOS gate terminal coupled to the PMOS source terminal.

15. The RFIC of claim 14, further comprising a gate resistor coupled to the PMOS source terminal and the gate region of the switch FET.

16. The RFIC of claim 1 , integrated into an RF front-end module, the RF front-end module being incorporated into at least one of the following items: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

17. A method of constructing a radio frequency integrated circuit (RFIC) having a switching field effect transistor (FET), comprising: bonding a gate region to a body region of the switch FET; as well as A dynamic bias control circuit is formed between the gate region and the body region of the switch FET, wherein the dynamic bias control circuit includes at least one transistor between the gate region and the body region of the switch FET.

18. The method of claim 17, wherein the dynamic bias control circuit comprises: an N-channel metal oxide semiconductor (NMOS) transistor including an NMOS source terminal, an NMOS drain terminal, an NMOS body terminal, and an NMOS gate terminal, the NMOS source terminal being coupled to the gate region of the switch FET; as well as a P-channel metal oxide semiconductor (PMOS) transistor comprising a PMOS source terminal coupled to the body region of the switch FET, a PMOS drain terminal coupled to the NMOS drain terminal, a PMOS body terminal coupled to the NMOS body terminal, and a PMOS gate terminal coupled to the NMOS source terminal and the gate region of the switch FET.

19. The method of claim 18, wherein the dynamic bias control circuit further comprises a gate resistor coupled to the NMOS source terminal, the PMOS gate terminal, and the gate region of the switch FET.

20. The method of claim 17, further comprising integrating the RFIC into an RF front-end module, the RF front-end module being incorporated into at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

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