Solid-state imaging device

Abstract

The present invention relates to a solid-state imaging device that achieves desired characteristics in a more appropriate layout. There is provided a solid-state imaging device including: a plurality of pixels each having a photoelectric conversion element and a plurality of wiring capacitance elements; and a readout unit that reads out a signal from the plurality of pixels, the solid-state imaging device having a structure in which charges overflowing from the photoelectric conversion element are stored in the first wiring capacitance element and charges overflowing from the first wiring capacitance element are stored in the second wiring capacitance element, and the readout unit individually reads out a signal of each of the photoelectric conversion element, the first wiring capacitance element, and the second wiring capacitance element. This disclosure can be applied to, for example, a CMOS-type solid-state imaging device.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, and in particular to a solid-state imaging device capable of realizing desired characteristics with a more appropriate layout. Background Art

[0002] As a structure of a pixel of an image sensor, there is known a structure provided with a storage capacitor that stores charges overflowing from a photodiode (for example, see Patent Document 1 and Patent Document 2).

[0003] Patent document 1 discloses a pixel structure provided with a capacitor including a cylindrical capacitor as a storage capacitor, which stores charges overflowing from a photodiode. Patent document 2 discloses a pixel structure provided with a first storage capacitor and a second storage capacitor storing charges overflowing from a photodiode on the same plane as the photodiode. [Citation list] [Patent Document]

[0004] Patent Document 1: JP2020-129795A Patent Document 2: JP2006-245522A Summary of the invention [Technical issues]

[0005] Although the storage capacitor is arranged as a storage structure in the structure disclosed in Patent Document 1, there is concern that increasing the capacitance within the pixel in order to expand the dynamic range will reduce the conversion efficiency and thus degrade the random noise. Therefore, it is necessary to limit the capacitance within the pixel so that the SN ratio reaches a certain standard or above, and it is difficult to strike a balance between the capacitance within the pixel and the dynamic range.

[0006] On the other hand, in the structure disclosed in Patent Document 2, in order to achieve a wider dynamic range while maintaining the SN ratio, the storage capacitors are arranged in a two-stage structure, and the two storage capacitors are arranged on the same plane as the photodiode, so the plane area on the light incident surface side of the photodiode is limited. Therefore, a technology for achieving desired characteristics with a more appropriate layout is required.

[0007] In view of this situation, the present disclosure achieves desired characteristics with a more appropriate layout. [Solutions to technical issues]

[0008] According to the first aspect of the present disclosure, a solid-state imaging device includes: a plurality of pixels, each of which has a photoelectric conversion element and a plurality of wiring capacitance elements; and a readout unit, which reads out signals from the plurality of pixels, the solid-state imaging device having a structure in which charges overflowing from the photoelectric conversion element are stored in a first wiring capacitance element and charges overflowing from the first wiring capacitance element are stored in a second wiring capacitance element, and the readout unit separately reads out the signals of each of the photoelectric conversion element, the first wiring capacitance element and the second wiring capacitance element.

[0009] According to the first aspect of the present disclosure, a solid-state imaging device has the following structure: the charge overflowing from the photoelectric conversion element is stored in the first wiring capacitance element, and the charge overflowing from the first wiring capacitance element is stored in the second wiring capacitance element, and the signal of each of the photoelectric conversion element, the first wiring capacitance element and the second wiring capacitance element is read out separately.

[0010] According to the second aspect of the present disclosure, a solid-state imaging device includes: a plurality of pixels, each of the pixels having a plurality of photoelectric conversion elements and a plurality of wiring capacitance elements; and a readout unit, which reads out signals from the plurality of the pixels, the solid-state imaging device having the following structure: a first wiring capacitance element and a second wiring capacitance element are respectively connected to floating diffusions of a first photoelectric conversion element and a second photoelectric conversion element, and charges overflowing from the first photoelectric conversion element are stored in the first wiring capacitance element, charges overflowing from the second photoelectric conversion element are stored in the second wiring capacitance element, and the readout unit separately reads out signals of each of the first photoelectric conversion element, the second photoelectric conversion element, the first wiring capacitance element and the second wiring capacitance element.

[0011] According to the second aspect of the present disclosure, a solid-state imaging device has the following structure: the charge overflowing from the first photoelectric conversion element is stored in the first wiring capacitance element, and the charge overflowing from the second photoelectric conversion element is stored in the second wiring capacitance element, and the signal of each of the first photoelectric conversion element, the second photoelectric conversion element, the first wiring capacitance element and the second wiring capacitance element is read out separately.

[0012] It should be noted that the solid-state imaging device according to one aspect of the present disclosure may be an independent device, or may be an internal block constituting one device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] [ Figure 1 ] Figure 1 is a diagram showing a configuration example of an embodiment of a solid-state imaging device to which the present disclosure is applied. [ Figure 2 ] Figure 2 is a cross-sectional view showing a first example of the structure of a pixel. [ Figure 3 ] Figure 3 is a cross-sectional view showing an example of the structure of a MIM capacitor element. [ Figure 4 ] Figure 4 is a diagram showing a first example of a TG type circuit configuration of a pixel. [ Figure 5 ] Figure 5 is with Figure 4 TG type circuit structure corresponding to the plan view of the pixel. [ Figure 6 ] Figure 6 It is shown Figure 4 A timing diagram of an example of a readout operation of a circuit configuration of a pixel in FIG. [ Figure 7 ] Figure 7 is a diagram showing a first example of an OFG type circuit configuration of a pixel. [ Figure 8 ] Figure 8 is with Figure 7 FIG. 1 is a plan view corresponding to the OFG type circuit structure of the pixel. [ Fig. 9 ] Fig. 9 is a cross-sectional view showing a second example of the structure of a pixel. [ Fig.10 ] Fig.10 is a cross-sectional view showing a third example of the structure of a pixel. [ Fig.11 ] Fig.11 is a diagram showing a second example of the TG type circuit configuration of a pixel. [ Fig.12 ] Fig.12 It is shown Fig.11 A timing diagram of an example of a readout operation of a circuit configuration of a pixel in FIG. [ Fig.13 ] Fig.13 is a diagram showing a second example of the OFG type circuit configuration of a pixel. [ Fig.14 ] Fig.14 is a cross-sectional view showing another example of the structure of a pixel. [ Fig.15 ] Fig.15 is with Fig.14 The plane image corresponding to the pixels in . [ Fig.16 ] Fig.16 It is shown Fig.14 A diagram of an example of a circuit configuration of a pixel in FIG. [ Fig.17 ] Fig.17 It is shown Fig.16 A timing diagram of an example of a readout operation of a circuit configuration of a pixel in FIG. [ Fig.18 ] Fig.18 is a cross-sectional view showing another example of the structure of the MIM capacitor element. [ Fig.19 ] Fig.19 : is a block diagram showing a configuration example of an electronic device including a built-in solid-state imaging device to which the present disclosure is applied. DETAILED DESCRIPTION

[0014] <Device Configuration> Figure 1 is a diagram showing a configuration example of an embodiment of a solid-state imaging device to which the present disclosure is applied.

[0015] exist Figure 1 The solid-state imaging device 10 is a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device and includes a pixel array unit 21 , a vertical drive unit 22 , a column signal processing unit 23 , a horizontal drive unit 24 , an output unit 25 , and a control unit 26 .

[0016] The pixel array unit 21 includes a plurality of pixels 100 two-dimensionally arranged in a matrix form on a semiconductor substrate made of silicon (Si) or the like. The pixel 100 includes a photodiode, a plurality of pixel transistors, etc. In the pixel array unit 21, for the plurality of pixels 100 two-dimensionally arranged in a matrix form, a pixel drive line 41 is formed in each row and connected to the vertical drive unit 22, and a vertical signal line 42 is formed in each column and connected to the column signal processing unit 23.

[0017] The vertical driving unit 22 is configured as a shift register, an address decoder, etc., and drives each pixel 100 arranged in the pixel array unit 21. A signal output from each pixel 100 selected and scanned by the vertical driving unit 22 is supplied to the column signal processing unit 23 via the vertical signal line 42.

[0018] The column signal processing unit 23 performs predetermined signal processing (for example, noise removal processing or sampling processing) on ​​signals output from each pixel 100 of the selected row via the vertical signal line 42 for each pixel column of the pixel array unit 21 , and temporarily holds the signals after the signal processing.

[0019] The horizontal driving unit 24 is configured as a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to the pixel columns of the column signal processing unit 23. Through the selection and scanning by the horizontal driving unit 24, the signal processed by the column signal processing unit 23 is output to the output unit 25 via the horizontal signal line 51.

[0020] The output unit 25 performs predetermined signal processing on the signals sequentially input from the respective column signal processing units 23 via the horizontal signal line 51 , and outputs the resultant signals.

[0021] The control unit 26 includes a timing generator and the like that generates various timing signals, and controls driving of the vertical driving unit 22 , the column signal processing unit 23 , the horizontal driving unit 24 and the like based on the various timing signals generated by the timing generator.

[0022] Next, in the solid-state imaging device 10, as a configuration of the pixels 100 two-dimensionally arranged in the pixel array unit 21 and a readout unit that reads out signals from the plurality of pixels 100, first to fifth configurations will be described. For example, the readout unit includes a vertical drive unit 22, a column signal processing unit 23, and a control unit 26.

[0023] <First Structure> Figure 2 is a cross-sectional view showing a first example of the structure of the pixel 100. Figure 2 In the three directions orthogonal to each other in space, the first direction and the second direction orthogonal to each other in the same plane are the X direction and the Y direction, respectively, and the third direction orthogonal to the first direction and the second direction is the Z direction. Figure 2 , the thickness direction of each layer is described as the Z direction. The same applies to other drawings described later.

[0024] Each pixel 100 is formed by stacking a semiconductor layer 11 and a wiring layer 12. A color filter 101 and an on-chip microlens 102 are arranged on the light incident surface side of the semiconductor layer 11. Each pixel 100 is provided with a color filter 101 and an on-chip microlens 102. The color filter 101 is configured as a filter that allows transmission of a wavelength corresponding to one of, for example, red (R), green (G), and blue (B).

[0025] The photodiode 111 is formed on a semiconductor substrate made of silicon (Si) or the like in the semiconductor layer 11. For example, the semiconductor substrate includes a P-well layer in a portion of the top surface and an area near the top surface, and includes an N-type area having a conductivity type different from the P-well layer in other areas. Therefore, the photodiode 111 is formed as a photoelectric conversion element. Each pixel 100 is electrically and optically isolated by an inter-pixel isolation portion 112. The inter-pixel isolation portion 112 is formed by burying a metal film, an insulating film, etc. in a groove formed by penetrating the semiconductor substrate from the surface on the side opposite to the light incident surface.

[0026] The wiring layer 12 is a multilayer wiring layer including a plurality of wiring layers, which are obtained by stacking on a plurality of levels and forming wiring 122 in each level, and a wiring interlayer film 121 is inserted between each level. The wiring interlayer film 121 is formed as a film using materials such as silicon oxide (SiO2). The wiring 122 is formed of copper (Cu) and the like. In the wiring layer 12, as wiring capacitance elements having different capacitances between wiring layers, MIM (Metal Insulator Metal: Metal Insulator Metal) capacitance elements 131 and MIM capacitance elements 132 are arranged.

[0027] Each pixel 100 is provided with a MIM capacitor element 131 and a MIM capacitor element 132. The MIM capacitor element 131 and the MIM capacitor element 132 are arranged so that at least a portion of each other overlaps in the plane in the X and Y directions. In addition, in the Z direction, the MIM capacitor element 132 is arranged at a deeper position than the MIM capacitor element 131 and is arranged between different wiring layers. That is, in the wiring layer 12, the MIM capacitor element 131 is arranged between the first wiring layer, and the MIM capacitor element 132 is arranged between the second wiring layer.

[0028] The MIM capacitor element 131 stores the charge overflowing from the photodiode 111. The MIM capacitor element 132 stores the charge overflowing from the MIM capacitor element 131. This structure enables the charge overflowing from the photodiode 111 to be stored in the MIM capacitor element 131 and the MIM capacitor element 132 together with the charge stored in the photodiode 111, and the charge to be read out.

[0029] Figure 3 1 is a cross-sectional view showing an example of the structure of the MIM capacitor element 131. Figure 3, the MIM capacitor element 131 has a three-dimensional structure in the X, Y and Z directions. The MIM capacitor element 131 has a structure formed by stacking an upper electrode 141, a lower electrode 142, and a dielectric 143 sandwiched between the upper electrode 141 and the lower electrode 142. A cap film 144 is formed on the upper surface of the upper electrode 141. The upper electrode 141 is connected to the wiring 122A via the contact 123A. The lower electrode 142 is connected to the wiring 122B.

[0030] The upper electrode 141 is formed of a single layer film using a material such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or tungsten nitride (WN), or a stacked film formed by stacking these materials. Similar to the upper electrode 141, the lower electrode 142 is formed of a single layer film or a stacked film using a material such as titanium nitride (TiN). The dielectric 143 is formed of a single layer film using a high dielectric constant material such as aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO) or niobium oxide (NbO), or a stacked film formed by stacking these materials. The cap film 144 is formed of a film using a material such as silicon nitride (SiN), silicon oxide (SiO) or silicon carbonitride (SiCN).

[0031] The MIM capacitor element 132 has Figure 3 The MIM capacitor element 131 shown in FIG. 1 is similar in structure to the MIM capacitor element 131 shown in FIG. 1 , but the film type, thickness, and area of ​​the dielectric 143 are different. As for the film type of the dielectric 143, the film type can be changed not only by changing the above-mentioned materials, but also by using films having different characteristics even in the case of the same material. The thickness of the dielectric 143 is shown in the Z direction, and Figure 3 143 is represented by h. The area of ​​dielectric 143 is the area of ​​the plane in the X and Y directions. This difference between the structures makes the capacitance of MIM capacitor element 131 and MIM capacitor element 132 different. For example, it is desirable to make the capacitance of MIM capacitor element 132 greater than the capacitance of MIM capacitor element 131, and to make the capacitance ratio of these capacitors about 1:30.

[0032] As described above, although the MIM capacitor element 131 and the MIM capacitor element 132 have a structure in which at least one of the film type, thickness, and area of ​​the dielectric 143 is different, other structures may also be different. For example, the MIM capacitor element 131 and the MIM capacitor element 132 may have different heights. Figure 3 In the figure, H is used. In addition, the structures and manufacturing processes of the MIM capacitor element 131 and the MIM capacitor element 132 may be different. The MIM capacitor element 131 and the MIM capacitor element 132 have a three-dimensional structure, so the capacitance per unit area can be increased and miniaturization can be achieved.

[0033] Figure 4 is a diagram showing a first example of a circuit configuration of the pixel 100. Figure 4 , the pixel 100 includes a photodiode 111 , a MIM capacitor 131 , a MIM capacitor 132 , a transfer transistor 161 , an FD 162 , a switch transistor 163 , a reset transistor 164 , an amplifier transistor 165 , a selection transistor 166 , a first storage transistor 167 , and a second storage transistor 168 .

[0034] The transfer transistor 161 is provided between the photodiode 111 and the FD 162, and transfers the charge stored in the photodiode 111 to the FD 162 according to the drive signal TGL applied to the gate voltage of the transfer transistor 161. The FD 162 is a floating diffusion (FD) that converts the charge from the photodiode 111 into a voltage signal.

[0035] The FD 162 is connected to a switching transistor 163 for switching conversion efficiency, and is connected to a reset transistor 164 via the switching transistor 163. In addition, the FD 162 is also connected to the vertical signal line 42 via an amplification transistor 165 and a selection transistor 166. A first storage transistor 167 is connected between the switching transistor 163 and the reset transistor 164. The first storage transistor 167 is connected to the MIM capacitance element 131 and the second storage transistor 168. The second storage transistor 168 is connected to the MIM capacitance element 132. The upper electrode of the MIM capacitance element 131 and the upper electrode of the MIM capacitance element 132 are connected to a common control power supply (VMID).

[0036] The switch transistor 163 switches the connection state between the FD162, the reset transistor 164, and the first storage transistor 167 according to the drive signal FDG applied to the gate voltage of the switch transistor 163. The first storage transistor 167 switches the connection state with the MIM capacitor element 131 according to the drive signal FCG1 applied to the gate electrode of the first storage transistor 167. The second storage transistor 168 switches the connection state with the MIM capacitor element 132 according to the drive signal FCG2 applied to the gate electrode of the second storage transistor 168.

[0037] For example, in the storage period, the charge before the photodiode 111 is saturated is stored in the photodiode 111, and the charge when the photodiode 111 is oversaturated can be stored in the MIM capacitor element 131 via the transfer transistor 161, the switch transistor 163, and the first storage transistor 167. In addition, the charge when the photodiode 111 and the MIM capacitor element 131 are oversaturated can be stored in the MIM capacitor element 132 via the second storage transistor 168.

[0038] The reset transistor 164 discharges the charges of the FD 162, the MIM capacitor element 131, and the MIM capacitor element 132 and resets them according to the drive signal RST applied to the gate electrode of the reset transistor 164. The amplifier transistor 165 is an input unit of the source follower circuit, has a gate electrode connected to the FD 162 and a drain connected to the power supply voltage (VDD), and reads out the charge obtained by the photoelectric conversion of the photodiode 111. That is, the amplifier transistor 165 includes a source connected to the vertical signal line 42 via the selection transistor 166 to form a constant current source and a source follower circuit connected to one end of the vertical signal line 42.

[0039] The selection transistor 166 is connected between the source of the amplifier transistor 165 and the vertical signal line 42. The selection transistor 166 puts the pixel 100 in a selected state according to a drive signal SEL applied to a gate electrode of the selection transistor 166. When the pixel 100 is in the selected state, a signal output from the amplifier transistor 165 is read out by the column signal processing unit 23 via the vertical signal line 42.

[0040] Figure 5 is a plan view showing a first example of the configuration of the pixel 100. Figure 5 In the plan view, Figure 4 Components that correspond to those in the circuit diagrams of FIG. 1 are assigned the same reference numerals. Figure 4 and Figure 5 In the embodiment, the charge overflowing from the photodiode 111 is stored in the MIM capacitor element 131 and the MIM capacitor element 132 via the transfer transistor 161 serving as the transfer gate. That is, Figure 4 and Figure 5 The structure shown is a TG (Transfer Gate) type structure. Figure 4 and Figure 5 The configuration shown is a configuration in which the FD 162 connected to the MIM capacitance element 131 and the MIM capacitance element 132 is isolated by the operation of the second storage transistor 168 to read out the charges respectively stored in the MIM capacitance element 131 and the MIM capacitance element 132 .

[0041] Next, we will refer to Figure 6 An example of a readout operation of the pixel 100 is described with reference to the timing diagram of FIG. Figure 6 In the VMID Figure 4 The common control signals of the MIM capacitor elements 131 and 132 in the circuit diagram of FIG. SEL, FDG, TGL, RST, FCG1 and FCG2 represent the common control signals to be applied to the MIM capacitor elements 131 and 132. Figure 4The driving signal is applied by the vertical driving unit 22 under the control of the control unit 26. When the driving signal reaches the H level, each transistor enters the on state, and when the driving signal reaches the L level, each transistor enters the off state.

[0042] exist Figure 6 In the embodiment, after the shutter (SHT) is released at time t0, the storage period starts. When the control signal VMID and the drive signals FDG, TGL, RST, FCG1, and FCG2 reach the H level before the storage period, the FD 162 and the MIM capacitive elements 131 and 132 are reset. When the drive signal FDG reaches the H level at time t1 after the storage period and then the drive signal SEL reaches the H level, the reset level (P-PD_L) of the low conversion efficiency of the photodiode 111 can be obtained. Then, when the drive signal FDG reaches the L level at time t2 in a state where the drive signal SEL continues to be the H level, the reset level (P-PD_H) of the high conversion efficiency of the photodiode 111 can be obtained.

[0043] Next, when the drive signal SEL reaches the L level and the drive signal TGL reaches the H level at time t3, a signal level (D-PD_H) of high conversion efficiency of the photodiode 111 can be obtained. In addition, when the drive signal FDG reaches the H level immediately before time t4 and the drive signal SEL reaches the L level and the drive signal TGL reaches the H level at time t4, a signal level (D-PD_L) of low conversion efficiency can be obtained. It should be noted that the drive signal FDG maintains the H level thereafter.

[0044] The signal level and reset level obtained as described above are output from the pixel 100 so that the column signal processing unit 23 can read out a signal obtained from the charge stored in the photodiode 111 by performing CDS (Correlated Double Sampling) based on these signal level and reset level (PD read (CDS)).

[0045] Subsequently, when the drive signal FCG1 reaches the H level at time t5, the signal level (D-MIM1) of the MIM capacitor element 131 can be obtained. The drive signal FCG1 maintains the H level at time t5 or thereafter. Next, when the drive signal SEL reaches the L level and the drive signal FCG2 reaches the H level at time t6, the signal level (D-MIM2) of the MIM capacitor element 132 can be obtained. The drive signal FCG2 maintains the H level between time t6 and time t8. Next, when the drive signal RST reaches the H level at time t7, the reset level (P-MIM2) of the MIM capacitor element 132 can be obtained. When the drive signal SEL reaches the L level and the drive signal FCG2 reaches the L level at time t8, the reset level (P-MIM1) of the MIM capacitor element 131 can be obtained.

[0046] The signal level and reset level obtained as described above are output from the pixel 100, so that by performing DDS (Double Data Sampling) based on these signal levels and reset levels, the column signal processing unit 23 can read out the signal obtained from the charges respectively stored in the MIM capacitor element 131 and the MIM capacitor element 132 (PD+MIM1+MIM2 read (DDS)). That is, the charges respectively stored in the photodiode 111, the MIM capacitor element 131, and the MIM capacitor element 132 can be read out separately.

[0047] Although the above configuration has been described as a TG type configuration, other configurations may be adopted. For example, an OFG (Over Flow Gate) type configuration may be adopted in which the overflow path from the photodiode 111 is another path different from the transfer gate. Figure 7 An OFG type configuration is shown as a second example of the circuit configuration of the pixel 100. In addition, Figure 8 is with Figure 7 The plan view corresponding to the circuit configuration in .

[0048] exist Figure 7 , the photodiode 111 is connected to the transfer transistor 161 and to the connection transistor 181 as an overflow gate. The connection transistor 181 is connected to the connection point of the first storage transistor 167, the second storage transistor 168 and the MIM capacitor element 131. The connection transistor 181 switches the connection state between the photodiode 111 and the MIM capacitor element 131 according to the drive signal OFG applied to the gate electrode of the connection transistor 181.

[0049] Therefore, the charge before the photodiode 111 is saturated is stored in the photodiode 111, and the charge when the photodiode 111 is oversaturated is stored in the MIM capacitor element 131 via the connection transistor 181. In addition, the charge when the photodiode 111 and the MIM capacitor element 131 are oversaturated can be stored in the MIM capacitor element 132 via the connection transistor 181 and the second storage transistor 168.

[0050] Both the TG type structure and the OFG type structure are structures that isolate the floating diffusions connected to the MIM capacitor element 131 and the MIM capacitor element 132 through the second storage transistor 168 and read out the charges stored in the respective floating diffusions. Compared with the OFG type structure, the TG type structure can be constructed by reducing the number of transistors. According to the OFG type structure, the area of ​​the floating diffusion when reading out the charges stored in the MIM capacitor element 131 and the MIM capacitor element 132 is separated from the area of ​​the floating diffusion when reading out the charges stored in the photodiode 111, so that the noise when the former reads out the charges can be reduced.

[0051] As described above, the solid-state imaging device 10 has a multi-stage structure (two-stage structure) in which each pixel 100 is arranged with the MIM capacitor element 131 and the MIM capacitor element 132 having different capacitances, the charge overflowing from the photodiode 111 is stored in the MIM capacitor element 131 and the MIM capacitor element 132, and the signal obtained from the charge stored in the photodiode 111, the MIM capacitor element 131, and the MIM capacitor element 132 is read out separately. It should be noted that the readout method only needs to read out the signal obtained from the charge stored in the photodiode 111, the MIM capacitor element 131, and the MIM capacitor element 132 separately, and is not limited to Figure 6 The operations shown can also be used with other readout methods.

[0052] By the way, according to the above-mentioned patent document 1, although the storage capacitor for storing the charge overflowing from the photodiode is arranged as a primary structure, in the case of the primary structure, increasing the capacitance within the pixel in order to expand the dynamic range will reduce the conversion efficiency, so the random noise deteriorates in proportion to the square root of the capacitance.

[0053] That is, the conversion efficiency (η) of a pixel is proportional to the FD capacitance according to η[V / e-]=q[C] / C fd [F] is determined and decreases as the capacitance increases. On the other hand, in the case of the primary structure, the random noise component is read out by DDS, so the circuit noise, kTC noise and AMP noise dominate. Here, when the circuit noise is σ AFE , kTC noise is σ KTC , AMP noise is σ AMPIn the case of total is the sum of the squares of the individual noises. To convert the noise component into electron counts, the noise component is divided by the conversion efficiency, so σ total / η[e-rms] holds true. KTC It is inversely proportional to √2kT / C and capacitance, and when converted to the number of electrons, its degree of degradation depends on the square root of the capacitance. Therefore, it is necessary to limit the capacitance within the pixel so that the SN ratio reaches a certain reference value or more, and it is difficult to strike a balance between the capacitance within the pixel and the dynamic range.

[0054] In addition, according to the above-mentioned patent document 2, although the storage capacitor storing the charge overflowing from the photodiode is arranged as a two-stage structure to achieve a wider dynamic range while maintaining the SN ratio, in this structure, there is no wiring capacitance element (MIM capacitance element) arranged as a storage capacitor. Therefore, the two storage capacitors are arranged on the same plane as the photodiode, so that the area of ​​the photodiode (the area of ​​the plane on the light incident surface side) is limited. In addition, the photodiode and the two storage capacitors are arranged on the same plane, so it is not suitable for miniaturization of pixels.

[0055] In contrast, the solid-state imaging device 10 to which the present disclosure is applied has the following structure: the two-stage MIM capacitor elements are constructed as storage capacitors for storing charges overflowing from the photodiode 111, so that by sequentially reading out the signals obtained from the charges stored in the photodiode 111, the MIM capacitor element 131, and the MIM capacitor element 132, the conversion efficiency ratio can be suppressed to a level matching the capacitance ratio (approximately 1:30), and the dynamic range can be expanded without deteriorating the SN ratio of the MIM capacitor element.

[0056] In addition, MIM capacitor element 131 and MIM capacitor element 132 are wiring capacitor elements, and are arranged between wiring layers, so that MIM capacitor element 131 and MIM capacitor element 132 are not arranged on the same plane as photodiode 111, and the area of ​​photodiode 111 (the area of ​​the plane on the light incident surface side) is not limited. In addition, photodiode 111, MIM capacitor element 131 and MIM capacitor element 132 are not arranged on the same plane, so it is also conducive to the miniaturization of pixels. Although it is difficult to arrange the photodiode and the two storage capacitors on the same plane according to the pixel size, especially when the capacitance ratio of the storage capacitor of the two-stage structure is about 1:30, it is difficult to arrange the photodiode and the two storage capacitors on the same plane, but arranging MIM capacitor elements 131 and MIM capacitor elements 132 with different capacitances between wiring layers is conducive to miniaturization.

[0057] As described above, in the solid-state imaging device 10 to which the present disclosure is applied, the pixel 100 has the first structure ( Figure 2and other figures), the photodiode 111 and the MIM capacitor elements 131 and 132 are not arranged on the same plane, and it is possible to suppress the degradation of the SN ratio and expand the dynamic range. That is, it is possible to achieve desired characteristics with a more appropriate layout.

[0058] <Second Structure> Although the first structure ( Figure 2 and other drawings) are described as a configuration in which the MIM capacitor element 131 and the MIM capacitor element 132 are arranged between different wiring layers in the wiring layer 12, but a configuration in which the MIM capacitor element 131 and the MIM capacitor element 132 are arranged between the same wiring layers may also be adopted. Fig. 9 is a cross-sectional view showing a second example of the structure of a pixel. Fig. 9 In the wiring layer 12, the MIM capacitor element 131 and the MIM capacitor element 132 are arranged at the same position in the Z direction and arranged between the same wiring layers. That is, in the wiring layer 12, the MIM capacitor element 131 and the MIM capacitor element 132 are both arranged between the first wiring layers.

[0059] exist Fig. 9 In the embodiment, the MIM capacitor element 131 and the MIM capacitor element 132 have Figure 3 The structure shown in FIG. 1 is different in film type, thickness, etc. of dielectric 143, and thus in capacitance. Fig. 9 , the capacitance ratio of the capacitance of the MIM capacitance element 131 and the capacitance of the MIM capacitance element 132 is also a desired capacitance ratio.

[0060] The second configuration can adopt a TG type or OFG type configuration similar to the above-mentioned first configuration as its circuit configuration. In addition, in the second configuration, the configuration and operation of the readout unit for separately reading out the charges stored in the photodiode 111, the MIM capacitor element 131 and the MIM capacitor element 132 are the same as those of the above-mentioned first configuration. The description of these configurations and operations is repeated, so it will be omitted.

[0061] <Third Structure> Although in the first construction ( Figure 2 and other figures) and the second configuration ( Fig. 9 ), the inter-pixel isolation portion 112 is formed as a groove formed from the surface on the side opposite to the light incident surface, but a structure in which the inter-pixel isolation portion 112 is formed as a groove formed from the light incident surface side may also be adopted. Fig.10 is a cross-sectional view showing a third example of the structure of a pixel. Fig.10 In the embodiment, the pixel isolation portion 113 is formed by burying a metal film, an insulating film, or the like in a groove formed at a predetermined depth from the light incident surface side in a semiconductor substrate.

[0062] exist Fig.10 In the embodiment, the MIM capacitor element 131 and the MIM capacitor element 132 are arranged between different wiring layers in the wiring layer 12, but may be arranged between the same wiring layers. The MIM capacitor element 131 and the MIM capacitor element 132 have different capacitances to achieve a desired capacitance ratio.

[0063] The third configuration can adopt a TG type or OFG type configuration similar to the above-mentioned first configuration as its circuit configuration. In addition, in the third configuration, the configuration and operation of the readout unit for separately reading out the charges stored in the photodiode 111, the MIM capacitor element 131 and the MIM capacitor element 132 are also the same as the configuration and operation of the above-mentioned first configuration. The description of these configurations and operations is repeated, so it will be omitted.

[0064] <Fourth Structure> Although the first construction ( Figure 4 ) is a TG type circuit structure in which a common control power supply (VMID) is connected to the upper electrode of the MIM capacitor element 131 and the upper electrode of the MIM capacitor element 132 to share the control signal (VMID signal), but the MIM capacitor element 131 and the MIM capacitor element 132 can also be controlled individually. Fig.11 It is shown Figure 4 FIG. 1 is another example of a TG type circuit configuration. Fig.11 In the embodiment, the upper electrode of the MIM capacitor element 131 is connected to the control power supply VMID1, and the upper electrode of the MIM capacitor element 132 is connected to the control power supply VMID2.

[0065] Fig.11 The circuit configuration in can independently control the control signal VMID1 of the MIM capacitor element 131 and the control signal VMID2 of the MIM capacitor element 132, and individually adjust the amount of charge (amount of electrons) stored in the MIM capacitor element 131 and the MIM capacitor element 132, respectively. In addition, when the voltage of the control signal VMID is increased during the storage period, the saturation charge of the MIM capacitor element increases and the dark current decreases, so that the SN ratio and the dynamic range are balanced. Therefore, in Fig.11 In the circuit configuration of FIG. 1 , the MIM capacitor element 131 and the MIM capacitor element 132 are independently controlled by using the control signal VMID1 and the control signal VMID2 , and optimal voltage control is achieved. This makes it easy to achieve both the SN ratio and the dynamic range of the MIM capacitor element.

[0066] Fig.12 It is used to illustrate Fig.11 A timing diagram showing an example of a read operation of the circuit configuration in FIG. Figure 6 Compared with the timing diagram in Fig.12 In the timing diagram in FIG. 1 , the common control signal VMID of the MIM capacitor elements 131 and 132 becomes the control signal VMID1 of the MIM capacitor element 131 and the control signal VMID2 of the MIM capacitor element 132. Therefore, the MIM capacitor element 131 and the MIM capacitor element 132 are controlled separately. Fig.12 The timing of the driving signal (e.g., SEL) in Figure 6 The timing in is similar, so its description will be omitted.

[0067] It should be noted that although Fig.11 An example of a TG type circuit configuration is shown, but an OFG type circuit configuration can also adopt the same configuration. Fig.13 It is shown Figure 7 FIG. 1 is another example of an OFG type circuit configuration shown in FIG. Fig.11 ,exist Fig.13 In the embodiment, the upper electrode of the MIM capacitor element 131 is connected to the control power supply VMID1, and the upper electrode of the MIM capacitor element 132 is connected to the control power supply VMID2, so the MIM capacitor element 131 and the MIM capacitor element 132 can be controlled separately.

[0068] <Fifth Structure> Fig.14 is a cross-sectional view showing another example of the structure of the pixel 100 . Fig.14 The cross-sectional view corresponds to Fig.15 X-X' section in the plan view.

[0069] Each pixel 100 is formed by stacking a semiconductor layer 11 and a wiring layer 12. In the semiconductor layer 11, a photodiode 211-1 and a photodiode 211-2 are formed for each pixel 100. Fig.15 As shown in the plan view of FIG. 1 , in the area of ​​the plane in the X and Y directions (the plane on the light incident surface side), the L-shaped area is the area of ​​the photodiode 211-1, and the remaining rectangular area is the area of ​​the photodiode 211-2. As described above, the area of ​​the light receiving surface of the photodiode 211-1 is larger than the area of ​​the light receiving surface of the photodiode 211-2, and the photodiode 211-1 has high sensitivity to light. That is, the pixel 100 is provided with two photodiodes having different sensitivities.

[0070] The light incident surface side of the photodiode 211-1 and the photodiode 211-2 is provided with a color filter 201 and an on-chip microlens 202. Fig.15As shown in the plan view, three on-chip microlenses 202-1-1 to 202-1-3 are provided to correspond to the L-shaped area of ​​the photodiode 211-1, and one on-chip microlens 202-2 is provided to correspond to the rectangular area of ​​the photodiode 211-2. The shape and number of on-chip microlenses 202 arranged in each pixel 100 are arbitrary, for example, the diameters of the on-chip microlenses 202-1-1 and 202-1-3 can be made larger than the diameters of the on-chip microlenses 202-1-2 and 202-2.

[0071] For example, the color filter 201 is configured as a filter that allows the same color wavelength to be transmitted for each pixel 100. Each pixel 100 is isolated by an inter-pixel isolation section 212. In addition, in each pixel 100, the photodiode 211-1 and the photodiode 211-2 are also isolated by the inter-pixel isolation section 212.

[0072] The wiring layer 12 is a multilayer wiring layer including a plurality of wiring layers obtained by stacking in a plurality of stages and forming wiring 222 in each stage with a wiring interlayer film 221 interposed between each stage. In the wiring layer 12, the MIM capacitor element 231 and the MIM capacitor element 232 are arranged as wiring capacitor elements having different capacitances. Each pixel 100 is provided with the MIM capacitor element 231 and the MIM capacitor element 232. The MIM capacitor element 231 and the MIM capacitor element 232 are arranged between different wiring layers. The MIM capacitor element 231 and the MIM capacitor element 232 may have the same capacitance as the wiring layer 12. Figure 3 That is, the MIM capacitor element 231 and the MIM capacitor element 232 may have a structure in which at least one of the film type, thickness and area of ​​the dielectric is different. For example, the capacitance of the MIM capacitor element 232 is greater than the capacitance of the MIM capacitor element 231.

[0073] The MIM capacitor element 231 stores the charge overflowing from the photodiode 211-1. The MIM capacitor element 232 stores the charge overflowing from the photodiode 211-2. This structure enables the charge overflowing from the photodiodes 211-1 and 211-2 to be stored in the MIM capacitor element 231 and the MIM capacitor element 232 together with the charge stored in the photodiodes 211-1 and 212-2, and the charge to be read out.

[0074] Fig.16 It is shown Fig.14 FIG. 1 is a diagram showing an example of a circuit configuration of a pixel 100 in FIG. Fig.16, the pixel 100 includes photodiodes 211 - 1 and 211 - 2 , MIM capacitors 231 and 232 , a transfer transistor 261 , an FD 262 , a switch transistor 263 , a reset transistor 264 , an amplifier transistor 265 , a selection transistor 266 , a switch transistor 267 , a storage transistor 268 , and an FD 269 .

[0075] The transfer transistor 261 is provided between the photodiode 211-1 and the FD 262, and transfers the charge stored in the photodiode 211-1 to the FD 262 according to the drive signal TGL applied to the gate voltage of the transfer transistor 261. The FD 262 is a floating diffusion that converts the charge from the photodiode 211-1 into a voltage signal. The FD 262 is connected to the vertical signal line 42 via the amplification transistor 265 and the selection transistor 266.

[0076] FD 262 is connected to a switching transistor 263 for switching conversion efficiency, and is connected to a switching transistor 267 and a storage transistor 268 via the switching transistor 263. The switching transistor 267 is connected to the MIM capacitor element 231 and the reset transistor 264. The region including the connection point of the photodiode 211-2, the MIM capacitor element 232, and the storage transistor 268 is FD 269. FD 269 is a floating diffusion portion that converts the charge from the photodiode 211-2 into a voltage signal. The upper electrode of the MIM capacitor element 231 and the upper electrode of the MIM capacitor element 232 are connected to a control power supply (VMID).

[0077] The switch transistor 263 switches the connection state between the FD262, the switch transistor 267, and the storage transistor 268 according to the drive signal FDG applied to the gate voltage of the switch transistor 263. The switch transistor 267 switches the connection state between the switch transistor 263, the MIM capacitor element 231, and the reset transistor 264 according to the drive signal LCG applied to the gate voltage of the switch transistor 267. The storage transistor 268 switches the connection state between the switch transistor 263 and the FD 269 according to the drive signal FCG applied to the gate electrode of the storage transistor 268.

[0078] For example, in the storage period, the charge before the photodiode 211-1 is saturated is stored in the photodiode 211-1, and the charge when the photodiode 211-1 is oversaturated can be stored in the MIM capacitor element 231 via the transfer transistor 261, the switch transistor 263, and the switch transistor 267. In addition, the charge of the photodiode 211-2 can be stored in the MIM capacitor element 232.

[0079] Next, we will refer to Fig.17 The timing diagram in Fig.16 An example of a readout operation of pixel 100 in FIG. Fig.17 In the VMID Fig.16 SEL, FDG, TGL, RST, LCG, and FCG represent common control signals to be applied to the MIM capacitor elements 231 and 232 in the circuit diagram. Fig.16 The driving signal of the gate electrode of each transistor in the circuit diagram.

[0080] exist Fig.17 In the embodiment, the storage period starts after the shutter (SHT) is released at time t0. When the control signal VMID and the drive signals FDG, TGL, RST, LCG, and FCG reach the H level before the storage period, the FDs 262 and 269 and the MIM capacitive elements 231 and 232 are reset. When the drive signal FDG reaches the H level at time t1 after the storage period and then the drive signal SEL reaches the H level, the reset level (P-SP1_M) of the intermediate conversion efficiency of the photodiode 211-1 can be obtained. Then, when the drive signal FDG reaches the L level at time t2 in a state where the drive signal SEL continues to be the H level, the reset level (P-SP1_H) of the high conversion efficiency of the photodiode 211-1 can be obtained.

[0081] Next, when the drive signal SEL reaches the L level and the drive signal TGL reaches the H level at time t3, a signal level (D-SP1_H) of high conversion efficiency of the photodiode 211-1 can be obtained. In addition, when the drive signal FDG reaches the H level immediately before time t4 and the drive signal SEL reaches the L level and the drive signal TGL reaches the H level at time t4, a signal level (D-SP1_M) of intermediate conversion efficiency can be obtained. It should be noted that the drive signal FDG maintains the H level thereafter.

[0082] The signal level and reset level obtained as described above are output from the pixel 100 , so that by performing CDS based on these signal level and reset level, a signal obtained from the charge stored in the photodiode 211 - 1 can be read out (PD Read (CDS)).

[0083] Subsequently, when the drive signal LCG reaches the H level immediately before time t5, the signal level (D-SP1_L) of the low conversion efficiency of the photodiode 211-1 can be obtained. The drive signal LCG maintains the H level until the time immediately before time t7. Next, when the drive signal SEL reaches the L level and the drive signal RST reaches the H level at time t6, the reset level (P-SP1_L) of the low conversion efficiency of the photodiode 211-1 can be obtained. The signal level and reset level obtained as described above are output from the pixel 100, so that by performing DDS based on these signal levels and reset levels, the charge stored in the MIM capacitor element 231 and the charge stored in the photodiode 211-1 can be read out (PD+MIM1 read (DDS)).

[0084] Subsequently, when the drive signal FCG reaches the H level at time t7, the signal level (D-SP2) of the photodiode 211-2 can be obtained. The drive signal FCG maintains the H level thereafter. Next, when the drive signal SEL reaches the L level and the drive signal RST reaches the H level at time t8, the reset level (P-SP2) of the photodiode 211-2 can be obtained. The signal level and reset level obtained as described above are output from the pixel 100, so that by performing DDS based on these signal levels and reset levels, the charge stored in the MIM capacitor element 232 and the charge stored in the photodiode 211-2 can be read out (PD+MIM2 reads (DDS)). As described above, the charges stored in the photodiode 211-1, the photodiode 211-2, the MIM capacitor element 231 and the MIM capacitor element 232 can be read out separately.

[0085] It should be noted that although Fig.14 The cross-sectional view of FIG. 2 shows a case where the MIM capacitor element 231 and the MIM capacitor element 232 are arranged between different wiring layers, but the MIM capacitor element 231 and the MIM capacitor element 232 may be arranged between the same wiring layers. Fig.14 Although the inter-pixel isolation portion 212 is formed as a groove penetrating the surface on the side opposite to the light incident surface in the cross-sectional view of FIG. 1 , a configuration in which the inter-pixel isolation portion 212 is formed as a groove formed at a predetermined depth from the light incident surface side may be adopted.

[0086] As described above, the solid-state imaging device 10 has the following structure (so-called multi-stage structure): Each pixel 100 is provided with photodiodes 211-1 and 211-2 having different sensitivities and MIM capacitor elements 231 and 232 having different capacitances. The charge overflowing from the photodiode 211-1 is stored in the MIM capacitor element 231, the charge overflowing from the photodiode 211-2 is stored in the MIM capacitor element 232, and the charges stored in the photodiode 211-1, the photodiode 211-2, the MIM capacitor element 231, and the MIM capacitor element 232 are read out respectively.

[0087] Here, the MIM capacitor element 231 is connected to the FD 262 of the photodiode 211-1, and the MIM capacitor element 232 is connected to the FD 269 of the photodiode 211-2. It should be noted that the readout method only needs to separately read out the signals obtained from the charges stored in the photodiode 211-1, the photodiode 211-2, the MIM capacitor element 231, and the MIM capacitor element 232, and is not limited to Fig.17 the operations shown, and other readout methods can be used.

[0088] As described above, in the solid-state imaging device 10 to which the present disclosure is applied, the pixel 100 has a fifth structure ( Fig.14 and other drawings), such that the photodiodes 211-1 and 211-2 and the MIM capacitor elements 231 and 232 are not arranged on the same plane, and the dynamic range can be expanded according to the sensitivity ratio of the photodiodes 211-1 and 211-2 having different sensitivities and the MIM capacitor elements 231 and 232 having different capacitances. That is, the desired characteristics can be achieved with a more appropriate layout.

[0089] <Modification Example> <Other Structures of MIM Capacitor Elements> Although in the above description, the three-dimensional structure has been described as the structure of the MIM capacitor elements 131 and 132, other structures can also be adopted. Fig.18 is a cross-sectional view showing another example of the structure of the MIM capacitor element 131. In Fig.18 it, the MIM capacitor element 131 has a two-dimensional structure in the X and Y directions.

[0090] The MIM capacitor element 131 has a structure formed by stacking an upper electrode 151, a lower electrode 152, and a dielectric 153 sandwiched between the upper electrode 151 and the lower electrode 152, wherein the upper electrode 151 is formed by a single-layer film or a laminated film using a material such as titanium nitride (TiN), and the lower electrode 152 is formed by a single-layer film or a laminated film using a material such as titanium nitride (TiN). The dielectric 153 is formed by a single-layer film or a laminated film of a high dielectric material such as aluminum oxide (AlO). A cap film 154 formed by a film such as silicon nitride (SiN) is formed on the upper surface of the upper electrode 151. The upper electrode 151 is connected to the wiring 122C via the contact 123B. The lower electrode 152 is connected to the wiring 122D.

[0091] The MIM capacitor element 132 may have Fig.18 The structure of the MIM capacitor element 131 shown in FIG. 1 is similar to that of the MIM capacitor element 131. At least one of the film type, thickness, and area of ​​the dielectric 153 is different, so that the MIM capacitor element 131 and the MIM capacitor element 132 have different capacitances. The thickness of the dielectric 153 is Fig.18 The area of ​​the dielectric 153 is the area of ​​the plane in the X and Y directions. Fig.14 The MIM capacitor elements 231 and 232 in the drawings and other figures are not limited to three-dimensional structures and may also have Fig.18 The two-dimensional structure shown. It should be noted that the number of MIM capacitor elements arranged in each pixel 100 is not limited to two, and can be three or more. In addition, in the fifth configuration, the number of photodiodes 211 formed in each pixel 100 is not limited to two, and can be three or more, and the MIM capacitor elements can be arranged according to the number of photodiodes 211.

[0092] <Example of light detection device> In the above description, the solid-state imaging device 10 is described as a CMOS type solid-state imaging device, and the CMOS type solid-state imaging device may have a back-illuminated structure in which light is incident from an upper layer (back side) located on the side opposite to the wiring layer side (front side) formed in the lower layer when viewed from a semiconductor substrate in which the photodiode 111 as a photoelectric conversion unit is formed. It should be noted that the CMOS type solid-state imaging device may have a front-illuminated structure in which the side on which light is incident is the wiring layer side (front side).

[0093] The solid-state imaging device 10 is an example of a light detection device to which the present disclosure is applied. That is, the light detection device to which the present disclosure is applied is not limited to the solid-state imaging device 10, and can be applied to a device that detects light such as a distance measurement sensor using an IR laser, for example. It should be noted that the configuration to which the present disclosure is applied is not limited to a CMOS type solid-state imaging device, and can also be applied to other solid-state imaging devices such as a CCD (Charge Coupled Device) type.

[0094] <Structure of electronic equipment> The solid-state imaging device to which the present disclosure is applied can be installed in electronic devices such as smartphones, tablet terminals, mobile phones, digital cameras, and digital video cameras. Fig.19 : is a block diagram showing a configuration example of an electronic device including a built-in solid-state imaging device to which the present disclosure is applied.

[0095] exist Fig.19 In the embodiment, the electronic device 1000 includes an imaging system, which includes an optical system 1011 including a lens group, Figure 1 The electronic device 1000 includes a solid-state imaging device 1012 having functions corresponding to the solid-state imaging device 10 in the image sensor 1000 and a DSP (Digital Signal Processor) 1013 as a camera signal processing unit. In addition to the imaging system, a CPU (Central Processing Unit) 1010, a frame memory 1014, a display 1015, an operating system 1016, an auxiliary memory 1017, a communication I / F 1018, and a power supply system 1019 are connected to each other via a bus 1020.

[0096] The CPU 1010 controls the operation of each unit of the electronic device 1000. The optical system 1011 acquires incident light (image light) from a subject and forms an image on a light detection surface of the solid-state imaging device 1012. The solid-state imaging device 1012 converts the light amount of the incident light that forms an image on the light detection surface by the optical system 1011 into an electrical signal in units of pixels, and outputs the electrical signal as a signal. The DSP 1013 performs predetermined signal processing on the signal output from the solid-state imaging device 1012.

[0097] The frame memory 1014 temporarily records the image data of the still image or video taken by the imaging system. The display 1015 is a liquid crystal display or an organic EL display, and displays the still image or video taken by the imaging system. The operating system 1016 issues operation commands for various functions of the electronic device 1000 in response to user operations.

[0098] The auxiliary memory 1017 is a storage medium including a semiconductor memory such as a flash memory, and records image data of a still image or a video captured by the imaging system. The communication I / F 1018 has a communication module supporting a predetermined communication method, and transmits image data of a still image or a video captured by the imaging system to other devices via a network.

[0099] The power supply system 1019 appropriately supplies various power sources as operating power sources to the CPU 1010 , the DSP 1013 , the frame memory 1014 , the display 1015 , the operating system 1016 , the auxiliary memory 1017 , and the communication I / F 1018 as power supply targets.

[0100] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications may be made without departing from the essential spirit of the present disclosure. In addition, the effects described in this specification are merely exemplary and non-restrictive, and other effects may be obtained.

[0101] The present disclosure may also adopt the following configurations.

[0102] (1) A solid-state imaging device comprising: a plurality of pixels, each of the pixels having a photoelectric conversion element and a plurality of wiring capacitance elements; and a readout unit that reads out signals from a plurality of said pixels, The solid-state image pickup device has a structure in which the charge overflowing from the photoelectric conversion element is stored in a first wiring capacitance element and the charge overflowing from the first wiring capacitance element is stored in a second wiring capacitance element, and The readout unit individually reads out a signal of each of the photoelectric conversion element, the first wiring capacitance element, and the second wiring capacitance element. (2) The solid-state image pickup device according to (1) above, wherein the first wiring capacitance element and the second wiring capacitance element are arranged between different wiring layers. (3) The solid-state imaging device according to (1) above, wherein the first wiring capacitance element and the second wiring capacitance element are a first MIM capacitance element and a second MIM capacitance element having different capacitances. (4) The solid-state imaging device according to (3) above, wherein the first MIM capacitive element and the second MIM capacitive element have a structure in which at least one of a film type, a thickness, and an area of ​​a dielectric is different. (5) The solid-state imaging device according to (3) or (4) above, wherein the first MIM capacitive element and the second MIM capacitive element have a three-dimensional structure. (6) A solid-state imaging device according to any one of (1) to (4), wherein the solid-state imaging device has the following structure: the charge overflowing from the photoelectric conversion element overflows to the first wiring capacitance element from an overflow path different from a path of a transfer gate that transfers the charge stored in the photoelectric conversion element. (7) A solid-state imaging device comprising: a plurality of pixels, each of the pixels having a plurality of photoelectric conversion elements and a plurality of wiring capacitance elements; and a readout unit that reads out signals from a plurality of said pixels, The solid-state image pickup device has a structure in which a first wiring capacitance element and a second wiring capacitance element are connected to floating diffusions of a first photoelectric conversion element and a second photoelectric conversion element, respectively, and charges overflowing from the first photoelectric conversion element are stored in the first wiring capacitance element, charges overflowing from the second photoelectric conversion element are stored in the second wiring capacitance element, and The readout unit individually reads out a signal of each of the first photoelectric conversion element, the second photoelectric conversion element, the first wiring capacitance element, and the second wiring capacitance element. (8) The solid-state image pickup device according to (7) above, wherein the first wiring capacitance element and the second wiring capacitance element are arranged between different wiring layers. (9) The solid-state imaging device according to (7) above, wherein the first wiring capacitance element and the second wiring capacitance element are a first MIM capacitance element and a second MIM capacitance element having different capacitances. (10) The solid-state imaging device according to (9) above, wherein the first MIM capacitance element and the second MIM capacitance element have a structure in which at least one of a film type, a thickness, and an area of ​​a dielectric is different. (11) The solid-state imaging device according to (9) or (10) above, wherein the first MIM capacitive element and the second MIM capacitive element have a three-dimensional structure. (12) The solid-state imaging device according to any one of (7) to (10), wherein the first photoelectric conversion element and the second photoelectric conversion element have different sensitivities.

[0103] Reference numerals list 10 Solid-state imaging device 21 Pixel Array Unit 22 vertical drive units 23 columns signal processing circuit 24 Horizontal drive units 25 Output Units 26 Control Unit 42 vertical signal lines 100 pixels 101 Color Filters 102 On-chip microlenses 111 Photodiode 112, 113 Pixel isolation part 121 Wiring interlayer film 122 Wiring 131 MIM capacitor element 132 MIM capacitor elements 141 Upper electrode 142 Lower electrode 143 Dielectric 144 Covering film 161 Pass transistor 162 FD 163 Switching transistor 164 Reset transistor 165 Amplifier transistor 166 Select transistor 167 First storage transistor 168 Second storage transistor 181 Connecting the Transistor 201 Color Filter 202 On-chip microlenses 211-1, 211-2 Photodiode 212 Pixel isolation part 221 Wiring interlayer film 222 Wiring 231 MIM capacitor element 232 MIM capacitor element 261 Pass transistor 262, 269 FD 263 Switching transistor 264 Reset transistor 265 Amplifier Transistor 266 Select transistor 267 Switching transistor 268 Storage transistor 1000 Electronic equipment

Claims

1. A solid-state imaging device, comprising: a plurality of pixels, each of the pixels having a photoelectric conversion element and a plurality of wiring capacitance elements; as well as a readout unit that reads out signals from a plurality of said pixels, wherein the solid-state imaging device has a structure in which the charge overflowing from the photoelectric conversion element is stored in a first wiring capacitance element and the charge overflowing from the first wiring capacitance element is stored in a second wiring capacitance element, and The readout unit individually reads out a signal of each of the photoelectric conversion element, the first wiring capacitance element, and the second wiring capacitance element.

2. The solid-state imaging device according to claim 1, wherein The first wiring capacitance element and the second wiring capacitance element are arranged between different wiring layers.

3. The solid-state imaging device according to claim 1, wherein The first wiring capacitance element and the second wiring capacitance element are a first MIM capacitance element and a second MIM capacitance element having different capacitances.

4. The solid-state imaging device according to claim 3, wherein: The first MIM capacitive element and the second MIM capacitive element have a structure in which at least one of a film type, a thickness, and an area of ​​a dielectric is different.

5. The solid-state imaging device according to claim 4, wherein: The first MIM capacitive element and the second MIM capacitive element have a three-dimensional structure.

6. The solid-state imaging device according to claim 5, wherein: The solid-state imaging device has a structure in which the charge overflowing from the photoelectric conversion element overflows to the first wiring capacitance element from an overflow path different from a path of a transfer gate that transfers the charge stored in the photoelectric conversion element.

7. A solid-state imaging device, comprising: a plurality of pixels, each of the pixels having a plurality of photoelectric conversion elements and a plurality of wiring capacitance elements; as well as a readout unit that reads out signals from a plurality of said pixels, The solid-state imaging device has a structure in which a first wiring capacitance element and a second wiring capacitance element are connected to floating diffusions of a first photoelectric conversion element and a second photoelectric conversion element, respectively, and charges overflowing from the first photoelectric conversion element are stored in the first wiring capacitance element, and charges overflowing from the second photoelectric conversion element are stored in the second wiring capacitance element, and The readout unit individually reads out a signal of each of the first photoelectric conversion element, the second photoelectric conversion element, the first wiring capacitance element, and the second wiring capacitance element.

8. The solid-state imaging device according to claim 7, wherein: The first wiring capacitance element and the second wiring capacitance element are arranged between different wiring layers.

9. The solid-state imaging device according to claim 7, wherein: The first wiring capacitance element and the second wiring capacitance element are a first MIM capacitance element and a second MIM capacitance element having different capacitances.

10. The solid-state imaging device according to claim 9, wherein: The first MIM capacitive element and the second MIM capacitive element have a structure in which at least one of a film type, a thickness, and an area of ​​a dielectric is different.

11. The solid-state imaging device according to claim 10, wherein: The first MIM capacitive element and the second MIM capacitive element have a three-dimensional structure.

12. The solid-state imaging device according to claim 7, wherein: The first photoelectric conversion element and the second photoelectric conversion element have different sensitivities.

Images