A fourier transform infrared spectroscopy measurement system and method

Abstract

A Fourier transform infrared spectrum measurement system and method, the system comprises a sampling device, a field programmable gate array (FPGA) and a host computer; the host computer is used for receiving a sampling rate parameter input by a user and sending the sampling rate parameter to the FPGA; the FPGA is used for calculating a clock frequency according to the sampling rate parameter, setting the clock frequency and generating a clock signal to send to the sampling device; the sampling device is used for collecting interferogram data according to the clock signal and sending the interferogram data to the FPGA after processing; the FPGA is further used for forwarding the interferogram data to the host computer; and the host computer is further used for completing spectrum measurement according to the interferogram data. Through the scheme, a spectrum measurement system with adjustable sampling rate, spectrum band and resolution is realized, the processing speed is fast, the control of the sampling rate is more accurate, and the system is easy to integrate and has lower cost.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of spectral measurement technology, and in particular to a Fourier transform infrared spectroscopy measurement system and method. Background Art

[0002] Fourier transform spectrometer (FTS) is a major spectroscopic technique in recent decades. Its core technology is to use Fourier transform to extract spectral data from the interferogram (interferometer output).

[0003] The most fundamental principle of the Fourier transform spectrometer is dual-beam interference. Since people began studying Fourier transform spectrometers, various new and extended structures have been built. For example, the interference pattern acquisition device built based on the Michelson interferometer structure uses a beam splitter to split a beam of light emitted by a radiation source into two paths. After passing through different optical paths, the two beams are then coupled together using a coupler. Because the two beams of light have the same source and the optical path lengths of the two optical paths are similar, they meet the coherence conditions of light: the same frequency, the same vibration direction, and a constant phase difference. Therefore, the recoupled light is coherent light. In addition, the front-end interference pattern acquisition device of the Fourier transform spectrometer can also include Mach-Zehnder interferometers and Fabry-Perot interferometers.

[0004] The interferogram acquisition system is the core component of the Fourier transform spectrometer. Its performance and quality directly affect the spectrometer's output. However, existing interferogram acquisition systems have various problems (such as clock stability and synchronization issues). Therefore, we need to implement a better interferogram acquisition system to achieve spectral measurement. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The present disclosure provides a Fourier transform infrared spectroscopy measurement system and method, which solves the clock stability and synchronization problems faced in spectral measurement. The solution has a fast processing speed and more accurate sampling rate control.

[0007] An embodiment of the present disclosure provides a Fourier transform infrared spectroscopy measurement system, which includes a sampling device, a field programmable gate array (FPGA), and a host computer; the host computer is used to receive a sampling rate parameter input by a user and send the sampling rate parameter to the FPGA; the FPGA is used to calculate a clock frequency based on the sampling rate parameter, set the clock frequency, and generate a clock signal to send to the sampling device; the sampling device is used to collect interference pattern data based on the clock signal, and send the processed interference pattern data to the FPGA; the FPGA is also used to forward the interference pattern data to the host computer; and the host computer is also used to complete spectral measurement based on the interference pattern data.

[0008] An embodiment of the present disclosure also provides a Fourier transform infrared spectrum measurement method, which uses the spectrum measurement system described in any embodiment of the present disclosure. The method includes: a host computer receives a sampling rate parameter input by a user and sends the sampling rate parameter to a field programmable gate array (FPGA); the FPGA calculates a clock frequency based on the sampling rate parameter, sets the clock frequency, and generates a clock signal and sends it to the sampling device; the sampling device collects interference pattern data based on the clock signal, processes the interference pattern data, and sends it to the FPGA; the FPGA forwards the interference pattern data to the host computer; and the host computer completes the spectrum measurement based on the interference pattern data.

[0009] Compared to related technologies, the disclosed embodiments provide a Fourier transform infrared spectroscopy measurement system and method. In this system, a clock frequency is calculated and set within an FPGA based on a user-entered sampling rate parameter. This allows the sampling device to sample according to the clock signal generated by the FPGA, achieving sampling rate control. After sampling, the collected interferogram data is sent to a host computer for the host computer to complete the spectral measurement. On the one hand, this solution is entirely controlled by the FPGA, whose time base is the same crystal oscillator. Data from different clock domains is processed across clock domains within the FPGA, eliminating the issue of signal asynchrony. On the other hand, due to the more precise internal time accuracy of the FPGA, the sampling rate control of this solution is also more accurate. Furthermore, due to the FPGA's parallel processing capabilities, the processing speed is faster.

[0010] Other features and advantages of the embodiments of the present application will be described in the following description, and in part will become apparent from the description or be understood by practicing the embodiments of the present application. The objectives and other advantages of the embodiments of the present application can be achieved and obtained through the structures particularly pointed out in the description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0012] Figure 1 Schematic diagram of a Fourier transform infrared spectroscopy measurement system according to an embodiment of the present disclosure;

[0013] Figure 2 A schematic diagram of the command interaction for configuring an optical fiber adjustable delay line device on an FPGA according to an embodiment of the present disclosure;

[0014] Figure 3 This is a schematic diagram of the acquisition part of the spectrum measurement system according to an embodiment of the present disclosure connected to a spectrometer;

[0015] Figure 4a-4f Interference spectrum diagram when the adjustable delay line according to one embodiment of the present disclosure is connected to different optical fiber lengths;

[0016] Figure 5 A schematic diagram of the structure of a Mach-Zehnder interferometer constructed for an embodiment of the present disclosure;

[0017] Figure 6 A schematic diagram of the overall network communication framework of a spectrum measurement system according to an embodiment of the present disclosure;

[0018] Figure 7 This is a graph showing the light responsivity of the photodetector ET-3010 at different wavelengths according to an embodiment of the present disclosure;

[0019] Figure 8a This is a frequency division simulation timing diagram when the sampling frequency is 50KHz according to an embodiment of the present disclosure;

[0020] Figure 8b This is a frequency division simulation timing diagram of an embodiment of the present disclosure when the sampling frequency is 100KHz;

[0021] Figure 9 This is the host computer software interface for measuring with a 1550nm laser as the light source in one embodiment of the present disclosure, including the collected interference pattern and the restored spectrum.

[0022] Figure 10 This is a Fourier transform restored spectrum diagram when measuring with a 1550nm laser as the light source according to one embodiment of the present disclosure;

[0023] Figure 11 This is a flow chart of a Fourier transform infrared spectroscopy measurement method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0025] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0026] The present disclosure provides a Fourier transform infrared spectroscopy measurement system. Figure 1 As shown, the system may include a sampling device, a field programmable gate array FPGA and a host computer;

[0027] The host computer is used to receive a sampling rate parameter input by a user and send the sampling rate parameter to the FPGA;

[0028] The FPGA is used to calculate the clock frequency according to the sampling rate parameter, set the clock frequency, and generate a clock signal to send to the sampling device;

[0029] The sampling device is used to collect interference pattern data according to the clock signal, and send the interference pattern data to the FPGA after processing;

[0030] The FPGA is further configured to forward the interference pattern data to the host computer;

[0031] The host computer is further used to complete spectrum measurement according to the interference pattern data.

[0032] The Fourier transform infrared spectrum measurement system of the embodiment calculates and sets the clock frequency according to the sampling rate parameter input by the user in the FPGA, so that the sampling device can sample according to the clock signal generated by the FPGA to realize the control of the sampling rate; and after sampling, the collected interferogram data is sent to the host computer for the host computer to complete the spectrum measurement. On the one hand, the control of the system is completed by the FPGA, and the time reference is the same crystal oscillator, and the FPGA internally performs cross-clock domain processing on the data of different clock domains, so that the system will not have the problem of asynchronous signals; on the other hand, the time precision of the FPGA is more accurate, so the sampling rate control of the system is also more accurate; in addition, the FPGA has the ability of parallel processing, so the processing speed is faster. In summary, the embodiment uses the FPGA to realize a spectrum measurement system with adjustable sampling rate, which has fast processing speed and more accurate sampling rate control.

[0033] It should be noted that the host computer includes application software, and the system realizes interaction with the user through the application software. For example, the application software can be built based on the Matlab (Matrix Laboratory, a mathematical calculation software) platform, or can be built based on the Qt (Q Toolkit, a cross-platform C++ development library), and no limitation is made in this regard.

[0034] In an example embodiment of the present disclosure, the system further comprises a photoelectric detection device; the photoelectric detection device is configured to receive an interference light signal and perform photoelectric signal conversion on the interference light signal to generate an electrical signal; for example, the electrical signal refers to a current intensity signal that changes over time;

[0035] The sampling device collects interferogram data according to the clock signal and sends the interferogram data to the FPGA, including: at the rising edge or falling edge of the clock signal, collecting the electrical signal and performing analog-to-digital conversion on the collected electrical signal to generate a digital signal and send it to the FPGA;

[0036] The FPGA forwards the interferogram data to the host computer, including: forwarding the digital signal to the host computer;

[0037] The host computer completes spectrum measurement according to the interferogram data, including: completing spectrum measurement according to the digital signal.

[0038] For example, the photoelectric detection device can be a photodetector, and the sampling device can be an analog-to-digital converter (ADC).

[0039] The Fourier transform infrared spectroscopy measurement system of this embodiment converts the interference light signal into an electrical signal through a photoelectric detection device. The electrical signal is then subjected to analog-to-digital conversion (sampling, quantization, and encoding) by a sampling device according to a clock signal. The generated digital signal is input into the FPGA and then forwarded to the host computer, thereby extracting spectral information from the interference light signal and ultimately achieving spectral measurement.

[0040] In an exemplary embodiment of the present disclosure, the system further includes a light source generator, an optical fiber adjustable delay line device (Optic Delay Line, ODL) and an optical coupler (Optic Coupler, OC), wherein the optical coupler includes a beam splitting optical coupler (also called a beam splitting OC) and a coupling optical coupler (also called a coupling OC); a first optical path and a second optical path are provided between the beam splitting optical coupler and the coupling optical coupler;

[0041] The host computer is further configured to receive configuration parameters of the optical fiber adjustable delay line device input by a user and send the configuration parameters to the FPGA;

[0042] The FPGA is further configured to receive configuration parameters of the optical fiber adjustable delay line device; and generate a first instruction according to the configuration parameters of the optical fiber adjustable delay line device, and forward the first instruction to the optical fiber adjustable delay line device;

[0043] The optical fiber adjustable delay line device is used to receive the first instruction and move according to the first instruction, so that the phase difference between the second optical path and the first optical path changes, generate the interference light signal, and send it to the photoelectric detection device.

[0044] For example, the FPGA can control the operation of the optical fiber adjustable delay line to generate the optical path difference through a UART (Universal Asynchronous Receiver / Transmitter) interface.

[0045] Exemplarily, the optical fiber adjustable delay line may be an electrically driven optical fiber adjustable delay line.

[0046] The spectral measurement system of this embodiment uses an FPGA to forward a first instruction generated by the user's input of the optical fiber variable delay line device configuration parameters to the optical fiber variable delay line device. This instruction controls the operation of the optical fiber variable delay line device to generate an interference light signal, ultimately achieving flexible and controllable data acquisition. This solution uses FPGA control of the adjustable delay line device, rather than direct computer control, resulting in faster processing speed and higher accuracy.

[0047] In addition, since the specific functions of the FPGA can be implemented by coding, the spectrum measurement system of this embodiment also has the advantage of being reconfigurable.

[0048] Compared with the interference pattern acquisition system built with a traditional optical structure, the system of this embodiment uses an all-fiber structure to build the acquisition system, which is easier to integrate and has lower costs.

[0049] In an example of this embodiment, the input end of the beam splitting optical coupler is connected to the output end of the light source generator;

[0050] The optical fiber adjustable delay line device is provided on the second optical path, with its input end connected to the output end of the beam splitting optical coupler, and its output end connected to the input end of the coupling optical coupler;

[0051] The output end of the coupling optical coupler is connected to the input end of the photoelectric detection device;

[0052] The control end of the optical fiber adjustable delay line device is connected to the FPGA via a serial port.

[0053] In one example of this embodiment, the configuration parameters of the optical fiber adjustable delay line device include a device start scanning point, an end scanning point, a scanning speed of the optical fiber adjustable delay line device, and a system unit of the optical fiber adjustable delay line device. The scanning speed refers to the speed at which the mechanical components within the optical fiber adjustable delay line device move. By setting the scanning speed of the optical fiber adjustable delay line device, the speed of change / adjustment of the delay time can be adjusted.

[0054] The Fourier transform infrared spectroscopy measurement system in this example can use the FPGA to send instructions from the host computer to the fiber-optic variable delay line device based on the user-configured scanning start and end points and scanning movement speed. This can control the operation of the fiber-optic variable delay line device and realize the acquisition of interference patterns within a certain optical path difference.

[0055] Compared to traditional Fourier transform spectrometers, where the mirror's movement speed and distance are controlled by pre-set mechanical devices and cannot be changed, the spectral measurement system in this example uses an FPGA to control the adjustable delay line device. This allows for control of the speed and range of the optical fiber adjustable delay line during scanning (by setting the start and end points of the scan), enabling faster and more efficient spectral measurements (for example, shortening the sampling time of the interferogram to improve spectral measurement efficiency, optimizing spectral measurement resolution, and reducing measurement errors).

[0056] In an example of this embodiment, the FPGA and the optical fiber adjustable delay line device communicate based on a serial port transmission protocol and interact based on a response mode.

[0057] Exemplarily, the FPGA and the fiber-optic adjustable delay line device interact based on a response mode. Specifically, the FPGA sends a command that meets the requirements to the fiber-optic adjustable delay line device. If the fiber-optic adjustable delay line device correctly responds, it returns an "OK" response to the FPGA. If it fails to recognize the command or is unable to respond, it returns a "NO" response. Controlling the fiber-optic adjustable delay line device to scan via the FPGA requires sending multiple commands to the fiber-optic adjustable delay line device. This repetitive interaction is implemented using a state machine.

[0058] Exemplarily, the movement of the optical fiber adjustable delay line device is to move back and forth from the starting scanning point x1 to the ending scanning point x2 at a movement speed s until a stop command is received. Among them, s, x1, and x2 can be configured by the host computer software, and their default initial values ​​are 256ps / s, 170ps, and 180ps, respectively. The FPGA is initially in an idle state. When the flag signal for starting to configure the optical fiber adjustable delay line device is valid, the FPGA enters a state of interacting with the optical fiber adjustable delay line device. The instruction interaction diagram for FPGA configuration of the optical fiber adjustable delay line device can be referred to Figure 2 (“ps” is the system unit of the optical fiber tunable delay line device, "," " etc. represent different instruction identifiers). For example, the process of setting the delay unit of the optical fiber adjustable delay line device can be as follows: FPGA first sends a PSU instruction to the optical fiber adjustable delay line device in the format of " ", sets the delay unit of the optical fiber adjustable delay line device to "ps". After sending the PSU command, the FPGA immediately enters the state of receiving the PSU command response. If the optical fiber adjustable delay line device correctly receives the PSU command, it will change the system unit to "ps" and reply to the FPGA with an "OK". After receiving "OK", the FPGA enters the state of waiting to send the next command. If the command is correct, but the set value exceeds the device's allowable range, the device will not execute the command operation and reply "NO". If there is a problem with the communication line, no response will be received or garbled information will be received. If no "OK" response is received, the FPGA will remain in the state of receiving responses. In this case, the FPGA development board should be reset and initialized, and the optical fiber adjustable delay line device should be configured again from the idle state. After the FPGA receives the response from the optical fiber adjustable delay line device, there will be a 1ms interval before sending the next command. This is to prevent the optical fiber adjustable delay line device from responding in a timely manner due to excessive operation, which may cause damage. The 1ms interval t is a global variable parameter and can be modified as needed.

[0059] In an exemplary embodiment of the present disclosure, the host computer can also be used to receive other acquisitions input by the user, such as the number of acquisitions, the type of light source, the spectral coordinates, etc., so as to realize the setting of different numbers of interference pattern acquisitions, the adjustment of the wavenumber range of the measurement spectrum, and the measurement of both single-wavelength light sources and multi-wavelength light sources and other functional settings.

[0060] The Fourier transform infrared spectrum measurement system of this embodiment can realize multiple acquisitions of interference patterns by setting the number of sampling times, thereby reducing noise.

[0061] In an exemplary embodiment of the present disclosure, the beam-splitting optical coupler may be an optical coupler with a splitting ratio of 5:5.

[0062] The Fourier transform infrared spectroscopy measurement system of this embodiment uses an optical coupler with a splitting ratio of 5:5 as the beam splitting optical coupler. This can ensure that the power and polarization state of the two beams reaching the coupled optical coupler are the same, thereby maximizing the interference contrast and facilitating spectral sampling.

[0063] In an exemplary embodiment of the present disclosure, the system further includes a polarization controller (PC); the polarization controller is provided on the first optical path and is used to change the polarization deviation of the optical signals on the first optical path and the second optical path.

[0064] The Fourier transform infrared spectroscopy measurement system of this embodiment, by providing a polarization controller on the first optical path, can, on the one hand, change the polarization deviation of the optical signals in the first optical path and the second optical path, thereby enhancing the interference effect; on the other hand, it can make the modulation depth sufficiently large (for example, greater than 10dB), thereby resolving the problem of excessive noise despite interference in direct measurement caused by fiber bending and connection losses.

[0065] In an exemplary embodiment of the present disclosure, the light source generator may be an ASE (Amplified Spontaneous Emission) broadband light source generator, and the wavelength range of the broadband light source generated by the ASE broadband light source generator may be 1520 nm to 1580 nm.

[0066] The spectrum measurement system in this example uses an ASE broadband light source generator as the light source generator to generate a broadband light source, so that the cosine interference spectrum can be seen in the spectrometer, making it easier to determine the lengths of the two arms and whether interference can occur.

[0067] It should be noted that the light source generator in the embodiment is not limited to the ASE wide spectrum light source generator, and can be any type of light source generator, and no limitation is made thereto, such as a single-wavelength 1550nm laser, a multimode 1310nm laser, and the like.

[0068] In an example embodiment of the present disclosure, the first light path can be provided with a delay optical fiber (also referred to as ODL-Delay); the length of the delay optical fiber is greater than the length of the cable in the optical fiber adjustable delay line device, and is less than the sum of the length of the cable in the optical fiber adjustable delay line device and the delay length supported by the optical fiber adjustable delay line device.

[0069] For example, since the lengths of the two optical fiber pigtails of the beam splitting OC output end are consistent, after the optical fiber adjustable delay line device ODL is added, a length of optical fiber ODL-Delay similar to the length of the optical fiber adjustable delay line device should be added. Assuming that the total length of the optical fiber adjustable delay line device pigtails is L, and the maximum light path length that can be filled by the optical fiber adjustable delay line device is Lmax, then the length range of the ODL is Lmax-L l s , the maximum light path length that can be filled by the optical fiber adjustable delay line device is Lmax x , and the length range of the ODL is Lmax-L l s +x In order to have the maximum intensity interference phenomenon, that is, the zero point of the interference pattern can be collected subsequently, the length of the ODL-Delay must satisfy Lmax-L l d l s <l d <l s +x In actual operation, the length of the ODL pigtail is more than two meters, a single-mode optical fiber with a length close to two meters is taken, and an optical fiber head is fused to each end of the optical fiber. The length of the ODL-Delay after the optical fiber head is fused is compared with the length of the ODL. In the best case, the length of the ODL-Delay is obviously 1-3 cm longer than the length of the ODL pigtail. The length of the ODL-Delay must not be shorter than the length of the ODL pigtail, otherwise interference cannot be generated.

[0070] As shown in Figure 3 , the interference spectrum can be observed by an optical spectrum analyzer (OSA) connected to the output end of the coupling optical coupler. For example, the output power of the ASE wide spectrum light source can be set to 10.23 mW. At the beginning, the adjustable delay line device does not add a delay, so the optical path difference of the fiber Mach-Zehnder interferometer built is too large, which is not sufficient to generate an interference phenomenon, and therefore the interference spectrum cannot be seen on the optical spectrum analyzer, as shown in Figure 4a ​The spectrum shown at this time is the spectrum of the ASE light source. The tunable delay line device is then set to different time delays, and when the time delay is in the range of 160-190 ps, obvious interference can be generated. When the parameter is set to 164 ps, the interference spectrum observed on the optical spectrum analyzer is as shown in Figure 4b When the parameters are set to 170 ps, 174 ps, 178 ps and 184 ps, the interference spectra are as shown in Figure 4c , Figure 4d , Figure 4e , Figure 4f It can be seen that when the time delay of the fiber tunable delay line device is changed from 160 ps to 190 ps, the optical path difference of the two arms of the fiber Mach-Zehnder interferometer gradually decreases and then gradually increases, and passes through a point of zero optical path difference. As can be seen from the interference spectrum, this zero point is about 174 ps. It can also be seen that as the optical path difference decreases, the number of wave peaks in the interference spectrum decreases. When the optical path difference is zero, theoretically, there is no phase difference between the two light signals, and no interference occurs. At this time, the spectrum observed in the optical spectrum analyzer is consistent with the spectrum of the light source, as shown in Figure 4d and Figure 4a According to the calculation, the modulation depth of the Mach-Zehnder interferometer structure of the system is about 13 dB. At this time, the light signal output by the coupling OC is connected to the photodetector and then connected to the oscilloscope, and the frequency and amplitude of the electrical signal output by the photodetection device are analyzed.

[0071] In an example embodiment of the present disclosure, the system can further include an oscilloscope connected to the photodetector.

[0072] The spectrum measurement system of the present embodiment can analyze the frequency and amplitude of the electrical signal output by the photodetection device by connecting the oscilloscope.

[0073] For example, the light signal output by the coupling optical coupler is connected to the photodetector and then connected to the oscilloscope, and the tunable delay line device is set to reciprocate between 160 ps and 190 ps. As the optical path difference changes, interference wave packets can be observed on the oscilloscope interface. The smaller the interval of the tunable delay line, the more wave packets can be observed. Moreover, when the electrical signal is in the order of mV, the electrical signal after photoelectric conversion can be amplified.

[0074] In an exemplary embodiment of the present disclosure, the peripheral interface of the FPGA development board can adopt a USB serial port, a Type-C serial port, or a GPIO interface, but the GPIO interface is preferred to improve program portability. The FPGA uses the GPIO interface to multiplex the serial port, sending and receiving instructions to configure and control the operation of the electric fiber-optic variable delay line device. The GPIO interface is soldered to the FPGA development board in the form of a row of pins. For example, two GPIO pins that do not function as power and ground can be selected as the transmit and receive data lines for serial communication.

[0075] It's important to note that when using the GPIO interface to connect the FPGA development board and the fiber-optic adjustable delay line, the GPIO pins' output voltages conform to the TTL level standard, with 3.6V to 5V interpreted as a logic 1 and 0V to 2.4V as a logic 0. The adjustable delay line's control interface uses the RS232 standard, with voltages between -3V and -15V interpreted as a logic 1 and between 3V and 15V as a logic 0. This suggests that directly connecting the GPIO pins to the adjustable delay line's serial interface can result in data reception errors. Therefore, a voltage converter can be added between the FPGA and the adjustable delay line to avoid data reception errors caused by a direct GPIO connection.

[0076] In an exemplary embodiment of the present disclosure, the system further comprises a flange; the flange is provided on the first optical path and / or the second optical path, and the power of the two beams of light reaching the coupling optical coupler can be adjusted by adjusting the tightness thereof.

[0077] Exemplarily, the number of flanges can be 4, and their positions can be set as follows: for example, the first flange is located on the first optical path, its input end is connected to the output end of the beam splitter coupler, and its output end is connected to the input end of the delay optical fiber; the second flange is located on the first optical path, its input end is connected to the output end of the polarization controller, and its output end is connected to the input end of the coupling optical coupler; the third flange is located on the second optical path, its input end is connected to the output end of the beam splitter coupler, and its output end is connected to the input end of the adjustable delay line device; the fourth flange is located on the second optical path, its input end is connected to the output end of the adjustable delay line device, and its output end is connected to the input end of the coupling optical coupler. It should be noted that this application does not limit the number of flanges, and the number of flanges can be set according to actual scenario requirements.

[0078] The spectrum measurement system of the embodiment can achieve similar power of the two beams of light reaching the coupling light coupler by adjusting the tightness of the flange, reduce the loss of the interference light signal, such as bending loss, fiber fusion loss, flange connection loss, equipment loss, etc.

[0079] In an example of the embodiment, as shown in Figure 5 The system can further include an adjustable attenuator to better make the power of the two beams of light before coupling consistent.

[0080] It should be noted that the spectrum measurement system of the embodiment can include an adjustable attenuator and a flange, the flange is used for fine adjustment, and the adjustable attenuator is used for more accurate adjustment, so as to improve the quality and accuracy of spectrum measurement. Of course, if the fine adjustment by the flange can meet the actual demand, the adjustable attenuator can not be arranged.

[0081] In an example of the embodiment, the host computer is further configured to receive a sampling number (or acquisition number) parameter input by a user and send the sampling number parameter to the FPGA.

[0082] The FPGA is further configured to receive the sampling number parameter and control the fiber adjustable delay line device to perform scanning motion for a corresponding number of times according to the sampling number parameter, so as to complete sampling for a corresponding number of times.

[0083] The spectrum measurement system of the embodiment can set the sampling number in the host computer, realize multiple acquisition of the interference pattern, make the spectrum smoother, and realize denoising.

[0084] In an example of the embodiment, the FPGA and the host computer communicate through a network port.

[0085] In summary, the embodiment builds a small, all-fiber structure, low-cost Fourier transform infrared spectrometer. The front end builds a fiber Mach-Zehnder interferometer to generate interference light. Based on the parameter configuration control of the electrically adjustable delay line device, the linear change of the optical path difference of the two arms is generated to generate an interference pattern. Based on the FPGA, an interference pattern sampling system is built. The interference pattern data is quantitatively collected by a sampling device (which can be an analog-to-digital converter). Based on the software (which can be software developed based on the Matlab platform) in the host computer, the collected interference pattern is displayed and restored, and a complete spectrum measurement system is realized.

[0086] The spectral measurement system of this embodiment uses an FPGA to transmit the collected interferogram data to a host computer, which has the following advantages: First, the FPGA has a variety of peripheral interfaces, such as serial ports and network ports, which facilitate instrument control and data transmission; second, the FPGA has parallel processing capabilities. After power-on, all logic gates calculate the corresponding output values ​​based on the input at each moment, allowing "multi-threaded" processing tasks; third, the internal structure of the FPGA makes it very suitable for high-speed signal processing. Processing software algorithms in the FPGA makes production processing faster.

[0087] The following is a detailed description of a spectrum measurement system provided by an embodiment of the present disclosure:

[0088] like Figure 1 As shown, the system may include: a light source generator, a beam splitting optical coupler, a coupling optical coupler, a fiber-optic adjustable delay line device, a polarization controller, a flange, a voltage converter, a photodetector, a sampling device (also referred to as an AD sampling module or AD in this embodiment), a field programmable gate array (FPGA), and a host computer. Furthermore, conventional modules such as amplification and filtering circuits and a power transformer may also be included. When implementing this system, it includes:

[0089] The first step is to implement remote configuration of the adjustable delay line based on the serial port:

[0090] (1) Physical configuration and connection, including:

[0091] For fiber-optic adjustable delay lines, General Photonics' Miniature Motorized Variable Optical Delay Line (MDL-002) is an option. The MDL-002 offers a precise continuous optical path delay range of 250ps to 1120ps. Existing motorized adjustable delay lines in laboratories offer a delay of 330ps, equivalent to 10cm in length. Its DC motor drive with integrated encoder offers an excellent delay resolution of 0.3µm, making it ideal for precise optical path length control or timing alignment. Delay resolution refers to the smallest unit of delay time that can be adjusted. Generally speaking, the higher the delay resolution, the wider the delay range of the fiber-optic adjustable delay line and the greater the adjustment accuracy.

[0092] The MDL-002 features remote operation. Based on a serial communication protocol, it can be remotely controlled by a computer via the built-in RS232 communication port. The functions corresponding to its different buttons can be configured using a fixed command format. Connect the adjustable delay line to a computer via an RS232 serial cable and test it by entering the provided command examples using the serial debugging software. If the command is correct, an "R" icon will appear in the upper left corner of the adjustable delay line display, indicating that it is in remote control mode and executing the corresponding command function. Therefore, a computer can configure the adjustable delay line based on a specific serial transmission protocol and a fixed command format. If an FPGA is to be used instead of a computer to achieve autonomous configuration of the adjustable delay line, the FPGA must have two functions: one is to implement the serial transmission protocol, and the other is to send specific commands according to a specific process.

[0093] The FPGA development board's peripheral interface can use a USB serial port, a Type-C serial port, or a GPIO interface, but the GPIO interface is preferred to improve program portability. The FPGA uses the GPIO interface to multiplex the serial port, sending and receiving commands to configure and control the operation of the electric optical variable delay line device. The GPIO interface is soldered to the FPGA development board in the form of a row of pins. For example, two GPIO pins that are not used for power and ground functions can be selected as the transmit and receive data lines for serial communication.

[0094] As for the voltage converter, you can use the RS232 to TTL converter model UT-210 from Yutai Hi-Tech. The pin assignments of its input and output interfaces are shown in Table 1 below:

[0095] Table 1 RS232-TTL converter pin assignment

[0096] DB9 Female(PIN) RS232C interface signal DB9 Male(PIN) TTL output signal 1 DCD 1 RXD 2 TXD 2 TXD 3 RXD 3 - 4 DTS 4 - 5 GND 5 GND

[0097] It should be noted that when using the voltage converter, the following points should be noted: first, the female head corresponds to the RS232 standard, and the male head corresponds to the TTL standard, so the female head is connected to the adjustable delay line, and the male head is connected to the GPIO pin of the FPGA; second, when the male head is connected to the FPGA pin, the RXD pin of the male head is connected to the TX pin of the FPGA, the TXD pin of the male head is connected to the RX pin of the FPGA, and the ground wire is connected; third, when the female head is connected to the adjustable delay line, do not directly insert the male head and the female head due to the adaptation of the male head and the female head, the pins of the male head and the female head should be connected, and the remote control interface of the adjustable delay line should be connected directly without crossing the line, that is, the TXD interface of the female head of the voltage converter should be connected to the TXD interface of the adjustable delay line, and the RXD interface should be connected to the RXD interface of the adjustable delay line in the same way, which is different from the general serial port connection method, and the ground wire is connected; fourth, the remote control interface of the adjustable delay line is the male head of the RS232 standard, but the pin definition corresponding to the DB9 male head of the voltage converter shown in Table 1 is different, the output signal corresponding to the PIN2 pin is RXD, and the output signal corresponding to the PIN3 pin is TXD, when connecting, the pin definition of the specific interface of the specific device should be connected according to the pin definition of the specific interface of the specific device, and the output signal of the pin should not be confused due to the same interface shape.

[0098] For the device, when using the serial port connection, the common ground wire should be connected to prevent damage to the device.

[0099] (2) Implement state transition mechanism, including:

[0100] The FPGA includes a top-level control module, a serial port transmission protocol and instruction construction module, a FIFO and a network port communication protocol module. Based on the above modules, the main functions of the FPGA are: communicating with the computer through the network port protocol, receiving the instructions configured by the user in the software interface of the host computer, the instructions containing the configuration information of the electrically adjustable delay line device, the configuration information being transmitted to the serial port transmission protocol and instruction construction module after being processed by the top-level control module, the FPGA sending the instructions to the electrically adjustable delay line through the serial port connection line for configuration, and the top-level control module collecting the ADC data of the effective adjustable delay line motion interval and storing it in the asynchronous FIFO, and then uploading it to the computer through the network port communication protocol module through the network cable.

[0101] In the serial port transmission protocol and instruction construction module, the function of the FPGA is to construct the corresponding instructions according to the parameter configuration sent by the host computer, and to configure the adjustable delay line device through the correct data interaction sequence, so that the adjustable delay line device works according to the parameters set by us.

[0102] Before implementing command interaction using the state transition mechanism, a serial communication protocol based on the FPGA was implemented. The serial communication rate of the adjustable delay line device was fixed at 9600 bps, and the serial communication rate in the program was also set to 9600 bps, with both communicating parties maintaining the same rate. In the serial communication protocol, data transmission and reception lines, as well as a common ground line, were set between the FPGA and the adjustable delay line device for data communication. Data was transmitted and received in a frame format. Each frame consisted of 10 bits, including a start bit, a stop bit, and 8 data bits. This meant that a single protocol frame could only transmit one byte of valid data, with each bit lasting for (clock frequency / 9600) clock cycles.

[0103] Within the FPGA, commands are sent to the adjustable delay line device via a serial transmission protocol to control its operation. The interaction between the FPGA and the adjustable delay line is a response mode. The FPGA sends a command that meets the requirements to the adjustable delay line. If the adjustable delay line responds correctly, the FPGA responds with an "OK" response. If it doesn't recognize the command or can't respond, it responds with a "NO" response. Controlling the adjustable delay line through the FPGA requires multiple commands to be sent to the adjustable delay line for scanning. This repetitive interaction is implemented using a state machine.

[0104] The ultimate goal of configuring the adjustable delay line movement on the FPGA is to collect interference patterns within a certain optical path difference. The MDL-002 provides a scanning function, which means that the adjustable delay line can move back and forth at a set speed within a certain delay range. Therefore, we need to send the scanning start point, scanning end point, and scanning speed s to the adjustable delay line device in the form of instructions. First, set the maximum movement speed to 256ps / s (MDL-002 provides 10 levels of speed, with the highest being 256ps / s) and the position of the initial point x1. The position of the initial point should be consistent with the position of the scanning starting point. Otherwise, during the scanning process, the device will first move to the position of the scanning starting point at the set scanning speed, which will affect the time we calculate to send the command to stop scanning. The reason for setting the speed of 256ps / s is that the adjustable delay line takes the least time to move from any position to the set initial point at the maximum movement speed, that is, t1 is the smallest. t1 represents the number of required clock cycles. Since the current delay value of the adjustable delay line is unknown, the delay distance of t1 is taken as its maximum delay range of 330ps. When the FPGA receives the " " command, it will move to the position x1 at a speed of 256ps / s. Therefore, the time interval from receiving the "OK" response to sending the next command must be greater than or equal to t1. The setting value of t1 in the FPGA code also needs to consider the clock cycle. As shown in the formula, the system clock frequency of the FPGA development board is 50MHz, and each cycle needs to add 20ns. Therefore, the setting value of t1 needs to be an integer multiple of 20, as shown in Formula 1.

[0105] Formula 1: ;

[0106] Among them, t1 represents the number of required clock cycles, Indicates the set value of t1.

[0107] When the initial point of the adjustable delay line is consistent with the scan start point to be set, the scanning speed s, the scan start point position x1, and the scan end point position x2 are set. These three values ​​are set based on the corresponding interference effect and the effect of the collected interference pattern to ensure that interference can be generated within this range and the interference zero point is passed. The command to start scanning is then sent. After receiving the "OK" response to the start command, the timing t2 begins. t2 represents the number of clock cycles required to scan from the start point to the end point. When the internal register counts to t2, the command to stop scanning is immediately sent. The calculation method of t2 is shown in the formula. The setting value of t2 is the same as t1, as shown in Formula 2. Writing code according to the above state transition mechanism can functionally enable the adjustable delay line device to scan according to the set parameters.

[0108] Formula 2: ;

[0109] Among them, t2 represents the number of clock cycles required to scan from the starting point to the end point. Indicates the set value of t2.

[0110] (3) Implement functional simulation and verification of the remote configuration of the adjustable delay line based on the serial port, including:

[0111] After completing the logical functions of an FPGA program, simulation software can be used to verify the functionality before proceeding to further testing. For example, Verilog pre-simulation is a simulator-based method for analyzing and checking designs before synthesis. Its purpose is to detect errors and potential problems in the design to ensure correct results in the actual project. This method can check for syntax errors, semantic errors, timing errors, and other issues, reducing debugging time and improving design quality before actual commissioning.

[0112] For example, you can use Modelsim software (a hardware description language simulation software) to simulate and write test files. The time unit and time accuracy in the time scale pre-compiled instructions are both 1ns. Write a 50MHz clock stimulus. To avoid the simulation time being too long, you can Figure 2 The time interval t is set to 1us, t1 is set to 2us, and t2 is calculated based on the device control parameters written in the test file. odl_start is set to 280ps and odl_end is set to 281ps, so t2 is equal to 195313. In Modelsim software, current_state is the state transition. Each number corresponds to a state. It is initially in state 0, that is, the idle state. After receiving the command to start configuring "key_begin", it enters state 1 and sends the command to configure the system unit " ", and then after receiving the response of "OK", it enters the counting state of the state interval t. When the count reaches 1us, it continues to send the next instruction, and so on. Figure 2 The adjustable delay line device is configured by interacting with the instructions shown in . The simulation results verify the correctness of the serial port transmission protocol and the timing of the state transition mechanism. After sending the "STOP" command and receiving the "OK" response, the device enters the completed state and then enters the idle state, awaiting the next configuration command. Because it is impossible to determine whether the adjustable delay line device begins scanning after sending the "OK" reply or after receiving the command, the valid signal period_flag for AD data acquisition is pulled high when the FPGA is about to receive the "OK" response state of the start scan command and is not pulled low until the setting is completed. Although this method collects redundant information, it ensures that all data during the adjustable delay line scan is collected for subsequent processing.

[0113] During the simulation process, if the adjustable delay line device does not respond after the FPGA sends a command, you can manually initialize the adjustable delay line device and then reset the state transfer machine by pulling up the initial_flag signal through the "Reset / Initialize" button on the host computer.

[0114] After the program function simulation is correct, to prevent device damage, first connect the FPGA and computer via a serial cable. The computer simulates the adjustable delay line device. Using the computer's serial debugging assistant software, manually reply "OK" after receiving instructions from the FPGA. This verifies the correctness of the serial communication protocol and the normal operation of the state machine. Then, change the connection method between the FPGA and the adjustable delay line back to the actual connection method. After the state machine starts, the "R" mark appears on the adjustable delay line display, and the scanning operation is carried out according to the parameters initialized within the program.

[0115] The simulation process verifies the correct remote configuration of the FPGA for the adjustable delay line device, ensuring the reliability of the system.

[0116] The second step is to implement a data transmission path based on the Ethernet protocol, including:

[0117] Regarding the FPGA, consider the Zynq 7020 Navigator from Zhengdian Atom. This development board features a dual-core ARM Cortex-A9 processor and an FPGA logic section. The FPGA logic section includes a Gigabit RJ45 Ethernet port and the YT8511 Ethernet physical layer chip, supporting 10M / 100M / 1000M communication rates. Because network communication between the development board and the computer doesn't involve upper-layer conversations or applications, only the physical, data link, and IP layers are required. Ethernet data communication involves data exchange according to the Ethernet protocol. Ethernet protocols construct data packets according to their corresponding data frame formats and transmit them according to the correct timing and logic. The network layer is responsible for routing and forwarding messages constructed by the transport layer. TCP and UDP are both transport layer protocols. TCP provides secure and reliable transmission through connection mechanisms, including sequence control and retransmission control. UDP is primarily used for communications requiring high-speed transmission and real-time performance. Because TCP's retransmission mechanism is complex and this system's LAN has relatively few devices, preventing network congestion, this project uses the UDP protocol for data transmission. The UDP protocol operates at the network layer. The prerequisite for inter-device communication using UDP is data link layer connectivity, which requires both devices to know each other's physical addresses. However, after the system is powered on, the development board and PC are unaware of each other's physical addresses. Therefore, before using UDP for communication, the Address Resolution Protocol (ARP) is required to dynamically convert IP addresses to physical addresses and obtain the MAC addresses of the communicating devices on the LAN.

[0118] In FPGA programming, the FPGA development board operates the adjustable delay line through a serial port. It also interacts with the host computer to obtain configuration parameters and transmit interferogram sampling data to the host for processing. In this system, Ethernet communication protocol can be used to communicate with the host computer.

[0119] The overall framework diagram of the network communication of this system can be shown as follows Figure 6 shown.

[0120] The data interface for communication between the MAC layer and the PHY chip is GMII, which has a total of seven data lines: gmii_rxc (receive data clock), gmii_rx_ctl (input data valid signal), gmii_rxd (input data), gmii_txc (send data clock), gmii_tx_ctl (output data valid signal), gmii_txd (output data), and gmii_rstn (PHY chip reset signal). Both the ARP module and the UDP module need to use the PHY chip to send and receive data, so the top layer of the two is an arbitration module to decide when to send which protocol message. The sampling device collects the interference pattern generated by the uniform transformation of the adjustable delay line in the Mach-Zehnder interferometer structure. It quantizes the analog signal on the rising edge of the clock. However, when the adjustable delay line is not operating, the data collected by the sampling device is meaningless. Therefore, the collected data is stored in the FIFO only during the time when the adjustable delay line is in motion. When a UDP message is sent, the data stored in the FIFO is uploaded to the computer as the payload of multiple UDP messages. The FIFO is asynchronous, with a write clock equal to the ADC sampling clock, a write bit width of 16 bits, and a depth of 512. The read clock is 125MHz, which is the Ethernet transmission clock, and a read bit width of 8 bits. Therefore, the asynchronous FIFO enables cross-clock domain processing of batch data.

[0121] ARP (Address Resolution Protocol) is a protocol used to obtain the MAC address of a target device. For example, an ARP request packet is broadcast within the local area network to obtain the target device's MAC address. When the target device receives the ARP request packet, it replies with an ARP response packet containing its own MAC address. This allows the sender to obtain the target device's MAC address, thus completing communication. For example, the total length of an ARP packet is 28 bytes, with the MAC address being 6 bytes and the IP address being 4 bytes. The hardware type field indicates the hardware interface type of both parties. The Ethernet value is 1, the protocol type is 0x0800, indicating an IP address, and the operation type field is 1 for the ARP request packet and 2 for the ARP response packet. Each field is correctly assigned a value within the FPGA, then the packet is assembled and transmitted according to the time sequence. Before obtaining the MAC address of the communicating device, the FPGA sends ARP request packets. After obtaining the MAC address, it stops sending ARP request packets. However, upon receiving an ARP request packet from the network, it reports its MAC address to the other device by sending an ARP response packet. After the ARP protocol interaction, data can be transmitted through the UDP protocol if the IP addresses and MAC addresses of both communicating parties are known.

[0122] For example, in the system of this embodiment, the data flow is as follows: for example, the FPGA's IP address is set to 192.168.0.2, and the host's IP address is set to 192.168.0.3. The FPGA locally knows the host's IP address but not its MAC address. Therefore, upon powering on, the FPGA first sends an ARP request broadcast message with its own MAC address. Upon receiving this, the host replies with an ARP response message, successfully acquiring the host's MAC address. Subsequently, the FPGA receives the adjustable delay line configuration instruction sent by the host via a UDP message. It decodes this instruction to obtain specific data parameters, and then configures the adjustable delay line device based on these parameters. During the adjustable delay line scan, the AD data collected by the FPGA is stored in an asynchronous FIFO. When the FIFO is full, it is sent to the host in the data portion of a UDP message, thereby achieving interferogram data acquisition.

[0123] Similarly, after completing this step, the Ethernet communication protocol module can be simulated and verified using a simulator to verify the correct functionality of the entire project. To shorten simulation time, the serial communication clock was changed from 50 MHz to 1 MHz, the sampling clock was set to 50 kHz, and the ODL was scanned from 179 ps to 180 ps at a rate of 256 ps / s.

[0124] When the FPGA begins operation, the des_mac signal is all zeros. At this point, it actively sends an ARP request message. Upon receiving the ARP response, des_mac parses the response message to obtain the corresponding destination MAC address. The simulation file does not construct a UDP message for the adjustable delay line device parameters, so the adjustable delay line operates according to the default parameters. After the FPGA parses the data portion of the UDP message and obtains the "begin to sample" field, the state transition mechanism controlling the remote operation of the adjustable delay line device begins. While the period_flag is high, the FPGA uploads the data collected by the AD via UDP messages. This data is buffered in an asynchronous FIFO. Next, we verify data continuity. The data collected by the AD is the sequence number constructed in the simulation file, which continuously changes from 0 to 4095. The last data in the UDP message data portion is 1254, and the first data in the next UDP message data portion is 1255. This indicates that although the data is uploaded to the host in segments, no data is lost.

[0125] After the simulation verification proves the function of the program design, the on-board verification is carried out, the test platform is built, the data collected by the AD end is replaced by the sequence data generated by the FPGA internally, and the sequence data is uploaded during the operation of the adjustable delay line. The PC end reads the received data by software, so that the process of message interaction and whether there is data omission can be seen more clearly.

[0126] It can be seen that the actual message interaction from the power-on of the development board to the data upload is complete. During the operation of the adjustable delay line, the data stored in the FIFO is uploaded to the host as the payload of the UDP message every 1024 bytes, and finally the remaining data less than 1024 bytes in the FIFO is uploaded through a UDP message. The sequence number is written in the FIFO, and each data occupies 2 bytes. It can be seen from the expanded UDP message that the payload part is the sequence number generated by the FPGA, and there is no misplacement and no data loss. In summary, the function of uploading the data collected by the sampling device to the PC through the Ethernet communication protocol has been realized.

[0127] The third step is to realize the sampling of the interferogram data, including:

[0128] Regarding the light source generator, it can be a photodetector. The photodetector can be an ET-3010 InGaAs photodetector produced by the EOT company in the United States, which includes a PIN photodiode that converts optical power into current using the Photovoltaic Effect, with a measurement bandwidth greater than 2GHz. The light response of ET-3010 at different wavelengths is shown in Figure 7 As shown, the Responsivity (R) is one of the physical quantities used to measure the detection efficiency of the photodetector, and its calculation method is the ratio of photocurrent to incident light power. For example, when using an ASE broadband light source (wavelength range of 1520nm to 1580nm) to generate interference light, the light response of ET-3010 at different wavelengths is shown in Figure 7 It can be seen that the Responsivity of ET-3010 is the largest and the photodetection efficiency is the best at 1500nm to 1600nm, which meets the system light signal detection requirements.

[0129] Regarding the beam splitting optical coupler and the coupling optical coupler, two 1x2 optical couplers can be selected.

[0130] Regarding the sampling device, an analog-to-digital converter can be used to implement it. When choosing an AD chip model, three factors need to be considered: the range of the measurable electrical signal, the sampling conversion rate of the AD chip, and the quantization accuracy of the AD chip. For example, the analog-to-digital converter can use the AD9220 chip produced by ADI, which has a quantization accuracy of 12 bits and a sampling conversion rate of 10MSPS (Million Samples Per Second), taking advantage of the high performance and low power consumption of the AD9220 chip. The AD9220 chip supports an input analog voltage range of 0V to 2V. 0V corresponds to an output digital signal of 0, and 2V corresponds to an output digital signal of 4096. The sampling device is the AD9220 chip plus an external circuit. The allowable input voltage range is -5V~5V. The external circuit can convert the voltage between -5V~5V into the range of 0V~2V. Therefore, when calculating the actual voltage value based on the quantized value, -5V can correspond to 0 and 5V can correspond to 4096. If a certain analog voltage value V a quantified as V d ,but V a and V d The conversion relationship between them is:

[0131] , V a Represents the analog voltage value, V d Represents quantified V a ;

[0132] The AD9220 operates under a clock-driven power supply, controlling all internal conversion cycles. The AD9220 features an on-chip sample-and-hold amplifier and a multi-stage differential pipeline architecture, ensuring a 10MSPS data conversion rate with no missing codes across the entire temperature range. The AD9220 outputs data in binary format. When the input analog voltage exceeds the measurement range, the OTR (out-of-range) signal is pulled high. Conversely, when the input analog voltage is within the measurement range, the OTR signal is low. Therefore, the OTR signal can be used to determine whether the input analog voltage is within the measurement range.

[0133] The sampling clock is generated by the FPGA and provided to the sampling device. The sampling clock frequency is the sampling frequency during Fourier transform. If the sampling frequency is too high, the amount of data will be too large. For example, if the system clock of the FPGA module is 50MHz, if the maximum sampling rate supported by the sampling device is used for sampling, 32*10^6 data will be collected within 1 second. The quantization accuracy of the sampling device is 12bit, so sampling for 1 second will generate 48MB of data, which will put a certain pressure on the processing of the host computer. If the sampling frequency is too low, the waveform of the collected signal cannot be fully restored. Combined with the theoretical analysis of the interference pattern sampling law, the minimum sampling interval should be less than 0.3497um. The sampling interval in the actual system is The calculation method can be as follows:

[0134] ;

[0135] in, represents the sampling interval, Indicates the operating speed of the adjustable delay line device, Indicates the sampling frequency of the sampling device. It should be noted that The unit can be cm; when When the unit is cm, The unit is ps / s, and 10cm=330ps, so the formula needs to be divided by 33 to convert the units. The unit is cm.

[0136] The sampling interval depends on the scanning speed of the adjustable delay line device and the sampling frequency of the AD sampling module. Assuming that the scanning speed of the adjustable delay line device is set to 32ps / s, when the sampling frequency is 50KHz, the sampling interval is 0.1939um, which can detect the spectral wavenumber of the near-infrared band; assuming that the scanning speed of the adjustable delay line device is set to 4ps and the sampling frequency is 10KHz, the calculated sampling interval value is 0.1212um, which can still detect the spectrum of the near-infrared band. Therefore, the spectrum of different wavenumber ranges can be detected by balancing the two values ​​of the scanning speed of the adjustable delay line and the sampling rate of the analog-to-digital converter.

[0137] The host computer software program of the Fourier transform infrared spectroscopy measurement system of this embodiment can modify the sampling frequency. Therefore, the sampling frequency of the analog-to-digital converter is set as a global parameter. The code is written to implement it by using the principle of counting and dividing. The original clock frequency sys_clk is 50MHz. If the frequency of the ad_clk clock generated after the frequency division is set to 50KHz, the original clock needs to be flipped every time the counter div_clk_count counts to sys_clk / (2 * ad_clk) - 1 = 499. Figure 8aIt can be seen that the interval between the first marking line and the second marking line is 20us, that is, the period of ad_clk generated by frequency division is 20us, and the corresponding frequency is 50KHz; if the sampling clock frequency is set to 100KHz, then div_clk_count will flip every time it counts to 249, and Figure 8b As shown, it is verified that the program can realize the correctness of signal output and frequency division of any frequency, and realize the function of frequency division.

[0138] The spectrum measurement system of this embodiment is used for testing, and the spectrum of light sources in different infrared bands can be measured. Figure 9 This is the host computer software interface when the spectrum measurement system of this embodiment uses a single wavelength 1550nm laser as the light source for measurement, as shown in the following figure: Figure 9 As shown, the spectrum measurement system can be used to measure the wave number of a single wavelength 1550nm laser at 6453cm -1 This verifies that the spectrum measurement system supports the measurement of infrared waves with a wavelength of 1550nm. In addition, the spectrum measurement system disclosed in the present invention can support spectrum measurement of light sources in different infrared bands, which are not listed here one by one.

[0139] In addition, if Figure 10 As shown in the figure, this spectrum measurement system uses a 1550nm laser as the light source, sets the sampling frequency to 50KHz, sets the scanning speed of the adjustable delay line device to 4ps / s, sets the starting scanning point to 170ps, and sets the ending scanning point to 180ps. The amount of interferogram data collected is 250MB. After processing by the host computer software, the resolution of the measured spectrum is 5cm -1 The spectral resolution of this spectral measurement system can be reduced by increasing the scanning interval. The smaller the spectral resolution, the better the performance of the spectral instrument.

[0140] In summary, the spectrum measurement system of this embodiment can set the sampling times and sampling rate in the host computer to realize multiple acquisitions of interference patterns, thereby reducing noise; by adjusting the starting and ending scanning points of the optical fiber adjustable delay line device, the maximum optical path difference can be changed to obtain spectrum graphs with different spectral resolutions; by adjusting the scanning speed of the optical fiber adjustable delay line device and the sampling rate of the analog-to-digital converter, spectrum graphs of different bands can be measured.

[0141] The embodiment of the present disclosure provides a spectrum measurement method, which uses the Fourier transform infrared spectrum measurement system as described in any embodiment of the present disclosure, such as Figure 11 As shown, the method may include:

[0142] Step S111: The host computer receives the sampling rate parameter input by the user and sends the sampling rate parameter to the field programmable gate array FPGA;

[0143] Step S112: The FPGA calculates the clock frequency according to the sampling rate parameter, sets the clock frequency, and generates a clock signal and sends it to the sampling device;

[0144] Step S113: The sampling device collects interferogram data according to the clock signal, and after processing the interferogram data, sends it to the FPGA;

[0145] Step S114: The FPGA forwards the interferogram data to the host computer;

[0146] Step S115: The host computer completes the spectral measurement according to the interferogram data.

[0147] The Fourier transform infrared spectroscopy measurement system and method provided by the embodiments of the present disclosure solve the following problems existing in the existing interferogram collection system:

[0148] Clock stability and synchronization problem: In FTS, a precise clock is needed to synchronize the collection of interferograms. Any synchronization error or clock instability can cause distortion of the interferogram;

[0149] Electronic noise and environmental noise: Noise from the electronic part of the system or external environmental noise (such as electromagnetic interference) can mix into the interferogram, causing data distortion;

[0150] Temperature sensitivity: The various parts of the interferogram collection system, especially the optical part, can be sensitive to temperature changes. This can cause the interferogram to shift or change shape;

[0151] Quality and alignment of optical components: High-quality optical components and precise alignment are essential for obtaining high-quality interferograms. Any defects or alignment errors can cause distortion of the interferogram.

[0152] The optical fiber Mach-Zehnder interferometer structure built by the system has the following advantages compared with the interferometer of optical path structure:

[0153] Size and integration: Optical fiber Mach-Zehnder structure is usually more compact than optical path structure, because they do not need external optical elements and free-space optical path, and optical fiber system is also easier to integrate with other optical fiber systems;

[0154] Stability: Free-space optical path structure is easily affected by external environment, such as temperature, humidity, vibration, etc., while optical fiber structure is usually more stable and robust;

[0155] Alignment and maintenance: Free-space optical system needs precise alignment, which can lose alignment due to time, vibration or other external factors, and once correctly installed and aligned, optical fiber system usually requires less maintenance;

[0156] Flexibility: In some applications, such as when light needs to be transmitted from one point to another, optical fiber structures have obvious advantages due to their lightness and flexibility;

[0157] Environmental interference: Free-space optical systems are more susceptible to interference from air flow, dust, and other environmental factors, while optical fiber structures are less susceptible to the above interference;

[0158] Cost: Because free-space optical Mach-Zehnder interferometers require more external optical components and precise alignment, their manufacturing and maintenance costs may be higher than fiber-optic structures with the same function.

[0159] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the methods, systems, and devices disclosed above may be implemented as software, firmware, hardware, or any combination thereof. In hardware implementations, the division between functional modules / units described above does not necessarily correspond to the division between physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term "computer storage media" encompasses volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A Fourier transform infrared spectroscopy measurement system, characterized in that: The system includes a sampling device, a field programmable gate array FPGA and a host computer; The host computer is used to receive a sampling rate parameter input by a user and send the sampling rate parameter to the FPGA; The FPGA is used to calculate the clock frequency according to the sampling rate parameter, set the clock frequency, and generate a clock signal to send to the sampling device; The sampling device is used to collect interference pattern data according to the clock signal, and send the interference pattern data to the FPGA after processing; The FPGA is further configured to forward the interference pattern data to the host computer; The host computer is further used to complete spectrum measurement according to the interference pattern data.

2. The system according to claim 1, wherein: The system further includes a photoelectric detection device, which is configured to receive an interference light signal and convert the interference light signal into a photoelectric signal to generate an electrical signal. The sampling device collects interference pattern data according to the clock signal and sends the interference pattern data to the FPGA, including: collecting the electrical signal at the rising edge or the falling edge of the clock signal, performing analog-to-digital conversion on the collected electrical signal, generating a digital signal and sending it to the FPGA; The FPGA forwards the interference pattern data to the host computer, including: forwarding the digital signal to the host computer; The host computer completes spectrum measurement according to the interference pattern data, including: completing spectrum measurement according to the digital signal.

3. The system according to claim 2, characterized in that The system further includes a light source generator, an optical fiber adjustable delay line device, and an optical coupler, wherein the optical coupler includes a beam splitting optical coupler and a coupling optical coupler; a first optical path and a second optical path are provided between the beam splitting optical coupler and the coupling optical coupler; The host computer is further configured to receive configuration parameters of the optical fiber adjustable delay line device input by a user and send the configuration parameters to the FPGA; The FPGA is further configured to receive configuration parameters of the optical fiber adjustable delay line device; and generate a first instruction according to the configuration parameters of the optical fiber adjustable delay line device, and forward the first instruction to the optical fiber adjustable delay line device; The optical fiber adjustable delay line device is used to receive the first instruction and move according to the first instruction, so that the phase difference between the second optical path and the first optical path changes, generate the interference light signal, and send it to the photoelectric detection device.

4. The system according to claim 3, wherein: The input end of the beam splitting optical coupler is connected to the output end of the light source generator; The optical fiber adjustable delay line device is provided on the second optical path, with its input end connected to the output end of the beam splitting optical coupler, and its output end connected to the input end of the coupling optical coupler; The output end of the coupling optical coupler is connected to the input end of the photoelectric detection device; The control end of the optical fiber adjustable delay line device is connected to the FPGA via a serial port.

5. The system according to claim 3, wherein: The configuration parameters of the optical fiber adjustable delay line device include the starting scanning point of the optical fiber adjustable delay line device, the ending scanning point of the optical fiber adjustable delay line device, the movement speed of the optical fiber adjustable delay line device during scanning, and the system unit of the optical fiber adjustable delay line device.

6. The system according to claim 3, wherein: The beam splitting optical coupler has a beam splitting ratio of 5:

5.

7. The system according to claim 3, wherein: The system also includes a polarization controller; The polarization controller is provided on the first optical path, and is used to change the polarization deviation of the optical signals of the first optical path and the second optical path.

8. The system according to claim 3, wherein: The system also includes a flange; The flange is provided on the first optical path and / or the second optical path, and is used to adjust the power of the two beams of light reaching the coupling optical coupler.

9. The system according to claim 3, characterized in that: The first optical path is provided with a delay optical fiber, the length of which is greater than the length of the cable in the optical fiber adjustable delay line device and less than the sum of the length of the cable in the optical fiber adjustable delay line device and the delay length supported by the optical fiber adjustable delay line device.

10. A Fourier transform infrared spectroscopy measurement method, characterized in that: Using the spectral measurement system according to any one of claims 1 to 9, the method comprises: The host computer receives the sampling rate parameter input by the user and sends the sampling rate parameter to the field programmable gate array FPGA; The FPGA calculates the clock frequency according to the sampling rate parameter, sets the clock frequency, and generates a clock signal to send to the sampling device; The sampling device collects interference pattern data according to the clock signal, processes the interference pattern data, and sends the processed interference pattern data to the FPGA; The FPGA forwards the interference pattern data to the host computer; The host computer completes spectrum measurement according to the interference pattern data.

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