Signal test circuit, test chip and test device

Abstract

The present application discloses a signal test circuit, a test chip and a test device, and relates to the technical field of device signal test. The disclosed signal test circuit includes: a plurality of signal feedback terminals connected to the device to be tested to connect the data signal output by the device to be tested; a plurality of comparators, wherein the positive input terminal of one comparator is used to connect a signal feedback terminal, and the negative input terminal is used to connect a reference signal; the positive input terminals of the remaining comparators are respectively connected to a reference signal, and the negative input terminals are respectively connected to a signal feedback terminal; a plurality of time-to-digital converters, wherein the input terminal of each time-to-digital converter is connected to the output terminal of a comparator, and each time-to-digital converter is used to convert a pulse signal output by the corresponding comparator into a digital signal. The present application realizes testing under different reference voltages, improves the test efficiency, and does not need to adjust the output reference voltage of the test chip separately, thus simplifying the test process.

Description

Technical Field

[0001] The present invention relates to the technical field of device signal testing, and in particular to a signal testing circuit, a testing chip and a testing device. Background Art

[0002] In the current chip voltage testing scheme, each voltage usually needs to be tested one by one, and the output reference voltage of the test chip must be adjusted separately during each test, which is a very cumbersome process. Summary of the invention

[0003] The main purpose of the present invention is to provide a signal testing circuit and a signal detection device, aiming to improve the testing efficiency.

[0004] To achieve the above object, the present invention provides a signal testing circuit, the signal testing circuit is connected to a device to be tested, and the signal testing circuit comprises:

[0005] A plurality of signal feedback terminals, used for accessing the device under test to access the data signal output by the device under test;

[0006] A plurality of comparators, wherein the non-inverting input terminal of one of the comparators is used to access a signal feedback terminal, and the inverting input terminal is used to access a reference signal; the non-inverting input terminals of the remaining comparators are respectively connected to a reference signal, and the inverting input terminals are respectively connected to a signal feedback terminal;

[0007] A plurality of time-to-digital converters, each of which has an input terminal connected to an output terminal of a comparator, and each of which is used to convert a pulse signal outputted by the corresponding comparator into a digital signal.

[0008] Optionally, the plurality of signal feedback terminals are used to access data signals output by the same device under test;

[0009] The plurality of comparators receive the same data signal and output corresponding pulse signals after comparing the data signal with the corresponding reference signal.

[0010] Optionally, among the multiple signal feedback ends, each of the signal feedback ends is used to access a data signal output by a different device under test, or each of the signal feedback ends is used to access a different data signal output by the same device under test;

[0011] The plurality of comparators are respectively connected to different data signals, and after comparing the data signals with corresponding reference signals, output corresponding pulse signals.

[0012] Optionally, the plurality of comparators are divided into at least two comparator groups, each comparator group includes at least two comparators, and the two comparators are connected to a data signal output by the same device under test;

[0013] The multiple time-to-digital converters are divided into at least two time-to-digital converter groups, the number of the time-to-digital converter groups corresponds to the number of the comparator groups, and the time-to-digital converters in each of the time-to-digital converter groups are connected to the output ends of the comparators of the corresponding comparator groups.

[0014] Optionally, the signal testing circuit further includes:

[0015] A plurality of first switches, wherein a first switch is arranged in series between every two of the signal feedback ends;

[0016] A plurality of second switches are provided, wherein a second switch is connected in series between the input terminal of each time-to-digital converter and the output terminal of each comparator.

[0017] Optionally, the signal test circuit has common read / write and user-defined modes:

[0018] In a normal read / write mode, the plurality of first switches and the plurality of second switches are all disconnected to disconnect the electrical connection between the comparator and the time-to-digital converter, and the data signal and the reference signal are compared by the comparator and then output;

[0019] In the user-defined mode, the first switches and the second switches are all closed, so that the data signal is output to the corresponding comparator, and after being compared with the reference signals one by one, a pulse signal is output to the time-to-digital converter.

[0020] Optionally, the time-to-digital converter comprises:

[0021] a first buffer, an input terminal of the first buffer being connected to an output terminal of the comparator; and

[0022] A plurality of groups of clock dividers are sequentially connected in series with the first buffer.

[0023] Optionally, the clock divider includes:

[0024] Second buffer;

[0025] a trigger, wherein an input terminal of the trigger is electrically connected to an input terminal of the second buffer;

[0026] A third buffer, wherein the input end of the third buffer is used to access the time pulse signal, and the output end of the third buffer is connected to the controlled end of the trigger.

[0027] Optionally, the signal testing circuit further includes a reference signal generating circuit, the output end of the reference signal generating circuit is electrically connected to the plurality of comparators respectively, and the reference signal generating circuit is used to generate and output the reference signal to the plurality of comparators for comparison.

[0028] Optionally, the signal testing circuit further includes:

[0029] A plurality of delay circuits, wherein an input terminal of each of the delay circuits is correspondingly connected to an output terminal of the comparator;

[0030] A plurality of samplers, wherein input terminals of the plurality of samplers are connected to an output terminal of the delay circuit;

[0031] A plurality of third switches, wherein first ends of the plurality of third switches are connected to an output end of the sampler.

[0032] The present invention also provides a test chip, wherein the test chip comprises the signal test circuit as described above.

[0033] The present invention also provides a testing device, the testing device comprising the signal testing circuit as described above;

[0034] and / or, a test chip as described above.

[0035] The embodiment of the present invention connects a signal test circuit to a device under test, and provides a plurality of signal feedback terminals, a plurality of comparators and a plurality of time-to-digital converters in the signal test circuit, wherein the three are provided in a one-to-one correspondence, wherein the signal feedback terminal is connected to the device under test to access a data signal output by the device under test, a non-phase input terminal of one of the plurality of comparators is used to access a signal feedback terminal, and an inverting input terminal is used to access a reference signal; the non-phase input terminals of the remaining comparators are respectively connected to a reference signal, and the inverting input terminals are respectively connected to a signal feedback terminal, and time-to-digital converters provided in a one-to-one correspondence with the comparators are provided to convert the pulse signal output by the corresponding comparator into a digital signal, thereby realizing testing under different reference voltages, improving the test efficiency, and eliminating the need to separately adjust the output reference voltage of the test chip, simplifying the test process, and connecting to the device under test through the plurality of signal feedback terminals, multiple data signals can be tested simultaneously, greatly improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Figure 1 is a circuit block diagram of a signal testing circuit according to an embodiment of the present invention;

[0039] Figure 2 for Figure 1 A circuit block diagram of a set of signal test circuits in;

[0040] Figure 3 A circuit block diagram of a signal testing circuit according to another embodiment of the present invention;

[0041] Figure 4 is a first circuit schematic diagram of a signal testing circuit according to an embodiment of the present invention;

[0042] Figure 5 is a second circuit schematic diagram of the signal testing circuit according to an embodiment of the present invention;

[0043] Figure 6 A circuit block diagram of a signal testing circuit according to another embodiment of the present invention;

[0044] Figure 7 A circuit block diagram of a signal testing circuit according to another embodiment of the present invention;

[0045] Figure 8 for Figure 6 A timing diagram of a time-to-digital converter in FIG.

[0046] Fig. 9 A circuit block diagram of a signal testing circuit according to another embodiment of the present invention;

[0047] Fig.10 FIG. 4 is a circuit block diagram of a signal testing circuit according to another embodiment of the present invention.

[0048] Description of Figure Numbers:

[0049]

[0050] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and the well-known modules, units and their connections, links, communications or operations are not shown or described in detail. In addition, the described features, architectures or functions can be combined in any way in one or more embodiments. It should be understood by those skilled in the art that the various embodiments described below are only for illustration and not for limiting the scope of protection of the present invention. It can also be easily understood that the modules or units or processing methods in the various embodiments described herein and shown in the drawings can be combined and designed according to various different configurations. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] The limitations of various nouns or methods referred to in the following embodiments, except for those that are logically untenable, are generally based on the broad concepts that can be implemented under the premise of the disclosure in the embodiments. Under such understanding, the various specific subordinate specific limitations of the nouns or methods should be regarded as the inventive content of the present invention, and should not be understood narrowly or interpreted in a biased manner on the grounds that the specification does not disclose the specific limitations. Similarly, under the premise that it can be implemented logically, the order of the steps in the method is flexible and changeable, and the specific subordinate specific limitations in the broad concepts of various nouns or methods all fall within the scope of protection of the present invention.

[0053] The main solution of the embodiment of the present application is: by connecting a signal test circuit with a device to be tested, and providing a plurality of signal feedback terminals, a plurality of comparators and a plurality of time-to-digital converters in the signal test circuit, the three being provided in a one-to-one correspondence, wherein the signal feedback terminal is connected to the device to be tested so as to access a data signal output by the device to be tested, the non-phase input terminal of one of the plurality of comparators is used to access a signal feedback terminal, and the inverting input terminal is used to access a reference signal; the non-phase input terminals of the remaining comparators are respectively connected to a reference signal, and the inverting input terminals are respectively connected to a signal feedback terminal, and then time-to-digital converters provided in a one-to-one correspondence with the comparators are provided to convert the pulse signals output by the corresponding comparators into digital signals.

[0054] In the chip voltage testing scheme of the prior art, each voltage usually needs to be tested one by one, and the output reference voltage of the test chip must be adjusted separately during each test, which is a very cumbersome process.

[0055] The present application provides a solution to achieve testing under different reference voltages, thereby improving test efficiency and eliminating the need to individually adjust the output reference voltage of a test chip, thereby simplifying the test process. By connecting to a device under test via multiple signal feedback terminals, multiple data signals can be tested simultaneously, greatly improving test efficiency.

[0056] It should be understood that the signal testing circuit is connected to the device under test 40 .

[0057] Reference Figure 1 and Figure 2 In one embodiment of the present invention, the signal testing circuit includes a plurality of signal feedback terminals 10, a plurality of comparators 20 and a plurality of time-to-digital converters 30, wherein:

[0058] Multiple signal feedback terminals 10 are used to access the device under test 40 to access the data signal output by the device under test 40; the positive input terminal of one of the comparators 20 is used to access a signal feedback terminal 10, and the negative input terminal is used to access a reference signal; the positive input terminals of the remaining comparators 20 are respectively connected to a reference signal, and the negative input terminals are respectively connected to a signal feedback terminal 10; the input terminal of each of the time-to-digital converters 30 is connected to the output terminal of one of the comparators 20, and each of the time-to-digital converters 30 is used to convert a pulse signal output by the corresponding comparator 20 into a digital signal.

[0059] The time-to-digital converter 30 can count the received pulse signals through an internal trigger, and convert the count value into a corresponding digital signal for output.

[0060] The signal feedback terminal 10 will be Figure 4 or Figure 5 As shown, multiple data signals, that is, DQ signals, can be connected as follows Figure 4 As shown, only one DQ0 signal is simultaneously connected to multiple comparators 20, or Figure 5 Shown are multiple DQ signals, such as DQ0~DQ7.

[0061] The comparator 20 can be a high-speed comparator 20, which is used to compare the input positive and negative phase signals. When the positive phase input signal is greater than the negative phase input signal, a high level pulse signal is output, otherwise a low level pulse signal is output, thereby realizing the comparison process between the data signal and the reference signal, and outputting the corresponding pulse signal. The time-to-digital converter 30 can be a high-precision converter, which can convert the width or delay time of the pulse signal output by the comparator 20 into a corresponding digital signal, so as to output the corresponding digital signal to the processing, realize the accurate test of multiple data signals, and because of the use of the time-to-digital converter 30, the precision and accuracy of the test can be greatly improved.

[0062] Wherein, multiple comparators are set to compare different data signals and reference signals in parallel, so that multiple data signals can be processed simultaneously to improve test efficiency. Each comparator 20 works independently without affecting each other, so that even if a problem occurs in the test of one data signal, it will not affect the test of other data signals. Wherein, the reference signal of each comparator is set to a different voltage amplitude to implement the test of data signals with different voltage amplitudes.

[0063] The device under test 40 may be any device that needs to test a data signal, such as a memory, a processor or other electronic devices.

[0064] In this embodiment, the signal test circuit is first connected to the device under test 40, and the device under test 40 will send out a corresponding data signal, that is, a DQ signal. One device under test 40 can send out multiple identical data signals at the same time, or send out different data signals, and access through the signal feedback terminal 10, and then sequentially connect the comparator 20 and the time digital converter 30 after the signal feedback terminal 10, so that the signal feedback terminal 10, the comparator 20 and the time digital converter 30 are set one by one, and there are several signal feedback terminals 10 inputs, and there are as many comparators 20 and time digital converters 30; for example, the signal feedback terminal 1 0 is 8, then there are 8 comparators 20 and time-to-digital converters 30, and they are connected accordingly; wherein, the non-phase input terminal of one comparator 20 among the multiple comparators 20 is used to access a signal feedback terminal 10, and the inverting input terminal is used to access a reference signal; the non-phase input terminals of the remaining comparators 20 are respectively connected to a reference signal, and the inverting input terminals are respectively connected to a signal feedback terminal 10, and then a time-to-digital converter 30 is provided which is arranged one by one corresponding to the comparator 20 to convert the pulse signal output by the corresponding comparator 20 into a digital signal, so as to realize testing under different reference voltages and improve the testing efficiency.

[0065] A reference signal is connected to the non-phase input terminal of each comparator of the present invention, and the same data signal connected to the inverting input terminal can be compared by multiple comparators at the same time, or different data signals connected to the inverting input terminals can be compared by different comparators at the same time. Since multiple comparators 20 can be connected to different reference voltages at the same time, there is no need to adjust the output reference voltage of the test chip separately during the test of the device under test 40. No matter whether the device under test 40 is tested using different reference voltages at the same time, or multiple test devices are respectively connected to a group of signal feedback terminals 10, comparators 20 and time-to-digital converters 30 for testing, there is no need to adjust the output reference voltage of the test chip separately, which can greatly simplify the test process. Moreover, by connecting multiple signal feedback terminals 10 to the device under test 40, multiple data signals can be tested simultaneously, which greatly improves the test efficiency.

[0066] Optionally, refer to Figure 1 and Figure 4 As shown, another embodiment of the present invention provides a signal testing circuit, based on the above Figure 1 In the embodiment shown, the plurality of signal feedback terminals 10 are used to access the data signal output by the same device under test 40, wherein;

[0067] The plurality of comparators 20 receive the same data signal, compare the data signal with the corresponding reference signal, and then output a corresponding pulse signal.

[0068] The data signal may be the same data signal, for example Figure 4 As shown, the data signals connected to the multiple signal feedback terminals 10 are all DQ0; at this time, multiple comparators 20 can compare the same data signal under different reference voltages at the same time, thereby outputting multiple corresponding pulse signals. Each comparator 20 corresponds to a specific reference voltage, so that the test can be performed under different voltage conditions, thereby improving the comprehensiveness and accuracy of the test. The time-to-digital converter 30 is responsible for converting these pulse signals into digital signals for subsequent processing and analysis.

[0069] In addition, you can Figure 4 In the order shown, the voltage amplitudes of the reference signals Ref1~Ref7 can be increasing or decreasing in sequence, or in any other order, depending on the test requirements and the design of the test scheme. By adopting this design, a comprehensive test of the data signal under different reference voltages can be achieved, which effectively improves the accuracy and reliability of the test. At the same time, since multiple comparators 20 and time-to-digital converters 30 work in parallel, the speed and efficiency of the test can be greatly improved, making the test process faster and more efficient. In addition, a comparator can be provided with a reference signal, and a data signal can be compared with multiple reference signals at the same time.

[0070] Optionally, refer to Figure 1 , Figure 3 and Figure 5 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 1 In the illustrated embodiment, among the multiple signal feedback terminals 10, each of the signal feedback terminals 10 is used to access a data signal output by a different device under test 40, or each of the signal feedback terminals 10 is used to access a different data signal output by the same device under test 40;

[0071] The plurality of comparators 20 are respectively connected to different data signals, and after comparing the data signals with corresponding reference signals, output corresponding pulse signals.

[0072] In this embodiment, Figure 4The difference between the embodiments shown is that the above embodiments are connected to the same data signal, while in this embodiment, the data signals connected to each signal feedback terminal 10 are different, but the change trends of multiple data signals are the same, that is, each signal feedback terminal 10 can be connected to different data signals in DQ0~DQ7 respectively, but the change trends of DQ0~DQ7 are increasing or decreasing. In this way, each comparator 20 can independently test different data signals, and each data signal can get a result as long as the comparator is used once, which effectively improves the flexibility and scope of application of the test. For example, in a complex test environment, there may be multiple devices under test 40 that need to be tested at the same time, and the data signals output by each device may be different, but the change trend of the data signals is increasing or decreasing. At this time, these data signals can be connected respectively through multiple signal feedback terminals 10, and tested through the corresponding comparators 20 and time-to-digital converters 30, thereby realizing parallel testing of multiple different data signals, greatly improving the efficiency and accuracy of the test. Or if multiple identical devices under test 40 need to be tested through multiple voltage data, the position of a data signal can be considered as a process. In order to improve the test efficiency, for example, there are six test devices A to F. After A is tested in DQ0, it enters the position of DQ1 for testing, and then B is tested in DQ0. By analogy, the data signals of multiple test devices are tested in a pipeline manner under the same time digital converter 30, thereby greatly improving the utilization rate and test efficiency of the test equipment. At the same time, since each comparator 20 and time digital converter 30 work independently, even if a test device has a problem, it will not affect the normal test of other test devices, thereby improving the reliability and stability of the test. In addition, this design can also easily expand the test scale. It only needs to increase the number of signal feedback terminals 10, comparators 20 and time digital converters 30 to achieve the test of more devices under test 40 and data signals, meeting the test requirements of different scales and complexities.

[0073] Optionally, refer to Figure 1 as well as Figure 4 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 1 In the embodiment shown, the plurality of comparators 20 are divided into at least two groups of comparators 20, each group of comparators 20 includes at least two comparators 20, and the two comparators 20 are connected to the data signal output by the same device under test 40;

[0074] The multiple time-to-digital converters 30 are divided into at least two groups of time-to-digital converters 30. The number of the time-to-digital converters 30 groups corresponds to the number of the comparator 20 groups. The time-to-digital converters 30 in each of the time-to-digital converters 30 groups are connected to the output ends of the comparators 20 of the corresponding comparator 20 groups.

[0075] In this embodiment, the plurality of comparators 20 are divided into at least two groups of comparators 20, each group of comparators 20 includes at least two comparators 20, and such a design can improve the efficiency and flexibility of the test. Among them, the comparators 20 in each group of comparators 20 can simultaneously compare the data signals output by the same device under test 40 under different reference voltages, thereby outputting a plurality of corresponding pulse signals. Each comparator 20 corresponds to a specific reference voltage, so that the test can be performed under different voltage conditions, thereby improving the comprehensiveness and accuracy of the test.

[0076] At the same time, the time digital converter 30 is also divided into at least two groups of time digital converters 30, and the time digital converters 30 in each group of time digital converters 30 are connected to the output ends of the comparators 20 of the corresponding comparator 20. In this way, each group of time digital converters 30 can convert the pulse signal output by the corresponding comparator 20 into a digital signal for subsequent processing and analysis. Through this grouping design, parallel testing of data signals under different reference voltages can be achieved, thereby improving the speed and efficiency of the test.

[0077] Optionally, refer to Figure 4 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 1 In the embodiment shown, the signal test circuit further includes a plurality of first switches 50 and a plurality of second switches 60, wherein:

[0078] A first switch 50 is serially connected between every two of the signal feedback terminals 10 ; a second switch 60 is serially connected between each input terminal of the time-to-digital converter 30 and an output terminal of the comparator 20 .

[0079] The first switch 50 may be a mechanical switch, an electromagnetic switch or other types of switches, and is used to control the connection state between the signal feedback terminals 10. The first switch 50 can be set to connect multiple signal feedback terminals 10 when necessary to reduce current loss and reduce parasitic resistance in the circuit, thereby realizing the test of different data signals.

[0080] The second switch 60 may also be a mechanical switch, an electromagnetic switch or other types of switches, and is used to control the connection state between the time digital converter 30 and the comparator 20. When it is necessary to enter the test mode, the path between the input end of the time digital converter 30 and the comparator 20 is turned on, or when it is necessary to selectively test the output signals of certain comparators 20, the corresponding time digital converter 30 can be selectively connected by opening or closing the second switch 60, so as to implement the test of the output signal of the specific comparator 20.

[0081] Optionally, refer to Figure 4 as well as Figure 5 Another embodiment of the present invention provides a signal testing circuit, based on the above Figure 4 In the embodiment shown, the signal test circuit has common read / write and user-defined modes:

[0082] In the normal read / write mode, the first switches 50 and the second switches 60 are all disconnected to disconnect the electrical connection between the comparator and the time-to-digital converter, the data signal and the reference signal are compared and then output by the comparator 20, and the comparator 20 and the time-to-digital converter 30 are disconnected;

[0083] In the user-defined mode, multiple first switches 50 and multiple second switches 60 are all closed so that the data signal is output to the corresponding comparator, and after being compared one by one with multiple reference signals and multiple data signals in the corresponding comparator 20, a pulse signal is output to the time-to-digital converter 30.

[0084] In the normal read / write mode, the data signal does not need to be compared with the reference signal, and the data signal is directly input through the signal feedback terminal 10 and is read or written after being processed. At this time, the comparator 20 and the time-to-digital converter 30 do not participate in the transmission and processing of the signal, so the multiple first switches 50 and the multiple second switches 60 are all in the off state to avoid interference and influence on the signal.

[0085] In the user-defined mode, in order to meet specific test requirements, multiple first switches 50 and multiple second switches 60 are closed, so that the signal test circuit enters a special test state. In this state, multiple reference signals are compared with multiple data signals in the corresponding comparator 20 to check whether the data signal meets the expected voltage level or logic state. The comparator 20 compares the input positive and negative phase signals and outputs a high level or low level pulse signal. Then, these pulse signals are transmitted to the corresponding time-to-digital converter 30 and converted into digital signals for subsequent processing and analysis.

[0086] By providing common read / write and user-defined modes, the signal test circuit of the present invention can flexibly adapt to different test scenarios and requirements. In common read / write mode, the circuit can efficiently transmit and process data signals; while in user-defined mode, the circuit can comprehensively test and verify data signals to ensure their quality and reliability.

[0087] Optionally, refer to Figure 6 as well as Figure 8 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 1 In the embodiment shown, the time-to-digital converter 30 includes a first buffer 31 and a plurality of clock dividers 32, wherein:

[0088] The input end of the first buffer 31 is connected to the output end of the comparator 20; and a plurality of groups of the clock dividers 32 are sequentially connected in series with the first buffer.

[0089] The first buffer 31 can be used to temporarily store the pulse signal output by the comparator 20 to avoid signal loss and interference during transmission. It has a higher input impedance and a lower output impedance, which can effectively isolate and protect the signal source and the load, and ensure the stable transmission of the signal. The design of the first buffer 31 can make the signal have better anti-interference ability and stability during transmission, thereby improving the accuracy and reliability of the test.

[0090] Multiple groups of clock dividers 32 are connected in series in sequence, and can perform frequency division processing on the input clock signal to obtain clock signals of different frequencies. The input end of the first group of clock dividers 32 is connected to the output end of the first buffer 31, receives the pulse signal processed by the buffer, and converts it into a clock signal of lower frequency. The subsequent clock dividers 32 continue to divide the clock signal output by the previous stage to obtain more clock signals of different frequencies. These clock signals can be used for subsequent digital signal processing and analysis to achieve accurate testing and verification of data signals.

[0091] By adopting this design, the time-to-digital converter 30 can achieve high-precision conversion and measurement of pulse signals, thereby improving the precision and accuracy of the test. At the same time, due to the use of multiple groups of clock dividers 32, the frequency of the clock signal can be flexibly adjusted to adapt to different test requirements and test environments.

[0092] Optionally, refer to Figure 7 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 6 as well as Figure 8 In the illustrated embodiment, the clock divider 32 includes a second buffer 321, a trigger 322 and a third buffer 323, wherein:

[0093] The input end of the trigger 322 is electrically connected to the input end of the second buffer 321 ; the input end of the third buffer 323 is used to access the time pulse signal, and the output end of the third buffer 323 is connected to the controlled end of the trigger 322 .

[0094] The second buffer 321 can be used to temporarily store the pulse signal or clock signal from the first buffer 31 to avoid signal loss and interference during transmission. It also has a higher input impedance and a lower output impedance, which can effectively isolate and protect the signal source and the load, and ensure stable signal transmission. The design of the second buffer 321 can make the signal have better anti-interference ability and stability during transmission, thereby improving the accuracy and reliability of the test.

[0095] The trigger 322 is used to generate a trigger signal according to an input signal (such as a clock signal or a time pulse signal) to control the working state of the subsequent circuit. The input end of the trigger 322 is electrically connected to the output end of the second buffer 321 to receive the signal processed by the second buffer 321. At the same time, the controlled end of the trigger 322 is connected to the output end of the third buffer 323 to receive the time pulse signal from the third buffer 323. When the time pulse signal arrives, the trigger 322 is triggered to generate a trigger signal to control the operation of the subsequent circuit.

[0096] The third buffer 323 is used to temporarily store and transmit the time pulse signal. Its input end is connected to the time pulse signal source, and its output end is connected to the controlled end of the trigger 322. The design of the third buffer 323 can ensure the stable transmission of the time pulse signal and accurately control the triggering moment of the trigger 322, thereby improving the precision and accuracy of the test. Figure 8 The timing relationship between the data signal and the data signals output by multiple triggers is displayed, and the final output result is obtained. The output result shows the detailed working principle of the clock divider 32 in the signal test circuit, so as to better realize high-precision testing and verification of the data signal.

[0097] By adopting this design, the clock divider 32 can realize the frequency division processing of the input signal and generate an accurate trigger signal to control the operation of the subsequent circuit, which helps to realize the accurate test and verification of the data signal and improve the accuracy and reliability of the test.

[0098] Optionally, refer to Fig. 9 Another embodiment of the present invention provides a signal testing circuit based on the above Figure 1 In the embodiment shown, the signal testing circuit further includes a reference signal generating circuit 100, the output ends of the reference signal generating circuit 100 are electrically connected to the plurality of comparators 20 respectively, and the reference signal generating circuit 100 is used to generate and output the reference signal to the plurality of comparators 20 for comparison.

[0099] The test circuit can be applied to a test device, which includes a reference signal generating circuit 100 , that is, the reference signal generating circuit 100 can be integrated in a test chip, or can be installed in the test device but set independently of the test chip.

[0100] The reference signal generating circuit 100 is used to generate a plurality of different reference signals. Among them, the reference signal generating circuit 100 may include a plurality of voltage sources or signal generators, which can output reference signals with different voltage amplitudes or waveform characteristics. These reference signals are transmitted to a plurality of comparators 20 respectively and compared with the data signal output by the device under test 40. By adjusting the voltage amplitude or waveform characteristics of the reference signal, different test conditions and scenarios can be simulated, thereby achieving a comprehensive test of the data signal. In addition, the output end of the reference signal generating circuit 100 is electrically connected to a plurality of comparators 20, which can ensure that the reference signal can be accurately transmitted to each comparator 20, thereby improving the accuracy and reliability of the test.

[0101] Optionally, refer to Fig.10 Another embodiment of the present invention provides a signal testing circuit, based on the above Figures 1 to 9 In any of the embodiments shown, the signal testing circuit further includes a plurality of delay circuits 70, a plurality of samplers 80, and a plurality of third switches 90, wherein:

[0102] The input end of each delay circuit 70 is connected to the output end of a comparator 20 ; the input ends of the plurality of samplers 80 are connected to the output end of a delay circuit 70 ; and the first ends of the plurality of third switches 90 are connected to the output end of a sampler 80 .

[0103] When the third switch 90 is closed, the data signal output by the device to be tested 40 flows along the signal feedback terminal 10, passes through the comparator 20, the delay unit, the sampler 80 and the third switch 90 in sequence, and forms an edge test path to test the edge characteristics of the data signal. The delay circuit 70 is used to delay the pulse signal output by the comparator 20 to simulate the delay effect of the data signal during the transmission process. By adjusting the parameters of the delay circuit 70, the length of the delay can be controlled to simulate different transmission delay conditions. The sampler 80 is used to sample the delayed pulse signal to obtain the state information of the signal at different time points. The setting of the third switch 90 can connect the output end of the sampler 80 to the subsequent processing circuit when necessary, so as to further process and analyze the sampled signal.

[0104] In this embodiment, an edge test path is constructed by introducing a delay circuit 70, a sampler 80 and a third switch 90, and multiple groups of delay circuits 70, samplers 80 and third switches 90 are constructed as multiple edge test paths. One or more edge test paths can simulate the delay and distortion that a data signal may encounter during actual transmission, thereby achieving a comprehensive test of the edge characteristics of the data signal, so as to improve the accuracy and reliability of the test and ensure that the device under test 40 can work normally under various conditions.

[0105] The present invention also provides a test chip, which includes the signal test circuits of all the above embodiments.

[0106] It is worth noting that since the test chip of the present invention is based on the above-mentioned signal test circuit, the embodiments of the test chip of the present invention include all technical solutions of all embodiments of the above-mentioned signal test circuit, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0107] The present invention further provides a testing device, which includes the signal testing circuit as described in the above embodiment and / or the testing chip as described in the above embodiment.

[0108] It is worth noting that since the testing device of the present invention is based on the above-mentioned testing chip, the embodiments of the testing device of the present invention include all technical solutions of all embodiments of the above-mentioned testing chip, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0109] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A signal testing circuit, characterized in that: The signal testing circuit is connected to the device to be tested, and the signal testing circuit comprises: A plurality of signal feedback terminals, used for accessing the device under test to access the data signal output by the device under test; A plurality of comparators, wherein the non-inverting input terminal of one of the comparators is used to access a signal feedback terminal, and the inverting input terminal is used to access a reference signal; the non-inverting input terminals of the remaining comparators are respectively connected to a reference signal, and the inverting input terminals are respectively connected to a signal feedback terminal; A plurality of time-to-digital converters, each of which has an input terminal connected to an output terminal of a comparator, and each of which is used to convert a pulse signal outputted by the corresponding comparator into a digital signal; The signal testing circuit further includes: A plurality of first switches, wherein one first switch is arranged in series between every two of the signal feedback ends; A plurality of second switches are provided, and a second switch is connected in series between the input terminal of each time-to-digital converter and the output terminal of one of the comparators.

2. The signal testing circuit according to claim 1, characterized in that: The plurality of signal feedback terminals are used to access data signals output by the same device under test; The plurality of comparators receive the same data signal and output corresponding pulse signals after comparing the data signal with the corresponding reference signal.

3. The signal testing circuit according to claim 1, characterized in that: Among the multiple signal feedback terminals, each of the signal feedback terminals is used to access data signals output by different devices under test, or each of the signal feedback terminals is used to access different data signals output by the same device under test; The plurality of comparators are respectively connected to different data signals, and after comparing the data signals with corresponding reference signals, output corresponding pulse signals.

4. The signal testing circuit according to claim 1, characterized in that: The plurality of comparators are divided into at least two comparator groups, each comparator group includes at least two comparators, and the two comparators are connected to the data signal output by the same device under test; The multiple time-to-digital converters are divided into at least two time-to-digital converter groups, the number of the time-to-digital converter groups corresponds to the number of the comparator groups, and the time-to-digital converters in each of the time-to-digital converter groups are connected to the output ends of the comparators of the corresponding comparator groups.

5. The signal testing circuit according to claim 1, characterized in that: The signal test circuit has common read and write modes and user-defined modes: In a normal read / write mode, the plurality of first switches and the plurality of second switches are all disconnected to disconnect the electrical connection between the comparator and the time-to-digital converter, and the data signal and the reference signal are compared by the comparator and then output; In the user-defined mode, the first switches and the second switches are all closed, so that the data signal is output to the corresponding comparator, and after being compared with the reference signals one by one, a pulse signal is output to the time-to-digital converter.

6. The signal testing circuit according to claim 1, characterized in that: The time-to-digital converter comprises: a first buffer, an input terminal of the first buffer being connected to an output terminal of the comparator; and A plurality of groups of clock dividers are sequentially connected in series with the first buffer.

7. The signal testing circuit according to claim 6, characterized in that: The clock divider comprises: Second buffer; a trigger, wherein an input terminal of the trigger is electrically connected to an input terminal of the second buffer; A third buffer, wherein the input end of the third buffer is used to access the time pulse signal, and the output end of the third buffer is connected to the controlled end of the trigger.

8. The signal testing circuit according to claim 1, characterized in that: The signal testing circuit also includes a reference signal generating circuit, the output ends of which are electrically connected to the plurality of comparators respectively, and the reference signal generating circuit is used to generate and output the reference signal to the plurality of comparators for comparison.

9. The signal testing circuit according to any one of claims 1 to 8, characterized in that: The signal testing circuit further includes: A plurality of delay circuits, wherein an input terminal of each of the delay circuits is correspondingly connected to an output terminal of the comparator; A plurality of samplers, wherein input terminals of the plurality of samplers are connected to an output terminal of the delay circuit; A plurality of third switches, wherein first ends of the plurality of third switches are connected to an output end of the sampler.

10. A test chip, characterized in that: The test chip comprises the signal test circuit according to any one of claims 1 to 9.

11. A testing device, characterized in that: The testing device comprises a signal testing circuit as claimed in any one of claims 1 to 9; And / or, the test chip as claimed in claim 10.

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