Chip voltage margin test method, device and system

Abstract

The invention provides a chip voltage margin test method, device and system, and the method comprises the steps: controlling a power module to obtain different test voltages according to different offsets on the basis of the standard voltage on the basis that the output voltage of the power module is the standard voltage; and controlling the power supply module to sequentially output each test voltage to the to-be-tested chip, and controlling the to-be-tested chip to execute a test operation under each test voltage. And judging whether the to-be-tested chip meets a preset voltage margin requirement or not based on the test operation results of the to-be-tested chip under each test voltage. According to the scheme, the to-be-tested chip is tested by adjusting the test voltage output by the power supply module, chips which do not meet requirements under the conditions of voltage fluctuation sensitivity, low voltage or high voltage and the like can be screened, and the quality of factory chips is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a chip voltage margin testing method, device and system. Background Art

[0002] With the development of science and technology, the dependence on electronic products is gradually increasing. The high requirements for equipment quality have driven manufacturers to conduct comprehensive testing on their chips and systems. System-on-chip (SoC) and system-in-package (SIP) chips are the main test objects of system-level testing (SLT), so chip manufacturers will add chip system-level testing to chip mass production and shipment testing. Whether the test plan design in chip system-level testing is perfect directly affects the reliability of chips shipped to customer sites.

[0003] Chip system-level testing is to build an environment that is the same as the terminal usage scenario, run the chip in this environment, and write specific programs for some functional modules. The function and performance of the chip are evaluated through the results of program execution, and then an automated sorting machine is used to classify and collect the screened chips of various levels.

[0004] In the current chip system-level testing scheme, a set of SLT boards are usually designed specifically for the chip to be tested. The board includes the power supply required for the normal operation of the chip to be tested, the test processor used to configure the chip to be tested, and also includes some peripheral chipsets that need to be connected to some physical interfaces in the chip to be tested. During the test, the test processor will configure the functions of the chip to be tested before executing each test item, read the test results after the test is completed, make a judgment on the chip grade based on the test results, and report them to the automatic sorting machine.

[0005] In the current chip system-level test, the chip to be tested is placed in a typical chip voltage environment to complete all tests. However, there is no way to effectively screen out some chips that may fail under low or high chip voltage conditions, which ultimately leads to the flow of such chips to the client. For such chips with poor voltage margin, they will be affected by differences in client hardware design, the working environment of the client's equipment, and a long period of operation, resulting in functional abnormalities under certain specific conditions. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a chip voltage margin testing method, device and system, so as to screen chips that are sensitive to voltage fluctuations, low voltage or high voltage and do not meet the requirements, so as to ensure the quality of the chips leaving the factory.

[0007] In a first aspect, the present invention provides a chip voltage margin testing method, which is applied to a test processor, wherein the test processor is respectively connected to a chip to be tested and a power module, and the method comprises:

[0008] On the basis that the output voltage of the power module is a standard voltage, controlling the power module to obtain different test voltages according to different offsets in sequence on the basis of the standard voltage;

[0009] Controlling the power supply module to sequentially output each of the test voltages to the chip to be tested;

[0010] Controlling the chip under test to perform a test operation under each of the test voltages;

[0011] Based on the test operation results of the chip under test at each of the test voltages, it is determined whether the chip under test meets a preset voltage margin requirement.

[0012] In an optional implementation manner, the step of controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage includes:

[0013] Setting a plurality of offsets based on the standard voltage, and rewriting a value in a voltage register of the power module based on the plurality of offsets;

[0014] The power supply module is controlled to read the values ​​in the voltage register in sequence, and obtain the test voltage according to the read values.

[0015] In an optional implementation manner, the step of setting a plurality of offsets based on the standard voltage includes:

[0016] Setting an offset percentage based on the standard voltage and setting a step value for each offset;

[0017] A plurality of offsets are obtained based on the standard voltage, the offset percentage and the step value.

[0018] In an optional implementation manner, the step of obtaining the test voltage according to the read value includes:

[0019] Convert the read binary value to decimal format;

[0020] Multiply the converted value by the set granularity value to obtain the test voltage.

[0021] In an optional implementation, the chip under test includes a transmitting end and a receiving end;

[0022] The step of controlling the chip under test to perform a test operation under each of the test voltages includes:

[0023] Under each of the test voltages, controlling the transmitting end of the chip under test to send a test signal outwardly, and receiving the test signal through the receiving end of the chip under test;

[0024] Obtaining a signal bit error rate based on a received test signal and an outwardly transmitted test signal;

[0025] A test operation result is obtained based on the signal bit error rate.

[0026] In an optional implementation, the step of controlling the chip under test to perform a test operation under each of the test voltages includes:

[0027] Under each of the test voltages, writing test data into the register of the chip to be tested;

[0028] Reading the test data in the register of the chip to be tested;

[0029] Compare the read test data with the written test data to obtain the test operation result.

[0030] In an optional implementation, the preset voltage margin requirement includes a first preset voltage margin requirement and a second preset voltage margin requirement;

[0031] The step of judging whether the chip under test meets the preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages comprises:

[0032] Detecting whether a test operation result of the chip under test under the test voltage being the standard voltage indicates that the chip is working normally, and if the result indicates that the chip is working abnormally, determining that the chip under test does not meet a preset voltage margin requirement;

[0033] If the characterization is normal, then detecting whether the test operation results of the chip under test under the condition that the test voltage is within the positive offset percentage and the negative offset percentage of the standard voltage all characterize that the chip is working normally;

[0034] If the test operation result under the positive offset percentage only indicates normal operation, it is determined that the chip under test meets the first preset voltage margin requirement;

[0035] If the test operation results under the positive offset percentage and the negative offset percentage both indicate normal operation, it is determined that the chip under test meets the second preset voltage margin requirement.

[0036] In an optional embodiment, the test processor and the power module are connected via a power management bus interface, the test processor and the chip to be tested are connected via a high-speed serial expansion bus interface, and the chip to be tested and the power module are connected via a power supply pin.

[0037] In a second aspect, the present invention provides a chip voltage margin test device, which is applied to a test processor, wherein the test processor is respectively connected to a chip to be tested and a power module, and the device comprises:

[0038] A control module, for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being a standard voltage;

[0039] The control module is further used to control the power supply module to sequentially output each of the test voltages to the chip to be tested;

[0040] The control module is further used to control the chip under test to perform a test operation under each of the test voltages;

[0041] The test module is used to determine whether the chip under test meets a preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages.

[0042] In a third aspect, the present invention provides a chip voltage margin test system, the system comprising a test processor and a chip to be tested and a power module connected to the test processor;

[0043] The test processor is used for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being the standard voltage;

[0044] The power supply module is used to sequentially output each of the test voltages to the chip under test under the control of the test processor;

[0045] The test processor is also used to control the chip to be tested to perform a test operation under each of the test voltages;

[0046] The test processor is further used to determine whether the chip under test meets a preset voltage margin requirement based on test operation results of the chip under test at each of the test voltages.

[0047] The present application provides a chip voltage margin test method, device and system. On the basis that the output voltage of the power module is a standard voltage, the power module is controlled to obtain different test voltages according to different offsets on the basis of the standard voltage. The power module is controlled to output each test voltage value of the chip to be tested in turn, and the chip to be tested is controlled to perform a test operation under each test voltage. Based on the test operation results of the chip to be tested under each test voltage, it is determined whether the chip to be tested meets the preset voltage margin requirements. In this solution, by adjusting the test voltage output by the power module to test the chip to be tested, it is possible to screen out chips that do not meet the requirements under conditions such as sensitive voltage fluctuations, low voltage or high voltage, thereby ensuring the quality of the chips leaving the factory. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A schematic diagram of the architecture of a chip voltage margin test system provided in an embodiment of the present application;

[0050] Figure 2 A flowchart of a chip voltage margin testing method provided in an embodiment of the present application;

[0051] Figure 3 for Figure 2 A flowchart of the sub-steps included in S11;

[0052] Figure 4 for Figure 3 A flowchart of the sub-steps included in S111;

[0053] Figure 5 A schematic diagram of a voltage register of a power module in an embodiment of the present application;

[0054] Figure 6 for Figure 3 A flowchart of the sub-steps included in S112;

[0055] Figure 7 for Figure 2 One of the flowcharts of the sub-steps included in S13;

[0056] Figure 8 for Figure 2 Flowchart 2 of the sub-steps included in S13;

[0057] Fig. 9 for Figure 2A flowchart of the sub-steps included in S14;

[0058] Fig.10 A functional module block diagram of a chip voltage margin testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0060] See also Figure 1 , is a schematic diagram of an application scenario of the chip voltage margin test method provided in an embodiment of the present application, in which a chip voltage margin test system is included, and the test system includes a test processor and a chip to be tested and a power module connected to the test processor. The chip voltage margin test method provided in this embodiment aims to perform tests on the chip to be tested under various conditions, so as to detect whether the chip to be tested meets certain voltage margin requirements.

[0061] The test processor can control the power module and the chip under test, and the power module can provide voltage for the chip under test. The test processor can determine whether the chip under test meets the requirements based on the test results of the chip under test.

[0062] like Figure 1 As shown in , the test processor and the power module are connected through the power management bus interface (PMBUS), the test processor and the chip to be tested are connected through the PCIe interface, the chip to be tested and the power module are connected through the power supply pin, and the power supply pin of the chip to be tested is connected to the power supply output pin of the power module. In addition, the input end of the power module also has a power supply voltage input, for example, the power supply voltage can be 12V. The chip to be tested is also connected to the clock input required for chip operation, the peripheral circuit required for chip testing, etc.

[0063] In this embodiment, the test processor may be a test processor of model LS1023ASN7KQB. The power module may be a DC voltage drop power module, for example, model IS6608A.

[0064] The power management bus is connected between the test processor and the power module to realize the transmission of control instructions, data, etc.

[0065] In addition, in this embodiment, the power supply PPU_1V2 output by the power module is connected to the 1V2 power domain of the chip under test.

[0066] Based on the above, please refer to Figure 2The embodiment of the present application provides a chip voltage margin testing method, which can be applied to the above-mentioned test processor. The specific implementation steps of the method are as follows:

[0067] S11, on the basis that the output voltage of the power module is a standard voltage, controlling the power module to obtain different test voltages according to different offsets in sequence on the basis of the standard voltage.

[0068] S12, controlling the power supply module to output the test voltages to the chip under test in sequence.

[0069] S13, controlling the chip under test to perform a test operation under each of the test voltages.

[0070] S14, judging whether the chip under test meets a preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages.

[0071] In this embodiment, the standard voltage refers to the typical voltage of the chip to be tested, that is, theoretically, the chip to be tested can be in a normal working state under this standard voltage. Considering that the working environment of the chip may deviate from the ideal environment when it was originally designed, for example, it may be in a working environment of high temperature, high humidity, low power supply voltage, etc. Therefore, it is necessary to test whether the chip can maintain a normal working state when the voltage fluctuates.

[0072] Based on this, in this embodiment, the test processor can control the power module to obtain different test voltages according to different offsets based on the standard voltage. The test processor can pre-write the rewriting code and run the rewriting code to rewrite the test voltage of the power module.

[0073] On this basis, when performing a test, the power module can output various test voltages to the chip under test in sequence to provide the test voltage for the chip under test.

[0074] When the power supply voltages of the chip under test are different test voltages, the test processor can control the chip under test to perform test operations, for example, it can perform high-speed signal performance testing, chip register testing, etc.

[0075] The test operation result obtained can indicate whether the chip under test is working normally. In this way, the upper limit and lower limit of the test voltage of the chip under test in normal operation can be found. Based on the upper limit, lower limit and standard voltage, the voltage margin of the chip under test in normal operation can be obtained. By comparing the voltage margin with the preset voltage margin requirement, it can be determined whether the chip under test meets the preset voltage margin requirement.

[0076] On this basis, the chips under test that do not meet the preset voltage margin requirements can be screened out to avoid directly shipping the chips under test and causing abnormal working conditions in subsequent products, thereby ensuring the quality of the chips before delivery.

[0077] The chip voltage margin test method provided in this embodiment can screen out chips that do not meet the requirements under conditions such as sensitive to voltage fluctuations, low voltage or high voltage, by adjusting the test voltage output by the power module to test the chip to be tested, thereby ensuring the quality of the chips leaving the factory.

[0078] See also Figure 3 In this embodiment, the step of controlling the power supply module to obtain different test voltages according to different offsets based on the standard voltage can be achieved in the following manner:

[0079] S111, setting a plurality of offsets on the basis of the standard voltage, and rewriting the value in the voltage register of the power module based on the plurality of offsets.

[0080] S112, controlling the power supply module to read the values ​​in the voltage register in sequence, and obtaining the test voltage according to the read values.

[0081] In this embodiment, assuming that the standard voltage is 1.2V, a plurality of offsets are obtained by performing positive and negative offsets on the basis of the standard voltage. For example, the offsets obtained may include 1.21V, 1.22V, 1.19V, 1.18V, etc.

[0082] See also Figure 4 In this embodiment, the step of setting a plurality of offsets based on the standard voltage can be implemented in the following manner:

[0083] S1111, setting an offset percentage based on the standard voltage, and setting a step value for each offset.

[0084] S1112, obtaining a plurality of offsets based on the standard voltage, the offset percentage and the step value.

[0085] In this embodiment, the offset percentage may include a positive offset percentage and a negative offset percentage, for example, the offset percentage may be 10% in the positive direction and 10% in the negative direction. That is, assuming that the standard voltage is 1.2V, the upper limit of the offset in the positive direction is 1.32V, and the lower limit of the offset in the negative direction is 1.08V. A plurality of offsets are set between the upper limit and the lower limit.

[0086] In addition, the step value for each offset can be set, and the size of the step value affects the granularity of the test voltage. For example, the step value can be set to 2mV or the like without limitation.

[0087] In addition, the power module includes a voltage register for voltage output, and the power module outputs a corresponding voltage to the chip under test based on the value in the voltage register. Therefore, rewriting the value in the voltage register of the power module based on the obtained multiple offsets can be understood as writing the offsets into the voltage register.

[0088] Figure 5 A schematic diagram of a voltage register in a power module is schematically shown in FIG. 1 , wherein the voltage register is composed of 16 bits of binary, the lower 12 bits are readable and writable bits, and the remaining 4 bits are read-only bits.

[0089] In this embodiment, the value in the voltage register is rewritten by writing an automated test script. The following schematically shows the script code for rewriting:

[0090] proc fun_voltageRegulator{skew_device0[DUT dut2]}{

[0091] set 0x41_base_voltage 1.2

[0092] set 0x41_granularity 2

[0093] set default_skew_value$skew_device0

[0094] foreach hit_skew_device[list"skew_device"]{

[0095]

[0096]

[0097] }

[0098] }

[0099] When executing the test, the power module can read the values ​​in the voltage register in sequence under the control of the test processor, and then convert them into corresponding test voltages to output to the chip under test.

[0100] See also Figure 6 Specifically, the step of obtaining the test voltage according to the read value by the power module can be implemented in the following manner:

[0101] S1121, converting the read binary format value into a decimal format.

[0102] S1122, multiply the converted value by the set granularity value to obtain a test voltage.

[0103] The value in the voltage register is a binary value. After reading, it needs to be converted to a decimal value. Then the converted value is multiplied by the set granularity value to obtain the test voltage. Among them, the granularity value can be understood as a value that controls the granularity of the test voltage. For example, if the granularity value is set larger, the granularity of the test voltage is larger. If the granularity value is set smaller, the granularity of the test voltage is smaller. If you need to keep consistent with the original offsets, you can set the granularity value to 1.

[0104] The power supply module outputs the test voltages to the chip under test in sequence, so that the chip under test performs the test at each test voltage.

[0105] In this embodiment, the chip under test includes a transmitting end and a receiving end. Figure 7 In a possible implementation, the step of controlling the chip under test to perform a test operation at each test voltage can be implemented in the following manner:

[0106] S131A, under each of the test voltages, controlling the transmitting end of the chip under test to send a test signal outwardly, and receiving the test signal through the receiving end of the chip under test.

[0107] S132A, obtaining a signal bit error rate based on the received test signal and the outwardly sent test signal.

[0108] S133A, obtaining a test operation result based on the signal bit error rate.

[0109] In this embodiment, the test operation is performed on the chip under test at each test voltage. At each test voltage, the test processor can control the chip under test to send a test signal to the outside, and the test signal can be a high-speed signal, which has the characteristics of high data transmission rate, signal integrity, low delay and synchronization.

[0110] At the same time, the receiving end of the chip under test can also receive a test signal. The signal bit error rate can be obtained based on the received test signal and the test signal sent out. Specifically, the number of bits with errors in the received test signal can be determined, and the total number of transmitted bits of the test signal sent out can be obtained. The bit error rate is obtained by dividing the number of bits with errors by the total number of transmitted bits.

[0111] A signal that is too weak or too strong may lead to an increase in the bit error rate, and the size of the test voltage will affect the strength of the signal. Therefore, the calculated signal bit error rate can be compared with the preset bit error rate to obtain the test operation result, and then determine whether the chip under test is working properly based on the test operation result. For example, if the calculated signal bit error rate is greater than the preset bit error rate, it indicates that the bit error rate is too high, indicating that the chip under test is not working properly at this time. It further indicates that the chip under test cannot work properly under the current test voltage.

[0112] In addition, in this embodiment, the test operation can also be performed on the register of the chip to be tested, see Figure 8 In another possible implementation, the step of controlling the chip under test to perform a test operation at each test voltage may be implemented in the following manner:

[0113] S131B, writing test data into the register of the chip to be tested under each of the test voltages.

[0114] S132B, read the test data in the register of the chip to be tested.

[0115] S133B, compare the read test data with the written test data to obtain the test operation result.

[0116] In this embodiment, the test data is written into the register of the chip to be tested in a write-before-read manner, and then the test data is read from the register. Then the read test data is compared to see whether it is the same as the written test data. If they are the same, it can be shown that the chip to be tested can work normally under the corresponding test voltage. Otherwise, it can be shown that the chip to be tested does not work normally under the corresponding test voltage.

[0117] In this embodiment, based on the above test operation, according to the test operation results of the chip under test at each test voltage, it is determined whether the chip under test meets the preset voltage margin requirement, and the preset voltage margin requirement may include a first preset voltage margin requirement and a second preset voltage margin requirement. This step can be specifically implemented in the following manner, please refer to Fig. 9 :

[0118] S141, detecting whether the test operation result of the chip under test under the test voltage being the standard voltage indicates that the chip is working normally. If the result indicates that the chip is working abnormally, executing the following step S145; if the result indicates that the chip is working normally, executing the following step S142.

[0119] S142, detect whether the test operation results of the chip under test when the test voltage is within the positive offset percentage and the negative offset percentage of the standard voltage both indicate that it is working normally. If only the test operation results under the positive offset percentage indicate that it is working normally, execute the following step S143; if the test operation results under both the positive offset percentage and the negative offset percentage indicate that it is working normally, execute the following step S144.

[0120] S143, determining whether the chip under test meets the first preset voltage margin requirement.

[0121] S144, determining whether the chip under test meets the second preset voltage margin requirement.

[0122] S145, determining that the chip under test does not meet a preset voltage margin requirement.

[0123] In this embodiment, a first preset voltage margin requirement and a second preset voltage margin requirement are preset, wherein the second preset voltage margin requirement has a higher standard than the first preset voltage margin requirement.

[0124] Among them, if the test operation results of the chip under test under the standard voltage indicate that it is working normally, then a more specific analysis and judgment can be performed later. If the test operation structure of the chip under test under the standard voltage indicates that it is not working properly, then it can be directly determined that the chip under test does not meet the preset voltage margin requirements.

[0125] Assume that the positive offset percentage of the standard voltage is 10%, and the negative offset percentage is also 10%. If the chip under test works normally at the standard voltage and the test voltage within the positive offset percentage of the standard voltage, but does not work properly at the test voltage within the negative offset percentage, it can be determined that the chip under test meets the first preset voltage margin requirement, and the chip that meets the first preset voltage margin requirement will be shipped as a level 2 chip.

[0126] If the chip under test works normally under the test voltage within the positive offset percentage and the negative offset percentage of the standard voltage, it can be determined that the chip under test meets the second preset voltage margin requirement. The chip that meets the second preset voltage margin requirement can be shipped as a level 1 chip.

[0127] Thus, through the above method, the chips that do not meet the preset voltage margin requirement and only meet the first preset voltage margin requirement can be screened out.

[0128] The chip voltage margin test method provided in this embodiment realizes a method of rewriting the output voltage of the power module based on the PMBUS interface using a test processor during system-level testing through hardware circuit design and execution of test scripts, and then performing functional and performance tests on the chip to be tested to screen out chips that do not meet the voltage margin requirements.

[0129] Based on the same application idea, please refer to Fig.10 , an embodiment of the present application also provides a functional module schematic diagram of a chip voltage margin test device. This embodiment can divide the functional modules of the chip voltage margin test device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic, which is only a logical function division, and there may be other division methods in actual implementation.

[0130] For example, when each functional module is divided into corresponding functional modules, Fig.10 The chip voltage margin test device shown is only a schematic diagram of the device, wherein the chip voltage margin test device may include a control module and a test module, and the functions of each functional module of the chip voltage margin test device are respectively described in detail below.

[0131] A control module, for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being a standard voltage;

[0132] The control module is further used to control the power supply module to sequentially output each of the test voltages to the chip to be tested;

[0133] The control module is further used to control the chip under test to perform a test operation under each of the test voltages;

[0134] The test module is used to determine whether the chip under test meets a preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages.

[0135] It can be understood that the control module and the test module can be used to execute the above S11 to S14. The detailed implementation of the control module and the test module can refer to the relevant contents of the above S11 to S14.

[0136] In a possible implementation, the control module may be used to:

[0137] Setting a plurality of offsets based on the standard voltage, and rewriting a value in a voltage register of the power module based on the plurality of offsets;

[0138] The power supply module is controlled to read the values ​​in the voltage register in sequence, and obtain the test voltage according to the read values.

[0139] In a possible implementation, the control module may be specifically used for:

[0140] Setting an offset percentage based on the standard voltage and setting a step value for each offset;

[0141] A plurality of offsets are obtained based on the standard voltage, the offset percentage and the step value.

[0142] In a possible implementation, the control module may be used to:

[0143] Convert the read binary value to decimal format;

[0144] Multiply the converted value by the set granularity value to obtain the test voltage.

[0145] In a possible implementation, the chip under test includes a transmitting end and a receiving end; the control module is used to control the chip under test to perform a test operation in the following manner:

[0146] Under each of the test voltages, controlling the transmitting end of the chip under test to send a test signal outwardly, and receiving the test signal through the receiving end of the chip under test;

[0147] Obtaining a signal bit error rate based on a received test signal and an outwardly transmitted test signal;

[0148] A test operation result is obtained based on the signal bit error rate.

[0149] In a possible implementation, the control module is used to control the chip under test to perform a test operation in the following manner:

[0150] Under each of the test voltages, writing test data into the register of the chip to be tested;

[0151] Reading the test data in the register of the chip to be tested;

[0152] Compare the read test data with the written test data to obtain the test operation result.

[0153] In a possible implementation, the preset voltage margin requirement includes a first preset voltage margin requirement and a second preset voltage margin requirement; the above-mentioned test module can be specifically used for:

[0154] Detecting whether a test operation result of the chip under test under the test voltage being the standard voltage indicates that the chip is working normally, and if the result indicates that the chip is working abnormally, determining that the chip under test does not meet a preset voltage margin requirement;

[0155] If the characterization is normal, then detecting whether the test operation results of the chip under test under the condition that the test voltage is within the positive offset percentage and the negative offset percentage of the standard voltage all characterize that the chip is working normally;

[0156] If the test operation result under the positive offset percentage only indicates normal operation, it is determined that the chip under test meets the first preset voltage margin requirement;

[0157] If the test operation results under the positive offset percentage and the negative offset percentage both indicate normal operation, it is determined that the chip under test meets the second preset voltage margin requirement.

[0158] In one possible implementation, the test processor and the power module are connected via a power management bus interface, the test processor and the chip under test are connected via a high-speed serial expansion bus interface, and the chip under test and the power module are connected via a power supply pin.

[0159] The chip voltage margin testing device provided in this embodiment can implement the chip voltage margin testing method in any one of the implementation modes in the above embodiments, and has the same beneficial effects. For details, please refer to the relevant description of the above embodiments, and this embodiment will not be described in detail here.

[0160] An embodiment of the present application also provides a chip voltage margin testing system, which includes a testing processor and a chip to be tested and a power supply module connected to the testing processor.

[0161] The test processor is used for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being the standard voltage;

[0162] The power supply module is used to sequentially output each of the test voltages to the chip under test under the control of the test processor;

[0163] The test processor is also used to control the chip to be tested to perform a test operation under each of the test voltages;

[0164] The test processor is further used to determine whether the chip under test meets a preset voltage margin requirement based on test operation results of the chip under test at each of the test voltages.

[0165] The chip voltage margin testing system provided in this embodiment can implement the chip voltage margin testing method in any one of the implementation modes in the above embodiments, and has the same beneficial effects. For details, please refer to the relevant description of the above embodiments, and this embodiment will not be described in detail here.

[0166] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0167] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0168] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0169] It should be noted that if the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially be embodied in the form of a software product, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM) random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0170] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0171] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip voltage margin testing method, characterized in that: Applied to a test processor, the test processor is connected to a chip to be tested and a power module respectively, and the method comprises: On the basis that the output voltage of the power module is a standard voltage, controlling the power module to obtain different test voltages according to different offsets in sequence on the basis of the standard voltage; Controlling the power supply module to sequentially output each of the test voltages to the chip to be tested; Controlling the chip under test to perform a test operation under each of the test voltages; Based on the test operation results of the chip under test at each of the test voltages, it is determined whether the chip under test meets a preset voltage margin requirement.

2. The chip voltage margin testing method according to claim 1, characterized in that: The step of controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage includes: Setting a plurality of offsets based on the standard voltage, and rewriting a value in a voltage register of the power module based on the plurality of offsets; The power supply module is controlled to read the values ​​in the voltage register in sequence, and obtain the test voltage according to the read values.

3. The chip voltage margin testing method according to claim 2, characterized in that: The step of setting a plurality of offsets based on the standard voltage comprises: Setting an offset percentage based on the standard voltage and setting a step value for each offset; A plurality of offsets are obtained based on the standard voltage, the offset percentage and the step value.

4. The chip voltage margin testing method according to claim 2, characterized in that: The step of obtaining the test voltage according to the read value includes: Convert the read binary value to decimal format; Multiply the converted value by the set granularity value to obtain the test voltage.

5. The chip voltage margin testing method according to claim 1, characterized in that: The chip to be tested includes a transmitting end and a receiving end; The step of controlling the chip under test to perform a test operation under each of the test voltages includes: Under each of the test voltages, controlling the transmitting end of the chip under test to send a test signal outwardly, and receiving the test signal through the receiving end of the chip under test; Obtaining a signal bit error rate based on a received test signal and an outwardly transmitted test signal; A test operation result is obtained based on the signal bit error rate.

6. The chip voltage margin testing method according to claim 1, characterized in that: The step of controlling the chip under test to perform a test operation under each of the test voltages includes: Under each of the test voltages, writing test data into the register of the chip to be tested; Reading test data in the register of the chip to be tested; Compare the read test data with the written test data to obtain the test operation result.

7. The chip voltage margin testing method according to claim 1, characterized in that: The preset voltage margin requirement includes a first preset voltage margin requirement and a second preset voltage margin requirement; The step of judging whether the chip under test meets the preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages comprises: Detecting whether a test operation result of the chip under test under the test voltage being the standard voltage indicates that the chip is working normally, and if the result indicates that the chip is working abnormally, determining that the chip under test does not meet a preset voltage margin requirement; If the characterization is normal, then detecting whether the test operation results of the chip under test under the condition that the test voltage is within the positive offset percentage and the negative offset percentage of the standard voltage all characterize that the chip is working normally; If the test operation result under the positive offset percentage only indicates normal operation, it is determined that the chip under test meets the first preset voltage margin requirement; If the test operation results under the positive offset percentage and the negative offset percentage both indicate normal operation, it is determined that the chip under test meets the second preset voltage margin requirement.

8. The chip voltage margin testing method according to claim 1, characterized in that: The test processor is connected to the power module via a power management bus interface, the test processor is connected to the chip under test via a high-speed serial expansion bus interface, and the chip under test is connected to the power module via a power supply pin.

9. A chip voltage margin testing device, characterized in that: Applied to a test processor, the test processor is connected to a chip to be tested and a power module respectively, and the device comprises: A control module, for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being a standard voltage; The control module is further used to control the power supply module to sequentially output each of the test voltages to the chip to be tested; The control module is further used to control the chip under test to perform a test operation under each of the test voltages; The test module is used to determine whether the chip under test meets a preset voltage margin requirement based on the test operation results of the chip under test at each of the test voltages.

10. A chip voltage margin test system, characterized in that: The system includes a test processor and a chip to be tested and a power module connected to the test processor; The test processor is used for controlling the power module to obtain different test voltages according to different offsets in sequence based on the standard voltage, based on the output voltage of the power module being the standard voltage; The power supply module is used to sequentially output each of the test voltages to the chip under test under the control of the test processor; The test processor is also used to control the chip to be tested to perform a test operation under each of the test voltages; The test processor is further used to determine whether the chip under test meets a preset voltage margin requirement based on test operation results of the chip under test at each of the test voltages.

Images