Chip testing system and testing method thereof

Abstract

The present invention proposes a chip testing system and a testing method thereof. The testing system includes: a testing machine, a switching circuit and a bias power supply. The present invention introduces a bias power supply between the ground reference terminal of the chip to be tested and the power ground of the testing system to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so that there is a voltage difference between the ground terminal of the testing machine and the ground reference terminal of the chip to be tested, so that the testing machine can perform reverse testing on the electronic components in the chip to be tested without a negative voltage power supply, thereby reducing the cost of the testing machine. At the same time, a switching circuit is provided between the ground terminal of the testing machine and the ground reference terminal of the chip to be tested, and the voltage difference between the ground reference terminal and the ground terminal of the chip to be tested is controlled by controlling the closing and opening of the switching circuit, so that this test structure can meet the different requirements of contact testing and high-speed data transmission testing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing system and a testing method thereof. Background Art

[0002] As the global semiconductor industry continues to grow, the application market for semiconductor testing equipment is also showing a clear growth trend. In recent years, the country has vigorously supported and promoted the semiconductor industry, and domestic companies have also made breakthroughs in the field of chip testers. Benefiting from the development of the entire domestic semiconductor industry, the localization rate of chip testers is expected to be significantly improved in the future.

[0003] Chip testing usually involves sending chip communication clock signals, chip select signals, and input signals to the chip under test, and determining whether the chip under test passes the test based on whether the correct output signal is obtained from the chip under test. Because the DC characteristic test of chip IO usually includes the measurement of multiple parameters such as voltage and current. Since chip IO may need to work within the positive and negative voltage range, the test circuit must be able to provide the corresponding voltage range to ensure the comprehensiveness and accuracy of the test.

[0004] The DC test of the traditional tester requires a power supply with negative voltage for measurement, but the power chip supporting negative voltage has a complex structure and high cost. Therefore, a chip testing system that can replace the power supply tester with negative voltage is needed to realize reverse voltage testing. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip testing system and a testing method thereof, aiming to solve the problem that the power supply chip supporting negative voltage of the traditional testing machine is complex in structure and high in cost.

[0006] In view of the above problems, the present invention provides a chip testing system, the testing system comprising:

[0007] A tester generates at least one set of forward / reverse test signals and outputs them to the chip under test in sequence according to the test process, so that the chip under test executes the test program according to the forward / reverse test signals and generates test results. The tester is used to receive the test results fed back by the chip under test to detect abnormal conditions of the chip under test;

[0008] The test machine has a ground terminal electrically connected to a power ground;

[0009] A switch circuit, used for controlling the connection or disconnection between the ground terminal and the ground reference terminal of the chip to be tested;

[0010] The bias power supply is used to provide a stable voltage to the ground reference terminal of the chip to be tested when the ground terminal and the ground reference terminal of the chip to be tested are disconnected, so as to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground.

[0011] Optionally, the test machine has a test terminal, and the test terminal is used to access the chip to be tested;

[0012] One end of the switch circuit is electrically connected to the ground terminal, and the other end is electrically connected to the ground reference terminal of the chip to be tested;

[0013] One end of the bias power supply is electrically connected to the ground reference end of the chip to be tested, and the other end is electrically connected to the power ground.

[0014] Optionally, the test system has a contact test mode and a high-speed data transmission test mode;

[0015] In the contact test mode, the switch circuit controls the ground terminal to be disconnected from the ground reference terminal of the chip to be tested, so as to introduce a voltage provided by a bias power supply between the ground reference terminal of the chip to be tested and the power ground, so as to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so as to have a voltage difference between the ground terminal of the tester and the ground reference terminal of the chip to be tested;

[0016] In the high-speed data transmission test mode, the switch circuit controls the connection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, so that the ground reference terminal of the chip to be tested and the ground terminal are at the same potential.

[0017] Optionally, the test signal includes a forward test signal and a reverse test signal;

[0018] When the forward test signal is transmitted along an unexpected propagation path in the chip under test, no path is formed in the chip under test;

[0019] When the reverse test signal is transmitted along an unexpected propagation path in the chip under test, a path is formed in the chip under test.

[0020] Optionally, the switch circuit includes a capacitor and a switch, one end of the capacitor is electrically connected to a ground terminal, and the other end is electrically connected to a ground reference terminal of the chip to be tested, and two ends of the switch are connected in parallel to two ends of the capacitor.

[0021] Optionally, the test end is provided with a power supply terminal, a ground terminal and a test terminal, the power supply terminal is electrically connected to the power input terminal of the chip to be tested, the ground terminal is electrically connected to the ground reference terminal of the chip to be tested, and the test terminal is electrically connected to the test port of the chip to be tested;

[0022] The power supply terminal is used to provide power to the chip under test;

[0023] The switch circuit and the bias power supply are electrically connected to the chip to be tested via a ground terminal;

[0024] The test terminal is used to transmit the test signal to the chip to be tested.

[0025] Optionally, a ground diode is provided in the chip to be tested, the positive electrode of the ground diode is electrically connected to the ground reference terminal of the chip to be tested, and the negative electrode of the ground diode is electrically connected to the test port.

[0026] Optionally, the testing machine comprises:

[0027] The main control circuit is used to generate a test signal, respond to the feedback signal of the chip under test, and control the switch circuit to close or open;

[0028] A power supply circuit, used to supply power to the test machine and the chip under test;

[0029] The main control circuit is electrically connected to the switch circuit and the test terminal, and the power supply circuit is electrically connected to the power supply terminal and the bias power supply.

[0030] The present invention further provides a chip testing method. Based on the above chip testing system, the testing method includes:

[0031] In the contact test mode, the switch circuit is controlled to be disconnected to control the disconnection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, and the bias power supply is controlled to provide a stable voltage to the ground reference terminal of the chip to be tested to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so that there is a voltage difference between the ground terminal of the tester and the ground reference terminal of the chip to be tested;

[0032] In the high-speed data transmission test mode, the switch circuit is controlled to be closed to control the connection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, so that the ground reference terminal of the chip to be tested and the ground terminal are at the same potential.

[0033] Optionally, in the contact test mode, the step of controlling the switch circuit to be disconnected to control the disconnection between the ground terminal and the ground reference terminal of the chip to be tested, and controlling the bias power supply to provide a stable voltage to the ground reference terminal of the chip to be tested to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground also includes:

[0034] Generate a set of forward / reverse test signals;

[0035] Based on the chip under test receiving the test signal, the measuring module in the tester obtains the current information in the chip under test and transmits the current information to the main control module, and the main control module determines whether the chip under test forms a path based on the current current information and the expected current information;

[0036] Under the positive test signal, the main control module determines that the chip under test does not form a path, and then determines that the chip under test is abnormal;

[0037] Under the reverse test signal, the main control module determines that the chip under test forms a path, and then determines that the chip under test has an abnormality.

[0038] The present invention proposes a chip testing system and a testing method thereof, which introduces a bias power supply between the ground reference terminal of the chip to be tested and the power ground of the testing system to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so that there is a voltage difference between the ground terminal and the ground reference terminal of the chip to be tested, so that the tester can perform reverse testing on the electronic components in the chip to be tested without a negative voltage power supply, thereby reducing the cost of the tester. At the same time, a switch circuit is provided between the ground terminal of the tester and the ground reference terminal of the chip to be tested, and the voltage difference between the ground reference terminal and the ground terminal of the chip to be tested is controlled by controlling the closing and opening of the switch circuit, so that this test structure meets the different requirements of contact testing and high-speed data transmission testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0040] Figure 1 A structural diagram of a chip testing system of the present invention;

[0041] Figure 2 A logical structure diagram of an embodiment of a chip testing system of the present invention;

[0042] Figure 3 The present invention is a flowchart of a chip testing method.

[0043] Description of the reference numerals: test machine 01, switch circuit 02, bias power supply 03, chip to be tested 04.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0047] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] The present invention provides a chip detection system, such as Figure 1 As shown, the detection system includes:

[0050] The test machine 01 generates at least one set of forward / reverse test signals and outputs them to the chip under test 04 in sequence according to the test process, so that the chip under test 04 executes the test program according to the forward / reverse test signals and generates test results. The test machine 01 is used to receive the test results fed back by the chip under test 04 to detect abnormal conditions of the chip under test 04;

[0051] The test machine 01 has a ground terminal electrically connected to a power ground;

[0052] The switch circuit 02 is used to control the connection or disconnection between the ground terminal and the ground reference terminal of the chip to be tested 04;

[0053] The bias power supply 03 is used to provide a stable voltage to the ground reference terminal of the chip under test 04 when the ground terminal and the ground reference terminal of the chip under test 04 are disconnected, so as to increase the potential of the ground reference terminal of the chip under test 04 relative to the power ground.

[0054] More specifically, the traditional tester 01 often needs to have a negative voltage for measurement when performing DC testing. By providing a negative voltage, the test circuit can cover the entire voltage range in which the chip IO may work, thereby ensuring the comprehensiveness of the test. In some application scenarios, the chip IO may receive a negative voltage signal. Therefore, these actual application scenarios can be simulated by the negative voltage test circuit to verify the compatibility and stability of the chip IO. The negative voltage test circuit can also be used to detect the behavior of the chip IO under abnormal voltage conditions, such as testing of functions such as overvoltage protection and undervoltage lockout.

[0055] Among them, the methods of achieving negative voltage include:

[0056] Using a negative voltage tester 01, these devices are usually highly accurate and versatile, and can meet a variety of complex testing needs. At the same time, power chips that support negative voltages are often complex in structure and costly.

[0057] Self-made test circuit with negative voltage, if there is no test machine with negative voltage 01, negative voltage can be provided by self-made test circuit. This usually requires the use of some electronic components to build a voltage divider circuit, voltage follower, adder, etc. to achieve the required voltage range and accuracy.

[0058] Compared with the test machine 01 with negative voltage, the test circuit has lower cost. By selecting appropriate electronic components and circuit design, the cost can be reduced while ensuring performance; the test circuit can be flexibly designed and adjusted according to different test requirements. For example, the output range and accuracy of the negative voltage can be changed by changing the circuit parameters; the test circuit is usually composed of relatively simple electronic components, so it is easy to maintain and repair, and once a fault occurs, the problem can be easily found and repaired.

[0059] The present invention generates a set of forward / reverse test signals, and the test signals include forward test signals and reverse test signals; more specifically, the test signals can be forward current and reverse current, and these currents can be forward current (used to test a diode connected to a power supply) or negative current (used to test a diode connected to ground). The forward current is used to simulate the normal current flow from the power supply to the diode, and the reverse current is used to simulate the abnormal or reverse flow from the diode to the ground. The forward current and reverse current are taken as examples below.

[0060] The chip under test 04 executes the test program according to the test signal and generates a test result. The test machine 01 is used to receive the test result fed back by the chip under test 04 to detect abnormal conditions of the chip under test 04 .

[0061] Under the forward test signal, the current value (forward current) flowing through the diode and the voltage drop at this time are recorded, and the test result is fed back to the test machine 01. Based on the current current information and the expected current information, the test machine 01 determines that it is an open circuit if the measured value is greater than the preset high limit value; if the measured value is less than the preset low limit value, it is determined to be a short circuit.

[0062] Under the reverse test signal, the current value (reverse leakage current) flowing through the diode is recorded, and the test result is fed back to the test machine 01. Based on the current current information and the expected current information, the test machine 01 determines that the circuit is open if the measured value is less than the preset lower limit.

[0063] In the present invention, the reverse test signal is controlled by the switch circuit 02 and the bias power supply 03. The bias power supply 03 is used to provide a stable voltage to the ground reference terminal of the chip under test 04 when the ground terminal and the ground reference terminal of the chip under test 04 are disconnected, so as to increase the potential of the ground reference terminal of the chip under test 04 relative to the power ground.

[0064] The control switch circuit 02 is disconnected, and the switch circuit 02 controls the ground terminal and the ground reference terminal of the chip to be tested 04 to be disconnected. The voltage provided by the bias power supply 03 is introduced between the ground reference terminal of the chip to be tested 04 and the power ground to increase the potential of the ground reference terminal of the chip to be tested 04 relative to the power ground, so that there is a voltage difference between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04; the voltage difference is used to provide a negative current output by the test machine to the chip to be tested.

[0065] At the same time, the control switch circuit 02 is closed so that the ground reference terminal of the chip under test 04 is at the same potential as the ground terminal. Furthermore, the digital logic chip is used in the test to perform high-speed data transmission test, and the ground voltage of the chip under test 04 is consistent with that of the digital logic chip, meeting the requirements of the high-speed data transmission test, and detecting the chip under test 04 without being affected by the digital logic chip.

[0066] The present invention introduces a bias power supply 03 between the ground reference terminal of the chip to be tested 04 and the power ground of the test system to increase the potential of the ground reference terminal of the chip to be tested 04 relative to the power ground, so that there is a voltage difference between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04, so that the test machine 01 can perform reverse testing on the electronic components in the chip to be tested 04 without a negative power supply, thereby reducing the cost of the test machine 01.

[0067] At the same time, a switch circuit 02 is provided between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04. The voltage difference between the ground reference terminal and the ground terminal of the chip to be tested 04 is controlled by controlling the closing and opening of the switch circuit 02, so that this test structure can meet the different requirements of contact testing and high-speed data transmission testing, so that the test machine can adapt to the switching of different tests.

[0068] In one embodiment, the test machine 01 has a detection terminal, which is used to access the chip under test 04; the detection terminal of the test machine 01 is the interface between the test system and the chip under test. These detection terminals are connected to the chip under test through physical connections (such as sockets, probes, etc.) and electrical connections (such as signal lines, power lines, etc.). The main function of the detection terminal is to provide the required test signals (such as voltage, current, clock signals, etc.) to the chip under test and receive the output signals (such as data signals, status signals, etc.) of the chip under test.

[0069] One end of the switch circuit 02 is electrically connected to the ground terminal, and the other end is electrically connected to the ground reference terminal of the chip to be tested 04; by opening / closing the switch circuit 02, the ground reference terminal of the chip to be tested 04 and the ground terminal can be disconnected / connected. When the switch circuit 02 is opened, there is a voltage difference between the ground reference terminal of the chip to be tested 04 and the ground terminal; when the switch circuit 02 is closed, the ground reference terminal of the chip to be tested 04 and the ground terminal are at the same potential.

[0070] One end of the bias power supply 03 is electrically connected to the ground reference end of the chip under test 04, and the other end is electrically connected to the power ground. By introducing the bias power supply 03 between the ground reference end of the chip under test 04 and the power ground of the test system, the potential of the ground reference end of the chip under test 04 relative to the power ground is increased.

[0071] In one embodiment, the detection system has a contact test mode and a high-speed data transmission test mode. The present invention controls the voltage difference between the ground reference terminal and the ground terminal of the chip to be tested 04 by controlling the closing and opening of the switch circuit 02, so that this test structure meets the different requirements of the contact test and the high-speed data transmission test, so that the test machine 01 can adapt to the switching of different tests.

[0072] In the contact test mode, the switch circuit 02 controls the ground terminal and the ground reference terminal of the chip to be tested 04 to be disconnected, so as to introduce the voltage provided by the bias power supply 03 between the ground reference terminal of the chip to be tested 04 and the power ground, so as to increase the potential of the ground reference terminal of the chip to be tested 04 relative to the power ground, so that there is a voltage difference between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04.

[0073] Contact test (Open-Short test) is the first step in chip testing. The main purpose of this test is to confirm whether all signal pins are open or short. If open or short occurs, the following tests will be meaningless, so Open-Short test is usually the first test item.

[0074] In this test mode, the switch circuit 02 controls the disconnection between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04. The present invention realizes reverse detection of the chip to be tested 04 by increasing the potential of the ground reference terminal of the chip to be tested 04 relative to the power ground, so that the test system is capable of testing similar structures such as on-chip diodes without supporting negative voltages.

[0075] In the high-speed data transmission test mode, the switch circuit 02 controls the connection between the ground terminal of the tester 01 and the ground reference terminal of the chip under test 04, so that the ground reference terminal of the chip under test 04 and the ground terminal are at the same potential.

[0076] The main purpose of the high-speed data transmission test mode is to evaluate the performance, stability and reliability of the device or chip under high-speed data transmission conditions. Through testing, it can be ensured that the device or chip can meet the design requirements and show good performance in actual applications.

[0077] High-speed data transmission test mode usually includes the following test methods:

[0078] Transmission speed test: Measures the transmission speed of a device or chip by sending and receiving high-speed data streams; evaluates the bandwidth and latency performance of a device or chip during high-speed data transmission.

[0079] Transmission quality test: Check parameters such as bit error rate, signal-to-noise ratio and channel amplitude during data transmission; evaluate the precision and accuracy of the device or chip during data transmission.

[0080] Signal integrity test: Use an oscilloscope or other test equipment to measure waveform characteristics such as amplitude, edges, and glitches; evaluate whether the signal maintains integrity during transmission, and whether there are problems such as signal reflection and jitter.

[0081] Conformance testing: Verify that the output signal of a device or chip complies with industry-specific serial data standards; ensure plug-and-play compatibility between multiple vendors and products.

[0082] In this embodiment, if Figure 2As shown, a digital logic chip is used in the test to perform a high-speed data transmission test. The ground voltage of the chip under test 04 is consistent with that of the digital logic chip, meeting the requirements of the high-speed data transmission test, and detecting the chip under test 04 without being affected by the digital logic chip.

[0083] In one embodiment, the test signal includes a forward test signal and a reverse test signal;

[0084] When the forward test signal is transmitted along an unexpected propagation path in the chip under test 04, no path is formed in the chip under test 04;

[0085] When the reverse test signal is transmitted along an unexpected propagation path in the chip under test 04 , a path is formed in the chip under test 04 .

[0086] Furthermore, when the tester 01 transmits the forward test signal to the chip under test 04, if the forward test signal is transmitted along the expected propagation path, the transmission path is completed in the chip under test 04. If the forward test signal fails to form the expected path, it may indicate that there is a fault inside the chip, such as an open circuit, a short circuit or a component failure.

[0087] When the tester 01 transmits the reverse test signal to the chip under test 04, if the reverse test signal is transmitted along the expected propagation path, no path will be formed. If the reverse test signal may be transmitted along an unexpected path due to some reason (such as design defects, manufacturing errors or external interference) and accidentally forms a path, the test confirms that the internal device of the chip under test 04 is faulty.

[0088] In one embodiment, the switch circuit 02 includes a capacitor and a switch, one end of the capacitor is electrically connected to the ground terminal, and the other end is electrically connected to the ground reference terminal of the chip to be tested 04, and the two ends of the switch are connected in parallel to the two ends of the capacitor. The capacitor can achieve electrical isolation between the ground reference terminal and the ground terminal of the chip to be tested 04. The capacitor can be used as a decoupling element to reduce noise and fluctuations on the power line. When the switch is closed, the capacitor can quickly absorb or release charge, thereby stabilizing the power supply voltage.

[0089] In one embodiment, the detection end is provided with a power supply terminal, a ground terminal and a test terminal, the power supply terminal is electrically connected to the power input terminal of the chip to be tested 04, the ground terminal is electrically connected to the ground reference terminal of the chip to be tested 04, and the test terminal is electrically connected to the test port of the chip to be tested 04;

[0090] The power supply terminal is used to provide power to the chip under test 04 ; it is the basis for ensuring that the chip under test 04 can work normally and respond to the test signal.

[0091] The switch circuit 02 and the bias power supply 03 are electrically connected to the chip to be tested 04 via the ground terminal;

[0092] The test terminal is used to transmit test signals to the chip under test 04. These test signals may include various analog or digital signals, which are used to evaluate the performance of the chip under test 04 under different conditions.

[0093] The detection end establishes a comprehensive electrical connection with the chip under test 04 through the power supply terminal, the ground terminal and the test terminal. This design allows the test system to perform detailed performance testing and verification on the chip under test 04, thereby ensuring that it can work normally in actual applications and meet the design requirements.

[0094] In one embodiment, if Figure 2 As shown, a ground diode is provided inside the chip to be tested 04, the positive electrode of the ground diode is electrically connected to the ground reference terminal of the chip to be tested 04, and the negative electrode of the ground diode is electrically connected to the test port. In this embodiment, the test machine 01 includes a PMU (Power Measurement Unit) and a digital logic chip. The PMU in the test machine 01 is responsible for sending test signals to the chip to be tested 04, and receiving and analyzing response signals from the chip to be tested 04. Through the PMU test machine 01, a comprehensive evaluation of chip performance, including speed, power consumption, stability, etc., can be achieved. The digital logic chip is used in the test machine 01 to realize functions such as generation, encoding, decoding and comparison of test signals. The digital logic chip is also responsible for controlling various parts of the test machine 01 to ensure the smooth progress of the test process.

[0095] The PMU is used to provide a negative current to the chip under test 04 and measure the voltage value. If the measured value is less than the preset lower limit, the diode to ground is judged to be open. In this embodiment, the transmission of negative current is achieved by increasing the ground potential of the chip under test 04.

[0096] It is worth noting that the PMU is used to provide a forward current to the chip under test 04 and measure the voltage value. If the measured value is greater than the preset high limit, it is judged as an open circuit; if the measured value is less than the preset low limit, it is judged as a short circuit. It is used to measure whether the diode at the power supply end is normal.

[0097] In one embodiment, the test machine 01 includes:

[0098] The main control circuit is used to generate a test signal, respond to the feedback signal of the chip under test 04, and control the switch circuit 02 to close or open;

[0099] A power supply circuit, used to supply power to the test machine 01 and the chip under test 04;

[0100] The main control circuit electrically connects the switch circuit 02 and the test terminal, and the power supply circuit electrically connects the power supply terminal and the bias power supply 03. Based on the test signal received by the chip under test 04, the measurement module in the test machine 01 obtains the current information in the chip under test 04, and transmits the current information to the main control module. The main control module determines whether the chip under test 04 forms a path based on the current current information and the expected current information. Under the forward test signal, the main control module determines that the chip under test 04 does not form a path, and then determines that the chip under test 04 is abnormal. Under the reverse test signal, the main control module determines that the chip under test 04 forms a path, and then determines that the chip under test 04 is abnormal.

[0101] The present invention also provides a chip detection method, such as Figure 3 As shown, based on the above chip detection system, in this embodiment, the tester 01 includes a PMU and a digital logic chip.

[0102] In the contact test mode, the control switch circuit 02 is disconnected to control the disconnection between the ground terminal of the test machine 01 and the ground reference terminal of the chip to be tested 04, and the bias power supply 03 is controlled to provide a stable voltage to the ground reference terminal of the chip to be tested 04 to increase the potential of the ground reference terminal of the chip to be tested 04 relative to the power ground.

[0103] In the high-speed data transmission test mode, the control switch circuit 02 is closed to control the connection between the ground terminal of the tester 01 and the ground reference terminal of the chip under test 04, so that the ground reference terminal of the chip under test 04 and the ground terminal are at the same potential. Furthermore, a digital logic chip is used in the test to perform a high-speed data transmission test, and the ground voltage of the chip under test 04 is kept consistent with that of the digital logic chip, meeting the requirements of the high-speed data transmission test, and detecting the chip under test 04 without being affected by the digital logic chip.

[0104] In one embodiment, in the contact test mode, the step of controlling the switch circuit 02 to be disconnected to control the disconnection between the ground terminal and the ground reference terminal of the chip under test 04, and controlling the bias power supply 03 to provide a stable voltage to the ground reference terminal of the chip under test 04 to increase the potential of the ground reference terminal of the chip under test 04 relative to the power ground also includes:

[0105] Step S100: In the contact test mode, a set of forward / reverse test signals is generated; in this embodiment, the PMU can provide a small current to each pin of the chip under test 04 to drive the protection diode for testing. These currents can be forward currents (for testing diodes connected to the power supply) or negative currents (for testing diodes connected to the ground).

[0106] Step S200: Control the switch circuit 02 to be disconnected, the switch circuit 02 controls the ground terminal to be disconnected from the ground reference terminal of the chip under test 04, and introduces the voltage provided by the bias power supply 03 between the ground reference terminal of the chip under test 04 and the power ground to increase the potential of the ground reference terminal of the chip under test 04 relative to the power ground, so that there is a voltage difference between the ground terminal of the test machine 01 and the ground reference terminal of the chip under test 04;

[0107] This voltage difference is used to provide negative current.

[0108] Step S300: Based on the chip under test 04 receiving the test signal, the measurement module in the test machine 01 obtains the current information in the chip under test 04, and transmits the current information to the main control module. The main control module determines whether the chip under test 04 forms a path based on the current current information and the expected current information;

[0109] Step S400: Under the positive test signal, the main control module determines that the chip under test 04 does not form a path, and then determines that the chip under test 04 is abnormal;

[0110] Use the PMU to supply a forward current to the pin to be tested and measure the voltage. If the measured value is greater than the preset upper limit, it is judged as an open circuit; if the measured value is less than the preset lower limit, it is judged as a short circuit.

[0111] Step S500: Under the reverse test signal, the main control module determines that the chip under test 04 forms a path, and then determines that there is an abnormality in the chip under test 04. Use the PMU to provide a negative current to the pin under test and measure the voltage value. If the measured value is less than the preset lower limit, it is determined to be an open circuit.

[0112] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A chip testing system, characterized in that: The test system comprises: A tester generates at least one set of forward / reverse test signals and outputs them to the chip under test in sequence according to the test process, so that the chip under test executes the test program according to the forward / reverse test signals and generates test results. The tester is used to receive the test results fed back by the chip under test to detect abnormal conditions of the chip under test; The test machine has a ground terminal electrically connected to a power ground; A switch circuit, used for controlling the connection or disconnection between the ground terminal and the ground reference terminal of the chip to be tested; The bias power supply is used to provide a stable voltage to the ground reference terminal of the chip to be tested when the ground terminal and the ground reference terminal of the chip to be tested are disconnected, so as to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground.

2. The chip testing system according to claim 1, characterized in that: The test machine has a test terminal, and the test terminal is used to access the chip to be tested; One end of the switch circuit is electrically connected to the ground terminal, and the other end is electrically connected to the ground reference terminal of the chip to be tested; One end of the bias power supply is electrically connected to the ground reference end of the chip to be tested, and the other end is electrically connected to the power ground.

3. The chip testing system according to claim 1, characterized in that: The test system has a contact test mode and a high-speed data transmission test mode; In the contact test mode, the switch circuit controls the ground terminal to be disconnected from the ground reference terminal of the chip to be tested, so as to introduce a voltage provided by a bias power supply between the ground reference terminal of the chip to be tested and the power ground, so as to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so as to have a voltage difference between the ground terminal of the tester and the ground reference terminal of the chip to be tested; In the high-speed data transmission test mode, the switch circuit controls the connection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, so that the ground reference terminal of the chip to be tested and the ground terminal are at the same potential.

4. The chip testing system according to any one of claims 1 to 3, characterized in that: The test signal includes a forward test signal and a reverse test signal; When the forward test signal is transmitted along an unexpected propagation path in the chip under test, no path is formed in the chip under test; When the reverse test signal is transmitted along an unexpected propagation path in the chip under test, a path is formed in the chip under test.

5. The chip testing system according to claim 2, characterized in that: The switch circuit includes a capacitor and a switch. One end of the capacitor is electrically connected to the ground end, and the other end is electrically connected to the ground reference end of the chip to be tested. Both ends of the switch are connected in parallel to both ends of the capacitor.

6. The chip testing system according to claim 2, characterized in that: The test end is provided with a power supply terminal, a ground terminal and a test terminal, the power supply terminal is electrically connected to the power input terminal of the chip to be tested, the ground terminal is electrically connected to the ground reference terminal of the chip to be tested, and the test terminal is electrically connected to the test port of the chip to be tested; The power supply terminal is used to provide power to the chip under test; The switch circuit and the bias power supply are electrically connected to the chip to be tested via a ground terminal; The test terminal is used to transmit the test signal to the chip to be tested.

7. The chip testing system according to claim 6, characterized in that: A ground diode is provided in the chip to be tested, the positive electrode of the ground diode is electrically connected to the ground reference terminal of the chip to be tested, and the negative electrode of the ground diode is electrically connected to the test port.

8. The chip testing system according to claim 6, characterized in that: The testing machine comprises: The main control circuit is used to generate a test signal, respond to the feedback signal of the chip under test, and control the switch circuit to close or open; A power supply circuit, used to supply power to the test machine and the chip under test; The main control circuit is electrically connected to the switch circuit and the test terminal, and the power supply circuit is electrically connected to the power supply terminal and the bias power supply.

9. A chip testing method, characterized in that: Based on the chip testing system according to any one of claims 1 to 8, the testing method comprises: In the contact test mode, the switch circuit is controlled to be disconnected to control the disconnection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, and the bias power supply is controlled to provide a stable voltage to the ground reference terminal of the chip to be tested to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground, so that there is a voltage difference between the ground terminal of the tester and the ground reference terminal of the chip to be tested; In the high-speed data transmission test mode, the switch circuit is controlled to be closed to control the connection between the ground terminal of the tester and the ground reference terminal of the chip to be tested, so that the ground reference terminal of the chip to be tested and the ground terminal are at the same potential.

10. The chip testing method according to claim 9, characterized in that: The step of controlling the switch circuit to be disconnected in the contact test mode to control the ground terminal to be disconnected from the ground reference terminal of the chip to be tested, and controlling the bias power supply to provide a stable voltage to the ground reference terminal of the chip to be tested to increase the potential of the ground reference terminal of the chip to be tested relative to the power ground also includes: Generate a set of signal positive / reverse test signals; Based on the chip under test receiving the test signal, the measuring module in the tester obtains the current information in the chip under test and transmits the current information to the main control module, and the main control module determines whether the chip under test forms a path based on the current current information and the expected current information; Under the positive test signal, the main control module determines that the chip under test does not form a path, and then determines that the chip under test is abnormal; Under the reverse test signal, the main control module determines that the chip under test forms a path, and then determines that the chip under test has an abnormality.

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