Clock calibration circuit

Abstract

The embodiment of the invention provides a clock calibration circuit. The circuit comprises a first sampling circuit; the second sampling circuit is connected with the first sampling circuit in series; the first sampling circuit comprises a phase-locked loop (PLL); a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; the first data serializer is connected with the first DCC in series, the second data serializer is connected with the first DCC in series, the second sending driver is connected with the second data serializer in series, and the PLL is used for outputting a clock signal so as to drive the first data serializer to send data to be sent to the first sending driver and drive the second data serializer to send a feedforward clock signal to the second sending driver; and the second sending driver is used for sending the feed-forward clock signal to the first receiving driver of the second sampling circuit so as to determine the feed-forward clock signal as a sampling clock of the second sampling circuit.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular, to a clock calibration circuit. Background Art

[0002] In the prior art, the packaging integration of multiple bare cores has been widely used in the semiconductor industry, including mainstream central processing units (CPUs) and general-purpose graphics processor units (GP-GPUs). The development of small chips in packages is driven by many factors. At present, the cross-die (unpackaged chip particles) or cross-package sampling clock calibration technologies in the chiplet (chiplet interconnection) field mainly include the CDR (Clock and Data Recovery) technology commonly used by serdes (Serializer / Deserializer) - clock data recovery technology; AIB, UCIe (Universal chipletInterconnect Express, unified chiplet interconnection protocol) and other technologies use clock feedforward (clock-forwarding) technology - the clock of the sending data is simultaneously fed forward to the receiving side to sample the received data.

[0003] Figure 1 is a chiplet sampling diagram in the prior art, such as Figure 1 As shown in the figure, the data clock layout and routing needs to be done in the back end. When DQS is sampled to RX, it passes through DLL (R90), which makes the DQS phase shift 90 degrees from IO output to RX FIFO clock input point, as shown in the figure. Figure 1 It is located in the data center. The technical difficulty of implementing this solution is to ensure that the total delay of DLL + clock tree = T / 4. This technology is based on a 4GHz clock, that is, T / 4 = 62.5ps. For a parallel port architecture that drives multiple lanes (channels), such as 40 to 64 lanes, the clock tree best coner (best process corner: the best range of process parameter changes) is usually 70 to 80ps under 3nm or 5nm processes, and the worst conner (refers to the process corner that causes the largest clock tree delay) is more than 120ps.

[0004] Figure 2 This is a structural diagram of a 90-degree phase shift generated on the transmitting side in the prior art, such as Figure 2 As shown, Figure 2 The implementation method in the example is to align the data and clock on the TX side and the data and clock on the RX side at the back end. When working, a 90-degree phase shift can be generated on the transmitting side through detection, and the sampling clock on the receiving side is aligned with the center of the data. Figure 2The implementation scheme in has the following shortcomings: the sending side fwdclk (the clock signal on the sending side) needs to copy txclk (the clock on the sending side) to drive the distributed clock tree of multiple lanes to ensure that the IO output port txdat of the left circuit is aligned with fwdclk (after fwdclk is adjusted 90 degrees, the fwdclk edge is aligned with the data center).

[0005] In the clock calibration circuit of the prior art, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes problems such as delay deviation in the circuit, and no effective solution has been proposed yet.

[0006] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology. Summary of the invention

[0007] An embodiment of the present application provides a clock calibration circuit to at least solve the problem that in the clock calibration circuit of the prior art, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes delay deviation in the circuit.

[0008] According to one aspect of an embodiment of the present application, a clock calibration circuit is provided, comprising: a first sampling circuit; and a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit comprises: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmitting driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC, and a second transmitting driver connected in series with the second data serializer, wherein the PLL is used to output a clock signal to drive the first data serializer to send the data to be sent to the first transmitting driver, and to drive the second data serializer to send a feedforward clock signal to the second transmitting driver; and the second transmitting driver is used to send the feedforward clock signal to the first receiving driver in the second sampling circuit to determine the feedforward clock signal as the sampling clock of the second sampling circuit.

[0009] In an exemplary embodiment, the second sampling circuit includes: a second receiving driver connected in series with the first sending driver, used to receive the data to be sent sent by the first sending driver, and send the data to be sent to a first data deserializer connected in series with the small delay buffer through a small delay buffer connected in series with the second receiving driver.

[0010] In an exemplary embodiment, the second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer respectively, and is used to compensate for the intrinsic delay of the first DCC.

[0011] In an exemplary embodiment, the second sampling circuit includes: a second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree, wherein the first receiving driver is used to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

[0012] In an exemplary embodiment, the second sampling circuit includes: a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer, respectively, to supplement the intrinsic delay of the second PI.

[0013] In an exemplary embodiment, the second sampling circuit includes: a third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is used to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links correspond to different transmission drivers respectively.

[0014] In an exemplary embodiment, the first sampling circuit includes: a third PI connected in series with the first clock tree and the first data serializer, respectively, and configured to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, wherein the multiple data links and the TRACK links correspond to different transmission drivers, respectively.

[0015] In an exemplary embodiment, the second sampling circuit includes: a first data checking module, connected in series with the first data deserializer and the second PI, respectively, for adjusting the delay value of the second PI during data link training; and / or a second data checking module, connected in series with the second data deserializer and the second PI, respectively, for adjusting the delay value of the second PI during TRACK link training.

[0016] In an exemplary embodiment, the second sampling circuit includes: a first delay locked loop DLL, which is connected in series with the second clock tree and the first data deserializer respectively; the second sampling circuit also includes: a second DLL, which is connected in series with the second clock tree and the second data deserializer respectively.

[0017] In an exemplary embodiment, the second sampling circuit includes: a third DLL, which is connected in series with the second DCC and the second PI, respectively, and is used to delay multiple data links and TRACK links, wherein the multiple data links and the TRACK links correspond to different transmission drivers, respectively.

[0018] According to the present application, a clock calibration circuit includes: a first sampling circuit; a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit includes: a phase-locked loop PLL; a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC, and a second transmission driver connected in series with the second data serializer, wherein the PLL is used to output a clock signal to drive the first data serializer to send the data to be sent to the first transmission driver The invention relates to a device for transmitting a feedforward clock signal to the second transmitting driver, and driving the second data serializer to transmit a feedforward clock signal to the second transmitting driver; the second transmitting driver is used to transmit the feedforward clock signal to the first receiving driver in the second sampling circuit, so as to determine the feedforward clock signal as the sampling clock of the second sampling circuit, thereby solving the problem that in the clock calibration circuit of the prior art, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side is prone to cause delay deviation in the circuit, and then the second sampling circuit on the receiving side can perform clock calibration according to the feedforward clock signal sent by the first sampling circuit, thereby avoiding the problem that in the prior art, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side is prone to cause delay deviation in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The exemplary embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a schematic diagram of chiplet sampling in the prior art;

[0021] Figure 2 It is a schematic diagram of a structure in which a 90-degree phase shift is generated on the transmitting side in the prior art;

[0022] Figure 3 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present application;

[0023] Figure 4 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present application;

[0024] Figure 5 is a PI logic block diagram according to an embodiment of the present application;

[0025] Figure 6 is an optional calibration process diagram according to an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of eye diagram alignment according to an embodiment of the present application;

[0027] Figure 8 is a diagram of alignment of TRACK data boundary and clock edge according to an embodiment of the present application;

[0028] Fig. 9 is a graph of a sampling clock drifting to the right according to an embodiment of the present application;

[0029] Fig.10 is a circuit diagram of a clock calibration circuit according to an embodiment of the present application;

[0030] Fig.11 is another circuit diagram of a clock calibration circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Figure 3 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present application, such as Figure 3 As shown, the clock calibration circuit includes:

[0034] A first sampling circuit; and a second sampling circuit connected in series with the first sampling circuit; wherein,

[0035] The first sampling circuit includes: a phase-locked loop PLL 30; a first duty cycle calibrator DCC31 connected in series with the PLL; a first phase interpolator PI 32 connected in series with the first DCC 31; a first clock tree 33 connected in series with the first PI 32; a first data serializer 34 connected in series with the first clock tree 33; a first transmission driver 35 connected in series with the first data serializer 34;

[0036] a second data serializer 36 connected in series with the first DCC 31, and a second transmission driver 37 connected in series with the second data serializer 36, wherein the PLL 30 is used to output a clock signal to drive the first data serializer 34 to send the data to be sent to the first transmission driver 35, and drive the second data serializer 36 to send a feedforward clock signal to the second transmission driver 37;

[0037] The second transmission driver 37 is used to transmit the feedforward clock signal to the first reception driver 38 in the second sampling circuit, so as to determine the feedforward clock signal as the sampling clock of the second sampling circuit.

[0038] The embodiment of the present application provides a clock calibration circuit, including: a first sampling circuit; a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit includes: a phase-locked loop PLL; a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC, and a second transmission driver connected in series with the second data serializer, wherein the PLL is used to output a clock signal to drive the first data serializer to send the data to be transmitted to the first transmission driver , and drives the second data serializer to send a feedforward clock signal to the second sending driver; the second sending driver is used to send the feedforward clock signal to the first receiving driver in the second sampling circuit to determine the feedforward clock signal as the sampling clock of the second sampling circuit, which solves the problem that in the clock calibration circuit of the prior art, the clock calibration process of the first sampling circuit on the sending side and the second sampling circuit on the receiving side is prone to cause delay deviation in the circuit, and then the second sampling circuit on the receiving side can perform clock calibration according to the feedforward clock signal sent by the first sampling circuit, avoiding the problem that the clock calibration process of the first sampling circuit on the sending side and the second sampling circuit on the receiving side in the prior art is prone to cause delay deviation in the circuit.

[0039] In an exemplary embodiment, the second sampling circuit includes: a second receiving driver connected in series with the first sending driver, used to receive the data to be sent sent by the first sending driver, and send the data to be sent to a first data deserializer connected in series with the small delay buffer through a small delay buffer connected in series with the second receiving driver.

[0040] It can be understood that the second receiving driver is used to receive the data to be sent sent by the first sending driver in the first sampling circuit, and when the second receiving driver receives the data to be sent, it sends the data to be sent to the first data deserializer through the small delay buffer. In other words, the transmission path of the data to be sent is: from the first sending driver to the second receiving driver, through the small delay buffer, to the first data deserializer.

[0041] In an exemplary embodiment, the second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer respectively, and is used to compensate for the intrinsic delay of the first DCC.

[0042] It can be understood that, in the above circuit, the DCC buffer is connected in series with the second receiving driver and the small delay buffer respectively, and the DCC buffer can be used to compensate for the intrinsic delay of the first DCC in the circuit, that is, the DCC buffer is used to compensate for the inherent delay of the DCC in the above circuit, that is, the time for the data to be sent to pass through the DCC from input to output.

[0043] In an exemplary embodiment, the second sampling circuit includes: a second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree, wherein the first receiving driver is used to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

[0044] It can be understood that the above-mentioned second sampling circuit is composed of a second DCC, a second PI, a second clock tree, a first data deserializer, a second data deserializer, etc., wherein the feedforward clock signal is sent to the first data deserializer and the second data deserializer respectively through the above-mentioned second DCC, the second PI and the second clock tree, in order to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

[0045] In an exemplary embodiment, the second sampling circuit includes: a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer, respectively, to supplement the intrinsic delay of the second PI.

[0046] It can be understood that, in the above circuit, the PI cache is connected in series with the second clock tree and the first data deserializer respectively, and the PI cache can be used to supplement the intrinsic delay of the second PI in the circuit, that is, the PI cache is used to supplement the inherent delay of the second PI in the above circuit, that is, the time it takes for the data to be sent to pass through the second PI from input to output.

[0047] In an exemplary embodiment, the second sampling circuit includes: a third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is used to be set to a fixed phase shift after the training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK link (which are basically consistent with the multiple data lane implementation circuits and can serve as a representative of data path delay) correspond to different transmit drivers respectively.

[0048] It can be understood that the second sampling circuit further includes: a third PI and a second data deserializer, wherein the third PI can be used to be set to a fixed phase shift after the training of multiple data links and TRACK links is completed.

[0049] In an exemplary embodiment, the first sampling circuit includes: a third PI connected in series with the first clock tree and the first data serializer, respectively, and configured to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, wherein the multiple data links and the TRACK links correspond to different transmission drivers, respectively.

[0050] In an exemplary embodiment, the second sampling circuit includes: a first data checking module, connected in series with the first data deserializer and the second PI, respectively, for adjusting the delay value of the second PI during data link training; and / or a second data checking module, connected in series with the second data deserializer and the second PI, respectively, for adjusting the delay value of the second PI during TRACK link training.

[0051] It can be understood that the above-mentioned second sampling circuit also includes: a first data checking module and / or a second data checking module, which can be used to adjust the delay value of the second PI during data link training and / or TRACK link training.

[0052] In an exemplary embodiment, the second sampling circuit includes: a first delay locked loop DLL, which is connected in series with the second clock tree and the first data deserializer respectively; the second sampling circuit also includes: a second DLL, which is connected in series with the second clock tree and the second data deserializer respectively.

[0053] It can be understood that the second sampling circuit further includes: a first delay phase-locked loop DLL and a second DLL.

[0054] In an exemplary embodiment, the second sampling circuit includes: a third DLL, which is connected in series with the second DCC and the second PI, respectively, and is used to delay multiple data links and TRACK links, wherein the multiple data links and the TRACK links correspond to different transmission drivers, respectively.

[0055] It can be understood that the above-mentioned second sampling circuit also includes: a third DLL, which is used to delay the processing of data link and TRACK link signals, and it can generate corresponding delay signals according to the input reference clock signal and control signal, thereby realizing delay control of data link and TRACK link signals.

[0056] The second DCC can control the delay of the third DLL and adjust the delay of the third DLL according to the input control signal, thereby achieving precise control of the delay of the data link and TRACK link signals.

[0057] In order to better understand the process of the above-mentioned clock calibration circuit, the implementation process of the above-mentioned clock calibration circuit is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0058] Next, the clock calibration circuit is further described in conjunction with the following embodiments.

[0059] The embodiments of the present application relate to a cross-die sampling clock calibration method, and more particularly to a cross-die sampling clock calibration technology in the chiplet field.

[0060] In the chiplet field, cross-die or cross-package sampling clock calibration technology is one of the key technologies. At present, the cross-die or cross-package sampling clock calibration technology in the chiplet field mainly includes CDR technology commonly used in serdes - clock data recovery technology; AIB, UCIe, etc. use clock feedforwarding technology - the clock of the transmitted data is fed forward to the receiving side to sample the received data.

[0061] The embodiment of the present application adopts clock feedforward (clock-forwarding) technology, which is a technology widely used in digital circuits to solve the problem of clock signal propagation delay and clock jitter in the circuit. In digital systems, clock signals are used to synchronize the operation of various components to ensure that they work at the right time. However, when the clock signal propagates in the circuit, due to factors such as delay and noise in the circuit, the clock signal may be jittered or delayed, thereby affecting the stability and performance of the system.

[0062] Clock feed-forward technology introduces an additional delay path in the circuit so that the clock signal can reach the target component in advance, thereby offsetting the propagation delay and reducing jitter. It is based on the principle that the propagation speed of the clock signal is faster than the propagation speed of the data signal. During the propagation of the clock signal, the clock signal is delivered to the target component that needs to be synchronized in advance to ensure that the target component can receive the clock signal at the correct time.

[0063] Clock feedforward technology can improve the reliability and performance of digital systems, reduce the impact of clock jitter on circuit operation, and enable the system to work more stably. It is widely used in high-speed digital circuits, timing circuits, and synchronous circuits.

[0064] One of the main functions of clock feedforward technology is sampling clock calibration, which is described as follows:

[0065] The feed-forward clock is calibrated to align with the receiving data center location and to be able to follow the drift of voltage and temperature during operation to meet the width requirements of the UCIe eye diagram (eye diagram used to analyze and diagnose optical signals in fiber-optic communication systems).

[0066] like Figure 1 , 2 The following are methods for aligning the output clock and data at the transmitter. One method is to directly generate a 90-degree phase-shifted sampling clock on the receiver side. The difficulty is that the clock tree on the receiver side is not easy to shorten, and the clock frequency cannot reach the 8GHz required by UCIe. The other method is to align the clock and data on both the transmitter and receiver sides, and use a copy clock tree and data pad delay to compensate for the receiver clock. The disadvantage is that it adds a lot of delay, increases power consumption, and has a relatively large delay skew (offset), which does not meet the eye width standard required by UCIe.

[0067] Among them, the clock tree refers to a tree structure used to synchronize the transmission and distribution of clock signals in the circuit. In digital circuit design, the clock signal is used to synchronize the operation of each logic gate to ensure that they are executed at the correct time interval. The design of the clock tree is to ensure that the clock signal can be accurately and stably transmitted to each logic gate to ensure the correct operation of the circuit.

[0068] Figure 4 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present application, such as Figure 4 As shown:

[0069] Among them, PLL: the abbreviation of PhaseLockedLoop, refers to the phase-locked loop; DLL: the abbreviation of Delay Loop Lock, refers to the delay phase-locked loop; DCC: the abbreviation of Duty Cycle Calibrater, refers to the accuracy requirement determined by the specific implementation frequency, usually requiring -0.02UI~0.02UI; DCC dummy: is a buffer to compensate for the DCC intrinsic delay, usually the delay is <10ps; Ser: the abbreviation of Serializer, refers to the data serializer; Des: the abbreviation of De-Serializer, refers to the data deserializer; PI: the abbreviation of Pahse interpolators, refers to the phase interpolator; PI dummy: is a buffer to compensate for the PI intrinsic delay, the intrinsic delay is <2ps; TX: refers to the transmit driver; RX: refers to the receiver; PD: Phase The abbreviation of detect refers to the phase detector; Deskew: an adjustable small delay line, about = 0.04UI (maximum delay of 5ps at 8Gbps); SBTX: the abbreviation of sideband, which refers to the sideband transmitter, and the operating frequency is generally 800MHz; SBRX: the abbreviation of sideband, which refers to the sideband receiver, and the operating frequency is generally 800MHz; (Among them, sideband data communication does not require calibration, SBTX sends data on the falling edge, and SBRX samples on the rising edge); TRACK: It is basically the same as the circuit implementation of multiple data lanes, and can be used as a representative of data path delay. Unlike the data lane, the clock input end of its des module has PI3 to achieve a 90-degree phase shift of the sampling clock.

[0070] Furthermore, the PLL output clock passes through the DCC (duty cycle calibrator) and then the phase interpolator PI1, and then drives the ser modules (parallel to serial) of multiple data lanes through the clock distribution (clock tree) to send data to TX (transmit driver); the ser module driving the TRACK lane sends fixed pattern data to TX. The DCC clock drives the ser module of the fwdclk lane to send fwdclk to TX as the sampling clock of the opposite die. Among them, the delay of the fwdclk path and the transmission data path does not need to be consistent.

[0071] The receiving side data lane (equivalent to the link in the above embodiment) and TRACK lane pass through RX (receiver), Dcc dummy (DCC intrinsic delay compensation buffer), deskew (adjusted small delay buffer, in order to align the deviation of each data lane) to des (deserializer). fwdclk is received by RX, passes through DCC and the distributed clock tree to the des modules of each data lane and TRACK lane as the sampling clock input. The receiving data path does not need to increase the delay to align with the sampling clock.

[0072] Figure 4 The DCC dummy and PI dummy are buffers that compensate for the intrinsic delay of DCC and PI.

[0073] Figure 5 is a PI logic block diagram according to an embodiment of the present application, such as Figure 5 As shown, there are 8-phase tap outputs in PI. Since there is a phase detector to track VT in 360 degrees and keep synchronization with the cycle, the phase delay of each of the 8 phases maintains a ratio with 360 degrees, so the 8-phase output clock is VT tracking compensated.

[0074] When 8:2, the 90-degree and 135-degree phase outputs are selected, PI=0, and the FOUT output is the FIN 90-degree phase-shifted clock.

[0075] It should be noted that this is only an example based on the embodiment of the present application and is not limited to the use of this structure. For example, PI1 and PI2 in the embodiment can also be replaced by DLL1 and DLL2.

[0076] like Figure 4 , 5 As shown, the sending side data lane input: PRBS (Pseudo-Random Binary Sequence) pseudo-random sequence / fixed pattern and tx_dat (upper layer normal data); TRACK lane input: PRBS pseudo-random sequence / fixed pattern; PRBS pseudo-random sequence / fixed pattern is used for initialization training.

[0077] Among them, the sending clock tree of the sending side is connected to PI1, the sampling clock tree of the receiving side is connected to PI2, and the sampling clock is connected to PI3 to the clock input of the TRACK lane (link channel) after passing through the clock tree. PI1 and PI2 are variable delay lines used for training or VT tracking. PI3 initially has only intrinsic delay. After the data lane and TRACK lane are trained and work normally, they need to be set to a fixed 90-degree phase shift to ensure that the sampling clock is located at the right boundary of the TRACK data.

[0078] Among them, on the receiving side, the PD phase detector is located at the data input and sampling clock input of the des module of the TRACK lane. During initialization, the clock on the TRACK and the fwdclk clock are phase-locked, because the TRACK is basically equivalent to one of the data lanes, and locking the TRACK and fwdclk clocks is equivalent to locking the data lane and fwdclk clock delay. The PD output is transferred to the transmitting end through the sideband to adjust the delay value of PI1, or directly adjust the delay value of PI2 on this side.

[0079] Among them, the data check module on the data lane is used to adjust the PI2 delay value during data lane training; the data check module on the TRACKlane is used to adjust the PI2 delay value during data lane training, and track VT to adjust the PI2 delay value during normal work.

[0080] It should be noted that, in the back-end implementation of the optional embodiment of the present invention, 1) the delay deviation between path2 and path3 needs to be minimized (for example, UCIe requires <0.14UI, UI is a data width, usually txclk cycle / 2); 2) the delay deviation between multiple data lanes and multiple Path2s of TRACK lanes needs to be minimized (according to UCIe requirements <0.04UI); 3) path1 and path4 are located in different Dies, involving different processes and different conners, and the deviation requirements are relatively loose, generally <0.5UI, but the clock tree is as short as possible, and the deviation of the two clock trees is as small as possible to reduce the delay change when VT changes;

[0081] It should be noted that the embodiment of the present invention initializes and calibrates path1+path2=path3+path4 after power-on reset. At this time, the entire link, the deskew buffer (buffer used to correct signal delay) has only intrinsic delay, generally about 1ps. Path1+path2=path3+path4 is calibrated by the PD phase detection located at die2. If path1+path2 is short, PI1 is increased, and vice versa. At this time, PI3 has only intrinsic delay. The control signal 1 output by the PD on Die2 can directly adjust the local PI2, or be sent to Die1 through a sideband signal to adjust PI1. Among them, the sideband implementation method is not limited, and the delay adjustment step is determined by the selected algorithm. The steps are different at different stages during the adjustment process. The initial step is large, and the subsequent two clock edges are getting closer and closer, and the step should also be smaller and smaller. Repeat this step multiple times, and when the edge error between the clock and TRACK reaches a certain value according to the algorithm, the lock is completed. This clock and data path are edge-aligned within a certain error.

[0082] Figure 6is a diagram of the calibration process of Path1+path2=path3+path4 according to an embodiment of the present application, such as Figure 6 As shown, CLKA represents the TRACK signal, and CLKB represents fwdclk. According to PI1-up and PI2-up, a multi-bit control signal 1 is generated and sent to PI1 and PI2 to adjust their delays. It needs to pass through the sideband to reach PI1.

[0083] In an optional embodiment of the present invention, the PD output of Die2 is disconnected, and PI2 scans the eye width for each data lane and TRACK lane based on the basic value of step 4 to find the respective midpoint positions. Specifically, random data or fixed pattern data is used to drive a data lane or TRACK in die1, and the PI value is recorded through testing on the receiving side of die2 based on different PI comparison results. A series of data is recorded from small to large to find the midpoint value. Each lane is tested one by one (including TRACK lane) to obtain a series of PI midpoint values.

[0084] Based on the PI midpoint values ​​of each lane obtained by the above solution, the maximum PI midpoint value is used as the basis. The deskew of the lane with the maximum PI midpoint value remains unchanged, and the deskew of other lanes is adjusted = maximum PI midpoint value - PI midpoint value of the lane to be adjusted. Retest once after each lane is adjusted to ensure that the received data is correct. Figure 7 , Figure 7 is a schematic diagram of eye diagram alignment according to an embodiment of the present application.

[0085] In an optional embodiment of the present invention, a fixed 90-degree phase shift is performed on PI3 of the des clock input terminal on the track lane so that the sampling clock is aligned from the center of its data to the right edge of its data, which makes it impossible to stably sample data. Figure 8 is a diagram of alignment of TRACK data boundary and clock edge according to an embodiment of the present application, such as Figure 8 If the data is normal,

[0086] Among them, Figure 8 In the example, SAM_CLK refers to the sampling clock before PI3, and is also the clock that aligns the center of all data lanes and TRACKlane eye diagrams. SAM_CLKP is the clock that samples TRACK after SAM_CLK is phase-shifted 90 degrees by PI3, and SAM_CLKN is the reverse clock of SAM_CLKP. SAM_CLKP and SAM_CLKN are two-phase sampling clocks in DDR mode.

[0087] Fig. 9 is a graph of the sampling clock drifting to the right according to an embodiment of the present application, such as Fig. 9As shown in the figure, when the sampling clock drifts to the right, the sampled even path is stable = 1, and the odd path is stable = 0. You can control PI2 to reduce the delay until the rx_TRACK data is as follows Figure 8 As shown, it means that the clock offset has been tracked and compensated.

[0088] The sampling clock drifts to the left, the sampled even path is stable = 0, and the odd path is stable = 1. You can control PI2 to increase the delay until the rx_TRACK data is as follows Figure 8 As shown, it means that the clock offset has been tracked and compensated.

[0089] Among them, the step of controlling PI2 to reduce or increase the delay is determined by the selected algorithm.

[0090] It should be noted that the above clock drift relative to the data path is not necessarily caused by the delay change of the clock path. It may actually be caused by the drift of the data path, or there may be drift in both paths.

[0091] In another alternative embodiment, Fig.10 is a circuit diagram of a clock calibration circuit according to an embodiment of the present application, such as Fig.10 As shown, the implementation scheme is:

[0092] 1. No longer calibrate Path1+path2=path3+path4 initially. Initially, only phase-lock path1 and path4 to 1UI (or 2UI, 3UI, 4UI), depending on the designed data rate. Taking 16Gbps as an example, 1UI=62.5ps, and the clock tree is usually 70ps~120ps, so it is more appropriate to set path1 path4 to phase-lock to 2UI.

[0093] 2. Track lane has one DLL1, and multiple data lanes each have one DLL2 ( Fig.10 Only one DLL2 is drawn for one data lane in the figure. The maximum delay value of DLL2 should be greater than 1UI, and the maximum delay value of DLL1 should be greater than 1.5UI.

[0094] 3. Add DLL dummy to each data lane and TRACK lane to compensate for the intrinsic delay of DLL1 or DLL2.

[0095] like Fig.10 The implementation steps and Figure 4 The implementation steps are different, specifically:

[0096] 1. For the above steps, the initial calibration of path1+path2=path3+path4 after power-on reset can be changed to deskew=DLL2 intrinsic delay at the beginning of work, and calibrate Path1 and path4. Through the PD phase detection on each die, lock to 2UI (or other integer UI, determined according to different data_rate). After locking, the data path and the clock path are basically aligned, and the maximum allowable deviation of the UCIe specification is 0.14UI.

[0097] 2. For the step of disconnecting Die2, the PD output can be changed to calibrate the TRACK and each data lane separately, one lane at a time. The method is: Die1 sends prbs data or fixed parttern (mode) data, adjusts DLL1 and DLL2 on the receiving path of Die2, obtains a series of DLL delay values ​​with correct detection data, and finds the midpoint value.

[0098] 3. For the above steps, the PI midpoint values ​​of each lane obtained based on the above solution can be changed to find the maximum midpoint value among multiple data lanes and TRACK lanes, and use this value as the standard to adjust the deskew of other lanes so that the delay = maximum DLL midpoint value - DLL midpoint value of the lane to be adjusted. Retest each lane after adjustment to ensure that the received data is correct.

[0099] 4. In the step of making a fixed 90-degree phase shift on PI3 of the des clock input terminal on the Track lane, increasing the delay of DLL1 of the des clock input terminal on the Tracklane causes the sampling clock to align from its data center to its right edge, making it impossible to stably sample data. When TRACK finds clock drift, it controls the DLL2 of each data lane and the DLL1 of TRACK to change in opposite directions until TRACK cannot sample stable data.

[0100] Among them, DLL1 and DLL2 support the lowest data rate of 8Gbps, for example, 1UI = 125ps. Therefore, the maximum delay of DLL2 is designed to be 128ps, which is enough to scan the eye width. 16 levels of coarse adjustment, 8 levels of fine adjustment, one level of coarse adjustment is slightly larger than 8 levels of fine adjustment, and one level of fine adjustment delay is 1ps. Dll1 requires 128+64=192ps, 24 levels of coarse adjustment, and the scanning range is 0~1.5UI.

[0101] It is important to note that to support the lowest data rate of 4 Gbps, DLL2 requires a maximum delay of 256 ps, which consumes a large amount of power.

[0102] 2) Fig.11 is another circuit diagram of a clock calibration circuit according to an embodiment of the present application, such as Fig.11 As shown, the implementation scheme is the same as above Fig.10 The difference between the solutions is:

[0103] 1. DLL2 is shared by multiple data lanes and TRACK lanes, with a maximum delay of >1UI, reducing area and power consumption;

[0104] 2. DLL1 connected to the DES input clock port in the Track lane is replaced by PI3. The 90-degree phase shift generated by PI when tracking VT is locked by VT, which has better tracking accuracy. Because the sampling clock drift of DLL1 output in alternative 1 is caused by the delay value of DLL1's own delay unit changing with VT (voltage temperature), DLL2 needs to change by the same amount, and the difference between the two will affect the tracking accuracy.

[0105] The implementation steps are the same as above Fig.10 The difference in the implementation steps is that during training and VT following, DLL1 and DLL2 of each data lane are adjusted, while alternative 2 adjusts PI3 and DLL2 common to all data lanes.

[0106] The above embodiment has the following four features:

[0107] 1. The transmission data on the transmitting side is not aligned with the feedforward clock fwdclk in a delayed manner. This solves the problem of fwdclk duplicating the transmission txclk clock tree in the prior art;

[0108] 2. The receiving side does not need to compensate for the sampling clock tree delay on the data path, and the sampling clock tree does not need to be delayed within 0.5UI. This solves the problem of the data path needing to compensate for the sampling clock tree delay in the prior art, and does not require the back-end to optimize the clock tree delay;

[0109] 3. Align the entire data path and clock path by using the method of offsetting the delays of the sending clock tree on the sending side and the sampling clock tree on the receiving side. The specific implementation is to perform phase detection on the receiving side for the TRACK data (carrying the clock signal) and the sampling clock fwdclk (or alternatively: phase-lock the sending clock tree on the sending side and the sampling clock tree on the receiving side, respectively, generally locked to 2UI or 4UI, determined according to the clock tree delay and UI value) to ensure that the delays of the two are the same. The phase-locking method can achieve higher accuracy than the existing technology. In addition, the overall path delay does not increase, and the impact of jitter caused by changes in temperature and voltage is relatively smaller;

[0110] 4. There is a temperature and voltage change following mechanism. Before working, first align the sampling clock to the center of the TRACK data through training to ensure that the sampled TRACK data is correct. During work, the phase is moved 90 degrees to the right boundary of the TRACK data through PI3 on ​​the TRACK. Ensure that the sampled parity bit does not get stable data during work (the sending side sends 1010...fixed pattern data on the TRACK lane). When the sampled parity bit gets a stable 1 or 0, it means that the sampling clock delay drifts, and the PI connected to the sampling clock tree can be adjusted to compensate for the drift delay.

[0111] The embodiment of the present application utilizes the characteristics that the delay of the sending clock tree on the data path and the sampling clock tree on the clock path are similar and can offset each other. Instead of aligning the data clock edges on each side of the sending side and the receiving side, the entire data path and clock path on the sending side and the receiving side are taken into consideration together, and the delays are equalized through PD locking. Various circuits such as clock tree replication and clock tree delay compensation are reduced. Specifically, it has the following advantages:

[0112] 1. Avoid adding a delay compensation circuit to the clock tree in the data path. This will not increase the total delay, will reduce the jitter caused by temperature and voltage changes, and will not cause deviations between the compensation circuit and the clock tree.

[0113] 2. The overall PD phase lock covers the complete data path and clock path, and the deviation can be made smaller. Alternatively, the sending clock tree and the receiving clock tree are phase locked separately, covering the maximum delay part, which is also the main part that changes when VT changes, and the overall delay can be small, and the clock data deviation can be smaller.

[0114] 3. The back-end implementation is simpler. No clock tree compensation circuit is required.

[0115] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A clock calibration circuit, characterized in that: include: a first sampling circuit; A second sampling circuit connected in series with the first sampling circuit; wherein, The first sampling circuit includes: a phase-locked loop PLL; a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; and a first transmission driver connected in series with the first data serializer. a second data serializer connected in series with the first DCC, and a second transmission driver connected in series with the second data serializer, wherein the PLL is used to output a clock signal to drive the first data serializer to send the data to be sent to the first transmission driver, and drive the second data serializer to send a feedforward clock signal to the second transmission driver; The second transmitting driver is used to transmit the feedforward clock signal to the first receiving driver in the second sampling circuit, so as to determine the feedforward clock signal as the sampling clock of the second sampling circuit.

2. The clock calibration circuit according to claim 1, characterized in that: The second sampling circuit includes: a second receiving driver, which is connected in series with the first sending driver, and is used to receive the data to be sent sent by the first sending driver, and send the data to be sent to the first data deserializer connected in series with the small delay buffer through the small delay buffer connected in series with the second receiving driver.

3. The clock calibration circuit according to claim 2, characterized in that: The second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer respectively, and is used to compensate for the intrinsic delay of the first DCC.

4. The clock calibration circuit according to claim 2, characterized in that: The second sampling circuit comprises: A second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree, wherein the first receiving driver is used to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

5. The clock calibration circuit according to claim 4, characterized in that: The second sampling circuit includes: a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer respectively, so as to supplement the intrinsic delay of the second PI.

6. The clock calibration circuit according to claim 4, characterized in that: The second sampling circuit comprises: A third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is used to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links correspond to different transmitting drivers respectively.

7. The clock calibration circuit according to claim 4, characterized in that: The first sampling circuit comprises: The third PI, which is respectively connected in series with the first clock tree and the first data serializer, is used to be set to a fixed phase shift after the training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links correspond to different transmission drivers respectively.

8. The clock calibration circuit according to claim 4, characterized in that: The second sampling circuit comprises: a first data checking module, connected in series with the first data deserializer and the second PI, respectively, for adjusting the delay value of the second PI during data link training; and / or The second data checking module is connected in series with the second data deserializer and the second PI respectively, and is used to adjust the delay value of the second PI during TRACK link training.

9. The clock calibration circuit according to claim 4, characterized in that: The second sampling circuit comprises: a first delay phase-locked loop DLL, connected in series with the second clock tree and the first data deserializer respectively; The second sampling circuit further includes: a second DLL connected in series with the second clock tree and the second data deserializer respectively.

10. The clock calibration circuit according to claim 4, characterized in that: The second sampling circuit comprises: The third DLL is connected in series with the second DCC and the second PI respectively, and is used for delaying a plurality of data links and a TRACK link, wherein the plurality of data links and the TRACK link correspond to different sending drivers respectively.

11. The clock calibration circuit according to any one of claims 1 to 10, characterized in that: The first sampling circuit includes: a first DIE sampling circuit; the second sampling circuit includes: a second DIE sampling circuit.

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