Caching method and device of universal flash memory

Abstract

The invention provides a caching method and device for a universal flash memory (UFS). The UFS caching method comprises the steps that at least one piece of current storage information of a UFS comprising a single-layer storage unit SLC buffer and a multi-layer storage unit is obtained every preset time, and the multi-layer storage unit comprises at least two layers of storage units; obtaining input data of a neural network based on the at least one piece of current storage information; obtaining adjustment information of the SLC buffer through a neural network based on the input data; and adjusting a size of the SLC buffer based on the adjustment information of the SLC buffer.

Description

Technical Field

[0001] The present invention relates to the field of storage, and more specifically, to a cache method and device for a universal flash storage (UFS). Background Art

[0002] Recently, cache technologies such as Turbo Write are commonly used in UFS. Existing TurboWrite technologies are mainly divided into static Turbo Write and dynamic Turbo Write. In UFS using static Turbo Write, the size of the single-layer storage unit (SLC) buffer remains unchanged during operation. This technology writes all the data on the host side into the SLC buffer, and then flushes the data in the SLC buffer to multi-layer storage units such as three-layer storage units (TLC) and four-layer storage units (QLC). In UFS using dynamic Turbo Write, the size of the SLC buffer is adjusted in real time according to the adjustment factor during operation, that is, the size of the SLC buffer can be increased when the overall available storage capacity increases, and the size of the SLC buffer can be reduced when the overall available storage capacity decreases.

[0003] However, according to static Turbo Write, the size of the SLC buffer is fixed, and all data sent from the host will be written to the SLC buffer first, which greatly increases the number of erases in the SLC buffer, thereby reducing the life of the SLC buffer; in addition, when the SLC buffer is full, subsequent data will be written to TLC, QLC, etc., causing a rapid drop in write performance and a poor user experience. On the other hand, according to dynamic Turbo Write, when the overall available storage capacity is small, the SLC buffer is adjusted to a smaller size. After the SLC buffer is full, subsequent data is written to TLC, QLC, etc., and the write performance drops sharply; in addition, when the overall available storage capacity is large, the SLC buffer is adjusted to a larger size, but the overall storage capacity is reduced, the storage utilization is not high, and the performance of the device cannot reach the optimal level. Summary of the invention

[0004] According to an example embodiment conceived by the present invention, a caching method of a universal flash storage (UFS) is provided, including: obtaining at least one current storage information of a UFS including a single-layer storage cell (SLC) buffer and a multi-layer storage cell at predetermined intervals, wherein the multi-layer storage unit includes storage cells of at least two layers; obtaining input data of a neural network based on the at least one current storage information; obtaining adjustment information of the SLC buffer through the neural network based on the input data; and adjusting the size of the SLC buffer based on the adjustment information of the SLC buffer.

[0005] The at least one current storage information of the UFS may include UFS current storage information, SLC buffer current storage information, and UFS current workload information.

[0006] The step of obtaining input data of the neural network based on the at least one current storage information may include: obtaining input data of the neural network based on the at least one current storage information, at least one UFS overall storage information corresponding to the at least one current storage information, and corresponding weights.

[0007] The neural network may be a mobile network V3 (Mobilenet_V3), the number of Bneck network layers of Mobilenet_V3 is set to small, the linear rectification ReLU activation function in Mobilenet_V3 is replaced with an H-Switch activation function, and the output dimension of Mobilenet_V3 is modified to output a single value as adjustment information of the SLC buffer.

[0008] According to another example embodiment of the present invention, there is provided a cache device of a universal flash storage (UFS), including: a storage information acquisition unit configured to acquire at least one current storage information of the UFS including a single-layer storage cell (SLC) buffer and a multi-layer storage unit at predetermined intervals, wherein the multi-layer storage unit includes storage cells of at least two layers; an input data acquisition unit configured to acquire input data of a neural network based on the at least one current storage information; an adjustment information acquisition unit configured to acquire adjustment information of the SLC buffer through the neural network based on the input data; and an adjustment unit configured to adjust the size of the SLC buffer based on the adjustment information of the SLC buffer.

[0009] The at least one current storage information of the UFS may include UFS current storage information, SLC buffer current storage information, and UFS current workload information.

[0010] The input data acquisition unit may also be configured to perform the following operation: acquiring input data of the neural network based on the at least one current storage information, at least one UFS overall storage information respectively corresponding to the at least one current storage information, and corresponding weights.

[0011] The neural network may be a mobile network V3 (Mobilenet_V3), the number of Bneck network layers of Mobilenet_V3 is set to small, the linear rectification ReLU activation function in Mobilenet_V3 is replaced with an H-Switch activation function, and the output dimension of Mobilenet_V3 is modified to output a single value as adjustment information of the SLC buffer.

[0012] According to another exemplary embodiment of the inventive concept, an electronic device is provided, including a memory and a processor, wherein computer executable instructions are stored in the memory, and when the instructions are executed by the processor, the aforementioned method is executed.

[0013] According to another exemplary embodiment of the inventive concept, there is provided a computer-readable medium having computer-executable instructions stored thereon, which, when executed, perform the aforementioned method.

[0014] According to an example embodiment conceived by the present invention, by dynamically calculating and deciding the current optimal SLC buffer size based on the storage information of the UFS and adjusting it, the device storage capacity can be fully utilized and the overall read and write performance and storage utilization of the host side can be improved; in addition, by using the current storage information of the UFS, the current storage information of the SLC buffer and the current workload information of the UFS to obtain the input data of the Mobilenet_V3 neural network, and adjusting and modifying the network structure of mobilenet_V3, the read and write performance of the host side can be optimized, effectively improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects and features of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a flowchart illustrating a caching method of a UFS according to an exemplary embodiment of the inventive concept;

[0017] Figure 2 is a schematic diagram illustrating Mobilenet_V3 according to an exemplary embodiment of the inventive concept;

[0018] Figure 3 is a block diagram illustrating a cache device of a UFS according to an example embodiment of the inventive concept;

[0019] Figure 4 is a schematic diagram illustrating a system to which a storage device is applied according to an example embodiment of the inventive concept;

[0020] Figure 5 is a block diagram illustrating a host storage system according to an example embodiment of the inventive concept;

[0021] Figure 6 is a diagram illustrating a data center to which a storage device is applied according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] In the following, various exemplary embodiments of the inventive concept are described with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, features and structures. However, it is not intended that the inventive concept be limited to specific embodiments by the various exemplary embodiments described herein, and it is intended that: the inventive concept covers all modifications, equivalents and / or substitutes of the inventive concept, as long as they are within the scope of the attached claims and their equivalents. The terms and words used in the following specification and claims are not limited to their dictionary meanings, but are only used to enable a clear and consistent understanding of the inventive concept. Therefore, it should be apparent to those skilled in the art that the following description of various exemplary embodiments of the inventive concept is provided for illustrative purposes only, and not for the purpose of limiting the inventive concept defined by the attached claims and their equivalents.

[0023] It should be understood that unless the context clearly indicates otherwise, the singular includes the plural.The terms "include", "comprising" and "having" used herein indicate the presence of functions, operations or elements of the inventive concept, but do not exclude other functions, operations or elements.

[0024] For example, the expression "A or B" or "at least one of A and / or B" may indicate A and B, A or B. For example, the expression "A or B" or "at least one of A and / or B" may indicate (1) A, (2) B, or (3) both A and B.

[0025] In various example embodiments of the inventive concept, it is intended that when a component (e.g., a first component) is referred to as being "coupled" or "connected" to another component (e.g., a second component) or being "coupled" or "connected" to another component (e.g., the second component), the component may be directly connected to the other component or may be connected through another component (e.g., a third component). In contrast, when a component (e.g., a first component) is referred to as being "directly coupled" or "directly connected" to another component (e.g., the second component) or being directly coupled to or directly connected to another component (e.g., the second component), there is no other component (e.g., the third component) between the component and the other component.

[0026] The expression "configured to" used in describing various example embodiments of the inventive concept may be used interchangeably with expressions such as "suitable for", "capable of", "designed to", "suitable for", "manufactured to", and "capable of", for example, depending on the circumstances. The term "configured to" may not necessarily indicate that it is "specially designed to" in terms of hardware. On the contrary, the expression "a device configured to..." in some cases may indicate that the device and another device or part "can..." For example, the expression "a processor configured to perform A, B, and C" may indicate a dedicated processor (e.g., an embedded processor) for performing the corresponding operations or a general-purpose processor (e.g., a central processing unit CPU or an application processor (AP)) for performing the corresponding operations by executing at least one software program stored in a memory device.

[0027] The terms used herein are to describe certain example embodiments of the inventive concept, but are not intended to limit the scope of other example embodiments. Unless otherwise noted herein, all terms (including technical or scientific terms) used herein may have the same meaning as those generally understood by those skilled in the art. Generally, the terms defined in the dictionary should be considered to have the same meaning as the contextual meaning in the relevant field, and, unless clearly defined herein, should not be understood differently or understood to have an overly formal meaning. In any case, the terms defined in the inventive concept are not intended to be interpreted as excluding the example embodiments of the inventive concept.

[0028] Figure 1 is a flow chart showing a caching method of a UFS according to an exemplary embodiment of the inventive concept. According to an exemplary embodiment of the inventive concept, the UFS may be a UFS using dynamic Turbo Write, but the present invention is not limited thereto, for example, the UFS may be a UFS using any caching technology including a single-layer storage unit (SLC) buffer and a multi-layer storage unit (which may include at least two layers of storage units, such as a multi-layer storage unit may include TLC, QLC, etc.) as described below.

[0029] Reference Figure 1 In step S110, at least one current storage information of a UFS including a single-layer storage cell (SLC) buffer and a multi-layer storage cell may be acquired every predetermined time, wherein the multi-layer storage cell includes a storage cell of at least two layers, such as a multi-layer storage cell may include a TLC, a QLC, etc. According to an example embodiment of the inventive concept, the predetermined time may be 5 minutes, but the present invention is not limited thereto.

[0030] According to example embodiments of the inventive concepts, at least one current storage information of the UFS may include UFS current storage information, SLC buffer current storage information, and UFS current workload information. According to an example embodiment of the present invention, by performing data analysis, the UFS current storage information can be further determined as the current UFS available storage size (including the SLC buffer and multi-layer storage units such as TLC and QLC) and the UFS throughput within a predetermined time (including the SLC buffer and multi-layer storage units such as TLC and QLC), the SLC buffer current storage information can be more specifically determined as the current SLC buffer size, the current SLC buffer available size, the adjustment status of the current SLC buffer size and the current SLC buffer life, and the UFS current workload information can be more specifically determined as the input and output (IO) write size of the UFS within a predetermined time (including the SLC buffer and multi-layer storage units such as TLC and QLC), the data heat within a predetermined time, the synchronization (here, synchronization refers to the synchronization between the UFS and the memory of the device to which the UFS belongs, the same below) data volume within a predetermined time (including all data, such as data, metadata, database data), the data synchronization data volume within a predetermined time (including only data) and the database synchronization data volume within a predetermined time (including only database data), so as to obtain better results.

[0031] In step S120, input data of the neural network may be obtained based on at least one current storage information. According to an example embodiment of the inventive concept, the step of obtaining input data of the neural network based on at least one current storage information may include: obtaining input data of the neural network based on at least one current storage information, at least one UFS overall storage information respectively corresponding to the at least one current storage information, and a corresponding weight. According to an example embodiment of the inventive concept, the input data of the neural network may be obtained by multiplying a ratio of the current storage information to the overall storage information of the UFS by a corresponding weight.

[0032] According to example embodiments of the inventive concept, input data of a neural network may be obtained through the following Equation 1 based on a current UFS available storage size.

[0033] [Equation 1]

[0034]

[0035] Among them, F represents the input data, S UFS available Indicates the current UFS available storage size, S UFS represents the overall storage size of UFS (including the SLC buffer and multi-layer storage units such as TLC and QLC), W1 represents the weight, and its value may be 0.435, but the present invention is not limited thereto.

[0036] According to example embodiments of the inventive concept, input data of a neural network may be obtained through the following Equation 2 based on a current SLC buffer size.

[0037] [Equation 2]

[0038]

[0039] Among them, F represents the input data, S SLC Indicates the current SLC buffer size, S UFS represents the overall storage size of UFS (including the SLC buffer and multi-layer storage units such as TLC and QLC), W2 represents the weight, and its value may be 0.628, but the present invention is not limited thereto.

[0040] According to example embodiments of the inventive concept, input data of a neural network may be obtained through the following Equation 3 based on an IO write size of a UFS within a predetermined time.

[0041] [Equation 3]

[0042]

[0043] Among them, F represents the input data, S IO write Indicates the IO write size of UFS within a predetermined time, S total write read represents the total IO read and write size of UFS, W3 represents the weight, and its value may be 0.279, but the present invention is not limited thereto.

[0044] The acquisition of other information is similar to the above information and will not be repeated here.

[0045] In addition, after multiplying the ratio of the current storage information to the overall storage information of the UFS by the corresponding weight, a data enhancement method may be applied to the acquired data (such as one-dimensional data) to obtain input data suitable for input to the neural network. For example, a data enhancement method may be applied to the acquired one-dimensional data to obtain three-dimensional data, such as obtaining 224×224×3 three-dimensional data suitable for a neural network such as Mobilenet_V3, but the present invention is not limited thereto.

[0046] In step S130, adjustment information of the SLC buffer may be acquired through a neural network based on the input data. According to an example embodiment of the inventive concept, the neural network may be Mobilenet_V3. Figure 2 Schematic diagram showing Mobilenet_V3 according to an exemplary embodiment of the present invention. Figure 2As shown, the number of network layers of Mobilenet_V3's Bneck (Bneck changes the traditionally used convolutional layer to use depth-wise separable convolution, splitting the ordinary convolution into a depth-wise convolution and a point-by-point convolution) can be set to small (i.e., 11 layers, but the present invention is not limited thereto), the linear rectification ReLU activation function in Mobilenet_V3 can be replaced with an H-Switch H-Switch activation function to make it more suitable for mobile-end computing, and the output dimension of Mobilenet_V3 can be modified to output a single value as adjustment information for the SLC buffer. According to an example embodiment conceived by the present invention, the matrix dimension of the fully connected layer of Mobilenet_V3 can be modified so that the matrices are multiplied to obtain a single value as output. According to an example embodiment conceived by the present invention, the current storage information of the above-mentioned UFS can be used to train Mobilenet_V3. It should be understood that Mobilenet_V3 is only an example and not a limitation of the present invention, and the present invention may also use other neural networks, such as residual networks.

[0047] In step S140, the size of the SLC buffer may be adjusted based on the adjustment information of the SLC buffer. According to an exemplary embodiment of the inventive concept, the adjustment information of the SLC buffer may be encoded and sent down to the driver layer of the UFS, and the driver layer may send the adjustment information of the SLC buffer down to the device layer to adjust the size of the SLC buffer.

[0048] Figure 3 is a block diagram illustrating a cache device of a UFS according to an example embodiment of the inventive concept.

[0049] Reference Figure 3 , a cache device 300 of a UFS according to an example embodiment of the inventive concept may include a storage information acquiring unit 310 , an input data acquiring unit 320 , an adjustment information acquiring unit 330 , and an adjustment unit 340 .

[0050] The storage information acquisition unit 310 may be configured to acquire at least one current storage information of a UFS including a single-layer storage unit SLC buffer and a multi-layer storage unit at predetermined intervals, wherein the multi-layer storage unit includes storage units of at least two layers. According to an example embodiment of the inventive concept, the at least one current storage information of the UFS may include UFS current storage information, SLC buffer current storage information, and UFS current workload information.

[0051] The input data acquisition unit 320 may be configured to acquire input data of the neural network based on at least one current storage information. The input data acquisition unit 320 may also be configured to perform the following operations: acquire input data of the neural network based on at least one current storage information, at least one UFS overall storage information respectively corresponding to the at least one current storage information, and corresponding weights.

[0052] The adjustment information acquisition unit 330 may be configured to acquire adjustment information of the SLC buffer through a neural network based on input data. According to an exemplary embodiment of the inventive concept, the neural network may be a mobile network V3 Mobilenet_V3, the number of Bneck network layers of Mobilenet_V3 may be set to be small, the linear rectification ReLU activation function in Mobilenet_V3 may be replaced with an H-Switch H-Switch activation function, and the output dimension of Mobilenet_V3 may be modified to output a single value as the adjustment information of the SLC buffer.

[0053] The adjustment unit 340 may be configured to adjust the size of the SLC buffer based on the adjustment information of the SLC buffer.

[0054] Figure 4 is a schematic diagram illustrating a system 1000 to which a storage device is applied according to an example embodiment of the inventive concept.

[0055] Figure 4 The system 1000 may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Figure 4 The system 1000 is not necessarily limited to a mobile system, and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0056] Reference Figure 4 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0057] The main processor 1100 may control all operations of the system 1000, and more specifically, may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0058] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and further include a controller 1120 for controlling the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. In some example embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations, etc. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and is implemented as a chip physically separated from other components of the main processor 1100.

[0059] The memories 1200a and 1200b may be used as main storage devices of the system 1000. Although the memories 1200a and 1200b may include volatile memories, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), etc., the memories 1200a and 1200b may include non-volatile memories, such as flash memory, phase change random access memory (PRAM), and / or resistive random access memory (RRAM), etc. The memories 1200a and 1200b may be implemented in the same package as the main processor 1100.

[0060] The storage devices 1300a and 1300b may be used as non-volatile storage devices, which are configured to store data regardless of whether they are powered on and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include memory controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, which are configured to store data via the control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM, etc.

[0061] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of solid-state devices (SSDs) or memory cards, and may be removably combined with other components of the system 100 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVMe is applied, but the present invention is not limited thereto.

[0062] The image capture device 1410 can capture still images or moving images. The image capture device 1410 may include a camera, a camcorder, and / or a webcam, etc.

[0063] The user input device 1420 may receive various types of data input by a user of the system 1000 and includes a touch pad, a keypad, a keyboard, a mouse, a microphone, and the like.

[0064] The sensor 1430 may detect various types of physical quantities that may be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, etc.

[0065] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, a modem, or the like.

[0066] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0067] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0068] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented by using various interface schemes, for example, Advanced Technology Attachment (ATA), Serial ATA (SATA), External Serial ATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, UFS interface, Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, and the like.

[0069] Figure 5 is a block diagram illustrating a host memory system 10 according to an example embodiment of the inventive concept.

[0070] The host storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a memory controller 210 and an NVM 220. According to an example embodiment of the inventive concept, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory configured to temporarily store data to be transmitted to or received from the storage device 200.

[0071] The storage device 200 may include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the UFS standard or the eMMC standard. Both the host 100 and the storage device 200 may generate a packet and send the packet according to the adopted standard protocol.

[0072] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of NVM. For example, the storage device 200 may include a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other types of memory.

[0073] According to an example embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the AP or a memory module external to the AP.

[0074] The host controller 110 may manage an operation of storing data (eg, write data) of the buffer area of ​​the host memory 120 in the NVM 220 or an operation of storing data (eg, read data) of the NVM 220 in the buffer area.

[0075] The memory controller 210 may include a host interface 211, a memory interface 212, and a CPU 213. In addition, the memory controller 210 may further include a flash translation layer (FTL), a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The memory controller 210 may further include a working memory (not shown) in which the FTL 214 is loaded. The CPU 213 may execute the FTL 214 to control data write and read operations on the NVM 220.

[0076] The host interface 211 may transmit and receive packets to and from the host 100. The packets transmitted from the host 100 to the host interface 211 may include commands or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host 100 may include responses to commands or data read from the NVM 220, etc. The memory interface 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0077] The FTL 214 may perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in the NVM 220. The wear leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the NVM 220 to be used evenly. As an example, the wear leveling operation may be implemented by using a firmware technique that balances the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0078] The packet manager 215 may generate a packet according to a protocol agreed to an interface of the host 100, or parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the memory controller 210, the buffer memory 216 may be outside the memory controller 210.

[0079] The ECC engine 217 may perform error detection and correction operations on read data read from the NVM 220. More specifically, the ECC engine 217 may generate parity bits for write data to be written to the NVM 220, and the generated parity bits may be stored together with the write data in the NVM 220. During reading of data from the NVM 220, the ECC engine 217 may correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the error-corrected read data.

[0080] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0081] Figure 6 is a diagram illustrating a data center 3000 to which a storage device is applied according to an example embodiment of the inventive concept.

[0082] Platform part - server (application / storage)

[0083] Reference Figure 6, the data center 3000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (e.g., a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to example embodiments, the number of applications 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0084] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Now, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMDIMM). In some example embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an example embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an example embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to the embodiment, the number of storage devices 3250 included in the storage server 3200 may be selected differently.

[0085] Platform part - Network

[0086] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability can be used. According to the access method of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0087] In one embodiment, the network 3300 may be a network dedicated to storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to the SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0088] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0089] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0090] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300. Alternatively, the application server 3100 may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m through the storage 3220 to 3220m of the storage servers 3200 to 3200m or directly to the storage 3120 to 3120n of the application servers 3100 to 3100n. The data moved through the network 3300 may be data encrypted for security or privacy.

[0091] Organic Relationship-Interface Structure / Type

[0092] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) solution, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented using various interface solutions, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0093] The storage server 3200 may further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via the control of the processor 3210.

[0094] In one embodiment, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In one embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0095] Organic Relationship-Interface Operation

[0096] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data in which an error is corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and may include cyclic redundancy coding (CRC) information. The data may be data encrypted for security or privacy.

[0097] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. Depending on the rising edge or falling edge of the write enable (WE) signal, the command and address signals may be latched in the page buffer.

[0098] Product section - Basic operation of SSD

[0099] The controller 3251 may control all operations of the storage device 3250. In one embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 of the storage server 3200, a processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) data to be written to the NAND flash memory device 3252 or data to be read from the NAND flash memory device 3252. And, the DRAM 3253 may store metadata. Here, the metadata may be user data or data generated by the controller 3251 for managing the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0100] According to an exemplary embodiment of the inventive concept, a computer readable medium is provided, on which a computer executable instruction is stored, and when the instruction is executed, the aforementioned method is performed. Examples of computer readable media here may include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (e.g., multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and provide the computer programs and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be run in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system, so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0101] According to an example embodiment conceived by the present invention, by dynamically calculating and deciding the current optimal SLC buffer size based on the storage information of the UFS and adjusting it, the device storage capacity can be fully utilized and the overall read and write performance and storage utilization of the host side can be improved; in addition, by using the current storage information of the UFS, the current storage information of the SLC buffer and the current workload information of the UFS to obtain the input data of the Mobilenet_V3 neural network, and adjusting and modifying the network structure of mobilenet_V3, the read and write performance of the host side can be optimized, effectively improving the user experience.

[0102] While the inventive concept has been shown and described with reference to particular example embodiments, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as defined by the claims and their equivalents.

Claims

1. A caching method for a universal flash storage UFS, comprising: Acquire at least one current storage information of a UFS including a single-layer storage unit SLC buffer and a multi-layer storage unit at predetermined intervals, wherein the multi-layer storage unit includes storage units of at least two layers; obtaining input data of the neural network based on the at least one currently stored information; Obtaining adjustment information of the SLC buffer through a neural network based on the input data; and The size of the SLC buffer is adjusted based on the adjustment information of the SLC buffer.

2. The UFS cache method according to claim 1, wherein: The at least one current storage information of the UFS includes UFS current storage information, SLC buffer current storage information, and UFS current workload information.

3. The UFS cache method according to claim 1, wherein: The step of obtaining input data of the neural network based on the at least one currently stored information comprises: Input data of the neural network is obtained based on the at least one current storage information, at least one UFS overall storage information respectively corresponding to the at least one current storage information, and corresponding weights.

4. The UFS cache method according to claim 1, wherein: The neural network is Mobilenet_V3. The number of Bneck network layers of Mobilenet_V3 is set to small, the linear rectification ReLU activation function in Mobilenet_V3 is replaced with the H-Switch H-Switch activation function, and the output dimension of Mobilenet_V3 is modified to output a single value as the adjustment information of the SLC buffer.

5. A cache device of a universal flash storage UFS, comprising: a storage information acquisition unit configured to acquire at least one current storage information of a UFS including a single-layer storage unit SLC buffer and a multi-layer storage unit at predetermined intervals, wherein the multi-layer storage unit includes storage units of at least two layers; an input data acquisition unit, configured to acquire input data of the neural network based on the at least one currently stored information; an adjustment information acquisition unit configured to acquire adjustment information of the SLC buffer through a neural network based on the input data; and The adjustment unit is configured to adjust the size of the SLC buffer based on the adjustment information of the SLC buffer.

6. The UFS cache device according to claim 5, wherein: The at least one current storage information of the UFS includes UFS current storage information, SLC buffer current storage information, and UFS current workload information.

7. The UFS cache device according to claim 5, wherein: The input data acquisition unit is further configured to perform the following operations: Input data of the neural network is obtained based on the at least one current storage information, at least one UFS overall storage information respectively corresponding to the at least one current storage information, and corresponding weights.

8. The UFS cache device according to claim 5, wherein: The neural network is Mobilenet_V3. The number of Bneck network layers of Mobilenet_V3 is set to small, the linear rectification ReLU activation function in Mobilenet_V3 is replaced with the H-Switch H-Switch activation function, and the output dimension of Mobilenet_V3 is modified to output a single value as the adjustment information of the SLC buffer.

9. An electronic device comprising a memory and a processor, wherein the memory stores computer executable instructions, and when the instructions are executed by the processor, the method according to any one of claims 1 to 4 is executed.

10. A computer-readable medium having computer-executable instructions stored thereon, wherein when the instructions are executed, the method according to any one of claims 1 to 4 is executed.

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