Vector processor

Abstract

The present application relates to a vector processor comprising a vector load store unit configured to split a memory access operation, send a memory access request to a cache for any one cache line associated with the split memory access operation, and upon receiving a memory access grant from the cache for the cache line, load data from one or more offset addresses in the cache line relative to a start address of the cache line and gather the loaded data, or scatter register data associated with the cache line and store the scattered register data to one or more offset addresses in the cache line relative to the start address of the cache line, respectively.

Description

Technical Field

[0001] This disclosure generally relates to the field of computers, and more particularly to vector processors. Background Technology

[0002] A Reduced Instruction Set Computer (RISC) processor is a type of processor that executes fewer types of computer instructions. The fundamental principle of RISC processors is to reduce the complexity of hardware design by streamlining the machine instruction set, while simultaneously increasing instruction execution speed. In RISC processors, both simple and complex operations are performed by blocks of simple instructions. Summary of the Invention

[0003] A vector processor according to an embodiment of the present disclosure includes a vector loading storage unit configured to: split a memory access operation, send a memory access request to a cache for any cache line associated with the split memory access operation, and, after receiving a memory access permission for the cache line from the cache, load data from one or more offset addresses in the cache line relative to the start address of the cache line and aggregate the loaded data, or scatter register data associated with the cache line and store the scattered register data respectively in one or more offset addresses in the cache line relative to the start address of the cache line. Attached Figure Description

[0004] Embodiments of this disclosure will be illustrated in the accompanying drawings by way of example rather than limitation, wherein similar reference numerals refer to similar elements.

[0005] Figure 1 This is a schematic diagram illustrating the data loading process when a vector loading memory unit in a vector processor implements step memory access according to an embodiment of the present disclosure.

[0006] Figure 2 This is a schematic diagram illustrating the logical structure of a vector loading storage unit according to an embodiment of the present disclosure.

[0007] Figure 3 It is shown in the figure. Figure 2 The diagram shows an example hardware implementation of the address generation module.

[0008] Figure 4 It is shown in the figure. Figure 2 The diagram shows an example hardware implementation of the data aggregation module.

[0009] Figure 5a It is shown in the figure. Figure 3 and Figure 4The diagram shows the logical structure of the input switch.

[0010] Figure 5b It is shown in the figure. Figure 3 and Figure 4 The diagram shows the logical structure of the intermediate switch.

[0011] Figure 5c It is shown in the figure. Figure 3 and Figure 4 The diagram shows the logical structure of the output switch.

[0012] Figure 6 This is a block diagram illustrating an example computing device in which a vector processor according to various embodiments of the present disclosure can be used. Detailed Implementation

[0013] Various aspects of the illustrative embodiments will be described using terminology commonly used by those skilled in the art to convey the essence of this disclosure to others skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments can be implemented using portions of the described aspects. Specific figures, materials, and configurations are given for illustrative purposes to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments can be implemented without these specific details. In other instances, well-known features may be omitted or simplified to avoid obscuring the illustrative embodiments.

[0014] Furthermore, the various operations are described sequentially as a plurality of discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must be sequentially related. In particular, these operations do not need to be performed in the order presented.

[0015] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not generally refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise requires, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0016] Vector instruction set architecture (MIND) is a widely adopted solution in mainstream processors. It features Single Instruction Multiple Data (SIMD) capability (i.e., the ability to process multiple sets of independent data with a single instruction), thus enhancing the processor's data parallelism and significantly improving its data processing performance. Compared to Graphics Processing Units (GPUs), MIND architecture does not require significantly higher power consumption. Furthermore, compared to other dedicated accelerators, MIND architecture offers high flexibility and programmability, attracting widespread attention in recent years.

[0017] Similar to the advanced RISC machine (ARM) and x86 instruction set architectures, the fifth-generation RISC (RISC-V) instruction set architecture also introduced a vector instruction set extension, which has gradually evolved into the stable version RVV1.0. The RVV instruction set specifies various types of memory access modes, including unit-stride memory access, strided memory access, indexed memory access, and segmented memory access. A key challenge for vector instruction set architectures is maximizing the performance of these memory access modes at the lowest possible cost.

[0018] For straddle memory accesses, current vector processors split memory access operations and issue a separate memory access request to the cache for each data element associated with the split memory access operation. However, when the straddle size is small, multiple data elements may reside in the same cache line. For example, with a straddle size of 2, a single 64-byte cache line can contain a maximum of 32 data elements. Consolidating memory accesses for these data elements into a single memory access instead of splitting them into 32 separate memory accesses can significantly improve the data access performance of vector processors.

[0019] In view of the above, a vector load memory unit for use in a vector processor according to an embodiment of the present disclosure is proposed. By merging memory accesses for each related data element in the same cache line into a single memory access, straddle memory access can be optimized and accelerated, memory operations can be reduced, thereby enhancing the data access performance of the vector processor.

[0020] Figure 1 This is a schematic diagram illustrating the data loading process when implementing straddle memory access using a vector load memory unit in a vector processor according to an embodiment of the present disclosure. Figure 1As shown, the vector load storage unit is configured to split memory access operations, send a memory access request to the cache for any cache line (hereinafter referred to as cache line L) associated with the split memory access operation, and load data from one or more offset addresses (e.g., offset address 0, offset address 1, ..., offset address k, where k is an integer greater than or equal to 0) in cache line L relative to the starting address of cache line L and aggregate them together.

[0021] Additionally, in some embodiments, the vector loading storage unit according to embodiments of this disclosure may also be configured to, upon receiving a memory access permission for cache line L from the cache, scatter the register data associated with cache line L and store the scattered register data respectively in one or more offset addresses relative to the starting address of cache line L.

[0022] Figure 2 This is a schematic diagram illustrating the logical structure of a vector loading memory unit according to an embodiment of the present disclosure. Figure 2 As shown, the vector loading memory unit 200 includes an address generation module 202 and a data aggregation module 204. The address generation module 202 is configured to generate address offsets relative to the start address of each offset address associated with the split memory access operation in cache line L based on the base address offset and stride used for step memory access for cache line L, and to generate data aggregation control signals for controlling the aggregation process of data bytes at each offset address associated with the split memory access operation in cache line L after loading, or to generate data dispersion control signals for controlling the dispersion process of register data associated with cache line L, based on the generated address offsets. The data aggregation module 204 is configured to receive data bytes at each offset address associated with the split memory access operation in cache line L from the outside, and to aggregate the received data bytes based on the data aggregation control signals for controlling the aggregation process of data bytes at each offset address associated with the split memory access operation in cache line L after loading.

[0023] In some embodiments, when counting the data bytes in cache line L starting from the data byte at the start address of cache line L, for the i-th data byte in cache line L (i is an integer greater than or equal to 0), the address generation module 202 can be configured to generate the address offset addr_offset of the offset address of the i-th data byte relative to the start address of cache line L according to the following equation:

[0024]

[0025] Where offset represents the base address offset used for a stride memory access to cache line L, stride represents the stride used for a stride memory access to cache line L, and eewb represents the effective element width in bytes for the data elements in cache line L.

[0026] In some embodiments, when the starting address of cache line L is denoted as Addr and the base address offset and stride used for step memory accesses of cache line L are denoted as offset and stride, respectively, the address generation module 202 can be configured to generate each offset address in cache line L associated with a memory access operation according to the following equations: offset address 0 = Addr + offset, offset address 1 = Addr + offset + stride, ..., offset address k = Addr + offset + k * stride, where k represents the number of steps and is an integer greater than 0, and offset, (offset + stride), ..., (offset + k * stride) are the address offsets of each offset address in cache line L associated with a memory access operation relative to the starting address Addr of cache line L.

[0027] Figure 3 It is shown in the figure. Figure 2 The diagram shows an example hardware implementation of the address generation module. Figure 3 As shown, the address generation module 202 includes an address generation section 2022 and an address propagation section 2024. The address generation section 2022 is configured to generate, using shifters and adders, address offsets of each offset address associated with the split memory access operation in cache line L relative to the starting address of cache line L, based on the base address offset and stride used for the step memory access for cache line L. The address propagation section 2024 is configured to generate, based on the address offsets generated by the address generation section 2022, a data aggregation control signal for controlling the aggregation process of data bytes at each offset address associated with the split memory access operation in cache line L after loading, or a data dispersion control signal for controlling the dispersion process of register data associated with cache line L, and control the dispersion network to disperse the register data associated with cache line L based on the generated data dispersion control signal.

[0028] like Figure 3 As shown, in some embodiments, the address generation section 2022 includes the following three types of address generation nodes:

[0029] Type 1: When k is a power of 2 but stride is not a power of 2, use a shifter to implement stride << log2(k) to generate the calculation result of stride * k (for example, nodes N11 and N12);

[0030] Type 2: When stride is a power of 2 but k is not a power of 2, use a shifter to implement k << log2(stride) to generate the calculation result of stride * k (for example, nodes N21, N22, and N23);

[0031] Type 3: When k is not a power of 2 and stride is not a power of 2, combine the calculation results of the address generation nodes of Type 1 and the calculation results of the address generation nodes of Type 2 to generate the calculation result of stride * k (for example, node N31). For example, stride * 6 can be calculated by using (stride * 3 << 1), and stride * 7 can be calculated by using (stride << 3 - stride).

[0032] Since the calculation cost of the address generation nodes of Type 3 is the highest, only one address generation node of Type 3 is included in the Figure 3 illustrated embodiment. As Figure 3 shown, in the case of eewb = 1 byte, when stride is not a power of 2, 5 address offsets can be generated at a time; when stride is a power of 2, 8 address offsets can be generated at a time.

[0033] In Figure 3In the illustrated embodiment, when eewb = 1 byte, the address offsets of each offset address associated with the split memory access operation relative to the start address of cache line L are offset, offset + stride, offset + 2 * stride, ..., offset + 7 * stride; when eewb = 2 bytes, the address offsets of each offset address associated with the split memory access operation relative to the start address of cache line L are offset, offset + 1, offset + stride, offset + stride + 1, ..., offset + 7 * stride, offset + 7 * stride + 1; when eewb = 4 bytes, the address offsets of each offset address associated with the split memory access operation relative to the start address of cache line L are offset, offset + 1, offset + 2, offset + 3, offset + stride, offset + stride + 1, offset + stride + 2, offset + stride + 3, ... When eewb = 8 bytes, the address offsets associated with the split memory access operations relative to the starting address of cache line L are offset+1, offset+2, …, offset+7, offset+stride, offset+stride+1, offset+stride+2, …, offset+stride+7, …, offset+7*stride, offset+7*stride +1, offset+offset+7*stride+2, …, offset+offset+7*stride +7.

[0034] like Figure 3 As shown, in some embodiments, the address generation section 2022 further includes multiple multiplexers, each of which is configured to output a corresponding address offset to the address propagation network 2024 based on the value of eewb (i.e., eewb = 1 byte, 2 bytes, 4 bytes, or 8 bytes).

[0035] like Figure 3As shown, in some embodiments, the address propagation section 2024 includes a distributed network consisting of multiple input switches, multiple intermediate switches, and multiple output switches, and is further configured to generate an offset scattering control signal (hereinafter referred to as offset ctrl_scatter) for controlling the propagation path of the address offset addr_offset in the distributed network, based on the address offset addr_offset and the connection relationship between the address offset addr_offset in one of the multiple input switches and other switches in the distributed network. This offset scattering control signal serves as a data aggregation control signal (hereinafter referred to as data aggregation control signal D_ctrl_gather) for controlling the aggregation process of data bytes at the offset address corresponding to the address offset addr_offset in cache line L after loading, or a data scattering control signal (hereinafter referred to as data scattering control signal D_ctrl_scatter) for controlling the scattering process of register data associated with cache line L that is input to one of the input switches where the address offset addr_offset is input.

[0036] like Figure 3 As shown, in some embodiments, the address propagation section 2024 includes a distributed network consisting of four switch layers: layer 0, layer 1, layer 2, and layer 3. The switches in layer 3 are all input switches. Each address offset output by the address generation section 2022 is input to the corresponding input switch. The switches in layers 1 and 2 are all intermediate switches, and the switches in layer 0 are all output switches. Each input switch in layer 3 and each output switch in layer 0 are connected to each other via an intermediate switch in layer 1 and an intermediate switch in layer 2.

[0037] like Figure 3As shown, in some embodiments, each switch level in the address propagation section 2024 includes the same number of switches. For example, in the case where each switch level in the address propagation section 2024 includes 8 switches: the first outputs of the first to eighth input switches S3_0 to S3_7 of level 3, in left-to-right order, are respectively connected to the first inputs of the first to eighth intermediate switches S2_0 to S2_7 of level 2, in left-to-right order; the second outputs of the first to fourth input switches S3_0 to S3_3 of level 3, in left-to-right order, are respectively connected to the second inputs of the fifth to eighth intermediate switches S2_4 to S2_7 of level 2, in left-to-right order; the first outputs of the first to eighth intermediate switches S2_0 to S2_7 of level 2, in left-to-right order, are respectively connected to the first to eighth intermediate switches S2_0 to S2_7 of level 1, in left-to-right order. The first input terminals of switches S1_0 to S1_7, and the second output terminals of the first to sixth intermediate switches S2_0 to S2_5 in the left-to-right order of level 2 are respectively connected to the second input terminals of the third to eighth intermediate switches S1_2 to S1_7 in the left-to-right order of level 1; the first output terminals of the first to eighth intermediate switches S1_0 to S1_7 in the left-to-right order of level 1 are respectively connected to the first input terminals of the first to eighth output switches S0_0 to S0_7 in the left-to-right order of level 0; the second output terminals of the first to seventh intermediate switches S1_0 to S1_7 in the left-to-right order of level 1 are respectively connected to the second input terminals of the second to eighth output switches S0_1 to S0_7 in the left-to-right order of level 0.

[0038] For example, in Figure 3 In the distributed network shown, assuming the address offset "5" is input to the input switch S3_2 of layer 3, the address propagation section 2024 generates an offset scatter control signal ctrl_scatter_5 based on the address offset "5" and the connection relationship between the input switch S3_2 of layer 3 and other switches in the distributed network. This signal controls the propagation path of the address offset "5" in the distributed network, so that the distributed network, based on the offset scatter control signal ctrl_scatter_5, propagates the address offset "5" from the input switch S3_2 of layer 3 through the intermediate switch S2_2 of layer 2 and the intermediate switch S1_4 of layer 1 to the output switch S0_5 of layer 0. In other words, Figure 3The distributed network shown can be configured to, for the address offset `addr_offset` generated by the address generation section 2022, propagate the address offset `addr_offset` from one of the multiple input switches to the corresponding output switch among the multiple output switches, based on the offset scatter control signal `ctrl_scatter` used to control the propagation path of the address offset `addr_offset`. Correspondingly, for the register data (hereinafter referred to as register data D) input to the level 3 input switch S3_2, the address propagation section 2024 uses the offset scatter control signal `ctrl_scatter` as the data scatter control signal `D_ctrl_scatter` to control the distributed network to propagate the register data D from the level 3 input switch S3_2 via the level 2 intermediate switch S2_2 and the level 1 intermediate switch S1_4 to the level 0 output switch S0_5.

[0039] Figure 4 It is shown in the figure. Figure 2 The diagram shows an example hardware implementation of the data aggregation module. Figure 4 As shown, the data aggregation module 204 includes an aggregation network configured to perform as Figure 3 The distributed network shown represents the inverse of the distributed process, namely the aggregation process.

[0040] like Figure 4 As shown, in some embodiments, the data aggregation module 204 includes an aggregation network consisting of multiple input switches, multiple intermediate switches, and multiple output switches. A data byte at an offset address corresponding to the address offset `addr_offset` generated by the address generation section 2022 is input to a corresponding input switch in the aggregation network. The aggregation network is configured to control the data byte at the offset address corresponding to `addr_offset` to be transferred from one input switch to a corresponding output switch in the aggregation network based on a data aggregation control signal D_ctrl_gather, which controls the aggregation process of the data byte at the offset address corresponding to `addr_offset` after loading.

[0041] like Figure 4As shown, in some embodiments, the data aggregation module 204 includes an aggregation network consisting of four switch layers: layer 0, layer 1, layer 2, and layer 3. The switches in layer 0 are all input switches, and data bytes corresponding to the address offset generated by the address generation part 2022 are respectively input to the corresponding input switches in layer 0. The switches in layer 1 and layer 2 are all intermediate switches, and the switches in layer 3 are all output switches. Each input switch in layer 0 and each output switch in layer 3 are connected to each other via an intermediate switch in layer 1 and an intermediate switch in layer 2.

[0042] like Figure 4 As shown, in some embodiments, each switch level in the data aggregation module 204 includes the same number of switches. For example, in the case where each switch level in the data aggregation module 204 includes 8 switches: the first outputs of the first to eighth input switches SW0_0 to SW0_7 of level 0, in left-to-right order, are respectively connected to the first inputs of the first to eighth intermediate switches SW1_0 to SW1_7 of level 1, in left-to-right order; the second outputs of the second to eighth input switches SW0_1 to SW0_7 of level 0, in left-to-right order, are respectively connected to the second inputs of the first to seventh intermediate switches SW1_0 to SW1_6 of level 1, in left-to-right order; the first outputs of the first to eighth intermediate switches SW1_0 to SW1_7 of level 1, in left-to-right order, are respectively connected to the first to eighth intermediate switches of level 2, in left-to-right order. The first input terminals of SW2_0 to SW2_7, and the second output terminals of the third to eighth intermediate switches SW1_2 to SW1_7 in the left-to-right order of Level 1 are respectively connected to the second input terminals of the first to sixth intermediate switches SW2_1 to SW2_5 in the left-to-right order of Level 2; the first output terminals of the first to eighth intermediate switches SW2_0 to SW2_7 in the left-to-right order of Level 2 are respectively connected to the first input terminals of the first to eighth output switches SW3_0 to SW3_7 in the left-to-right order of Level 3; and the second output terminals of the fourth to eighth intermediate switches SW2_4 to SW2_7 in the left-to-right order of Level 2 are respectively connected to the second input terminals of the first to fourth output switches SW3_0 to SW3_3 in the left-to-right order of Level 3.

[0043] For example, suppose in Figure 3In the distributed network shown, the address offset "5" is input to the input switch S3_2 of level 3. The distributed network then transmits the address offset "5" from the input switch S3_2 of level 3 through the intermediate switch S2_2 of level 2 and the intermediate switch S1_4 of level 1 to the output switch S0_5 of level 0. Accordingly, in Figure 4 In the aggregation network shown, data byte 5, corresponding to address offset "5", is input to the input switch SW0_5 of layer 0 of the aggregation network. The aggregation network transmits data byte 5 from the input switch SW0_5 of layer 0 through the intermediate switch SW1_4 of layer 1 and the intermediate switch SW2_2 of layer 2 to the output switch SW3_2 of layer 3.

[0044] Figure 5a It is shown in the figure. Figure 3 and Figure 4 The diagram shows the logical structure of the input switch. Figure 5a As shown, the input switch 500a includes an input terminal in0, a control input terminal sel, a first output terminal out0, and a second output terminal out1. If the control signal received by the control input terminal sel is set to 1, the input signal of the input terminal in0 is output by the second output terminal out1, and the first output terminal out0 outputs invalid information. If the control signal received by the control input terminal sel is set to 0, the input signal of the input terminal in0 is output by the first output terminal out0, and the second output terminal out1 outputs invalid information.

[0045] Figure 5b It is shown in the figure. Figure 3 and Figure 4 The diagram shows the logical structure of the intermediate switch. Figure 5b As shown, the intermediate switch 500b includes a first input terminal in0, a second input terminal in1, a control input terminal sel, a first output terminal out0, and a second output terminal out1. If the control signal received by the control input terminal sel is set to 1, the input signal of the first input terminal in0 is output by the second output terminal out1, and the input signal of the second input terminal in1 is output by the first output terminal out0. If the control signal received by the control input terminal sel is set to 0, the input signal of the first input terminal in0 is output by the first output terminal out0, and the input signal of the second input terminal in1 is output by the second output terminal out1.

[0046] Figure 5c It is shown in the figure. Figure 3 and Figure 4 The diagram shows the logical structure of the output switch. Figure 5cAs shown, the input switch 500c includes a first input terminal in0, a second input terminal in1, and an output terminal out0. Only one of the input signals of the first input terminal in0 and the second input terminal in1 is a valid signal, and the output terminal out0 outputs the valid signal.

[0047] In summary, the vector loading memory unit according to the embodiments of this disclosure can significantly reduce memory access operations and improve the performance of constant step-size cross-step memory access by merging memory accesses for each relevant offset position in the same cache line into a single memory access, and by aggregating the loaded data in the loading operation or dispersing the register data in the storage operation through a dedicated shift network.

[0048] Figure 6 This is a block diagram illustrating an example computing device in which a vector processor according to various embodiments of the present disclosure can be used. Figure 6 As shown, computing device 600 includes one or more processors (or processor cores) 610, one or more memory / storage devices 620, and one or more communication resources 630, wherein these processors, memory / storage devices, and communication resources can be communicatively coupled to each other via bus 640 or other interface circuitry. In embodiments utilizing node virtualization (e.g., network function virtualization, NFV), a hypervisor 602 can be executed to provide an execution environment for one or more network slices / subslices, thereby utilizing the hardware resources of computing device 600.

[0049] Processor 610 may include, for example, processor 612 and processor 614. Processor 610 may be, for example, a central processing unit (CPU), a RISC processor, a complex instruction set computer (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0050] Memory / storage device 620 may include main memory, disk storage devices, or any suitable combination thereof. Memory / storage device 620 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0051] Communication resource 630 may include an interconnect or network interface controller, component, or other suitable device for communicating with one or more peripheral devices 604 or one or more databases 606 or other network elements via network 608. For example, communication resource 630 may include wired communication components (e.g., for coupling via universal serial bus (USB), Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components.

[0052] Instructions 650 may include software, programs, application programs, applets, or other executable code for causing at least any one of the processors 610 to perform various processing procedures. Instructions 650 may reside wholly or partially within processor 610 (e.g., in the processor's cache), memory / storage device 620, or any suitable combination thereof. Furthermore, any portion of instructions 650 may be transferred from any combination of peripheral device 604 or database 606 to hardware resource 600. Therefore, the memory of processor 610, memory / storage device 620, peripheral device 604, and database 606 are examples of computer-readable and machine-readable media.

[0053] While certain embodiments have been illustrated and described herein for purposes of description, various alternative and / or equivalent embodiments or implementations that achieve the same purpose may be substituted for the illustrated and described embodiments without departing from the scope of this disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, the embodiments described herein are clearly limited only by the appended claims and their equivalents.

Claims

1. A vector processor comprising a vector load store unit configured to split a memory access operation in a strided memory access, send a memory access request to a cache for any one cache line associated with the split memory access operation, and upon receiving a memory access grant from the cache for the cache line, load data from and gather the loaded data in a single memory access from a plurality of offset addresses in the cache line relative to a start address of the cache line, or scatter and store scattered register data to a plurality of offset addresses in the cache line relative to the start address of the cache line, respectively, associated with the cache line, wherein, The vector load store unit comprises an address generation module, which comprises: an address generation part configured to generate, based on a base address offset and a stride employed for a strided memory access to the cache line, address offset quantities of respective offset addresses in the cache line associated with the split memory access operation relative to a start address of the cache line by using a shifter and an adder; an address propagation part configured to generate, based on the address offset quantities generated by the address generation part, data scatter control signals for controlling a scatter process of register data associated with the cache line and control a scatter network to scatter the register data associated with the cache line based on the generated data scatter control signals.

2. The vector processor of claim 1, wherein, The vector load store unit further comprises: a data gather module configured to receive, from outside, data bytes at respective offset addresses in the cache line associated with the split memory access operation and gather the received data bytes based on data gather control signals for controlling a gather process of the data bytes at respective offset addresses in the cache line associated with the split memory access operation after being loaded, wherein the address propagation part is further configured to generate, based on the address offset quantities generated by the address generation part, data gather control signals for controlling a gather process of the data bytes at respective offset addresses in the cache line associated with the split memory access operation after being loaded.

3. The vector processor of claim 1, wherein, The address generation part comprises three types of address generation nodes: a type 1 address generation node configured to generate a result of stride*k by implementing stride<<log2(k) using the shifter when the number of strides k is a power of 2 but the stride stride employed for the strided memory access to the cache line is not a power of 2; a type 2 address generation node configured to generate a result of stride*k by implementing k<<log2(stride) using the shifter when the stride stride employed for the strided memory access to the cache line is a power of 2 but the number of strides k is not a power of 2; a type 3 address generation node configured to generate a result of stride*k by combining a result of the type 1 address generation node and a result of the type 2 address generation node when the number of strides k is not a power of 2 and the stride stride employed for the strided memory access to the cache line is not a power of 2.

4. The vector processor of claim 1, wherein, The address propagation part is further configured to, for any one address offset generated by the address generation part, generate, based on the address offset and a connection relationship between an input switch in which the address offset is input and other switches in the scatter network, an offset scatter control signal for controlling a propagation path of the address offset in the scatter network, as a data gather control signal for controlling an aggregation process of data bytes at an offset address corresponding to the address offset in the cache line after being loaded or a data scatter control signal for controlling a scatter process of register data input to the input switch in which the address offset is input and associated with the cache line.

5. The vector processor of claim 4, wherein, The scatter network includes four switch levels of level 0, level 1, level 2 and level 3, the plurality of input switches are located at the level 3, the plurality of intermediate switches are located at the level 1 and the level 2, and the plurality of output switches are located at the level 0, each input switch in the plurality of input switches and each output switch in the plurality of output switches are data connected to each other via one intermediate switch in the level 1 and one intermediate switch in the level 2.

6. The vector processor of claim 5, wherein, Each of the four switch levels includes the same number of switches.

7. The vector processor of claim 5, wherein, The scatter network is configured to, for any one address offset generated by the address generation part, based on the offset scatter control signal for controlling the propagation path of the address offset in the scatter network, transfer the address offset from the input switch in which the address offset is input to a corresponding output switch in the plurality of output switches level by level.

8. The vector processor of claim 2, wherein, The data aggregation module includes an aggregation network configured to implement an aggregation process which is an inverse process of the scatter process implemented by the scatter network.

9. The vector processor of claim 8, wherein, The aggregation network includes a plurality of input switches, a plurality of intermediate switches and a plurality of output switches, a data byte at an offset address corresponding to any one address offset generated by the address generation part is input to a corresponding input switch in the plurality of input switches, and the aggregation network is configured to control the data byte at the offset address corresponding to the address offset to be transferred from the one input switch to a corresponding output switch in the plurality of output switches in the aggregation network based on a data gather control signal for controlling an aggregation process of the data byte at the offset address after being loaded.

10. The vector processor of claim 9, wherein, The aggregation network comprises four switch levels, level 0, level 1, level 2, and level 3, the plurality of input switches is located at the level 0, the plurality of intermediate switches is located at the level 1 and the level 2, the plurality of output switches is located at the level 3, each input switch of the plurality of input switches and each output switch of the plurality of output switches are data connected to each other via one intermediate switch of the level 1 and one intermediate switch of the level 2.

11. The vector processor of claim 10, wherein, Each of the four switch levels comprises the same number of switches.

Images