Data prefetching method, device, computer equipment and storage medium

Abstract

The present disclosure provides a data prefetching method, apparatus, computer device, and storage medium, which are applied to a processor. The method includes: after receiving a prefetching mode and a prefetching distance from a first-level storage structure, an nth-level storage structure of the processor determines target data addresses from a plurality of initial data addresses included in the prefetching mode according to the prefetching distance, where n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching; the nth-level storage structure sends a prefetching request corresponding to each target data address to the (n + 1)th-level storage structure. By implementing the method of the present disclosure, the timeliness of prefetching can be effectively improved, the pollution of the cache caused by prefetching can be reduced, and thus the overall performance of the processor can be enhanced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of processors, and in particular, to a data prefetching method, apparatus, computer device, and storage medium. Background Art

[0002] The development of the storage speed of processors lags far behind the development of the operation speed of processors. The increasingly severe "Memory Wall" problem severely restricts the further improvement of processor performance. The cache is a storage mechanism designed based on the principle of program access locality, and its purpose is to bridge the huge gap between the processor's computing speed and the storage access speed as much as possible. The "Memory Wall" problem has led to the development of caches in the direction of large capacity and multi-level. The multi-level cache structure can reduce the average latency of data access with good locality, but it cannot reduce the latency of the first memory access, that is, the latency of compulsory misses.

[0003] The prefetching technology is the key to improving the memory access performance of processors. An important way to improve the memory access performance is to reduce the miss rate of cache access. Prefetching is a way to reduce compulsory misses by prefetching cache lines that the processor may need into all levels of the storage hierarchy in advance. Prefetching is essentially a mechanism for guessing the program memory access addresses, so it is necessary to analyze the program behavior. The core is to utilize the spatial locality and temporal locality existing in the program execution process, and its performance improvement also shows a large correlation with the characteristics of the executed program. If the prefetched data block has not returned when the required data block is used, resulting in untimely prefetching, it will reduce the improvement effect of prefetching on the processor performance. Prefetching will occupy the storage bandwidth of the processor, generate additional power consumption, and in addition, if the wrong cache line is fetched and the prefetching timing is incorrect, it may also cause cache pollution. The implementation of prefetching needs to be cautious. If there are problems with prefetching, it will not only not improve the overall performance of the processor, but will instead reduce the performance of the processor.

[0004] In the related art, the problems of untimely prefetching and cache pollution caused by prefetching cannot be effectively solved. Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.

[0006] To this end, the purpose of the present disclosure is to provide a data prefetching method, apparatus, computer device, and storage medium, which can effectively improve the timeliness of prefetching, reduce the pollution of the cache caused by prefetching, and thus improve the overall performance of the processor.

[0007] To achieve the above object, a data prefetching method according to an embodiment of the first aspect of the present disclosure is applied to a processor and includes:

[0008] After receiving a prefetching mode and a prefetching distance from a first-level storage structure, an n-level storage structure of the processor determines a target data address from a plurality of initial data addresses included in the prefetching mode according to the prefetching distance, where n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the n-level storage structure does not perform data prefetching;

[0009] The n-level storage structure sends a prefetching request corresponding to each target data address to an (n + 1)-level storage structure.

[0010] To achieve the above object, a data prefetching apparatus according to an embodiment of the second aspect of the present disclosure is applied to a processor and includes:

[0011] A determination module, configured to, after an n-level storage structure of the processor receives a prefetching mode and a prefetching distance from a first-level storage structure, determine a target data address from a plurality of initial data addresses included in the prefetching mode according to the prefetching distance, where n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the n-level storage structure does not perform data prefetching;

[0012] A sending module, configured to send a prefetching request corresponding to each target data address from the n-level storage structure to an (n + 1)-level storage structure.

[0013] A computer device according to an embodiment of the third aspect of the present disclosure includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the program, the data prefetching method according to the embodiment of the first aspect of the present disclosure is implemented.

[0014] A non-transitory computer-readable storage medium according to an embodiment of the fourth aspect of the present disclosure has a computer program stored thereon, and when the program is executed by a processor, the data prefetching method according to the embodiment of the first aspect of the present disclosure is implemented.

[0015] A computer program product according to an embodiment of the fifth aspect of the present disclosure, when instructions in the computer program product are executed by a processor, execute the data prefetching method according to the embodiment of the first aspect of the present disclosure.

[0016] The data prefetching method, apparatus, computer device, and storage medium provided by the present disclosure. The method includes: after receiving the prefetching mode and prefetching distance from the first-level storage structure, the nth-level storage structure of the processor determines a target data address from multiple initial data addresses included in the prefetching mode according to the prefetching distance, where n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching; the nth-level storage structure sends a prefetching request corresponding to each target data address to the (n + 1)th-level storage structure. Thereby, the timeliness of prefetching can be effectively improved, the pollution of the cache by prefetching can be reduced, and thus the overall performance of the processor can be enhanced.

[0017] Aspects and advantages additional to the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0019] Figure 1 is a schematic flowchart of a data prefetching method according to an embodiment of the present disclosure;

[0020] Figure 2 is a schematic flowchart of a data prefetching method according to another embodiment of the present disclosure;

[0021] Figure 3 is a schematic flowchart of a data prefetching method according to another embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of a memory hierarchy according to the present disclosure;

[0023] Figure 5 is a multi-level timeliness prefetching architecture diagram according to the present disclosure;

[0024] Figure 6 is a prefetching component diagram of each level of cache according to the present disclosure;

[0025] Figure 7 is a schematic hardware implementation diagram of a spatial storage stream prefetching strategy according to the present disclosure;

[0026] Figure 8 is a schematic structural diagram of a data prefetching apparatus according to an embodiment of the present disclosure;

[0027] Figure 9 shows a block diagram of an exemplary computer device suitable for implementing the embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present disclosure, and should not be construed as a limitation of the present disclosure. On the contrary, the embodiments of the present disclosure include all variations, modifications and equivalents falling within the spirit and scope of the appended claims.

[0029] Figure 1 is a schematic flowchart of a data prefetching method proposed in an embodiment of the present disclosure.

[0030] It should be noted that the execution subject of the data prefetching method in this embodiment is a data prefetching device, which can be implemented in software and / or hardware, and this device can be configured in a computer device. The computer device can include, but is not limited to, a terminal, a server, etc. For example, the terminal can be a mobile phone, a personal digital assistant, etc.

[0031] As Figure 1 shown, the data prefetching method includes:

[0032] S101: After receiving the prefetching mode and prefetching distance from the first-level storage structure, the nth-level storage structure of the processor determines a target data address from a plurality of initial data addresses included in the prefetching mode according to the prefetching distance, where n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching.

[0033] The storage structure of the processor may refer to the structure configured in the processor for storing data. For example, it may include an N-level cache (Cache) on the processor chip.

[0034] The first-level storage structure may refer to the first-level cache L1 Cache closest to the processor core in the N-level cache.

[0035] The prefetching mode can be used to indicate the address of the data to be prefetched.

[0036] The prefetching distance refers to the number of initial data addresses for which the nth-level storage structure does not perform data prefetching.

[0037] The initial data address refers to the data address included in the prefetching mode. The target data address refers to the address from which the nth-level storage structure needs to prefetch data from the (n + 1)th-level storage structure.

[0038] It can be understood that the multiple initial data addresses included in the prefetch pattern are arranged in sequence. When the embodiment of the present disclosure determines the target data address from the multiple initial data addresses included in the prefetch pattern according to the prefetch distance, it can ignore a specified number of initial data addresses that are ranked at the front based on the prefetch distance and use the initial data addresses that are ranked at the back as the target data address.

[0039] S102: The nth level storage structure sends a pre-fetch request corresponding to each target data address to the (n+1)th level storage structure.

[0040] The pre-fetch request refers to a request sent by the n-th level storage structure to the n+1-th level storage structure for pre-fetching data corresponding to a target data address.

[0041] It can be understood that the pre-fetch request sent by the n-th level storage structure to the (n+1)-th level storage structure can be regarded as a data access request.

[0042] Optionally, in some embodiments, when the n-level storage structure sends a prefetch request corresponding to each target data address to the n+1-level storage structure, it may be to determine the first matching result between the prefetch request and the historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request that the n-level storage structure has sent to the n+1-level storage structure; when the first matching result indicates that the n-level storage structure has not sent a prefetch request to the n+1-level storage structure, the n-level storage structure sends a prefetch request to the n+1-level storage structure. In this way, the bandwidth and power consumption loss caused by the n-level storage structure sending prefetch requests to the same data address multiple times can be effectively avoided.

[0043] The historical pre-fetch record table refers to a pre-configured table for recording pre-fetch requests sent from the n-th level storage structure to the n+1-th level storage structure.

[0044] The first matching result may be used to indicate whether the historical pre-fetch record table contains the pre-fetch request.

[0045] That is, in the embodiment of the present disclosure, when the first matching result indicates that the n-th level storage structure has sent a pre-fetch request to the (n+1)-th level storage structure, the n-th level storage structure may ignore the corresponding pre-fetch request.

[0046] In this embodiment, after receiving the prefetch mode and prefetch distance of the first-level storage structure, the nth-level storage structure of the processor determines a target data address from multiple initial data addresses included in the prefetch mode according to the prefetch distance, where n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching; the nth-level storage structure sends a prefetch request corresponding to each target data address to the (n + 1)th-level storage structure. Thus, the timeliness of prefetching can be effectively improved, the pollution of the cache caused by prefetching can be reduced, and the overall performance of the processor can be enhanced.

[0047] Figure 2 It is a schematic flowchart of a data prefetching method proposed in another embodiment of the present disclosure.

[0048] As Figure 2 shown, the data prefetching method includes:

[0049] S201: After receiving a first access request from the corresponding upper-level storage structure, the nth-level storage structure determines a second matching result between the first access request and a historical prefetch record table, where the historical prefetch record table is used to record prefetch requests that the nth-level storage structure has sent to the (n + 1)th-level storage structure, and the upper-level storage structure corresponding to the first-level storage structure is the processor core of the processor.

[0050] Among them, the upper-level storage structure may refer to a storage structure closer to the processor core than the nth-level storage structure.

[0051] Among them, the first access request is a request sent by the upper-level storage structure to the nth-level storage structure for data access. In the embodiments of the present disclosure, the first access request includes a prefetch request sent by the upper-level storage structure to the nth-level storage structure.

[0052] Among them, the second matching result can be used to indicate whether the nth-level storage structure has sent a prefetch request with the same target data address as the first access request to the (n + 1)th-level storage structure.

[0053] That is to say, in the embodiments of the present disclosure, after receiving the first access request from the corresponding upper-level storage structure, the nth-level storage structure can first perform matching processing on the first access request based on the historical prefetch record table to determine whether the nth-level storage structure has sent a prefetch request with the same target data address as the first access request to the (n + 1)th-level storage structure.

[0054] S202: When the nth-level storage structure meets a preset condition, update the prefetch distance, where the preset condition includes: the second matching result indicates that the nth-level storage structure has sent a prefetch request with the same target data address as the first access request to the (n + 1)th-level storage structure, and there is no data corresponding to the first access request in the nth-level storage structure.

[0055] The preset condition herein refers to the condition configured for whether the nth-level storage structure needs to update the prefetch distance in the embodiments of the present disclosure. The specific content of this preset condition can be flexibly configured according to the application scenario, and no limitation is imposed thereon.

[0056] Optionally, in some embodiments, when updating the prefetch distance, it may be to determine the prefetch performance metric of the nth-level storage structure; and update the prefetch distance according to the prefetch performance metric. Thereby, the practicality and effectiveness of the updated prefetch distance can be ensured in combination with the prefetch performance metric of the nth-level storage structure.

[0057] The prefetch performance metric can be used to measure the data prefetch ability of the nth-level storage structure.

[0058] Optionally, in some embodiments, the prefetch performance metric includes at least one of the following: the prefetch hit rate of the nth-level storage structure; the number of times the nth-level storage structure continuously meets the preset condition. Thereby, the indication effect of the prefetch performance metric on the data prefetch ability of the nth-level storage structure can be ensured.

[0059] The prefetch hit rate can be used to indicate the number of successful times in multiple data prefetch processes.

[0060] In this embodiment, after receiving the first access request from the corresponding upper-level storage structure, the nth-level storage structure determines the second matching result between the first access request and the historical prefetch record table, where the historical prefetch record table is used to record the prefetch requests sent by the nth-level storage structure to the (n + 1)th-level storage structure, and the upper-level storage structure corresponding to the first-level storage structure is the processor core of the processor; when the nth-level storage structure meets the preset condition, update the prefetch distance, where the preset condition includes: the second matching result indicates that the nth-level storage structure has sent a prefetch request with the same target data address as the first access request to the (n + 1)th-level storage structure, and there is no data corresponding to the first access request in the nth-level storage structure. Thereby, flexible adjustment of the prefetch distance can be achieved to ensure that the updated prefetch distance can be applicable to diverse application scenarios.

[0061] Optionally, in some embodiments, when determining the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, it may be to determine the target data address from the multiple initial data addresses included in the prefetch mode according to the updated prefetch distance. Thus, the practicality of the obtained target data address can be effectively improved based on the updated prefetch distance.

[0062] Figure 3 It is a schematic flowchart of a data prefetch method proposed in another embodiment of the present disclosure.

[0063] As Figure 3 shown, the data prefetch method includes:

[0064] S301: The first-level storage structure of the processor receives the second access request of the processor core and generates a prefetch mode according to the second access request.

[0065] That is to say, in the embodiment of the present disclosure, the first-level storage structure of the processor can receive the second access request of the processor core and generate a prefetch mode according to the second access request, so as to provide a reliable execution basis for the prefetch processes of subsequent levels of storage structures.

[0066] Optionally, in some embodiments, when generating a prefetch mode according to the second access request, it may be to determine the target event identifier corresponding to the second access request; determine the historical event identifier matching the target event identifier from the pattern history table, where the pattern history table includes multiple historical event identifiers and the historical patterns corresponding to each historical event identifier; and use the historical pattern corresponding to the matching historical event identifier as the prefetch mode. Thus, the adapted prefetch mode can be quickly and accurately determined in combination with the historical data access situation of the processor, and the practicality of the obtained prefetch mode can be ensured.

[0067] S302: The first-level storage structure determines the prefetch distance corresponding to the nth-level storage structure and sends the prefetch mode and the prefetch distance to the nth-level storage structure.

[0068] In the embodiment of the present disclosure, when determining the prefetch distance corresponding to the nth-level storage structure, it may be based on a preset relationship table, which contains the prefetch distance corresponding to each storage structure, or it may also be to determine the prefetch distance corresponding to the nth-level storage structure based on a data combination method, and there is no limitation to this.

[0069] Optionally, in some embodiments, when determining the prefetch distance corresponding to the nth-level storage structure, it may be to determine the number of storage structure layers between the first-level storage structure and the nth-level storage structure; determine the initial distance corresponding to the nth-level storage structure according to the number of storage structure layers; and determine the prefetch distance corresponding to the nth-level storage structure according to the initial distance. Thus, the applicability of the obtained prefetch distance can be ensured by combining the position information of different storage structures.

[0070] Among them, the number of storage structure layers can be used to indicate the number of storage structure layers between the first-level storage structure and the nth-level storage structure. For example, the number of storage structure layers between the first-level storage structure and the seventh-level storage structure is 6.

[0071] Among them, the initial distance can refer to the prefetch distance in the initial state configured for the nth-level storage structure according to the number of storage structure layers.

[0072] For example, in the embodiments of the present disclosure, when determining the initial distance corresponding to the nth-level storage structure according to the number of storage structure layers, it may be based on a pre-configured relationship table that contains the initial distance corresponding to the above-mentioned number of storage structure layers, or it may also be based on statistical or intelligent learning methods to determine the initial distance corresponding to the nth-level storage structure according to the number of storage structure layers, and there is no limitation on this.

[0073] Optionally, in some embodiments, when determining the initial distance corresponding to the nth-level storage structure according to the number of storage structure layers, it may be to determine the product value of the preset distance value and the number of storage structure layers as the initial distance. Thus, the initial distance corresponding to different-level storage structures can be quickly configured based on the preset distance value.

[0074] Among them, the preset distance value can be flexibly configured according to the application scenario, and there is no limitation on this. For example, when the prefetch distance value is configured to be 2, the initial distance corresponding to the fifth-level storage structure is .

[0075] In the embodiments of the present disclosure, when determining the prefetch distance corresponding to the nth-level storage structure according to the initial distance, it may be to directly use the initial distance as the prefetch distance corresponding to the nth-level storage structure, or it may also be that a third-party device adjusts the initial distance to obtain the prefetch distance corresponding to the nth-level storage structure, and there is no limitation on this.

[0076] Optionally, in some embodiments, when determining the prefetch distance corresponding to the nth-level storage structure according to the initial distance, it may be to determine the prefetch performance metrics of the nth-level storage structure during multiple data prefetch processes; adjust the initial distance according to multiple prefetch performance metrics to obtain the prefetch distance corresponding to the nth-level storage structure. Thus, the prefetch performance metrics of the nth-level storage structure during multiple data prefetch processes can be combined to evaluate the data prefetch ability of the nth-level storage structure, and then the initial distance can be adaptively adjusted to ensure that the obtained preset distance can effectively improve the data prefetch ability of the nth-level storage structure.

[0077] For example, in the embodiments of the present disclosure, when determining the prefetch distance corresponding to the nth-level storage structure according to the number of storage structure layers, the specific value of the prefetch distance may be configured to be in a direct proportion relationship with the number of storage structure layers.

[0078] In this embodiment, the first-level storage structure of the processor receives the second access request from the processor core and generates a prefetch mode according to the second access request; the first-level storage structure determines the prefetch distance corresponding to the nth-level storage structure and sends the prefetch mode and the prefetch distance to the nth-level storage structure. Thus, the reliability of the prefetch mode and the prefetch distance obtained by the nth-level storage structure can be guaranteed.

[0079] Combined with the above embodiments, the present disclosure aims at the main problems of untimely prefetching and cache pollution caused by prefetching in prefetching. By setting the prefetch distance and fetching the prefetch block to different storage levels at different times, the timeliness of prefetching is improved, and the cache pollution caused by prefetching is reduced, thereby improving the overall performance of the processor.

[0080] As Figure 4 shown, Figure 4It is a schematic diagram of a memory hierarchy proposed according to the present disclosure. The processor includes multiple levels of memory hierarchy, including the N-level cache (Cache) on the processor chip and off-chip memory. The cache is usually composed of static random access memory (SRAM). The cache includes the first-level cache L1Cache, the second-level cache L2 Cache, the third-level cache L3 Cache, up to the N-level cache LN Cache (also called the last-level cache Last Level Cache, LLC). The off-chip memory is usually composed of dynamic random access memory (DRAM). From the first-level cache L1 Cache, the second-level cache L2 Cache, the third-level cache L3 Cache to the last-level cache LLC and off-chip memory, the distance of each level of memory hierarchy from the processor core is getting farther, the capacity is gradually increasing, and the access latency is also gradually increasing.

[0081] As Figure 5 shown, Figure 5 It is a multi-level timely prefetch architecture diagram proposed according to the present disclosure. The present disclosure provides a multi-level timely prefetch method and device, including: a prefetch component, a processor core, the N-level cache (Cache) on the chip, and off-chip memory.

[0082] Aiming at the problem that the prefetch by the prefetch component is too late and not timely, the present disclosure sets a prefetch distance, skips a section of the prefetch pattern (Pattern) at the head, and performs prefetch. The sign for the present disclosure to judge that the prefetch is too late is that when a normal memory access request accesses the cache, the prefetch request has been sent, but the data has not returned yet, that is, the normal access request hits the prefetch block, but the data of the prefetch block has not returned yet. In this case, by increasing the prefetch distance and sending a more subsequent pattern (Pattern) for prefetch, the problem of untimely prefetch caused by the prefetch being sent too late is solved.

[0083] The training of the prefetch pattern of the present disclosure is carried out using the access requests sent by the processor core to the first-level cache. The prefetch requests are sent to each level of cache. The prefetch of each level of cache does not affect each other. The prefetch pattern will be sent to each level of cache for prefetch, and the prefetch will be carried out separately at each level of cache. Finally, the prefetch will reach the first-level cache closest to the processor core. The prefetch of the processor for the following levels of cache can achieve the purpose of making the prefetch of the upper-level cache hit in the lower-level cache, which saves more prefetch time. Each level of prefetch request is a normal access request for the lower-level cache. If the prefetch is too late, the prefetch distance is dynamically adjusted, so as to realize the timely prefetch of each level of cache.

[0084] The prefetch pattern generation of the present disclosure is performed in the level-1 cache, and the training of prefetch pattern generation is carried out using the access requests issued by the processor core. Therefore, the prefetch pattern generation component is only in the level-1 cache. The generated prefetch pattern is sent to each level of cache for prefetching, and the prefetch distances sent to each level of cache are different.

[0085] As Figure 6 shown, Figure 6 FIG. is a prefetch component diagram of each level of cache proposed according to the present disclosure, and each level of cache includes the prefetch component of this level. The multi-level timely prefetch of the present disclosure includes a prefetch access pattern receiving component, a prefetch filtering component, and a prefetch issuing component.

[0086] The prefetch access pattern receiving component is responsible for receiving the prefetch access pattern sent by the prefetch generation component of the level-1 cache.

[0087] The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch distance.

[0088] The prefetch filtering component records the issued prefetch requests. When there is a new prefetch request, it first checks the prefetch filtering component. If the prefetch request has been issued, the same prefetch request is not issued repeatedly, saving memory access bandwidth.

[0089] After each level of cache receives the access request from the upper-level cache (including the prefetch request of the upper-level cache), it checks the prefetch filtering component of this level to determine whether it belongs to the situation where the prefetch request has been issued and the data has not returned. If it belongs to the situation where the prefetch request has been issued and the data has not returned, it means that the prefetch of this level is not timely and the prefetch distance needs to be adjusted. The subsequent prefetch will skip a prefetch distance and issue the subsequent prefetch pattern.

[0090] The prefetch pattern generation of the level-1 cache of the present disclosure is applicable to various prefetch strategies, and the commonly used spatial memory streaming (SMS) strategy is used as an example of prefetch pattern generation.

[0091] Spatial Memory Streaming (SMS) was proposed and evaluated in the context of server and scientific applications. The SMS hardware prefetcher utilizes spatial correlation. Whenever a certain spatial region is requested for the first time, SMS uses the information about the miss to look up the previously observed pattern in the table. As long as the application is using the spatial region, SMS starts observing and recording the accesses to the spatial region. Whenever the spatial region is no longer in use (i.e., the response blocks of the spatial region start to be evicted from the cache), the access information observed by SMS is stored in the Pattern History Table (PHT).

[0092] The information in the pattern history table PHT is in the form of <event, pattern> (<event,pattern> ). Event event can be Program Counter (PC) + Address, Program Counter (PC) + Offset, Address, Offset, i.e. PC+Address / PC+Offset / Address / Offset, etc., which is a piece of information associated with the observed access pattern. That is, if the event occurs again in the future, the corresponding storage access pattern will be used. For example, SMS selects Program Counter (PC) + Offset that triggers the access, i.e., the PC of the instruction that first accesses the spatial region plus the distance between the first requested cache block and the beginning of the spatial region, as the event related to the access pattern. In this way, whenever PC+Offset reappears, the relevant access pattern history will be used to issue a prefetch request. The pattern is the history of accesses that occurred in each spatial region. SMS encodes the access pattern as a bit vector. In this way, for each cache block in the spatial region, a bit is stored to indicate whether the block has been used in the spatial region in the last time, and it is marked as "1" if it is used, and "0" if it is not. Therefore, whenever a pattern is used, prefetch requests are only issued for blocks whose corresponding bits in the storage pattern are "1". Figure 7 It is a schematic diagram of the hardware implementation of the spatial storage stream prefetching strategy proposed in the present disclosure.

[0093] The present invention issues a spatial region prefetch request pattern to each level of cache, i.e., 0x24D8, ..., 0X24F7. When the prefetch request is sent to the next level storage system, it is found that the prefetch request of the next level storage system is sent but the data is not returned, so the distance of sending the prefetch request to the next level storage system is adjusted, such as sending a request to the secondary cache from 0x24F7 instead of 0x24D8. The adjustment of sending the prefetch request can be moved back one mode request each time, or multiple mode requests can be moved back each time, and it can be dynamically adjusted according to the timeliness evaluation of the prefetch.

[0094] The timeliness of prefetching can be evaluated based on the timeliness of prefetching. For example, if prefetching is not timely for the first time, the prefetching request is moved back by one mode request. If prefetching is not timely again, the prefetching distance is adjusted more aggressively, such as the prefetching request can be moved back by two mode requests. The prefetching distance can also be adjusted based on other performance indicators such as the hit rate of the cache at this level.

[0095] A larger prefetch distance is set for the cache levels farther from the processor in the multi-level cache. The prefetch unit skips a certain prefetch distance and sends it to the next-level cache for prefetching. For example, it skips a larger prefetch distance to the secondary cache for prefetching. In this way, when the primary cache performs prefetching again, it can hit in the secondary cache, which speeds up the prefetch speed of the primary cache. The specific prefetch distance to be skipped and sent to the next-level cache for prefetching can be generated through training. For example, initially, for each cache level prefetch, two requests are made from the shifted patterns. Subsequently, it is dynamically adjusted according to the evaluation of untimely prefetching or the hit rates of each cache level.

[0096] Figure 8 It is a schematic structural diagram of a data prefetching device proposed in an embodiment of the present disclosure.

[0097] As Figure 8 shown, the data prefetching device 80 is applied to a processor. The device includes:

[0098] A determination module 801, configured to, after the nth-level storage structure of the processor receives the prefetch pattern and prefetch distance of the first-level storage structure, determine a target data address from a plurality of initial data addresses included in the prefetch pattern according to the prefetch distance, where n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching;

[0099] A sending module 802, configured to send a prefetch request corresponding to each target data address from the nth-level storage structure to the n+1th-level storage structure.

[0100] It should be noted that the foregoing explanation of the data prefetching method also applies to the data prefetching device in this embodiment, and will not be elaborated here.

[0101] In this embodiment, after the nth-level storage structure of the processor receives the prefetch pattern and prefetch distance of the first-level storage structure, it determines a target data address from a plurality of initial data addresses included in the prefetch pattern according to the prefetch distance, where n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the nth-level storage structure does not perform data prefetching; the nth-level storage structure sends a prefetch request corresponding to each target data address to the n+1th-level storage structure. Thereby, the timeliness of prefetching can be effectively improved, the pollution of the cache by prefetching can be reduced, and thus the overall performance of the processor can be enhanced.

[0102] Figure 9 It shows a block diagram of an exemplary computer device suitable for implementing the embodiments of the present disclosure. Figure 9 The shown computer device 12 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0103] AsFigure 9 As shown, the computer device 12 is presented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects different system components (including the system memory 28 and the processing unit 16).

[0104] The bus 18 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. By way of example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnection (PCI) bus.

[0105] The computer device 12 typically includes a variety of computer system-readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0106] The memory 28 may include computer system-readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 can be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 9 not shown, commonly referred to as a "hard disk drive").

[0107] Although Figure 9Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a Compact Disc Read Only Memory (hereinafter referred to as "CD-ROM"), a Digital Video Disc Read Only Memory (hereinafter referred to as "DVD-ROM") or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 through one or more data medium interfaces. The memory 28 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments of the present disclosure.

[0108] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment. The program modules 42 generally execute the functions and / or methods in the embodiments described in the present disclosure.

[0109] The computer device 12 may also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and may also communicate with one or more devices that enable a human body to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication may be carried out through the input / output (I / O) interface 22. Moreover, the computer device 12 may also communicate with one or more networks (such as a Local Area Network (hereinafter referred to as "LAN"), a Wide Area Network (hereinafter referred to as "WAN") and / or a public network, such as the Internet) through the network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the computer device 12 through the bus 18. It should be understood that although not shown in the figure, other hardware and / or software modules may be used in combination with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0110] The processing unit 16 executes various functional applications and data processing by running the programs stored in the system memory 28, such as implementing the data prefetch method mentioned in the foregoing embodiments.

[0111] To implement the above embodiments, the present disclosure also provides a non-transitory computer-readable storage medium storing a computer program, which when executed by a processor, implements the data prefetching method as proposed in the foregoing embodiments of the present disclosure.

[0112] To implement the above embodiments, the present disclosure also provides a computer program product, which when the instruction processor in the computer program product executes, implements the data prefetching method as proposed in the foregoing embodiments of the present disclosure.

[0113] Those skilled in the art will readily conceive of other implementations of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only illustrative, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0114] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0115] It should be noted that in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0116] Any process or method description in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art of the embodiments of the present disclosure.

[0117] It should be understood that each part of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following well-known technologies in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0118] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by a program instructing relevant hardware. The said program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0119] In addition, in each of the various embodiments of the present disclosure, the functional units can be integrated into one processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0120] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, or the like.

[0121] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0122] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A data pre-fetching method, characterized in that: Applied to a processor, the method comprises: After receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the n-th level storage structure does not perform data prefetching; The nth level storage structure sends a pre-fetch request corresponding to each of the target data addresses to the n+1th level storage structure; The method further comprises: After receiving a first access request corresponding to an upper level storage structure, the nth level storage structure determines a second matching result between the first access request and a historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request sent by the nth level storage structure to the n+1th level storage structure, and the upper level storage structure corresponding to the first level storage structure is a processor core of the processor; The n-level storage structure updates the prefetch distance when a preset condition is met, wherein the preset condition includes: the second matching result indicates that the n-level storage structure has sent the prefetch request with the same target data address as the first access request to the n+1-level storage structure, and there is no data corresponding to the first access request in the n-level storage structure.

2. The method according to claim 1, characterized in that The sending a pre-fetch request corresponding to each of the target data addresses to the n+1th level storage structure includes: Determine a first matching result between the prefetch request and a historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request that the n-th level storage structure has sent to the n+1-th level storage structure; When the first matching result indicates that the n-th level storage structure has not sent the pre-fetch request to the n+1-th level storage structure, the n-th level storage structure sends the pre-fetch request to the n+1-th level storage structure.

3. The method according to claim 1, characterized in that The determining the target data address from a plurality of initial data addresses included in the prefetch mode according to the prefetch distance comprises: The target data address is determined from the multiple initial data addresses included in the prefetch pattern according to the updated prefetch distance.

4. The method according to claim 1, characterized in that The updating of the pre-fetch distance comprises: Determining a prefetch performance indicator of the nth level storage structure; The prefetch distance is updated according to the prefetch performance indicator.

5. The method according to claim 4, characterized in that The pre-fetch performance indicator includes at least one of the following: A prefetch hit rate of the n-th level storage structure; The number of times the n-th level storage structure continuously satisfies the preset condition.

6. The method according to claim 5, characterized in that The method further comprises: The first level storage structure of the processor receives a second access request from the processor core, and generates the pre-fetch pattern according to the second access request; The first level storage structure determines the pre-fetch distance corresponding to the n-th level storage structure, and sends the pre-fetch mode and the pre-fetch distance to the n-th level storage structure.

7. The method according to claim 6, characterized in that Generating the prefetch mode according to the second access request includes: determining a target event identifier corresponding to the second access request; Determining a historical event identifier that matches the target event identifier from a pattern history table, wherein the pattern history table includes a plurality of the historical event identifiers and a historical pattern corresponding to each of the historical event identifiers; The historical pattern corresponding to the matched historical event identifier is used as the pre-fetch pattern.

8. The method according to claim 6, characterized in that The determining the pre-fetch distance corresponding to the n-th level storage structure comprises: Determine the number of storage structure layers between the first-level storage structure and the n-th-level storage structure; Determining an initial distance corresponding to the n-th level storage structure according to the number of layers of the storage structure; The pre-fetch distance corresponding to the n-th level storage structure is determined according to the initial distance.

9. The method according to claim 8, characterized in that The determining, according to the number of layers of the storage structure, an initial distance corresponding to the n-th level storage structure comprises: A product value of a preset distance value and the number of layers of the storage structure is determined as the initial distance.

10. The method according to claim 8, characterized in that The step of determining the pre-fetch distance corresponding to the n-th level storage structure according to the initial distance includes: Determining the prefetching performance index of the n-th level storage structure during multiple data prefetching processes; The initial distance is adjusted according to the plurality of pre-fetch performance indicators to obtain the pre-fetch distance corresponding to the n-th level storage structure.

11. A data pre-fetching device, characterized in that: Applied to a processor, the device comprises: a determination module, for the nth level storage structure of the processor, after receiving the prefetch mode and prefetch distance of the first level storage structure, determining the target data address from a plurality of initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the nth level storage structure does not perform data prefetching; A sending module, used for the n-th level storage structure to send a pre-fetch request corresponding to each of the target data addresses to the n+1-th level storage structure; The determination module is further configured to determine, after the n-th level storage structure receives a first access request corresponding to the upper-level storage structure, a second matching result between the first access request and a historical prefetch record table, wherein the historical prefetch record table is configured to record the prefetch request sent by the n-th level storage structure to the n+1-th level storage structure, and the upper-level storage structure corresponding to the first-level storage structure is a processor core of the processor; An update module is used to update the prefetch distance when the n-th level storage structure meets a preset condition, wherein the preset condition includes: the second matching result indicates that the n-th level storage structure has sent the prefetch request with the same target data address as the first access request to the n+1-th level storage structure, and there is no data corresponding to the first access request in the n-th level storage structure.

12. A computer device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 10.

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