Data elimination method, device, storage device and computer-readable storage medium

Abstract

The present invention relates to data storage technology, and provides a data elimination method, device, storage device and computer-readable storage medium, which are applied to a storage device, wherein a plurality of cache data are stored in a cache of the storage device, and the method comprises: obtaining the access data amount of each preset cycle in a plurality of preset cycles, wherein the access data amount of each preset cycle is the data amount of cache data that has been accessed in each preset cycle and has not been accessed after the preset cycle; determining target cache data from a plurality of cache data according to the access data amount of the plurality of preset cycles and the preset cycle in which each cache data was most recently accessed; and performing elimination operation on the target cache data to delete the target cache data from the cache. The present invention can avoid the locking overhead caused by the LRU algorithm based on the linked list, and improve the elimination efficiency of the cache.

Description

Technical Field

[0001] The present invention relates to the field of data storage technology, and in particular to a data elimination method, apparatus, storage device and computer-readable storage medium. Background Art

[0002] Caching is a commonly used technology in data storage systems to speed up data access in data storage systems. Cache usually uses high-performance storage media such as memory to store frequently accessed data in the cache. When reading data, it is searched from the cache first. When writing data, it is first updated to the cache and then asynchronously flushed to other storage media in the data storage system. Since the cached storage media provides higher access performance, it speeds up the overall access efficiency of the data storage system.

[0003] Due to cost and system architecture constraints, cache space is usually limited and cannot cache all data. When the cache space reaches a certain level, it is necessary to eliminate some relatively infrequently accessed data to make room for caching other frequently accessed data. The Least Recently Used (LRU) algorithm is a commonly used elimination algorithm.

[0004] The LRU algorithm is usually implemented based on a bidirectional linked list. In order to ensure that the eliminated data is the data that has not been used for the longest time, the LRU linked list needs to be updated each time the data in the cache is accessed, and the currently accessed data is placed at the head of the linked list. If the linked list is full, the data at the end of the linked list needs to be eliminated.

[0005] In data storage systems, it is very common to provide multi-threaded data access scenarios. In order to avoid list pointer exceptions and program crashes caused by multiple threads operating the LRU list concurrently, each operation on the LRU list needs to be locked. The greater the concurrency, the greater the locking overhead, which affects the cache elimination efficiency and ultimately the overall access efficiency of the data storage system. Summary of the invention

[0006] The present invention aims to provide a data elimination method, apparatus, storage device and computer-readable storage medium, which can improve the elimination efficiency of cache.

[0007] The embodiments of the present invention can be implemented as follows:

[0008] In a first aspect, the present invention provides a data elimination method, which is applied to a storage device, wherein a cache of the storage device stores a plurality of cache data, and the method comprises:

[0009] Acquire the access data volume of each preset cycle in a plurality of preset cycles, wherein the access data volume of each preset cycle is the data volume of cache data accessed in each preset cycle and not accessed after the preset cycle;

[0010] Determining target cache data from the plurality of cache data according to the access data amounts of the plurality of preset cycles and the preset cycle in which each cache data was most recently accessed;

[0011] An elimination operation is performed on the target cache data to delete the target cache data from the cache.

[0012] In an optional implementation, the step of determining the target cache data from the plurality of cache data according to the access data amounts of the plurality of preset cycles and the preset cycle in which each cache data was most recently accessed comprises:

[0013] Determining a target cycle from the plurality of preset cycles according to the access data amounts of the plurality of preset cycles;

[0014] The cache data whose last accessed preset period is not later than the target period is used as the target cache data.

[0015] In an optional implementation manner, the step of determining a target period from the plurality of preset periods according to the access data amounts of the plurality of preset periods comprises:

[0016] According to the time sequence of the multiple preset cycles, starting from the latest preset cycle, the access data volume of each preset cycle is accumulated one by one;

[0017] If the access data statistics accumulated this time are greater than the preset data amount, the preset period corresponding to the access data amount accumulated this time is used as the target period.

[0018] In an optional implementation manner, the step of determining a target period from the plurality of preset periods according to the access data amounts of the plurality of preset periods comprises:

[0019] If the number of preset cycles is greater than the preset number, the earliest preset cycle is used as the target cycle.

[0020] In an optional embodiment, the method further comprises:

[0021] If the target data accessed in the current preset cycle does not hit the cache, storing the target data in the cache as target cache data;

[0022] Using the current preset period as the preset period during which the target cache data was last accessed;

[0023] According to the size of the target data, the access data amount of the current preset period is increased.

[0024] In an optional embodiment, the method further comprises:

[0025] If the target data accessed in the current preset period hits the target cache data in the cache, the preset period in which the target cache data was most recently accessed is used as the preset period to be updated;

[0026] According to the size of the target cache data, reducing the amount of access data to be updated in the preset period;

[0027] According to the size of the target cache data, increasing the amount of access data in the current preset cycle;

[0028] If the preset update condition is met, the current preset period is used as the preset period in which the target cache data was most recently accessed.

[0029] In an optional embodiment, the method further comprises:

[0030] If the target data is accessed for the first time within the current preset period, it is determined that the preset update condition is met; otherwise, it is determined that the preset update condition is not met.

[0031] In a second aspect, the present invention provides a data elimination device, which is applied to a storage device, wherein a cache of the storage device stores a plurality of cache data, and the device comprises:

[0032] An acquisition module, used to acquire the access data volume of each preset cycle in a plurality of preset cycles, wherein the access data volume of each preset cycle is the data volume of cache data accessed in each preset cycle and not accessed after the preset cycle;

[0033] A determination module, configured to determine target cache data from the plurality of cache data according to the access data amounts of the plurality of preset cycles and the preset cycle in which each cache data was most recently accessed;

[0034] The elimination module is used to perform an elimination operation on the target cache data to delete the target cache data from the cache.

[0035] In a third aspect, the present invention provides a storage device, including a processor and a memory, wherein the memory is used to store a program, and the processor is used to implement a data elimination method as described in any one of the aforementioned embodiments when executing the program.

[0036] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data elimination method as described in any one of the aforementioned embodiments.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention records the access data volume of cached data in each preset cycle according to a preset cycle, and determines the target cached data that needs to be eliminated according to the access data volume of multiple preset cycles and the preset cycle in which each cached data was most recently accessed. Since the access quantity of each preset cycle is the data volume of cached data that has been accessed in each preset cycle and has not been accessed after the preset cycle, there is no need to use a linked list to organize the cached data, and the target cached data that needs to be eliminated can be eliminated in time, thereby avoiding the locking overhead brought by the LRU algorithm based on the linked list and improving the cache elimination efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is an example diagram of using a linked list to organize cache data provided in this embodiment.

[0041] Figure 2 This is an example flowchart of the data elimination method provided in this embodiment.

[0042] Figure 3 This is an example diagram of the improved cache data organization provided in this embodiment.

[0043] Figure 4 This is an example diagram of the data elimination process provided in this embodiment.

[0044] Figure 5 This is an example block diagram of the data elimination device provided in this embodiment.

[0045] Figure 6 This is a block diagram of an example storage device provided in this embodiment.

[0046] Icons: 10 - storage device; 11 - processor; 12 - memory; 13 - bus; 100 - data elimination device; 110 - acquisition module; 120 - determination module; 130 - elimination module; 140 - update module. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0050] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0051] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0052] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0053] In order to eliminate cache data that is not frequently used in time, the LRU algorithm usually uses a linked list to organize cache data. Each time the cache data is accessed, the linked list needs to be updated, that is, the cache data just accessed is placed at the head of the linked list. If the linked list is full, the cache data at the end of the linked list needs to be eliminated. The operation of the linked list needs to be locked, otherwise multiple threads operating the linked list at the same time will cause the linked list pointer to be abnormal and the program to crash. In a large concurrency scenario, the locking overhead will also increase, which will become a performance bottleneck of the cache system. In addition, in order to improve the efficiency of linked list operations, a bidirectional linked list is usually used to organize the cache data so that the position of the cache data in the linked list can be moved in the fastest way. In the implementation of the bidirectional linked list, two pointers are required for each cache data, pointing to the two cache data adjacent to the cache data. When the amount of cache data is large, the space occupied by the pointer required by the bidirectional linked list is also relatively large.

[0054] For a more intuitive description of how linked lists organize cache data, please refer to Figure 1 , Figure 1 This is an example diagram of using a linked list to organize cache data provided in this embodiment. Figure 1 In the chain, the hash table is used for fast search of cached data. Each element is a cached data. Each cached data includes a pre pointer and a next pointer. The pre pointer points to the previous cached data, and the next pointer points to the next cached data. Through the pre pointer and the next pointer, the corresponding cached data can be easily moved to any position in the linked list.

[0055] As described above, the linked list cache data organization method has a relatively large lock overhead for updating the linked list, and the space occupied by the pointer is also relatively large. In view of this, the present embodiment provides a data elimination method, apparatus, storage device and computer-readable storage medium, the core improvement of which is that: instead of using a linked list to organize cache data, the amount of access data of the cached data in each preset cycle and the preset cycle in which each cached data was most recently accessed are recorded according to a preset cycle, and the cached data that has been least recently accessed is eliminated in time, thereby improving the cache elimination efficiency, which will be described in detail below.

[0056] Please refer to Figure 2 , Figure 2 This is a flowchart of a data elimination method provided in this embodiment, and the method includes the following steps:

[0057] Step S101 , obtaining the access data volume of each preset cycle in a plurality of preset cycles, wherein the access data volume of each preset cycle is the data volume of cache data accessed in each preset cycle and not accessed after the preset cycle.

[0058] In this embodiment, the number of cycles in a preset period can be determined according to the validity period and the frequency of elimination of the elimination strategy. For example, if the validity period is 1 hour and 1 minute is a preset period, the number of cycles in a preset period is 60. It is necessary to record the amount of accessed data in each of the 60 preset periods of each cycle, and it is also necessary to record the preset period in which each cache data was most recently accessed. That is, one cycle includes 60 cycles, and a loop array with a length of 60 can be used to record the amount of accessed data in the 60 preset periods of one cycle. When the number of preset periods is greater than 60, continue recording from the first element of the loop data, that is, the amount of accessed data in the 61st preset period is recorded in the first element of the loop array, and so on.

[0059] In this embodiment, a plurality of cache data are stored in the cache of the storage device, and the data size of all the cache data may be the same or different. For example, the size of each cache data is 4KB, or the size of some cache data is 4KB, and the size of some cache data is 8KB, etc. The access data volume of each preset cycle is the sum of the data volumes of the cache data accessed within the preset cycle. For example, within preset cycle a, two cache data are accessed: cache data 1 and cache data 2, the size of cache data 1 is 4KB, and the size of cache data 2 is 8KB, then the access data volume of preset cycle a is 4KB+8KB=12KB.

[0060] Step S102 , determining target cache data from a plurality of cache data according to the access data amounts of a plurality of preset cycles and the preset cycle in which each cache data was most recently accessed.

[0061] In this embodiment, the target cache data is data that needs to be eliminated and satisfies a preset least recently used elimination policy.

[0062] In this embodiment, since the number of preset cycles is relatively limited, the preset cycle in which each cached data is most recently accessed can be represented by a variable of an integer type. In computer language, the space occupied by an integer type variable is definitely smaller than the space occupied by two pointer type variables. For example, in a 32-bit machine, for C language, an integer type variable occupies 4 bytes and a pointer type variable occupies 4 bytes. For a cached data, the number of bytes occupied is reduced by 4 bytes. When the amount of cached data is large, the space saved by the method provided by this embodiment is also considerable.

[0063] Please refer to Figure 3 , Figure 3 This is an example diagram of the improved cache data organization provided in this embodiment. Figure 3In the memory, each element includes a variable cycleId for storing the preset cycle in which the element was most recently accessed. In addition, the storage device also maintains an array whose size is the same as the number of preset cycles. Each data element is used to record the amount of accessed data in the corresponding cycle. Each data element includes two parts: cycle and data-number. The former corresponds to the preset cycle, and the latter corresponds to the amount of accessed data in the preset cycle.

[0064] Step S103: performing an elimination operation on the target cache data to delete the target cache data from the cache.

[0065] In this embodiment, the elimination operation is performed on the target cache data, which may be to invalidate the target cache data or to release the space occupied by the target cache data.

[0066] The above method provided in this embodiment records the access data volume of cached data in each preset period and the preset period in which each cached data was most recently accessed according to the preset period, and timely eliminates the cached data that has been least recently accessed, thereby improving the cache elimination efficiency.

[0067] In an optional implementation manner, since each cache data records the preset period in which it was last accessed, the target cache data can be determined according to the preset period. One implementation manner is:

[0068] First, according to the access data amount of the plurality of preset periods, a target period is determined from the plurality of preset periods;

[0069] In this embodiment, for any cache data, if the preset cycle in which the cache data was most recently accessed is the target cycle or the preset cycle before the target cycle, the cache data is the target cache data.

[0070] According to different actual scenarios, this embodiment provides two implementation methods for determining the target period:

[0071] Method 1:

[0072] According to the time sequence of the multiple preset cycles, starting from the latest preset cycle, the access data volume of each preset cycle is accumulated one by one;

[0073] If the access data statistics accumulated this time are greater than the preset data volume, the preset period corresponding to the access data volume accumulated this time is used as the target period.

[0074] For example, the number of preset periods is 10, and each preset period corresponds to a start time. The preset periods in order from early to late start time are: preset period 1 to preset period 10. The earliest preset period is preset period 1, and the latest preset period is preset period 10. Starting from preset period 10, preset period 9 and preset period 8 are accumulated one by one. If the sum of the access data volume of preset period 10, preset period 9, and preset period 8 is greater than the preset data volume, preset period 8 is used as the target period.

[0075] Method 2:

[0076] If the number of preset cycles is greater than the preset number, the earliest preset cycle is used as the target cycle.

[0077] In this embodiment, the preset number can be set according to the actual elimination strategy, that is, cached data that has not been accessed for more than a preset time needs to be eliminated. For example, the preset cycles are 1, 2, and 3. Cache data that has not been accessed for more than 3 cycles needs to be eliminated. After cycle 3 ends, preset cycle 1 is used as the target cycle.

[0078] Secondly, the cache data whose last accessed preset period is not later than the target period is used as the target cache data.

[0079] It should be noted that method one and method two can be used separately or simultaneously. For example, the data volume of the target cache data of method one and method two can be calculated separately, and the target cache data with larger or smaller data volume can be eliminated according to actual needs.

[0080] In an optional implementation, if the target data is in the cache, it means that the cache is hit when the target data is accessed, otherwise, it means that the cache is not hit when the target data is accessed. When the cache is not hit, in order to improve the performance of subsequent access to the target data, the target data needs to be stored in the cache. Regardless of whether the cache is hit or not, the amount of access data in the current preset cycle and the preset cycle with the last access to the target cache data need to be updated, and the update methods of the two are different.

[0081] For the scenario of cache miss, the processing includes:

[0082] (1) If the target data accessed in the current preset cycle does not hit the cache, the target data is stored in the cache as cache data;

[0083] (2) taking the current preset cycle as the preset cycle in which the target cache data was most recently accessed;

[0084] (3) According to the size of the target data, increase the amount of access data in the current preset cycle.

[0085] For the scenario of hitting the cache, the processing includes:

[0086] (1) If the target data accessed in the current preset cycle hits the target cache data in the cache, the preset cycle in which the target cache data was last accessed is used as the preset cycle to be updated;

[0087] (2) reducing the amount of access data to be updated in a preset period according to the size of the target cache data;

[0088] (3) According to the size of the target cache data, increase the amount of access data in the current preset cycle;

[0089] In this embodiment, the target cache data is a copy of the target data temporarily stored in the cache. Since the target cache data is accessed within the current preset cycle, the access data volume of the current preset cycle needs to be increased, and at the same time, the access data volume of the target cache data in the preset cycle when it was most recently accessed needs to be reduced accordingly.

[0090] (4) If the preset update condition is met, the current preset period is used as the preset period in which the target cache data was most recently accessed.

[0091] In this embodiment, if the target data is accessed multiple times within a preset cycle, the target cache data will be hit multiple times. In order to avoid meaninglessly updating the target cache data for the preset cycle in which it was most recently accessed each time a hit is required, this embodiment performs an update only when a preset update condition is met, ensuring that no matter how many times the target cache data is hit within the current preset cycle, only one update is performed. This embodiment provides an implementation method for determining the preset update condition as follows:

[0092] If the target data is accessed for the first time within the current preset period, it is determined that the preset update condition is met, otherwise it is determined that the preset update condition is not met.

[0093] To more intuitively illustrate the process of data elimination, please refer to Figure 4 , Figure 4 In the example diagram of the data elimination process provided for this embodiment, the number of preset cycles is 3, the array size is 3, and before cycle 1 arrives, there are no elements in the cache and no elements in the hash table.

[0094] In cycle 1, two elements are inserted into the hash table: C and DEF, whose sizes are 2, 1, and 3 respectively. At this time, the preset cycle in which each element in the hash table was most recently accessed is cycle 1, and the data volume of each element is 2, 1, and 3 respectively. The first element in the array stores the access data volume of cycle 1: 2+1+3=6.

[0095] In cycle 2, two elements are inserted into the hash table: GH and IJK, whose sizes are 2 and 3 respectively. The last preset cycle in which these two elements were accessed is cycle 2. The second element in the array stores the amount of access data in cycle 2: 2+3=5.

[0096] Cycle 3 hits element DEF, so the access data volume of the third element in the array storing cycle 3 is: 2+3=5, the preset cycle in which DEF was most recently accessed is cycle 1, and the access data volume of the first element in the array storing cycle 1 is reduced by 3: 6-3=3, and the preset cycle in which DEF was most recently accessed is updated to cycle 3.

[0097] Cycle 4 hits element GH. Since the array is full, the access data of cycle 4 is placed in the first element of the array. At the same time, the preset cycle in which GH was last accessed is cycle 2, so the access data of cycle 2 is reduced by 2: 5-2=3.

[0098] If the preset period exceeds 3 and needs to be eliminated, the method 1 and method 2 described above in this embodiment can be used in combination to implement it. That is, according to method 1, data earlier than period 2 needs to be used as target cache data. According to method 2, if the preset data volume is 7, the access data volume of period 4 is 2, the access data volume of period 3 is 3, and the access data volume of period 2 is 3, then the cumulative access data volume of period 4, period 3, and period 2 is 8, and period 2 is the target period. The cached data of period 1 and period 2 are used as target cache data, and the method with the larger data volume of target cache data in method 1 and method 2 is selected for elimination, that is, the cached data of period 1 and period 2 are eliminated. The hash table after elimination includes two elements: DEF and GH.

[0099] It should be noted that the above are only examples involving access misses, access hits and elimination. In actual scenarios, the cached data can be more and the number of preset cycles can be more. However, the processing process is similar, and those skilled in the art can adapt and modify it based on the above disclosure to meet the needs of more actual scenarios.

[0100] In order to execute the corresponding steps in the above embodiment and each possible implementation method, a method for implementing the data elimination device 100 is given below. Figure 5 , Figure 5 This is a block diagram of the data elimination device provided in this embodiment. It should be noted that the basic principles and technical effects of the data elimination device 100 provided by the present invention are the same as those of the corresponding above-mentioned embodiments, and are not mentioned in this embodiment for the sake of brief description.

[0101] The data elimination device 100 includes an acquisition module 110 , a determination module 120 and an elimination module 130 .

[0102] An acquisition module 110 is used to acquire the access data volume of each preset period in a plurality of preset periods, where the access data volume of each preset period is the data volume of cache data accessed in each preset period and not accessed after the preset period;

[0103] A determination module 120, configured to determine target cache data from a plurality of cache data according to the access data amount of a plurality of preset cycles and the preset cycle in which each cache data was most recently accessed;

[0104] The elimination module 130 is used to perform an elimination operation on the target cache data to delete the target cache data from the cache.

[0105] In an optional implementation manner, the determination module 120 is specifically configured to:

[0106] Determining a target cycle from a plurality of preset cycles according to access data volumes of the plurality of preset cycles;

[0107] The cache data whose last access time of the preset cycle is not later than the target cycle is used as the target cache data.

[0108] In an optional implementation manner, when the determination module 120 is used to determine the target cycle from a plurality of preset cycles according to the access data amounts of the plurality of preset cycles, it is specifically used to:

[0109] According to the time sequence of the multiple preset cycles, starting from the latest preset cycle, the access data volume of each preset cycle is accumulated one by one;

[0110] If the access data statistics accumulated this time are greater than the preset data volume, the preset period corresponding to the access data volume accumulated this time is used as the target period.

[0111] In an optional implementation manner, when the determination module 120 is used to determine the target cycle from a plurality of preset cycles according to the access data amounts of the plurality of preset cycles, it is specifically used to:

[0112] If the number of preset cycles is greater than the preset number, the earliest preset cycle is used as the target cycle.

[0113] In an optional implementation, the data elimination device 100 further includes an updating module 140, and the updating module 140 is used to:

[0114] If the target data accessed in the current preset cycle does not hit the cache, the target data is stored in the cache as target cache data;

[0115] The current preset cycle is used as the preset cycle in which the target cache data was last accessed;

[0116] According to the size of the target data, the amount of access data in the current preset cycle is increased.

[0117] In an optional implementation, the updating module 140 is further configured to:

[0118] If the target data accessed in the current preset period hits the target cache data in the cache, the preset period in which the target cache data was most recently accessed is used as the preset period to be updated;

[0119] According to the size of the target cache data, the amount of access data to be updated in a preset period is reduced;

[0120] According to the size of the target cache data, the amount of access data in the current preset cycle is increased;

[0121] If the preset update condition is met, the current preset period is used as the preset period in which the target cache data was most recently accessed.

[0122] In an optional implementation, the updating module 140 is further configured to:

[0123] If the target data is accessed for the first time within the current preset period, it is determined that the preset update condition is met, otherwise it is determined that the preset update condition is not met.

[0124] The embodiment of the present invention also provides a block diagram of a storage device 10. The storage device 10 implements the data elimination method of the above embodiment. Figure 6 , Figure 6 This is a block diagram of a storage device 10 provided in this embodiment. The storage device 10 includes a processor 11, a memory 12 and a bus 13. The processor 11 and the memory 12 are connected via the bus 13.

[0125] The processor 11 may be an integrated circuit chip having the ability to process signals. In the implementation process, each step of the data elimination method of the above embodiment may be completed by an integrated logic circuit of hardware in the processor 11 or by instructions in the form of software. The above processor 11 may be a general-purpose processor, including a CPU (Central Processing Unit), a NP (Network Processor), etc.; it may also be a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Logic Gate Array) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0126] The memory 12 is used to store a program for implementing the data elimination method. The program may be a software function module stored in the memory 12 in the form of software or firmware or solidified in the OS (Operating System) of the storage device 10 .

[0127] After receiving the execution instruction, the processor 11 executes the program to implement the data elimination method of the above embodiment.

[0128] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the data elimination method in the aforementioned embodiment is implemented.

[0129] In summary, the embodiments of the present invention provide a data elimination method, apparatus, storage device and computer-readable storage medium, the method comprising: obtaining the access data volume of each preset cycle in multiple preset cycles, the access data volume of each preset cycle being the data volume of cache data that has been accessed in each preset cycle and not accessed after the preset cycle; determining target cache data from multiple cache data according to the access data volume of multiple preset cycles and the preset cycle in which each cache data was most recently accessed; performing elimination operation on the target cache data to delete the target cache data from the cache. The present invention can avoid the locking overhead caused by the linked list-based LRU algorithm and improve the elimination efficiency of the cache. Compared with the prior art, this embodiment has at least the following advantages: (1) there is no need to use a linked list to organize cache data, and the target cache data that needs to be eliminated can be eliminated in time, thereby avoiding the locking overhead caused by the LRU algorithm based on the linked list and improving the cache elimination efficiency; (2) the usage information of a cache data is only updated once within a preset period, reducing the number of locks and thus reducing the lock overhead; (3) atomic variables are used to record the periodic usage information of the cache data, reducing the granularity of the lock and thus reducing the lock overhead; (4) the usage information of each element uses an integer data type, which reduces the memory usage compared to the pointer of a bidirectional linked list.

[0130] The above are only various embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A data elimination method, characterized in that: Applied to a storage device, wherein a cache of the storage device stores a plurality of cache data, the method comprises: Acquire the access data volume of each preset cycle in a plurality of preset cycles, wherein the access data volume of each preset cycle is the data volume of cache data accessed in each preset cycle and not accessed after the preset cycle; Determining a target cycle from the plurality of preset cycles according to the access data amounts of the plurality of preset cycles; Using cache data whose last accessed preset period is not later than the target period as target cache data; Performing an elimination operation on the target cache data to delete the target cache data from the cache; The step of determining a target cycle from the plurality of preset cycles according to the access data amounts of the plurality of preset cycles comprises: According to the time sequence of multiple preset cycles, starting from the latest preset cycle, the access data volume of each preset cycle is accumulated one by one; if the access data statistics accumulated at that time are greater than the preset data volume, the preset cycle corresponding to the access data volume accumulated at that time is taken as the target cycle; The method further comprises: If the target data accessed in the current preset period hits the target cache data in the cache, the preset period in which the target cache data was most recently accessed is used as the preset period to be updated; According to the size of the target cache data, reducing the amount of access data in the preset period to be updated and increasing the amount of access data in the current preset period; If the target data is accessed for the first time within the current preset period, it is determined that the preset update condition is met, and the current preset period is used as the preset period in which the target cache data was most recently accessed; otherwise, it is determined that the preset update condition is not met.

2. The data elimination method according to claim 1, characterized in that: The step of determining a target cycle from the plurality of preset cycles according to the access data amounts of the plurality of preset cycles comprises: If the number of preset cycles is greater than the preset number, the earliest preset cycle is used as the target cycle.

3. The data elimination method according to claim 1, characterized in that: The method further comprises: If the target data accessed in the current preset cycle does not hit the cache, storing the target data in the cache as target cache data; Using the current preset period as the preset period during which the target cache data was last accessed; According to the size of the target data, the access data amount of the current preset period is increased.

4. A data elimination device, characterized in that: Applied to a storage device, wherein a cache of the storage device stores a plurality of cache data, the device comprises: An acquisition module, used to acquire the access data volume of each preset cycle in a plurality of preset cycles, wherein the access data volume of each preset cycle is the data volume of cache data accessed in each preset cycle and not accessed after the preset cycle; A determination module, configured to determine a target cycle from the plurality of preset cycles according to the access data amounts of the plurality of preset cycles; Using cache data whose last accessed preset period is not later than the target period as target cache data; The determination module is specifically used to: accumulate the access data volume of each preset period one by one according to the time sequence of multiple preset periods, starting from the latest preset period; if the access data statistics accumulated at that time are greater than the preset data volume, then use the preset period corresponding to the accumulated access data volume at that time as the target period; An elimination module, configured to perform an elimination operation on the target cache data to delete the target cache data from the cache; An update module is used to, if the target data accessed within the current preset cycle hits the target cache data in the cache, use the preset cycle in which the target cache data was most recently accessed as the preset cycle to be updated; according to the size of the target cache data, reduce the amount of accessed data in the preset cycle to be updated and increase the amount of accessed data in the current preset cycle; if the target data is accessed for the first time within the current preset cycle, determine that the preset update condition is met, and use the current preset cycle as the preset cycle in which the target cache data was most recently accessed, otherwise determine that the preset update condition is not met.

5. A storage device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store a program, and the processor is used to implement the data elimination method according to any one of claims 1 to 3 when executing the program.

6. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the data elimination method as described in any one of claims 1 to 3 is implemented.

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