SPI control circuit and chip

Abstract

Embodiments of the present disclosure provide an SPI control circuit and a chip, the SPI control circuit is connected with a plurality of SPI peripherals, a communication protocol of the SPI peripherals is an SPI protocol or a variant of the SPI protocol, the SPI control circuit comprises: an instruction storage module for storing a plurality of preset instructions, each of the plurality of SPI peripherals having a corresponding relationship with one or more of the plurality of preset instructions; and the control module is used for receiving an external instruction, converting the external instruction into a first preset instruction in the plurality of preset instructions, and operating the SPI peripheral corresponding to the first preset instruction according to the first preset instruction. According to the embodiment of the invention, the SPI peripherals of SPI protocols of different variants can be compatibly controlled, and the processing speed is high.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to an SPI control circuit and chip. Background Art

[0002] Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that can communicate with multiple slave devices. SPI can be used for serial data transmission and has a wide range of applications. For example, devices such as Flash memory usually use the SPI protocol for data transmission.

[0003] SPI has many variants, such as Dual SPI / Quad SPI / Octal SPI with increased transmission bandwidth, increased clock sampling edge (Dual Data transfer Rate, DDR), etc. These SPI variants have higher transmission efficiency.

[0004] For various variants of SPI protocol peripherals from different manufacturers, control modules need to be designed separately, which consumes a lot of time and energy of designers. In addition, each time the SPI device transmits data, a large number of registers need to be manually configured in advance, which is cumbersome. In addition, the SPI transmission speed is slow and the efficiency is low. Summary of the invention

[0005] Embodiments of the present disclosure provide a SPI control circuit and a chip.

[0006] In a first aspect, an embodiment of the present disclosure provides an SPI control circuit, wherein the SPI control circuit is connected to a plurality of SPI peripherals, wherein the communication protocol of the SPI peripherals is the SPI protocol or a variant of the SPI protocol, and the SPI control circuit comprises:

[0007] An instruction storage module, used for storing a plurality of preset instructions, each of the plurality of SPI peripherals having a corresponding relationship with one or more of the plurality of preset instructions;

[0008] The control module is used to receive an external instruction, convert the external instruction into a first preset instruction among the multiple preset instructions, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

[0009] In some embodiments, the control module is further used to receive an address signal, and search in the instruction storage module according to the address signal and the external instruction to convert the external instruction into the first preset instruction corresponding to the SPI peripheral indicated by the address signal.

[0010] In some embodiments, the SPI control circuit further includes a buffer module, and the SPI control circuit has a pre-fetch function. When the pre-fetch function is turned on, the data pre-fetched from the SPI peripheral is stored in the buffer module;

[0011] The control module is also used for searching in the buffer module whether data corresponding to the read instruction exists when the external instruction is a read instruction and if the pre-fetch function is in an on state; if so, feeding back the data corresponding to the external instruction; if not, converting the read instruction into the first preset instruction, and reading required data from the corresponding SPI peripheral according to the first preset instruction.

[0012] In some embodiments, the control module is further used to read both the required data and the pre-fetched data when reading required data from the SPI peripheral when the pre-fetch function is turned on, and store the pre-fetched data in the buffer module.

[0013] In some embodiments, the control module includes a first control module and a second control module;

[0014] The first control module is used to receive the external instruction, and when the external instruction is the read instruction, determine whether the pre-fetch function is in an on state, and if the pre-fetch function is in an on state, search in the buffer module whether there is data corresponding to the read instruction, and if so, feed back the data corresponding to the external instruction;

[0015] The first control module is further configured to send the external instruction to the second control module, or convert the external instruction into the first preset instruction and then send it to the second control module if the data corresponding to the read instruction does not exist in the buffer module or the external instruction is not the read instruction;

[0016] The second control module is used to receive the external instruction, convert the external instruction into the first preset instruction, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction; or receive the first preset instruction and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

[0017] In some embodiments, the second control module includes an arbitration control submodule, a sequence control submodule, and an input-output control submodule;

[0018] The arbitration control submodule is used to receive the external instruction or the first preset instruction sent by the first control module, perform arbitration according to the received instruction and the current task situation, and when the arbitration result satisfies the transmission of the current instruction, send the first preset instruction to the sequence control submodule, or convert the external instruction into the first preset instruction and then send it to the sequence control submodule;

[0019] The sequence control submodule is used to convert the preset instruction into an SPI instruction and then send it to the input / output control submodule;

[0020] The input / output control submodule is used to distribute the SPI instruction to the corresponding SPI peripheral.

[0021] In some embodiments, the second control module further comprises a cross-clock domain module, and the cross-clock domain module is connected between the arbitration control submodule and the sequence control submodule;

[0022] The cross-clock domain module is used to receive the first preset instruction sent by the arbitration control submodule, perform timing conversion on the first preset instruction, and then send it to the sequence control submodule; or, the cross-clock domain module is used to receive the external instruction sent by the arbitration control submodule, convert the external instruction into the first preset instruction, and then send it to the sequence control submodule.

[0023] In some embodiments, the SPI control circuit further includes a first first-in first-out module and a second first-in first-out module; the first first-in first-out module and the second first-in first-out module are both connected between the arbitration control submodule and the sequence control submodule;

[0024] The first first-in first-out module is used to temporarily store data read from the SPI peripheral;

[0025] The second first-in first-out module is used to temporarily store data written into the SPI peripheral.

[0026] In some embodiments, the buffer module includes a first buffer module and a second buffer module; the first buffer module and the second buffer module are both connected between the first control module and the second control module;

[0027] The first buffer module is used to temporarily store data written into the SPI peripheral;

[0028] The second buffer module is used to temporarily store data read from the SPI peripheral;

[0029] One or both of the first buffer module and the second buffer module are further used to store the pre-fetched data.

[0030] In some embodiments, the control module receives and responds to the external instruction via an AHB bus.

[0031] In some embodiments, the SPI control circuit includes at least one SPI bus interface, and each of the SPI bus interfaces is connected to at least one of the SPI peripherals;

[0032] The access mode of the SPI control circuit includes an independent access mode and a parallel access mode. In the independent access mode, each of the SPI peripherals is accessed individually through the connected SPI bus interface; in the parallel access mode, multiple SPI peripherals connected to different SPI bus interfaces are accessed in parallel, and multiple SPI peripherals connected to the same SPI bus interface are accessed individually, and one SPI peripheral is connected to the SPI control circuit through one SPI bus interface.

[0033] In some embodiments, the SPI control circuit includes multiple SPI bus interfaces, each of the SPI bus interfaces is connected to at least one of the SPI peripherals, and one of the SPI peripherals is connected to the SPI control circuit through multiple SPI bus interfaces; the access mode of the SPI control circuit also includes a combined access mode, in which the data received by the SPI peripheral is obtained by splicing partial data of the multiple SPI bus interfaces connected.

[0034] In some embodiments, the instruction storage module includes at least one display lookup table, each of which is used to store at least one of the preset instructions; the preset instructions are composed of: an instruction code, a number of data lines, and an operand; the instruction code indicates the operation corresponding to the preset instruction, the number of data lines indicates the number of bits transmitted, and the operand indicates the data rate of the transmission.

[0035] In a second aspect, an embodiment of the present disclosure provides a chip, comprising the SPI control circuit as described in any one of the first aspect.

[0036] The disclosed embodiment provides an SPI control circuit and chip, which pre-stores operation instructions corresponding to SPI peripherals of different SPI communication protocols from different manufacturers as preset instructions in an instruction storage module. When an external instruction for a certain SPI peripheral is received, the corresponding first preset instruction is directly searched in the instruction storage module, and then the first preset instruction is used to perform the corresponding operation on the SPI peripheral, thereby realizing compatible operation of SPI peripherals of different SPI communication protocols from different manufacturers using the same SPI control circuit, and having high adaptability. In addition, the preset instruction is directly searched and called from the instruction storage module, and there is no need to initiate transmission by complex configuration of registers, and the method is simple, fast and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the composition structure of an SPI control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0038] Figure 2 A schematic diagram of a connection between an SPI control circuit and an SPI peripheral provided in an embodiment of the present disclosure Figure 1 ;

[0039] Figure 3 A schematic diagram of a connection between an SPI control circuit and an SPI peripheral provided in an embodiment of the present disclosure Figure 2 ;

[0040] Figure 4 A schematic diagram of the composition structure of a LUT provided in an embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of the composition structure of an SPI control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0042] Figure 6 A schematic diagram of the composition structure of an SPI control circuit provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0047] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0048] Serial Peripheral Interface (SPI);

[0049] Flash memory;

[0050] Dual SPI;

[0051] Quad SPI (Quad SPI);

[0052] Octal SPI;

[0053] Controller (CTL);

[0054] Non-volatile Flash (NOR Flash);

[0055] NAND Flash;

[0056] Random Access Memory (RAM);

[0057] Central Processing Unit (CPU);

[0058] Field Programmable Gate Array (FPGA);

[0059] Hyper Flash;

[0060] Hyper RAM;

[0061] Bus;

[0062] Display Look-Up-Table (LUT);

[0063] Sequence(Sequence,Seq);

[0064] Single Data transfer Rate (SDR)

[0065] Dual Data transfer Rate (DDR);

[0066] Advanced High Performance Bus (AHB);

[0067] Advanced Microcontroller Bus Architecture (AMBA);

[0068] Intellectual Property core (IP / IPS);

[0069] First Input First Output (FIFO);

[0070] Input Output (IO);

[0071] Execute In Place (XIP);

[0072] Microcontroller Unit (MCU);

[0073] System on Chip (SoC).

[0074] For various variants of SPI protocol peripherals from different manufacturers, control modules need to be designed separately, which consumes a lot of time and energy of designers. In addition, each time the SPI device (i.e., SPI peripheral) transmits data, a large number of registers need to be manually configured in advance, which is cumbersome. In addition, the SPI transmission speed is slow and the efficiency is low.

[0075] Based on this, the embodiment of the present disclosure provides an SPI control circuit, which pre-stores the operation instructions corresponding to SPI peripherals of different SPI communication protocols from different manufacturers as preset instructions in an instruction storage module. When an external instruction for a certain SPI peripheral is received, the corresponding first preset instruction is directly searched in the instruction storage module, and then the first preset instruction is used to perform the corresponding operation on the SPI peripheral, thereby realizing the use of the same SPI control circuit to operate SPI peripherals of different SPI communication protocols from different manufacturers, and the adaptability is high. In addition, the preset instruction is directly searched and called from the instruction storage module, and there is no need to initiate transmission by complex configuration of registers. The method is simple, fast and efficient.

[0076] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0077] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the composition structure of an SPI control circuit 20 provided in an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the SPI control circuit 20 may include:

[0078] An instruction storage module 10, used for storing a plurality of preset instructions, each SPI peripheral in the plurality of SPI peripherals having a corresponding relationship with one or more of the plurality of preset instructions;

[0079] The control module 21 is used to receive an external instruction, convert the external instruction into a first preset instruction among multiple preset instructions, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

[0080] It should be noted that if Figure 1 As shown, the control module 21 in the SPI control circuit 20 is connected to multiple SPI peripherals, and is used to perform operations such as read / write / reset on the SPI peripherals according to instructions. The communication protocol of the SPI peripheral is the SPI protocol or a variant of the SPI protocol, and the communication protocols of multiple SPI peripherals are the same or different. For example, the variants of the SPI protocol may include: three-wire SPI, dual-channel SPI, four-channel SPI, eight-channel SPI, SDR mode, DDR mode, etc. For multiple SPI peripherals, it can be: the communication protocol of some of them is the SPI protocol, the communication protocol of some of them is the four-channel SPI, the communication protocol of another part is the DDR mode, etc.

[0081] It should also be noted that, in the embodiment of the present disclosure, the instruction storage module 10 may be an independent storage area not included in the SPI control circuit 20, or Figure 1As shown, the instruction storage module 10 may also be integrated in the SPI control circuit 20, which is not specifically limited; the SPI control circuit 20 may also be referred to as a SPI controller (Controller) or a SPI device controller.

[0082] The instruction storage module 10 pre-stores preset instructions for various operations corresponding to each SPI peripheral. When receiving an external instruction for a certain SPI peripheral from an external module (for example, a CPU serving as a control system, the CPU is taken as an example hereinafter), the control module 21 searches the instruction storage module 10 to obtain a preset instruction corresponding to the external instruction of the SPI peripheral (for ease of description, referred to as the first preset instruction), and then uses the first preset instruction to operate the SPI.

[0083] For SPI peripherals with different communication protocols and produced by different manufacturers, the relevant technology needs to design a control module separately to ensure the correct control of each SPI peripheral, which results in designers spending a lot of time and energy and increasing costs. Moreover, after receiving the instruction, the registers need to be complexly configured before the transmission can be initiated, which is inefficient.

[0084] In the embodiment of the present disclosure, the instruction storage module 10 is set to store preset instructions corresponding to multiple SPI peripherals. Taking the read instruction as an example, for each SPI peripheral, the preset instruction that meets the operation requirements of the SPI peripheral is pre-stored in the instruction storage module 10. In this way, when a read instruction for a certain SPI peripheral comes, the control module 21 searches in the instruction storage module 10 according to the received read instruction, finds the first preset instruction for performing a read operation on the SPI peripheral, and then uses the first preset instruction to read the SPI peripheral. Regardless of which manufacturer and which SPI communication protocol the SPI peripheral is, when receiving an external instruction to perform a certain operation on the SPI peripheral, the embodiment of the present disclosure only needs to search in the instruction storage module 10, and the relevant operation of the SPI peripheral can be quickly initiated according to the pre-set preset instruction, which can not only realize the use of the same SPI control circuit 20 to control SPI peripherals of different protocols and manufacturers, but also has high versatility and high speed, thereby improving processing efficiency.

[0085] The disclosed embodiment also provides a variety of connection methods between the SPI control circuit 20 and the SPI peripherals.

[0086] In one implementation, the SPI control circuit 20 includes at least one SPI bus interface, each SPI bus interface is connected to at least one SPI peripheral, and one SPI peripheral is connected to the SPI control circuit 20 via one SPI bus interface;

[0087] The access mode of the SPI control circuit 20 includes an independent access mode and a parallel access mode. In the independent access mode, each SPI peripheral is accessed individually through the connected SPI bus interface; in the parallel access mode, multiple SPI peripherals connected to different SPI bus interfaces are accessed in parallel, and multiple SPI peripherals connected to the same SPI bus interface are accessed individually.

[0088] It should be noted that, in this implementation, the control module 21 in the SPI control circuit 20 is connected to the SPI peripheral through the SPI bus interface. The SPI control circuit 20 may have one or more SPI channels, each SPI channel may be connected to one or more SPI peripherals, and the supported SPI peripherals include but are not limited to various devices such as serial NOR flash, serial NAND flash, FPGA, Hyper Flash, Hyper RAM, and one SPI peripheral is connected to the SPI control circuit 20 only through one SPI channel.

[0089] For example, the SPI control circuit 20 has two SPI channels, and each channel can be connected to two SPI peripherals. Figure 2 As shown, the two SPI channels are SPI bus port A (SPI Bus port A, referred to as port A) and SPI bus port B (SPI Busport B, referred to as port B), the two SPI peripherals connected to port A are device A1 (device A1) and device A2 (device A2), and the two SPI peripherals connected to port B are device B1 (device B1) and device B2 (device B2).

[0090] Among them, PCS_A1 / PCS_A2 / PCS_B1 / PCS_B2 are the chip select signals of device A1 / device A2 / device B1 / device B2 respectively; SCK_A is the clock signal of device A1 and device A2, SCK_B is the clock signal of device B1 and device B2; SIO_A[7:0] is the data signal of device A1 and device A2, SIO_B[7:0] is the data signal of device B1 and device B2. It can be understood that only when the chip select signal is enabled, the corresponding SPI peripheral can normally receive the data signal. Here, the data signal is 8 bits (0th to 7th bit: [7:0]) as an example.

[0091] The SPI control circuit 20 has two access modes: independent access mode (or single access mode) and parallel access mode. In independent access mode, data reception / transmission between the SPI control circuit 20 and the device is performed on port A / B respectively; in independent access mode, device A1, device A2, device B1 and device B2 cannot be accessed at the same time, but these four devices can be accessed individually. In parallel access mode, port A and port B can receive / transmit data at the same time, and the SPI control circuit 20 can automatically merge / split the received / transmitted data; in parallel access mode, device A1 and device A2 cannot be accessed at the same time, and device B1 and device B2 cannot be accessed at the same time.

[0092] In another implementation, the SPI control circuit 20 includes a plurality of SPI bus interfaces, each SPI bus interface is connected to at least one SPI peripheral, and an SPI peripheral is connected to the SPI control circuit 20 via a plurality of SPI bus interfaces;

[0093] The access mode of the SPI control circuit 20 also includes a combined access mode. In the combined access mode, the data received by the SPI peripheral is obtained by splicing partial data of multiple connected SPI bus interfaces.

[0094] It should be noted that, in this implementation, the control module 21 in the SPI control circuit 20 is also connected to the SPI peripheral through the SPI bus interface. The SPI control circuit 20 has multiple SPI channels, each SPI channel can be connected to one or more SPI peripherals, and one SPI peripheral can be connected to the SPI control circuit 20 through multiple SPI channels.

[0095] Still taking the data signal as 8 bits as an example, the SPI control circuit 20 also provides a combination mode of 8-bit transmission. The specific peripheral connection can be as follows: Figure 3 As shown. Figure 2 Different, in Figure 3In the figure, device 1 is connected to both port A and port B, wherein the lower four bits SIO[3:0] of the data port of device 1 are connected to the lower four bits SIO_A[4:0] of the data signal channel of port A, and the upper four bits SIO[7:4] of the data port of device 1 are connected to the lower four bits SIO_B[4:0] of the data signal channel of port B. The same is true for device 2, that is, the lower four bits (SIO_A[3:0] and SIO_B[3:0]) of the data signals of port A and port B are selected and spliced ​​into 8 bits for connection. Device 1 and device 2 are both connected to port A and port B at the same time, thereby realizing parallel access to the connected devices using the data channels of multiple SPI bus interfaces. At the same time, the upper four bits (SIO_A[7:4] and SIO_B[7:4]) of port A and port B can be spliced ​​as the data signals of device 3 and device 4 (not shown in the figure) to realize combined transmission control.

[0096] Here, only the chip select signal PCS_1 of device 1 is shown, PCS represents the chip select signal port of the device, SCK represents the clock port of the device, SIO[i] represents the i-th data port of the device, and other data ports such as the chip select signal port and the clock port can also be connected to the same or different SPI bus interfaces. It can be understood that the use of high / low 4-bit data as splicing here is only an example. In actual applications, data from different SPI bus interfaces can be spliced ​​in any feasible way to achieve multiplexing of SPI bus interface access devices. The above two connection methods can also be used in combination, and there is no specific limitation on this.

[0097] In some embodiments, the control module 21 is further used to receive an address signal, and search in the instruction storage module 10 according to the address signal and the external instruction to convert the external instruction into a first preset instruction corresponding to the SPI peripheral indicated by the address signal.

[0098] It should be noted that the external instruction indicates a specific operation to be performed on the SPI peripheral, such as read, write, reset, etc., and the address signal indicates which SPI the operation is for, and may also include a more specific storage address inside the SPI to implement operations such as configuration of the SPI peripheral, reading data from a specific area of ​​the SPI, etc. Therefore, the control module 21 specifically searches (or decodes) the instruction storage module 10 according to the address signal and the external instruction to obtain the first preset instruction corresponding to the SPI peripheral indicated by the address signal, so as to ensure that the determined first preset instruction is the preset instruction corresponding to the SPI peripheral that needs to be operated.

[0099] In some embodiments, the instruction storage module 10 includes at least one LUT, each LUT is used to store at least one preset instruction; the composition of the preset instruction includes: an instruction code, a number of data lines, and an operand; the instruction code indicates the operation corresponding to the preset instruction, the number of data lines indicates the number of bits transmitted, and the operand indicates the data rate of the transmission.

[0100] It should also be noted that in the embodiment of the present disclosure, the instruction storage module 10 (or instruction memory) can be implemented by one or more LUTs. Among them, LUT can be essentially considered as a RAM. After the data is written into the RAM in advance, each time a signal is input, it is equivalent to inputting an address to look up the table, find out the content corresponding to the address, and then output it.

[0101] The exemplary structure of the LUT in the embodiment of the present disclosure can be referred to Figure 4 As shown, the LUT can be pre-programmed, and the storage word length can be 32 bits. Assuming that there are 64 LUTs in total, one LUT is divided into N sequences (Sequence), for example, 16 sequences, and each sequence can store eight preset instructions (Inst1~Inst8). The length of a preset instruction can be 16 bits, where [15:10] bits are instruction codes (opcodes). For specific instruction codes and examples of their meanings, please refer to Table 1, but are not limited to Table 1. [9:8] bits are called the number of data lines (num_pads), which are used to select the transmission mode of SPI data as 1 / 2 / 4 / 8 bits or more bits, corresponding to the num_pads values ​​of 2'b00 / 2'b01 / 2'b10 / 2'b11 respectively. [7:0] bits are 8-bit operands (oprand), which include information such as whether the transmission mode is SDR mode or DDR mode, the number of transmitted bytes, and the number of dummy instruction cycles. The LUT can be pre-programmed according to different SPI peripherals and the required transmission. During the transmission process, it will directly start executing according to the instruction sequence in the LUT, avoiding the need to transmit instructions before each data transmission, thereby improving efficiency.

[0102] That is to say, in the embodiment of the present disclosure, the SPI control circuit 20 defines a set of internal instructions (preset instructions) for controlling the transmission of data. For example, the instruction code can refer to Table 1:

[0103] Table 1

[0104]

[0105]

[0106] For further information, see Figure 5 , which shows a schematic diagram of the composition structure of the SPI control circuit 20 provided in an embodiment of the present disclosure Figure 2 .like Figure 5 As shown, in some embodiments, the SPI control circuit 20 further includes a buffer module 22, and the SPI control circuit 20 has a pre-fetch function. When the pre-fetch function is turned on, the data pre-fetched from the SPI peripheral is stored in the buffer module 22;

[0107] The control module 21 is also used for searching whether there is data corresponding to the read instruction in the buffer module 22 when the external instruction is a read instruction and the prefetch function is in the on state. If so, the data corresponding to the external instruction is fed back. If not, the read instruction is converted into a first preset instruction and the required data is read from the corresponding SPI peripheral according to the first preset instruction.

[0108] The control module 20 is also used to read both the required data and the pre-fetched data when reading required data from the SPI peripheral when the pre-fetch function is turned on, and store the pre-fetched data in the buffer module 22.

[0109] It should be noted that the SPI control circuit 20 provided in the embodiment of the present disclosure supports two transmission modes, AHB and IPS. In the AHB transmission mode, the control module 21 receives and responds to external instructions through the AHB bus (AHB Bus), that is, the control module 21 is connected to the CPU that sends the external instructions through the AHB bus. The IPS mode initiates transmission by configuring the internal registers of the SPI controller in the traditional way. This method is slower than the AHB transmission speed, and the operation is also more complicated and inefficient.

[0110] AHB is a new generation of AMBA bus that was created to meet the requirements of high-performance, synthesizable design. It is a high-performance bus that supports multiple bus hosts and provides high-bandwidth operations. It is often used to connect various modules with AHB interfaces, such as CPU, on-chip RAM, and external memory. It has the characteristics of burst transmission and support for multiple master devices.

[0111] For the AHB transmission mode, the SPI control circuit 20 supports but is not limited to the 32 / 64-bit AHB bus protocol, communicates with the CPU through the AHB bus, and implements the isolation of the AHB interface and the internal circuit of the SPI control circuit 20. In the AHB transmission mode, the SPI control circuit 20 can be regarded as an ordinary AHB slave. The user of the IP does not need to pay attention to the internal behavior of the hardware. It only needs to pre-configure the buffer module 22 and initiate a transmission request according to the specification of the AHB protocol. The hardware will translate the AHB transmission request into a series of preset preset instructions and automatically implement the sending / receiving of data, which greatly simplifies the operation process and improves the access speed.

[0112] It should also be noted that the read operation in the AHB mode is cacheable. The buffer module 22 in the disclosed embodiment has a function similar to a cache. When reading data of an address in the AHB mode, the SPI control circuit 20 will first check whether the data is already cached in the buffer module 22. If so, the SPI control circuit 20 will not be operated through a series of instructions to access the peripherals, but the data to be read will be directly returned from the buffer module 22. In this way, since the SPI transmission process is omitted, in the case of a read hit, it is equivalent to directly accessing the peripherals through the AHB bus, which can greatly reduce the access time. The read operation in AHB mode also supports read prefetch, which is similar to cache prefetch. According to information such as AHB burst size and burst type, the SPI control circuit 20 can read data in advance from the starting address of the burst transfer / a beat of data and store it in the buffer module 22. In this way, for subsequent reads, the required data can be directly obtained from the buffer module 22 without the need for SPI transmission again, which greatly reduces the access time and improves the access efficiency.

[0113] It should also be noted that one way for the buffer module 22 to perform pre-fetching may be: when the pre-fetching function is turned on, when the control module 21 reads the required data corresponding to the current instruction from the SPI peripheral, it not only reads the required data, but also reads some more data as pre-fetched data and stores them in the buffer module 22. The more read data may be data in the next one or more addresses of the address currently read, or data in other adjacent addresses, or data in addresses that meet other conditions, for example, data that has been read the most times in history, data that is predicted to be read, etc., and there is no specific limitation on this.

[0114] like Figure 5 As shown, in some embodiments, the control module 21 includes a first control module 211 and a second control module 212;

[0115] The first control module 211 is used to receive an external instruction. When the external instruction is a read instruction, it determines whether the pre-fetch function is in an on state. If the pre-fetch function is in an on state, it searches the buffer module 22 for data corresponding to the read instruction. If so, it feeds back the data corresponding to the external instruction.

[0116] The first control module 211 is further configured to send the external instruction to the second control module 212, or convert the external instruction into a first preset instruction and then send it to the second control module 212 if there is no data corresponding to the read instruction in the buffer module 22 or the external instruction is not a read instruction;

[0117] The second control module 212 is used to receive an external instruction, convert the external instruction into a first preset instruction, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction; or receive the first preset instruction and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

[0118] It should be noted that, in the embodiment of the present disclosure, the first control module 211 is connected to the CPU via the AHB bus, and the second control module 212 is connected to the SPI peripheral via the SPI bus interface. When the first control module 211 receives an external instruction, it first determines the type of the external instruction. If the external instruction is a read instruction, the first control module 211 also determines whether the pre-fetch function of the buffer module 22 is turned on. The specific judgment method can be: there is a special status indicator bit in a register inside the SPI control circuit 20, and the first control module 211 can obtain the level state of the status indicator bit. If the status indicator bit is a preset level state, it is considered that the pre-fetch function is turned on, otherwise, it is considered that the pre-fetch function is not turned on; for example, the register is located in the buffer module 22, if the status indicator bit is "1" (high level), it is considered that the pre-fetch function is turned on, if the status indicator bit is "0" (low level), it is considered that the pre-fetch function is not turned on, but it is not limited to this judgment method.

[0119] After determining that the pre-fetch function is turned on, the first control module 211 searches in the buffer module 22 to determine whether the required data exists. If the required data is found, the data is directly fed back to the CPU, thereby eliminating the need to read the data in the SPI peripheral through a series of transmission processes, which greatly saves transmission time. Among them, some identification information can be used to indicate the source address of the pre-fetched data, so that the first control module 211 can determine whether the data is the required data by comparing the address.

[0120] If the required data is not found in the buffer module 22, it means that the required data has not been pre-fetched. At this time, the external instruction (it can be understood that each operation process often also requires an address signal, a chip select signal, the transmitted data, etc. The embodiment of the present disclosure is only briefly described in conjunction with the instruction and will not be specifically described later) is sent to the second control module 212, and the second control module 212 performs addressing and reads data from the corresponding SPI peripheral and provides feedback.

[0121] If the external instruction is not a read instruction, there is no need to search in the buffer module 22, and the steps of determining whether the pre-fetch function is enabled are skipped, and the external instruction is directly sent to the second control module 212, and the second control module 212 performs the corresponding operation.

[0122] Alternatively, the first control module 211 may first convert the external instruction into a first preset instruction and then send the first instruction to the second control module 212, and the second control module 212 operates the corresponding SPI peripheral according to the first preset instruction.

[0123] See also Figure 6 , which shows a schematic diagram of the composition structure of an SPI control circuit 20 provided in an embodiment of the present disclosure Figure 3 .like Figure 6 As shown, in some embodiments, the second control module 212 ( Figure 6 The reference numeral 212 is not shown) includes an arbitration control submodule 2121 (denoted as ARB_CTL), a sequence control submodule 2122 (denoted as SEQ_CTL) and an input / output control submodule 2123 (denoted as IO_CTL);

[0124] The arbitration control submodule 2121 is used to receive the external instruction or the first preset instruction sent by the first control module 211, perform arbitration according to the received instruction and the current task situation, and send the first preset instruction to the sequence control submodule 2122 when the arbitration result satisfies the transmission of the current instruction, or convert the external instruction into the first preset instruction and then send it to the sequence control submodule 2122;

[0125] The sequence control submodule 2122 is used to convert the first preset instruction into an SPI instruction and then send it to the input / output control submodule 2123;

[0126] The input / output control submodule 2123 is used to distribute SPI instructions to corresponding SPI peripherals.

[0127] It should be noted that Figure 6 The instruction storage module 10 is not shown. Figure 6 As shown, the arbitration control submodule 2121 is also called an arbitration controller or an arbitrator, which is used to coordinate cache, manage bus access and implement resource arbitration to ensure orderly data transmission. In the embodiment of the present disclosure, the arbitration control submodule 2121 is used to arbitrate requests from AHB and IPS. When there is an ongoing transmission, some bits of the internal related registers can display the type of transmission, and some bits can display whether the arbitrator is idle and whether it can respond to new transmission requests.

[0128] Exemplarily, there are four sources of Flash access instructions: 1. AHB write instruction, triggered by AHB write access; 2. AHB read instruction, triggered by AHB read access; 3. IP instruction, triggered by write IP instruction; 4. Suspend instruction (suspend AHB read prefetch sequence); It should be noted that AHB bus access will not trigger write instruction and read instruction at the same time; AHB read prefetch sequence is an AHB instruction sequence triggered by AHB read access when AHB prefetch function is turned on. After obtaining all read data of the current AHB read burst, the SPI controller will prefetch more data to reduce the read latency of the next AHB read access. The read AHB instruction will not be terminated when obtaining read data for the current AHB read burst. However, when there is a new IP instruction or AHB instruction request, the AHB read instruction that is pre-reading data will be terminated.

[0129] Exemplarily, the priorities granted by these four instruction sources are as follows: AHB read / write>IP instruction>suspend instruction. Therefore, when the arbitration control submodule 2121 receives an instruction sent by the first control module 211, the arbitration control submodule 2121 will perform arbitration. If there is no task in progress, the received instruction will be processed. If there is a task in progress, a priority judgment will be performed. If the priority of the received instruction is lower than the instruction corresponding to the task being executed, the received instruction will be processed after the task being executed is completed. If the priority of the received instruction is higher than the instruction corresponding to the task being executed, the task being executed will be interrupted, and the task corresponding to the received instruction will be executed first. After the task corresponding to the received instruction is executed, the interrupted task can be resumed.

[0130] Here, if the arbitration control submodule 2121 receives the first preset instruction, the first preset instruction is sent to the sequence control submodule 2122; if the arbitration control submodule 2121 receives an external instruction, it can be converted into the first preset instruction first, and then sent to the sequence control submodule 2122. After the sequence control submodule 2122 converts the first preset instruction into an SPI instruction that meets the bit number requirement (for example, 8 bits), it is sent to the input-output control submodule 2123, which distributes it to the corresponding SPI peripheral through the SPI communication interface, thereby realizing the corresponding operation.

[0131] Specifically, the sequence control submodule 2122 issues a corresponding SPI request according to the first preset instruction, and finally sends it to the SPI peripheral through the port A / B connected to the input / output control submodule 2123. The input / output control submodule 2123 is responsible for allocating specific transmissions to the two ports A and B.

[0132] Taking the command instruction (CMD_SDR / CMD_DDR) as an example, after being processed by the sequence control submodule 2122, the instruction code will be sent to the external Flash device through the input and output control submodule 2123. The instruction code is an 8-bit operand in the instruction, and the instruction code can be sent to port B and port A in parallel.

[0133] It should also be noted that different signals may operate at different clock frequencies. In this case, cross-clock domain conversion is often required. Figure 6 As shown, the second control module further includes a clock domain cross module 2124 (Clock Domain Cross), and the clock domain cross module 2124 is connected between the arbitration control submodule 2121 and the sequence control submodule 2122;

[0134] The cross-clock domain module 2124 is used to receive the first preset instruction sent by the arbitration control submodule 2121, and after performing timing conversion on the first preset instruction, send it to the sequence control submodule 2122; or, the cross-clock domain module 2124 is used to receive the external instruction sent by the arbitration control submodule 2121, and after converting the external instruction into the first preset instruction, send it to the sequence control submodule 2122.

[0135] It should be noted that if Figure 6 As shown, the instruction issued by the first control module 211 is recorded as AHB_CMD, the instruction issued by the arbitration control submodule 2121 is recorded as ARB_CMD, and the instruction issued by the cross-clock domain module 2124 is recorded as SEQ_CMD. The cross-clock domain module 2124 is a module for performing cross-clock domain processing on the signal to solve the metastable problem generated by the cross-clock domain on the hardware circuit. At the same time, it can also be decoded according to the content of ARB_CMD to generate SEQ_CMD.

[0136] like Figure 6 As shown, in some embodiments, the SPI control circuit 20 further includes a first first-in first-out module 231 (recorded as RX_FIFO ASYNC) and a second first-in first-out module 232 (recorded as TX_FIFO ASYNC); the first first-in first-out module 231 and the second first-in first-out module 232 are both connected between the arbitration control submodule 2121 and the sequence control submodule 2122;

[0137] A first FIFO module 231 is used to temporarily store data read from the SPI peripheral device;

[0138] The second FIFO module 232 is used to temporarily store the data written into the SPI peripheral.

[0139] Buffer module 22( Figure 6The reference numeral 22 is not shown) includes a first buffer module 221 (denoted as AHB_RX_BUF) and a second buffer module 222 (denoted as AHB_TX_BUF); the first buffer module 221 and the second buffer module 222 are both connected between the first control module 211 and the second control module 212;

[0140] A first buffer module 221, used for temporarily storing data written into the SPI peripheral;

[0141] A second buffer module 222, used for temporarily storing data read from the SPI peripheral;

[0142] One or both of the first buffer module 221 and the second buffer module 222 are further used to store pre-fetched data.

[0143] It should be noted that if Figure 6 As shown, both the first FIFO 231 and the second FIFO 232 can be asynchronous (ASYNC) FIFOs, and serve as the FIFO buffer areas for transmission (TX) and reception (RX), respectively. When writing data to the SPI peripheral in response to an AHB request, the data is temporarily stored in the second FIFO 232 during the transmission process, and is sequentially written into the corresponding SPI peripheral in the order of execution; when reading data from the SPI peripheral in response to an AHB request, the data read from the SPI peripheral is first temporarily stored in the first FIFO 231, and is sequentially fed back to the AHB bus in the order of execution and then transmitted to the external module.

[0144] The first buffer module 221 and the second buffer module 222 have a pre-fetching function, which can not only buffer data during data transmission, but also store the pre-fetched data.

[0145] Combination Figure 6 The SPI control circuit 20 shown, taking writing data as an example, before transmission, the LUT is configured according to the function and purpose of the peripheral. The configuration of the LUT is the same as the configuration method of all control status registers, and can be directly written. The LUT is configured with the instruction sequence for controlling the SPI peripheral. For different peripherals, there will be different control sequences. For example, Flash produced by different manufacturers will have different read / write instructions, so a configurable LUT is needed to support a variety of different peripherals.

[0146] When the AHB bus initiates a read request, if the prefetch function is turned on, it will first search for data from AHB_TX_BUF (assuming that the prefetched data is stored in AHB_TX_BUF). If the data to be read is found in AHB_TX_BUF, the subsequent process will not be performed, and the data will be returned directly from AHB_TX_BUF. If the data is not found, or the prefetch function is turned off, an arbitration exclusive transmission channel will be requested from the ARB_CTL module. After arbitration, the AHB_CMD will be processed across clock domains through the cross-clock domain module 2124, and decoded into SEQ_CMD in the LUT, and then sent to the SEQ_CTL module. The SEQ_CTL module will convert the received SEQ_CMD into an 8-bit SPI instruction and send it to the IO_CTL module. After receiving the instruction, the IO_CTL module will assign it to port A / B according to the connection settings. After the SPI peripheral returns the data, it will be processed in the SEQ_CTL module. If the read instruction is 32 bits, the 4 returned 8-bit SPI data need to be spliced ​​and sent to RX_FIFOASYNC, and finally sent to AHB_RX_BUF. The AHB bus receives the read data from AHB_RX_BUF and completes the transmission. The process of writing data is similar to the reading process, but does not include the pre-fetch function, and there is no process of waiting for external data to return.

[0147] Furthermore, the SPI control circuit 10 in the embodiment of the present disclosure also supports traditional IPS transmission, such as Figure 6 The SPI control circuit 10 further includes an IP controller 24 (denoted as IP_CTL), an IP first-in first-out module 251 (denoted as IP_RX_FIFO) and an IP buffer module 252 (denoted as IP_TX_BUF). The IP controller 24 is connected to the CPU via an IPS bus (IPS Bus), and the instructions issued are denoted as IP_CMD. The IP first-in first-out module 251 is used to temporarily store the data read from the SPI peripheral when reading data from the SPI peripheral based on an IPS request; the IP buffer module 252 is used to temporarily store the data written to the SPI peripheral when writing data to the SPI peripheral based on an IPS request. The IP first-in first-out module 251 may also include a corresponding controller (denoted as IP_RXF_CTL), and the IP buffer module 252 may also include a corresponding controller (denoted as IP_TXF_CTL). Similarly, the first first-in first-out module 231, the second first-in first-out module 232, the first buffer module 221 and the second buffer module 222 may also include a controller, but it is not shown in the figure.

[0148] In summary, the disclosed embodiment provides a device controller (i.e., SPI control circuit) based on the SPI protocol, supports various SPI variants, can be adapted to peripherals of the SPI protocol produced by different manufacturers, and has high versatility. The SPI control circuit can communicate with the CPU via the AHB bus, which greatly improves the transmission speed compared to the traditional SPI transmission, reduces the register configuration work required before the transmission, and simplifies the use of the device. In order to avoid manually sending instructions to control the transmission every time, an instruction memory is designed inside the SPI control circuit, which can be specifically a LUT. For the reading of peripheral data, the SPI control circuit also supports a faster XIP enhanced mode. In the XIP enhanced mode, the buffer module (e.g., AHB_RX_BUF) is transparent to the software, and the user does not need to manually modify the instruction sequence of the LUT to skip the CMD transmission. These tasks are all completed by the hardware. This design can save a lot of time and has higher transmission efficiency.

[0149] It can be seen that, on the one hand, the SPI control circuit supports devices based on various SPI variants from different manufacturers, supports various devices such as serial NOR flash, serial NAND flash, FPGA, Hyper Flash, Hyper RAM, etc., controls data transmission through a custom instruction set, and can pre-set instruction sequences for subsequent transmissions through the internal instruction memory (LUT), reducing operation complexity and improving transmission efficiency; on the other hand, it supports 32 / 64-bit AHB bus protocol, can communicate with the CPU through the AHB interface, implement software behavior through hardware, speed up access speed, simplify software personnel's operations, and support XIP enhanced mode; on the other hand, the configurable AHB send / receive buffer (AHB_TX_BUF / AHB_RX_BUF) supports pre-fetched read operations, and read data can be pre-fetched, further improving transmission efficiency.

[0150] In another embodiment of the present disclosure, a chip is provided. The chip includes the SPI control circuit 20 in any one of the aforementioned embodiments.

[0151] The chip can be MCU, SoC, etc., and there is no specific limitation on this.

[0152] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0153] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0154] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0155] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0156] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0157] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0158] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An SPI control circuit, characterized in that: The SPI control circuit is connected to a plurality of SPI peripherals, the communication protocol of the SPI peripherals is the SPI protocol or a variant of the SPI protocol, and the SPI control circuit comprises: An instruction storage module, used for storing a plurality of preset instructions, each of the plurality of SPI peripherals having a corresponding relationship with one or more of the plurality of preset instructions; The control module is used to receive an external instruction, convert the external instruction into a first preset instruction among the multiple preset instructions, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

2. The SPI control circuit according to claim 1, characterized in that: The control module is further used to receive an address signal, and search in the instruction storage module according to the address signal and the external instruction to convert the external instruction into the first preset instruction corresponding to the SPI peripheral indicated by the address signal.

3. The SPI control circuit according to claim 1, characterized in that: The SPI control circuit further comprises a buffer module, and the SPI control circuit has a pre-fetch function. When the pre-fetch function is turned on, the data pre-fetched from the SPI peripheral is stored in the buffer module; The control module is also used for searching in the buffer module whether data corresponding to the read instruction exists when the external instruction is a read instruction and if the pre-fetch function is in an on state; if so, feeding back the data corresponding to the external instruction; if not, converting the read instruction into the first preset instruction, and reading required data from the corresponding SPI peripheral according to the first preset instruction.

4. The SPI control circuit according to claim 3, characterized in that: The control module is further configured to read both the required data and the pre-fetched data when reading required data from the SPI peripheral device when the pre-fetch function is enabled, and store the pre-fetched data in the buffer module.

5. The SPI control circuit according to claim 3, characterized in that: The control module includes a first control module and a second control module; The first control module is used to receive the external instruction, and when the external instruction is the read instruction, determine whether the pre-fetch function is in an on state, and if the pre-fetch function is in an on state, search in the buffer module whether there is data corresponding to the read instruction, and if so, feed back the data corresponding to the external instruction; The first control module is further configured to send the external instruction to the second control module, or convert the external instruction into the first preset instruction and then send it to the second control module if the data corresponding to the read instruction does not exist in the buffer module or the external instruction is not the read instruction; The second control module is used to receive the external instruction, convert the external instruction into the first preset instruction, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction; Or receive the first preset instruction, and operate the SPI peripheral corresponding to the first preset instruction according to the first preset instruction.

6. The SPI control circuit according to claim 5, characterized in that: The second control module includes an arbitration control submodule, a sequence control submodule and an input-output control submodule; The arbitration control submodule is used to receive the external instruction or the first preset instruction sent by the first control module, perform arbitration according to the received instruction and the current task situation, and when the arbitration result satisfies the transmission of the current instruction, send the first preset instruction to the sequence control submodule, or convert the external instruction into the first preset instruction and then send it to the sequence control submodule; The sequence control submodule is used to convert the first preset instruction into an SPI instruction and then send it to the input / output control submodule; The input / output control submodule is used to distribute the SPI instruction to the corresponding SPI peripheral.

7. The SPI control circuit according to claim 6, characterized in that: The second control module further comprises a cross-clock domain module, and the cross-clock domain module is connected between the arbitration control submodule and the sequence control submodule; The cross-clock domain module is used to receive the first preset instruction sent by the arbitration control submodule, perform timing conversion on the first preset instruction, and then send it to the sequence control submodule; Alternatively, the cross-clock domain module is used to receive the external instruction sent by the arbitration control submodule, convert the external instruction into the first preset instruction, and then send it to the sequence control submodule.

8. The SPI control circuit according to claim 6, characterized in that: The SPI control circuit further includes a first first-in first-out module and a second first-in first-out module; the first first-in first-out module and the second first-in first-out module are both connected between the arbitration control submodule and the sequence control submodule; The first first-in first-out module is used to temporarily store data read from the SPI peripheral; The second first-in first-out module is used to temporarily store data written into the SPI peripheral.

9. The SPI control circuit according to claim 5, characterized in that: The buffer module includes a first buffer module and a second buffer module; the first buffer module and the second buffer module are both connected between the first control module and the second control module; The first buffer module is used to temporarily store data written into the SPI peripheral; The second buffer module is used to temporarily store data read from the SPI peripheral; One or both of the first buffer module and the second buffer module are further used to store the pre-fetched data.

10. The SPI control circuit according to any one of claims 1 to 9, characterized in that: The control module receives and responds to the external instruction via the AHB bus.

11. The SPI control circuit according to any one of claims 1 to 9, characterized in that: The SPI control circuit comprises at least one SPI bus interface, each of the SPI bus interfaces is connected to at least one of the SPI peripherals, and one of the SPI peripherals is connected to the SPI control circuit via one of the SPI bus interfaces; The access mode of the SPI control circuit includes an independent access mode and a parallel access mode. In the independent access mode, each of the SPI peripherals is accessed individually through the connected SPI bus interface; in the parallel access mode, multiple SPI peripherals connected to different SPI bus interfaces are accessed in parallel, and multiple SPI peripherals connected to the same SPI bus interface are accessed individually.

12. The SPI control circuit according to any one of claims 1 to 9, characterized in that: The SPI control circuit comprises a plurality of SPI bus interfaces, each of the SPI bus interfaces is connected to at least one of the SPI peripherals, and one of the SPI peripherals is connected to the SPI control circuit via a plurality of the SPI bus interfaces; The access mode of the SPI control circuit also includes a combined access mode. In the combined access mode, the data received by the SPI peripheral is obtained by splicing partial data of the multiple SPI bus interfaces connected thereto.

13. The SPI control circuit according to any one of claims 1 to 9, characterized in that: The instruction storage module includes at least one display lookup table, each of which is used to store at least one preset instruction; The preset instruction comprises: an instruction code, a number of data lines, and an operand; the instruction code indicates an operation corresponding to the preset instruction, the number of data lines indicates the number of bits transmitted, and the operand indicates a data rate of transmission.

14. A chip, characterized in that: Comprising the SPI control circuit as claimed in any one of claims 1 to 13.

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