Method for inserting timestamp in FPGA data

Abstract

The invention discloses a method for inserting a timestamp in FPGA data, and relates to the technical field of signal acquisition and processing, comprising: synchronously acquiring an external signal and a sampling signal of a second pulse, adjusting a threshold of a rising edge of the second pulse, when the set threshold is reached, a counter performs counting, the counter value is latched at the rising edge of the pulse and the counter is cleared, and the counter value and the total counter value between adjacent seconds are converted into an accurate timestamp; when an external signal needs to be processed, the timestamp does not enter a corresponding processing module along with the external signal, and at the same time calculates the time for processing the external signal, delays the timestamp by a corresponding time, and then groups the timestamp with the processed data for framing; the invention can insert a high-precision timestamp into data of a high sampling rate acquisition system.

Description

Technical Field

[0001] The invention relates to the technical field of signal acquisition and processing, in particular to a method for inserting a timestamp into FPGA data. Background Art

[0002] With the continuous development of electronic information technology, in the direction of signal processing, time-keeping equipment is constantly updated to meet the increasingly stringent accuracy requirements. At present, the accuracy of the second pulse of external time-keeping equipment on the market has reached the nanosecond level, which is fully capable of coping with systems with lower sampling rates. As the sampling rate continues to increase, users have higher requirements for the time accuracy of sampling information. The accuracy of the timestamp in the FPGA sampling system depends not only on the accuracy of the external time-keeping equipment itself, but also on the accuracy of the internal processing of the FPGA. The traditional serial port parsing time-keeping information can no longer meet the system's high-precision timestamp requirements. A set of timestamp information under the traditional solution may contain multiple sample point information. When the system sampling rate increases, the sample point information corresponding to a set of timestamp information becomes more, the accuracy of the timestamp information in a single device becomes lower, and the accuracy of synchronization between devices is greatly reduced, resulting in uncertainty problems introduced by the low accuracy of the timestamp information. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a method for inserting a timestamp in FPGA data. The present invention can insert a high-precision timestamp into the data of a high sampling rate acquisition system.

[0004] To achieve the above object, the technical solution adopted by the present invention is: a method for inserting a timestamp in FPGA data, comprising the following steps:

[0005] Step 1: Use the ADC chip to synchronously collect external signals and sampling signals of the second pulse, adjust the threshold of the rising edge of the second pulse, and when the set threshold is reached, count the counter, latch the counter value on the rising edge of the pulse and clear the counter, update the counter value on the rising edge of the pulse, and convert the counter value and the total counter value between adjacent seconds into an accurate timestamp;

[0006] Step 2: Write the timestamp together with the external signal into the cross-clock domain FIFO. When the external signal does not need to be processed, the original data of the external signal is directly framed and packaged with the counter generated by the second pulse and uploaded to the host computer. The host computer accurately calculates the timestamp information corresponding to each data based on the counter generated by the second pulse. When the external signal needs to be processed, the timestamp does not enter the corresponding processing module with the external signal, and the time for processing the external signal is calculated at the same time. The timestamp is delayed by the corresponding time and then framed with the processed data.

[0007] As a further improvement of the present invention, in step 1, there are one or more ADC chips, and the ADC chip includes at least two sampling channels.

[0008] As a further improvement of the present invention, in step 2, the timestamp is delayed by beating or writing the timestamp information into a cross-clock domain FIFO, and using a valid flag after signal processing as an enable signal for FIFO reading.

[0009] The present invention uses one acquisition channel of the ADC chip to sample the pulse-per-second signal, and the other ADC acquisition channels sample the required external signals to ensure the consistency of the sampled data and the high-precision timestamp signal at the same time. The sampled pulse-per-second signal follows the AD data for subsequent signal processing design to ensure that the delay of the high-precision timestamp signal is consistent with the delay of the sampled data signal processing. This method of inserting a high-precision timestamp ensures the accuracy of the timestamp within 1 second. Compared with the traditional method of analyzing the external time system, the time accuracy is accurate to one sampling point. As the AD sampling rate continues to increase, the accuracy of the timestamp will be greatly improved.

[0010] The beneficial effects of the present invention are:

[0011] In the high sampling rate system, the accuracy of the timestamp of the present invention reaches a few tenths of a nanosecond, each sampling point has a corresponding timestamp, and the timestamp and the sampling data are homologous, which provides a great guarantee for the accuracy of certain positioning devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Example

[0015] like Figure 1 As shown, a method for inserting a timestamp into FPGA data is applied to a high sampling rate sampling system that requires a high-precision sampling timestamp, and is used to solve the problem that the timestamp information in the current FPGA is not synchronized with the data or the accuracy is too low, including the following steps:

[0016] Step 1: Use the ADC chip to synchronously collect external signals and sampling signals of the second pulse, adjust the threshold of the rising edge of the second pulse, and when the set threshold is reached, count the counter, latch the counter value on the rising edge of the pulse and clear the counter, update the counter value on the rising edge of the pulse, and convert the counter value and the total counter value between adjacent seconds into an accurate timestamp;

[0017] Step 2: Write the timestamp together with the external signal into the cross-clock domain FIFO. When the external signal does not need to be processed, the original data of the external signal is directly framed and packaged with the counter generated by the second pulse and uploaded to the host computer. The host computer accurately calculates the timestamp information corresponding to each data based on the counter generated by the second pulse. When the external signal needs to be processed, the timestamp does not enter the corresponding processing module with the external signal, and the time for processing the external signal is calculated at the same time. The timestamp is delayed by the corresponding time and then framed with the processed data.

[0018] In this embodiment, (a) the threshold of the rising edge of the second pulse needs to be adjusted for sampling the second pulse; (b) the sampling data and the sampling timestamp are processed synchronously to ensure that the delay of the sampling timestamp is consistent with the delay of the sampling data after signal processing. The time units below the second are determined by the ratio of the counter generated by the second pulse to the current counter. Since the current total counter records the value of the previous second, in order to reduce the deviation, a high-stability crystal oscillator must be used to ensure the stability of the clock; (c) the rising edge obtained by sampling the second pulse is counted, and the counter value is updated on the rising edge of the pulse. The counter value and the total counter value between adjacent seconds are converted into an accurate timestamp; (d) the sampling clock has high requirements and needs to have a very high clock stability with an error within 1Hz. This can be guaranteed in hardware design by using a high-stability crystal oscillator as the reference source of the clock chip, and the clock chip locks out a stable sampling reference clock for ADC chip sampling.

[0019] Under the condition of ensuring the stability of the sampling clock, one or more ADC chips are used to synchronously collect signals and second pulses, support the synchronization of one or more signal timestamps, and obtain the corresponding accurate timestamps below the second level. The sampling system uses ADC chips to support at least dual-channel sampling. Channel one is used as the sampling interface of the second pulse PPS, and channel two is used as the sampling interface of the signal. The sampling signal of the second pulse is compared. When the set threshold is reached, it is considered to be a rising edge, that is, the beginning of the next second and the end of the previous second. This judgment method enables the accuracy of the second pulse to reach a few nanoseconds.

[0020] By setting a fixed delay for the high-precision timestamp, for example, the high-precision timestamp enters the cross-clock domain FIFO along with the sampled data, the synchronization relationship between the data and the high-precision timestamp can be maintained in subsequent signal processing.

[0021] When the sampled data is processed for signal processing, the high-precision timestamp cannot be synchronized into the filter and other IPs, but the specific data delay will be calculated according to the characteristics of the filter. The sampling timestamp can be obtained by beating, or by writing the timestamp information into the FIFO and reading it out using the valid flag after signal processing to ensure the synchronization between the data after signal processing and the high-precision timestamp.

[0022] Without signal processing, the raw data is directly framed with the counter generated by the second pulse and uploaded to the host computer. The host computer can accurately calculate the timestamp information corresponding to each data according to the counter generated by the second pulse. If signal processing is required, the preparation delay number of the processing module needs to be calculated, and the timestamp is delayed by the corresponding number of beats before the framing operation is performed.

[0023] Specifically, this embodiment includes a hardware processing part and an FPGA processing part.

[0024] The hardware processing part is used to ensure the stability of the input sampling clock, has the function of multi-channel sampling, and the stability of the external PPS. Only by ensuring a stable sampling clock and PPS can the accuracy of times below a second be guaranteed.

[0025] The cross-clock domain FIFO is used to ensure the accuracy of the corresponding timestamp information after the sampled data crosses the clock domain. The conversion clock may have a cycle deviation, and the identity of the timestamp information obtained needs to be guaranteed between multiple devices.

[0026] Delay, that is, the delay module. Since the timestamp information cannot be processed together with the data when the data is interpolated or extracted, it is necessary to first calculate the delay period of the output data of the corresponding signal processing algorithm and compensate it for the timestamp information in the Delay module.

[0027] The framing module inserts the timestamp information and the sub-second counter value into the data frame header so that the host computer can calculate the corresponding accurate timestamp after obtaining the data.

[0028] The above-mentioned embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for inserting a timestamp into FPGA data, characterized in that: The following steps are involved: Step 1, using an ADC chip to synchronously collect an external signal and a sampling signal of a second pulse, adjusting the threshold of the rising edge of the second pulse, counting the counter when the set threshold is reached, latching the counter value at the rising edge of the pulse and clearing the counter, updating the counter value at the rising edge of the pulse, and converting the counter value and the total counter value between adjacent seconds into an accurate timestamp; the ADC chip is one or more, and the ADC chip includes at least two sampling channels, one of which is used to sample the second pulse signal, and the other ADC sampling channels are used to sample the required external signals; Step 2: Write the timestamp together with the external signal into the cross-clock domain FIFO. When the external signal does not need to be processed, the original data of the external signal is directly framed and packaged with the counter generated by the second pulse and uploaded to the host computer. The host computer accurately calculates the timestamp information corresponding to each data based on the counter generated by the second pulse. When the external signal needs to be processed, the timestamp does not enter the corresponding processing module with the external signal, and the time for processing the external signal is calculated at the same time. The timestamp is delayed by the corresponding time and then framed with the processed data.

2. The method for inserting a timestamp in FPGA data according to claim 1, characterized in that: In step 2, the timestamp is delayed by beating or writing the timestamp information into the cross-clock domain FIFO, and using the valid flag after signal processing as the enable signal for FIFO reading.

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