A method and system for calculating voltage drop of memristor array

Abstract

The present application relates to the field of semiconductor technology, and provides a method and system for calculating voltage drop of a memristor array, wherein the initial bit line node voltage is iteratively calculated based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain the iterative bit line node voltage; the initial source line node voltage is iteratively calculated based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain the iterative source line node voltage; the unit iteration current of the memristor unit is obtained based on the iterative bit line node voltage and the iterative source line node voltage; if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, the iterative calculation is terminated, and the voltage drop phenomenon of the memristor array caused by the wire resistance can be simulated quickly and accurately, and a simulation verification method and tool are provided to solve the problem of inaccurate simulation calculation of the memristor caused by the voltage drop of the memristor array.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for calculating voltage drop of a memristor array. Background Art

[0002] A memristor is a nonlinear resistor with memory function, which can change its resistance by controlling the change of current. A memristor array is a cross array in which each row of memristors is connected together by a bit line and each column of memristors is connected together by a source line.

[0003] In the analog calculation of the memristor array, the input is represented by the node voltage applied to the memristor unit. The inaccuracy of the node voltage will seriously affect the accuracy of the analog calculation. Due to the existence of wire resistance, the voltage distribution in the memristor array is uneven (that is, there is a wire voltage drop), which in turn leads to inaccurate analog calculation of the memristor array. Summary of the invention

[0004] The embodiments of the present application provide a method and system for calculating voltage drop in a memristor array, which can solve the problem of uneven voltage distribution in a memristor array due to the existence of wire resistance, thereby causing inaccurate simulation calculation of the memristor array.

[0005] In a first aspect, an embodiment of the present application provides a method for calculating a voltage drop of a memristor array, comprising:

[0006] Setting the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node of the memristor array;

[0007] Obtaining ideal cell currents of a plurality of memristor cells based on the ideal bit line node voltage and the ideal source line node voltage;

[0008] Obtaining a plurality of ideal bit line node currents and a plurality of ideal source line node currents of the memristor array based on a plurality of the ideal unit currents;

[0009] Obtaining initial bit line node voltages of a plurality of memristor units based on the starting bit line voltage, the ideal bit line node current and the wire resistance;

[0010] Obtaining initial source line node voltages of a plurality of memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance;

[0011] Iteratively calculating the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage;

[0012] Iteratively calculating the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain an iterative source line node voltage;

[0013] Obtaining a cell iteration current of the memristor cell based on the iteration bit line node voltage and the iteration source line node voltage;

[0014] If the cell absolute difference between the cell iteration current of the next cycle and the cell iteration current of the previous cycle is less than the cell difference threshold, the iterative calculation is terminated.

[0015] In some embodiments, the obtaining of the ideal unit currents of the plurality of memristor units based on the ideal bit line node voltage and the ideal source line node voltage is specifically:

[0016] Based on the ideal bit line node voltage, the ideal source line node voltage and the cell ideal current formula , obtain the unit ideal current of multiple memristor units;

[0017] in, is the ideal unit current, is the ideal node voltage of row i bit line j column, is the ideal node voltage of source line i in column j, is the memristor unit resistance, is the resistance of the MOS tube.

[0018] In some embodiments, the multiple ideal bit line node currents and multiple ideal source line node currents of the memristor array are obtained based on the multiple ideal unit currents, specifically:

[0019] Based on multiple cell ideal current and bit line node current formulas , obtaining a plurality of ideal bit line node currents of the memristor array;

[0020] Based on the ideal current of multiple units and source line node current formula , obtaining a plurality of ideal source line node currents of the memristor array;

[0021] in, is the ideal node current of row i bit line j column, is the ideal node current of source line i in column j, is the ideal current of the unit.

[0022] In some embodiments, the iterative calculation of the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain the iterative bit line node voltage includes:

[0023] Based on a plurality of the initial bit line node voltages and bit line current formulas , obtaining the initial bit line node line current between the bit line nodes of the multiple memristors;

[0024] Iteratively calculating the initial bit line node voltage based on the starting bit line voltage, the initial bit line node line current and Ohm's law to obtain the iterative bit line node voltage;

[0025] in, is the initial bit line node line current of row i bit line j column, is the wire resistance, is the initial bit line node voltage of row i bit line j column, is the initial bit line node voltage of the i-th bit line (j-1) column.

[0026] In some embodiments, the iterative calculation of the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain the iterative source line node voltage includes:

[0027] Based on a plurality of the initial source line node voltages and source line current formulas , obtaining the initial source line node line current between the source line nodes of the multiple memristors;

[0028] Iteratively calculating the initial source line node voltage based on the starting source line voltage, the initial source line node line current and Ohm's law to obtain the iterative source line node voltage;

[0029] in, is the initial source line node line current of the source line i in the j column, is the wire resistance, is the initial source line node voltage of the source line i in the j column, is the initial source line node voltage of the (i+1)th column source line jth row.

[0030] In some embodiments, the obtaining of the unit iteration current of the memristor unit based on the iteration bit line node voltage and the iteration source line node voltage is specifically:

[0031] Based on the iterative bit line node voltage, the iterative source line node voltage and the cell iterative current formula , obtaining a unit iteration current of the memristor unit;

[0032] in, Iterate the node voltage for row i, bit line j, Iterate the node voltage for the j-column source line i-row, is the memristor unit resistance, is the MOS tube resistance, Iterate the current for the cell.

[0033] In some embodiments, if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then terminating the iterative calculation further includes:

[0034] When the iterative calculation ends, recording the iterative bit line node voltage of the memristor unit as the actual bit line node voltage and the iterative source line node voltage as the actual source line node voltage;

[0035] Obtaining node bit line voltage drops of a plurality of the memristor units based on the starting bit line voltage and the actual bit line node voltage;

[0036] The node source line voltage drops of the plurality of memristor units are obtained based on the starting source line voltage and the actual source line node voltage.

[0037] In some embodiments, the memristor array voltage drop calculation method further includes:

[0038] If the node bit line voltage drop and / or the node source line voltage drop is greater than a preset ratio threshold, a voltage drop abnormality alarm is generated, and the memristor unit with abnormal voltage drop is marked.

[0039] In some embodiments, if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then terminating the iterative calculation further includes:

[0040] Recording the number of iterations of performing the iterative calculation;

[0041] If the number of iterations is greater than the iteration threshold, an iteration number warning is generated.

[0042] Compared with the prior art, the present application provides a method and system for calculating voltage drop of a memristor array, which sets the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node of the memristor array; obtains the unit ideal currents of multiple memristor units based on the ideal bit line node voltage and the ideal source line node voltage; obtains multiple ideal bit line node currents and multiple ideal source line node currents of the memristor array based on the multiple unit ideal currents; obtains the initial bit line node voltage of multiple memristor units based on the starting bit line voltage, the ideal bit line node current and the wire resistance; obtains the initial source line node voltage of multiple memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance; obtains the initial source line node voltage of multiple memristor units based on the initial The initial bit line node voltage, the starting end bit line voltage and the wire resistance are iteratively calculated to obtain an iterative bit line node voltage; the initial source line node voltage is iteratively calculated based on the initial source line node voltage, the starting end source line voltage and the wire resistance to obtain an iterative source line node voltage; the unit iteration current of the memristor unit is obtained based on the iterative bit line node voltage and the iterative source line node voltage; if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, the iterative calculation is terminated, and the voltage drop phenomenon of the memristor array caused by the wire resistance can be simulated quickly and accurately, providing a simulation verification method and tool for solving the problem of inaccurate memristor simulation calculation caused by the voltage drop of the memristor array. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Hereinafter, the present invention will be described in more detail based on embodiments and with reference to the accompanying drawings.

[0044] Figure 1 is a flow chart of a method for calculating a voltage drop of a memristor array provided by an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of a 1T1R memristor array without considering wire resistance provided by an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of a 1T1R memristor array taking wire resistance into consideration according to an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of a 2T2R memristor array provided by an embodiment of the present invention;

[0048] Figure 5 is a pseudo code diagram of a method for calculating a voltage drop of a memristor array provided by an embodiment of the present invention;

[0049] Figure 6It is a schematic diagram of a memristor array voltage drop calculation system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention will be further described below in conjunction with the accompanying drawings.

[0051] A memristor is a nonlinear resistor with memory function. Its resistance value can be changed by controlling the change of current. A memristor array is a cross array in which each row of memristors is connected together by a bit line and each column of memristors is connected together by a source line. In the analog calculation of a memristor array, the input is represented by the node voltage applied to the memristor unit. The inaccuracy of the node voltage will seriously affect the accuracy of the analog calculation. Due to the existence of wire resistance, the voltage distribution in the memristor array is uneven (that is, there is a wire voltage drop), which leads to inaccurate analog calculation of the memristor array.

[0052] Since the traditional algorithm for calculating the voltage drop of a memristor is extremely slow, in order to quickly solve the IRdrop (i.e., voltage drop) phenomenon in a memristor array, such as Figure 2 As shown, first name the circuit nodes as follows: the nodes on BL (biteline) are named N BLij , where i is the number of the BL (starting from 0 and increasing from top to bottom), and j is the number of the node on a BL (starting from 0 and increasing from left to right). Figure 2 The nodes in the upper middle box correspond to the node names N BL12 ; Similarly, the node on SL (sourceline) is named N Slij , where i is the number of the node on a certain SL (starting from 0 and increasing from top to bottom), j is the number of the SL (starting from 0 and increasing from left to right), such as Figure 2 The nodes in the lower middle box correspond to the node names N SL12 (i.e., i and j refer to the i-th row and j-th column, and SL and BL specify whether the node is on SL or BL).

[0053] In the actual working condition of the circuit, the MOS tube can be equivalent to a switch with resistance. Therefore, if Figure 2In the 3*3 1T1R memristor array, there are 18 circuit nodes (9 on BL and 9 on SL). The traditional solution method requires to formulate Kirchhoff equations for each circuit node according to the node voltage to obtain an 18-dimensional Kirchhoff equation. Solving such a Kirchhoff equation requires inverting the 18-dimensional matrix. Since the memristor array in the actual circuit is often 256*256 or even 512*512, the dimension of its Kirchhoff equation is 524288, which is about 500,000. It is basically impossible to solve the inverse of a 500,000-dimensional matrix. Even if it can be solved, it takes a lot of time. Through experiments, it is found that using the traditional circuit simulation tool SPICE (Simulation Program with Integrated Circuit Emphasis, integrated circuit simulation program) to solve such a circuit, the result is still not solved after waiting for more than 24 hours. Such a long simulation time is unacceptable for in-memory chip design.

[0054] First, as Figure 1 As shown, the embodiment of the present application provides a method for calculating a voltage drop of a memristor array, comprising:

[0055] S101: Setting a starting bit line voltage, a starting source line voltage, an ideal bit line node voltage of a memristor unit node, and an ideal source line node voltage of a memristor unit node of the memristor array;

[0056] S102: Obtaining ideal cell currents of a plurality of memristor cells based on the ideal bit line node voltage and the ideal source line node voltage;

[0057] S103: obtaining a plurality of ideal bit line node currents and a plurality of ideal source line node currents of the memristor array based on the plurality of ideal unit currents;

[0058] It should be noted that if Figure 2 As shown, in the circuit solution of the memristor array, the main difficulty in solving the circuit is that the existence of the wire resistance causes the BL node voltage and the SL node voltage to be coupled, that is, the BL node voltage and the SL node voltage are not ideal values. If the memristor array is an ideal case (such as Figure 3As shown in FIG. 1 ), in an ideal case, the memristor array has a total of 6 nodes (if no circuit element is connected between two points, they are logically regarded as a circuit node), and the voltages of the 6 nodes are all ideal values ​​(the voltage of the starting bit line connected to the leftmost end of BL on BL, and the voltage of the reference voltage connected to the bottommost end of SL on SL), so it is very easy to calculate the ideal unit current on the 1T1R memristor unit, the current on the BL node and the SL node (that is, the ideal bit line node current and the ideal source line node current), so by setting the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node, it is easy to calculate the current in the ideal case.

[0059] It should be noted that the starting bit line voltage is the initial input voltage at the left end of the memristor bit line, the starting source line voltage is the initial input voltage at the lower end of the memristor unit, the ideal bit line node voltage corresponds one-to-one to the nodes on the memristor bit line, and the ideal source line node voltage corresponds one-to-one to the nodes on the memristor source line.

[0060] In some embodiments, the obtaining of the ideal unit currents of the plurality of memristor units based on the ideal bit line node voltage and the ideal source line node voltage is specifically:

[0061] Based on the ideal bit line node voltage, the ideal source line node voltage and the cell ideal current formula , obtain the unit ideal current of multiple memristor units;

[0062] in, is the ideal unit current, is the ideal node voltage of row i bit line j column, is the ideal node voltage of source line i in column j, is the memristor unit resistance, is the resistance of the MOS tube.

[0063] It should be noted that each memristor unit in the memristor array has an ideal unit current. By calculating the ideal unit current, the line current on the memristor bit line and the line current on the memristor source line can be calculated, thereby facilitating iterative calculation of the voltage drop.

[0064] In some embodiments, the multiple ideal bit line node currents and multiple ideal source line node currents of the memristor array are obtained based on the multiple ideal unit currents, specifically:

[0065] Based on multiple cell ideal current and bit line node current formulas , obtaining a plurality of ideal bit line node currents of the memristor array;

[0066] Based on the ideal current of multiple units and source line node current formula , obtaining a plurality of ideal source line node currents of the memristor array;

[0067] in, is the ideal node current of row i bit line j column, is the ideal node current of source line i in column j, is the ideal current of the unit.

[0068] It should be noted that, due to the ideal current of the unit is the current in the corresponding memristor unit, which is not the current of the memristor bit line node or the current on the memristor source line node. Therefore, when calculating the current on the memristor bit line node (i.e., the ideal bit line node current ), the current on the memristor source line node (i.e., the ideal source line node current ), the ideal current of the unit is required The node current on each row or the node current on each column is accumulated and summed to obtain the ideal bit line node current , the ideal source line node current .

[0069] S104: obtaining initial bit line node voltages of a plurality of memristor units based on the starting bit line voltage, the ideal bit line node current, and the wire resistance;

[0070] S105: obtaining initial source line node voltages of a plurality of memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance;

[0071] It should be noted that if Figure 3 As shown, the voltage at the left end of the memristor array bit line is the starting bit line voltage , since the ideal bit line node current and wire resistance Known, BL can be obtained by Ohm's law 00 The initial bit line node voltage of the node is obtained by 00 The initial bit line node voltage of the node can be determined according to the ideal bit line node current and wire resistance Continue to seek BL 01 The initial bit line node voltage of the node is obtained, thereby obtaining the initial bit line node voltage of all nodes on the bit line of the memristor array. Similarly, the initial source line node voltage of all nodes on the source line of the memristor array can also be obtained.

[0072] S106: iteratively calculating the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage;

[0073] In some embodiments, the iterative calculation of the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain the iterative bit line node voltage includes:

[0074] Based on a plurality of the initial bit line node voltages and bit line current formulas , obtaining the initial bit line node line current between the bit line nodes of the multiple memristors;

[0075] Iteratively calculating the initial bit line node voltage based on the starting bit line voltage, the initial bit line node line current and Ohm's law to obtain the iterative bit line node voltage;

[0076] in, is the initial bit line node line current of row i bit line j column, is the wire resistance, is the initial bit line node voltage of row i bit line j column, is the initial bit line node voltage of the i-th bit line (j-1) column.

[0077] It should be noted that after obtaining the initial bit line node voltages of the multiple nodes on the bit line of the memristor, the bit line current formula Obtain the current between the corresponding two bit line nodes, that is, the initial bit line node line current , according to the initial bit line node line current It is possible to easily calculate the voltage drop between two nodes on a bit line and perform iterative calculations, wherein the initial bit line node line current between different bit line nodes Generally speaking, the iterative calculation of the initial bit line node voltage is to continuously update the initial bit line node voltage according to the starting bit line voltage and the initial bit line node line current, and then update the initial bit line node line current according to the initial bit line node voltage, and iterate the calculation in this way, such as Figure 5 shown.

[0078] S107: iteratively calculating the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain an iterative source line node voltage;

[0079] In some embodiments, the iterative calculation of the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain the iterative source line node voltage includes:

[0080] Based on a plurality of the initial source line node voltages and source line current formulas , obtaining the initial source line node line current between the source line nodes of the multiple memristors;

[0081] Iteratively calculating the initial source line node voltage based on the starting source line voltage, the initial source line node line current and Ohm's law to obtain the iterative source line node voltage;

[0082] in, is the initial source line node line current of the source line i in the j column, is the wire resistance, is the initial source line node voltage of the source line i in the j column, is the initial source line node voltage of the (i+1)th column source line jth row.

[0083] It should be noted that after obtaining the initial source line node voltages of multiple nodes on the source line of the memristor, the source line current formula Obtain the current between the corresponding two source line nodes, that is, the initial source line node line current , according to the initial source line node line current It is possible to easily calculate the voltage drop between two nodes on the source line and perform iterative calculations, wherein the initial source line node line current between different source line nodes Generally speaking, the iterative calculation of the initial source line node voltage is to continuously update the initial source line node voltage according to the starting source line voltage and the initial source line node line current, and then update the initial source line node line current according to the initial source line node voltage, and the iterative calculation is repeated in this way, such as Figure 5 shown.

[0084] S108: Obtaining a cell iteration current of the memristor cell based on the iteration bit line node voltage and the iteration source line node voltage;

[0085] S109: If the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then the iterative calculation ends.

[0086] In some embodiments, the obtaining of the unit iteration current of the memristor unit based on the iteration bit line node voltage and the iteration source line node voltage is specifically:

[0087] Based on the iterative bit line node voltage, the iterative source line node voltage and the cell iterative current formula , obtaining a unit iteration current of the memristor unit;

[0088] in, Iterate the node voltage for row i, bit line j, Iterate the node voltage for the j-column source line i-row, is the memristor unit resistance, is the MOS tube resistance, Iterate the current for the cell.

[0089] It should be noted that the unit difference threshold can be generally set to 1e-6 A (i.e., 1uA), and the unit difference threshold can be adjusted according to specific parameters. If the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, it means that the iterative calculation result converges, and there is no difference between the iteration results of the previous and next cycles, and the calculation is accurate; if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is greater than or equal to the unit difference threshold, it is necessary to continue the iterative calculation.

[0090] In some embodiments, if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then terminating the iterative calculation further includes:

[0091] When the iterative calculation ends, recording the iterative bit line node voltage of the memristor unit as the actual bit line node voltage and the iterative source line node voltage as the actual source line node voltage;

[0092] Obtaining node bit line voltage drops of a plurality of the memristor units based on the starting bit line voltage and the actual bit line node voltage;

[0093] The node source line voltage drops of the plurality of memristor units are obtained based on the starting source line voltage and the actual source line node voltage.

[0094] In some embodiments, the memristor array voltage drop calculation method further includes:

[0095] If the node bit line voltage drop and / or the node source line voltage drop is greater than a preset ratio threshold, a voltage drop abnormality alarm is generated, and the memristor unit with abnormal voltage drop is marked.

[0096] It should be noted that after the iterative calculation of all memristor units is completed, the accurate node voltage, namely the actual bit line node voltage and the actual source line node voltage, is obtained. Based on the actual bit line node voltage and the actual source line node voltage, on the one hand, accurate simulation calculation can be performed; on the other hand, the node voltage drop can also be understood.

[0097] It should be noted that the preset ratio threshold can be 50% (can also be adjusted according to actual conditions), which means that there are serious problems in the current design and the chip needs to be redesigned. In this case, the array size can be reduced (cut into small sub-arrays) and the following can be adopted: Figure 4The 2T2R memristor array structure shown is optimized.

[0098] In some embodiments, if the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then terminating the iterative calculation further includes:

[0099] Recording the number of iterations of performing the iterative calculation;

[0100] If the number of iterations is greater than the iteration threshold, an iteration number warning is generated.

[0101] It should be noted that the number of iterative calculations reflects the severity of non-ideal characteristics in the CIM system (Compute in Memory) based on the memristor array. If the number of iterations is large, it means that the IR drop (voltage drop) problem is more serious. In subsequent designs, the IR drop problem can be alleviated by adopting a 2T2R memristor array structure and controlling the array size (i.e., cutting the RRAM array into small sub-arrays), thereby reducing the number of iterations.

[0102] It should be noted that the calculation method of the embodiment of the present application can also be used to calculate the voltage drop of a 2T2R memristor array, such as Figure 3 As shown, the currents in the positive and negative parts of the 2T2R memristor unit are calculated by Ohm's law:

[0103] ,

[0104] ,

[0105] Then the memristor unit current is obtained: ;

[0106] Then, the line currents on BL and SL are obtained by Ohm’s law, and the calculation method is the same as that of the 1T1R memristor array.

[0107] Second, as Figure 6 As shown, an embodiment of the present application provides a memristor array voltage drop calculation system, comprising:

[0108] A voltage setting module 210, used to set the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node of the memristor array;

[0109] A current calculation module 220, configured to obtain ideal unit currents of a plurality of memristor units based on the ideal bit line node voltage and the ideal source line node voltage;

[0110] The voltage calculation module 230 is used to obtain multiple ideal bit line node currents and multiple ideal source line node currents of the memristor array based on the multiple ideal unit currents; obtain the initial bit line node voltages of the multiple memristor units based on the starting bit line voltage, the ideal bit line node current and the wire resistance; and obtain the initial source line node voltages of the multiple memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance;

[0111] The iterative calculation module 240 is used to iteratively calculate the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage; iteratively calculate the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain an iterative source line node voltage; obtain the unit iteration current of the memristor unit based on the iterative bit line node voltage and the iterative source line node voltage; if the unit absolute difference between the unit iteration current of the subsequent cycle and the unit iteration current of the previous cycle is less than a unit difference threshold, the iterative calculation is terminated.

[0112] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and / or computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0113] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0114] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0115] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for calculating voltage drop of a memristor array, characterized in that: include: Setting the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node of the memristor array; Obtaining ideal cell currents of a plurality of memristor cells based on the ideal bit line node voltage and the ideal source line node voltage; Obtaining a plurality of ideal bit line node currents and a plurality of ideal source line node currents of the memristor array based on a plurality of the ideal unit currents; Obtaining initial bit line node voltages of a plurality of memristor units based on the starting bit line voltage, the ideal bit line node current and the wire resistance; Obtaining initial source line node voltages of a plurality of memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance; Iteratively calculating the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage; Iteratively calculating the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain an iterative source line node voltage; Obtaining a cell iteration current of the memristor cell based on the iteration bit line node voltage and the iteration source line node voltage; If the cell absolute difference between the cell iteration current of the next cycle and the cell iteration current of the previous cycle is less than the cell difference threshold, the iterative calculation is terminated.

2. The method for calculating voltage drop of a memristor array according to claim 1, characterized in that: The unit ideal current of the plurality of memristor units is obtained based on the ideal bit line node voltage and the ideal source line node voltage, specifically: Based on the ideal bit line node voltage, the ideal source line node voltage and the cell ideal current formula , obtain the unit ideal current of multiple memristor units; in, is the ideal unit current, is the ideal node voltage of row i bit line j column, is the ideal node voltage of source line i in column j, is the memristor unit resistance, is the resistance of the MOS tube.

3. The memristor array voltage drop calculation method according to claim 1, characterized in that: The method of obtaining a plurality of ideal bit line node currents and a plurality of ideal source line node currents of the memristor array based on the plurality of ideal unit currents is specifically as follows: Based on multiple cell ideal current and bit line node current formulas , obtaining a plurality of ideal bit line node currents of the memristor array; Based on the ideal current of multiple units and source line node current formula , obtaining a plurality of ideal source line node currents of the memristor array; in, is the ideal node current of row i bit line j column, is the ideal node current of source line i in column j, is the ideal current of the unit.

4. The method for calculating voltage drop of a memristor array according to claim 1, characterized in that: The iterative calculation of the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage includes: Based on a plurality of the initial bit line node voltages and bit line current formulas , obtaining the initial bit line node line current between the bit line nodes of the multiple memristors; Iteratively calculating the initial bit line node voltage based on the starting bit line voltage, the initial bit line node line current and Ohm's law to obtain the iterative bit line node voltage; in, is the initial bit line node line current of row i bit line j column, is the wire resistance, is the initial bit line node voltage of row i bit line j column, is the initial bit line node voltage of the bit line (j-1) column in the i row.

5. The memristor array voltage drop calculation method according to claim 1, characterized in that: The iterative calculation of the initial source line node voltage based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain the iterative source line node voltage includes: Based on a plurality of the initial source line node voltages and source line current formulas , obtaining the initial source line node line current between the source line nodes of the multiple memristors; Iteratively calculating the initial source line node voltage based on the starting source line voltage, the initial source line node line current and Ohm's law to obtain the iterative source line node voltage; in, is the initial source line node line current of the source line i in the j column, is the wire resistance, is the initial source line node voltage of the source line i in the j column, is the initial source line node voltage of the (i+1)th column source line jth row.

6. The method for calculating voltage drop of a memristor array according to claim 1, characterized in that: The unit iteration current of the memristor unit is obtained based on the iteration bit line node voltage and the iteration source line node voltage, specifically: Based on the iterative bit line node voltage, the iterative source line node voltage and the cell iterative current formula , obtaining a unit iteration current of the memristor unit; in, Iterate the node voltage for row i, bit line j, Iterate the node voltage for the j-column source line i-row, is the memristor unit resistance, is the MOS tube resistance, Iterate the current for the cell.

7. The memristor array voltage drop calculation method according to claim 1, characterized in that: If the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then the iterative calculation is terminated, and further includes: When the iterative calculation ends, recording the iterative bit line node voltage of the memristor unit as the actual bit line node voltage and the iterative source line node voltage as the actual source line node voltage; Obtaining node bit line voltage drops of a plurality of the memristor units based on the starting bit line voltage and the actual bit line node voltage; The node source line voltage drops of the plurality of memristor units are obtained based on the starting source line voltage and the actual source line node voltage.

8. The method for calculating voltage drop of a memristor array according to claim 7, characterized in that: Also includes: If the node bit line voltage drop and / or the node source line voltage drop is greater than a preset ratio threshold, a voltage drop abnormality alarm is generated, and the memristor unit with abnormal voltage drop is marked.

9. The memristor array voltage drop calculation method according to claim 1, characterized in that: If the unit absolute difference between the unit iteration current of the next cycle and the unit iteration current of the previous cycle is less than the unit difference threshold, then the iterative calculation is terminated, and further includes: Recording the number of iterations of performing the iterative calculation; If the number of iterations is greater than the iteration threshold, an iteration number warning is generated.

10. A memristor array voltage drop calculation system, characterized in that: include: A voltage setting module, used to set the starting bit line voltage, the starting source line voltage, the ideal bit line node voltage of the memristor unit node, and the ideal source line node voltage of the memristor unit node of the memristor array; A current calculation module, configured to obtain ideal unit currents of a plurality of memristor units based on the ideal bit line node voltage and the ideal source line node voltage; A voltage calculation module, used for obtaining a plurality of ideal bit line node currents and a plurality of ideal source line node currents of the memristor array based on a plurality of the ideal unit currents; Obtaining initial bit line node voltages of a plurality of memristor units based on the starting bit line voltage, the ideal bit line node current and the wire resistance; Obtaining initial source line node voltages of a plurality of memristor units based on the starting source line voltage, the ideal source line node current and the wire resistance; an iterative calculation module, configured to iteratively calculate the initial bit line node voltage based on the initial bit line node voltage, the starting bit line voltage and the wire resistance to obtain an iterative bit line node voltage; The initial source line node voltage is iteratively calculated based on the initial source line node voltage, the starting source line voltage and the wire resistance to obtain an iterative source line node voltage; the unit iteration current of the memristor unit is obtained based on the iterative bit line node voltage and the iterative source line node voltage; if the unit absolute difference between the unit iteration current of the subsequent cycle and the unit iteration current of the previous cycle is less than a unit difference threshold, the iterative calculation is terminated.

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