Bus circuit, wiring method of bus circuit, and chip

Abstract

The embodiment of the invention provides a bus circuit, a wiring method of the bus circuit and a chip, and relates to the technical field of integrated circuit design. The bus circuit comprises a bus with the bit width of W, the bus comprises W signal lines, W is a positive integer larger than 2, the bus circuit comprises a plurality of metal layers, the metal layers at least comprise a first metal layer and a plurality of second metal layers, and the first metal layer and the second metal layers are arranged in a staggered and stacked mode; and the W signal lines are arranged on the plurality of second metal layers in parallel along the bus transmission direction. According to the bus circuit provided by the invention, the crosstalk between the signal lines is relatively low.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a bus circuit, a wiring method of the bus circuit, and a chip. Background Art

[0002] With the continuous development of integrated circuit technology and the continuous evolution of circuit process size, the chip feature size continues to decrease. This causes the physical size of the signal line (i.e., metal line) in the signal transmission circuit on the chip and the spacing between the signal lines to gradually decrease, which in turn leads to an increase in the coupling parasitic capacitance between the signal lines, exacerbating the crosstalk problem between the signal lines, i.e., the noise problem. In addition, the crosstalk problem between signal lines can cause delays, glitches, and other effects on the chip circuit. Therefore, how to reduce the degree of crosstalk between signal lines has become an urgent problem to be solved. Summary of the invention

[0003] In view of the above problems, embodiments of the present application are proposed to provide a chip, a bit error rate testing method and a chip that overcome the above problems or at least partially solve the above problems, so as to solve the problem of high crosstalk between signal lines in the target signal transmission circuit.

[0004] In order to solve the above problem, an embodiment of the present application discloses a bus circuit, wherein a bus with a bit width of W includes: W signal lines, where W is a positive integer greater than 2, and the bus circuit includes:

[0005] A plurality of metal layers, the plurality of metal layers at least comprising: a first metal layer and a plurality of second metal layers, the first metal layer and the second metal layer being alternately stacked;

[0006] The W signal lines are arranged in parallel on the second metal layers along a bus transmission direction.

[0007] The embodiment of the present application further discloses a wiring method for a bus circuit, wherein a bus with a bit width of W includes W signal lines, where W is a positive integer greater than 2, and the bus circuit includes: a plurality of metal layers, wherein the plurality of metal layers include at least a first metal layer and a plurality of second metal layers, and the first metal layer and the second metal layer are arranged in an alternating and stacked manner; the method includes:

[0008] At least one signal line among the W signal lines is arranged in parallel along a bus transmission direction on each of the plurality of second metal layers, so that the W signal lines are arranged in parallel along the bus transmission direction on the plurality of second metal layers.

[0009] The embodiment of the present application further discloses a bus circuit, wherein the bus is divided into a plurality of sub-buses in the bus width expansion direction, and each of the sub-buses is divided into a plurality of bus segments in the bus transmission direction;

[0010] In any bus segment of each of the sub-buses, the signal lines of the sub-buses are distributed on a plurality of spaced metal layers in one of a plurality of preset coding modes;

[0011] The distribution of the preset multiple encoding modes on all the bus segments enables each signal line of the bus to have a balanced delay.

[0012] An embodiment of the present application further discloses a chip, which includes the bus circuit described in any one of the first aspects, or the bus circuit described in any one of the second aspects.

[0013] The embodiments of the present application include the following advantages:

[0014] In an embodiment of the present application, for a bus having a bit width of W and including W signal lines, the bus circuit provided by the embodiment of the present application includes multiple metal layers. The multiple metal layers include at least: a first metal layer and multiple second metal layers, and the first metal layer and the second metal layer are arranged in an alternating and stacked manner. W signal lines are arranged in parallel in the multiple second metal layers along the bus transmission direction, and W is a positive integer greater than 2. In the bus circuit, since the multiple second metal layers are separated by a first metal layer, there is a large distance between two adjacent metal layers where the signal lines are arranged, so that the crosstalk between the signal lines on the two adjacent second metal layers can be effectively reduced, thereby making the crosstalk between the signal lines of the entire bus circuit lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1 to 16 Schematic diagrams 1 to 16 of the structure of the bus circuit provided in the embodiments of the present application are respectively shown;

[0016] Fig.17 A flow chart of a bus circuit wiring method provided by an embodiment of the present application is shown;

[0017] Fig.18 A structural block diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0019] With the continuous development of integrated circuit technology, the chip process size continues to evolve. The delay of circuit devices such as transistors is reduced. However, the resistance of the metal wire per unit length becomes larger, and the capacitance of the metal wire per unit length remains basically unchanged. This makes the delay of the metal wire per unit length increase as the circuit process size decreases, gradually exceeding the delay of the circuit device, and becoming the main factor in the chip delay problem. Among them, the circuit process includes the metal interconnection process. The metal interconnection process refers to the process of depositing a metal film on an integrated circuit chip, forming wiring through photolithography technology, and interconnecting isolated components into the required circuit according to certain requirements. With the continuous reduction of the circuit process size and the continuous increase in the number of integrated circuit devices, the multi-layer metal wiring method under the metal interconnection process has been widely used.

[0020] Moreover, with the development of chip technology, the chip feature size continues to decrease. This causes the physical size of the signal line (i.e., metal line) in the signal transmission circuit on the chip and the spacing between the signal lines to gradually decrease, which in turn leads to an increase in the coupling parasitic capacitance between the signal lines, exacerbating the crosstalk problem between the signal lines, i.e., the noise problem. In addition, the crosstalk problem between the signal lines will cause delay changes, glitches, and other effects in the chip circuit. The delay change of the chip circuit will affect the performance of the circuit system, especially for the processor chip, the delay of the chip circuit is a crucial factor restricting its performance. The glitches in signal transmission may destroy the state of the gate-level devices in the chip circuit, causing the operation of the chip circuit to be blocked and causing circuit system failures.

[0021] Therefore, how to reduce the crosstalk between signal lines becomes an urgent problem to be solved.

[0022] In the embodiment of the present application, a multi-layer metal wire wiring method can be used to encode the bus to obtain the bus circuit provided by the embodiment of the present application. The bus circuit is also called a bus encoding circuit, which can reduce the crosstalk between signal lines to a certain extent and ensure the consistency of the transmission delay of W signal lines in the bus. In an optional scenario, the bus (Bus) can refer to a public communication trunk for transmitting information between various functional components in a computer. The bus is a common channel for transmitting information such as processors, memory, input and output, and output devices.

[0023] Please refer to Figure 1, which shows a schematic diagram of a bus circuit provided in an embodiment of the present application. The bus circuit can use spatial coding to lay out signal lines to reduce crosstalk between signal lines to a certain extent. The bus circuit in the embodiment of the present application can transmit data with a bit width of W, that is, the bus of the bus circuit refers to a bus with a bit width of W. The bus with a bit width of W may include W signal lines, each signal line is used to transmit one bit of data, and W is a positive integer greater than 2. Among them, the bus refers to a public communication trunk line for transmitting information between various functional components of a computer, and is a common channel for processors, memory, and input and output devices to transmit information. The bus is a group of lines that transmit data. As Figure 1 As shown, the bus circuit includes:

[0024] Multiple metal layers 100. The multiple metal layers 100 at least include: a first metal layer 101 and multiple second metal layers 102. The first metal layer 101 and the second metal layer 102 are arranged in an alternating manner. W signal lines 200 are arranged in parallel in the multiple second metal layers 102 along the bus transmission direction.

[0025] Among them, the metal layer is also called a metal wiring layer. Multiple second metal layers refer to the number of second metal layers being two or more. The bus transmission direction is parallel to the flow direction of data transmitted on the bus circuit. In one application scenario, the bus is a unidirectional bus. The bus transmission direction can be the flow direction of data transmitted on the bus circuit. In another application scenario, the bus is a bidirectional bus. The bus transmission direction can be the flow direction of data transmitted on the bus circuit. Alternatively, the bus transmission direction can also be the opposite direction of the flow direction of data transmitted on the bus circuit.

[0026] The W signal lines 200 are arranged in parallel in the plurality of second metal layers 102 along the bus transmission direction, which may mean that the W signal lines 200 may be arranged in parallel in two or more second metal layers along the bus transmission direction. That is, among the plurality of second metal layers 102, part of the second metal layers 102 or all of the second metal layers 102 may include one or more signal lines. When a second metal layer includes a plurality of signal lines, the spacing between adjacent signal lines among the plurality of signal lines is at least greater than the minimum wiring spacing.

[0027] In one example, if the number of second metal layers is greater than W, then the W second metal layers in the plurality of second metal layers 102 each include a signal line arranged in parallel along the bus transmission direction. In another example, if the number of second metal layers is less than W, then each second metal layer in the plurality of second metal layers includes at least one signal line arranged in parallel along the bus transmission direction, and the first number of second metal layers in the plurality of second metal layers each include two signal lines arranged in parallel along the bus transmission direction. The first number is the difference between the number of signal lines and the number of second metal layers. In another example, W / 2 second metal layers in the plurality of second metal layers each include two signal lines arranged in parallel along the bus transmission direction.

[0028] It should be noted that Figure 1 A schematic description is given by taking an example where a plurality of metal layers include four first metal layers 101 and three second metal layers 102 , and four signal lines respectively arranged in parallel in the three second metal layers 102 along a bus transmission direction.

[0029] Optionally, multiple metal layers in the bus circuit are stacked. The second metal layer with W signal lines can be a second metal layer located in the middle layer of the multiple metal layers stacked. The middle layer refers to the layer other than the top layer and the bottom layer of the multiple metal layers. For example, the second metal layer with W signals is the center layer of the multiple metal layers stacked. For example, it is assumed that the bus circuit is arranged on a chip of 12nm process, and the chip adopts the wiring process of 1P13M. The multiple metal layers of the bus circuit under the wiring process of 1P13M include: 1x metal layer, 1.25x metal layer, 2x metal layer, 4x metal layer and 14x metal layer, etc. Among them, 1x, 1.25x, 2x, 4x and 14x all represent the thickness of the metal layer, and the larger the number, the thicker the thickness of the metal layer. The bus circuit under the wiring process of 1P13M includes 13 metal layers, and the second metal layer with W signal lines can be multiple metal layers from the metal layer M4 located at the 4th layer to the metal layer M10 located at the 10th layer.

[0030] In the case where the bus circuit is arranged on the chip, the wiring area of ​​the multiple metal layers of the bus circuit in the chip environment usually increases in order from high to low levels, and the thickness of the metal layer usually decreases in order from high to low. The signal lines arranged on the lower metal layers are generally thinner and thinner, so the line resistance of the lower metal layers is larger. If the signal lines arranged on the lower metal layers are used for data transmission over a long distance, the data transmission delay is high due to the large line resistance of the signal lines, which makes it difficult to meet the design requirements of high-performance chips. The signal lines arranged on the higher metal layers are generally wider and thicker, so the line resistance of the higher metal layers is smaller. However, due to the requirement for the higher metal layers in the chip wiring design rules, only a very small number of signal lines can be distributed within the limited metal wiring area. Therefore, the higher metal layers are usually used to lay out the global power supply network and the clock network so as not to waste the wider metal layer area. The metal layers in the middle layers usually have similar characteristic parameters, and the chip wiring design rules are also similar. Therefore, by using the second metal layer located in the middle layer among the multiple metal layers to lay out W signal lines, the transmission delay of the laid out signal lines can be low, and the delay limit of the chip with higher performance can be met with a greater probability, and the second metal layer for laying out the signal lines can meet its corresponding chip wiring design rules with a greater probability. Among them, the characteristic parameters of the metal layer can include the square resistance of the metal layer, etc.

[0031] Further optionally, the multiple metal layers of the bus circuit can adopt a wiring method that alternates horizontally and vertically between layers. For example, if the wiring direction adopted by the metal layer of the even-numbered layer in the multiple metal layers is horizontal, that is, the signal line on the metal layer of the even-numbered layer is masked in a horizontal distribution manner, then the wiring direction adopted by the metal layer of the odd-numbered layer is vertical, that is, the signal line on the metal layer of the odd-numbered layer is masked in a vertical distribution manner. Based on this, the wiring direction of the second metal layer in the multiple metal layers can be consistent with the bus transmission direction. For example, continue to take the chip in which the aforementioned bus circuit is arranged in a 12nm process as an example. The chip adopts a 1P13M wiring process. Among the 13 metal layers included in the bus circuit under the 1P13M wiring process, the wiring direction of the metal layer of the even-numbered layer is horizontal, and the wiring direction of the metal layer of the odd-numbered layer is vertical. If it is assumed that the bus transmission direction of the bus is horizontal, the second metal layer with W signal lines arranged can be a plurality of metal layers of the even-numbered layers from metal layer M4 to metal layer M10. For example, the second metal layer on which W signal lines are arranged may be a metal layer M4 located at the 4th layer, a metal layer M6 located at the 6th layer, a metal layer M8 located at the 8th layer, and a metal layer M10 located at the 10th layer.

[0032] Multiple metal layers adopt this inter-layer alternating horizontal and vertical wiring method, which can not only make the chip including the bus circuit manufactured by the process have better inter-layer mechanical stress and ensure the structural stability of the chip, but also reduce the parallel wiring length of the signal line on two adjacent metal layers, so as to reduce the coupling capacitance between the two adjacent metal layers and further reduce the delay of the signal line.

[0033] In summary, for a bus with a bit width of W including W signal lines, the bus circuit provided by the embodiment of the present application includes multiple metal layers. The multiple metal layers include at least: a first metal layer and multiple second metal layers, and the first metal layer and the second metal layer are arranged in an alternating and stacked manner. W signal lines are arranged in parallel in the multiple second metal layers along the bus transmission direction, and W is a positive integer greater than 2. In the bus circuit, since the multiple second metal layers are separated by a first metal layer, there is a large distance between two adjacent metal layers where the signal lines are arranged, so that the crosstalk between the signal lines on the two adjacent second metal layers can be effectively reduced, thereby making the crosstalk between the signal lines of the entire bus circuit lower.

[0034] The structure of the bus circuit provided in the embodiment of the present application can have at least the following two optional situations based on the aforementioned structure. For the convenience of explanation, the following embodiment is described by taking the transmission direction of the bus as the horizontal direction and the bus width expansion direction, that is, the stacking direction from the top layer to the bottom layer in multiple metal layers as the vertical direction. The following embodiment of the present application introduces the two situations separately.

[0035] The first optional situation is to use the longitudinal coding method to lay out the signal lines to obtain the bus circuit.

[0036] Optionally, the W signal lines 200 are divided into at least two sub-buses. Each sub-bus includes at least one signal line. In the plurality of second metal layers 102 where the W signal lines are arranged, the signal lines included in each second metal layer 102 belong to different sub-buses.

[0037] The number of signal lines in each sub-bus may be the same or different. The signal lines of the same sub-bus are arranged in parallel on different second metal layers along the bus transmission direction. In this way, by grouping W signal lines and controlling the signal lines of the same sub-bus to be arranged on different second metal layers, the number of signal lines arranged on a single second metal layer can be effectively controlled. In addition, since the spacing between signal lines on the same metal layer has certain requirements, controlling the number of signal lines arranged on a single second metal layer can effectively control the wiring area of ​​a single second metal layer.

[0038] For example, assuming that W is 8, 8 signal lines (N1-N8) are divided into two sub-buses. The two sub-buses include a first sub-bus and a second sub-bus. The first sub-bus includes 4 signal lines (N1-N4). The second sub-bus includes 4 signal lines (N5-N8).

[0039] In one case, signal line N1 and signal line N5 are arranged in the same second metal layer, signal line N3 and signal line N7 are arranged in the same second metal layer, and signal line N2, signal line N4, signal line N6 and signal line N8 are arranged in four different second metal layers respectively.

[0040] In another case, signal line N1 and signal line N5 are arranged in the same second metal layer, signal line N2 and signal line N6 are arranged in the same second metal layer, signal line N3 and signal line N7 are arranged in the same second metal layer, and signal line N4 and signal line N8 are arranged in two different second metal layers respectively.

[0041] In some embodiments of the present application, the W signal lines can be divided into groups of N signal lines to obtain The number of the second metal layers can be N, where N is a positive integer. When W / N is an integer, each second metal layer includes W / N signal lines arranged in parallel along the bus transmission direction, and the signal lines included in each second metal layer belong to different sub-buses. When W / N is a non-integer, each second metal layer includes at least signal lines, each of the W%N second metal layers includes a plurality of N second metal layers arranged in parallel along the bus transmission direction. signal lines, and each signal line included in the second metal layer belongs to a different sub-bus.

[0042] In this way, the number of second metal layers used to lay out signal lines can be the same as the number of sub-bus divisions. Therefore, when the signal lines of the same sub-bus are laid out in different second metal layers, W signal lines can be laid out more evenly in multiple second metal layers, effectively controlling the number of signal lines on a single second metal layer, ensuring the spacing requirements between signal lines on the same metal layer, and thereby effectively controlling the wiring area of ​​a single second metal layer.

[0043] For an example, see Figure 2, which shows a schematic diagram of the structure of a bus circuit proposed in an embodiment of the present application. Assume that W is 8 and N is 4. W signal lines N1-N8 201-208 are divided into 2 sub-buses G1-G2. Sub-bus G1 includes signal lines N1-N4 201-204; sub-bus G2 includes signal lines N5-N8 205-208. And assume that the 4 second metal layers include: a second metal layer M4 1021, a second metal layer M6 1022, a second metal layer M8 1023 and a second metal layer M10 1024. As Figure 2 As shown, each second metal layer 102 includes two signal lines arranged in parallel along the bus transmission direction. Among them, the signal line N1 201 and the signal line N5 205 are arranged in the second metal layer M4 1021; the signal line N3 203 and the signal line N7 207 are arranged in the second metal layer M6 1022; the signal line N2 202 and the signal line N6 206 are arranged in the second metal layer M8 1023; the signal line N4 204 and the signal line N8 208 are arranged in the second metal layer M10 1024.

[0044] As another example, assume that W is 8 and N is 3. W signal lines N1-N8 are divided into three sub-buses G1-G3. Sub-bus G1 includes signal lines N1-N3; sub-bus G2 includes signal lines N4-N6; sub-bus G3 includes signal lines N7-N8. And assume that three second metal layers include: second metal layer M4 1021, second metal layer M6 1022, and second metal layer M8 1023. Each second metal layer 102 includes at least two signal lines arranged in parallel along the bus transmission direction, and two of the three second metal layers include three signal lines. For example, signal line N1, signal line N4, and signal line N7 are arranged in second metal layer M4 1021; signal line N2, signal line N5, and signal line N8 are arranged in second metal layer M8 1022; signal line N3 and signal line N6 are arranged in second metal layer M6 1023.

[0045] Further optionally, the projections of the signal lines belonging to the same sub-bus included in at least two of the N second metal layers overlap on the same horizontal plane, that is, the longitudinal physical positions of at least two signal lines belonging to the same sub-bus in at least two second metal layers overlap.

[0046] In an optional case, the projections of the signal lines belonging to the same sub-bus included in the two target second metal layers overlap on the same horizontal plane, and the two target second metal layers are separated by a second metal layer. Figure 2Take the bus circuit shown in FIG. 10 as an example. The projections of the signal line N1 201 and the signal line N2 202 in the second metal layer M4 1021 and the second metal layer M8 1023 on the same horizontal plane overlap, and the projections of the signal line N5 205 and the signal line N6 206 on the same horizontal plane overlap. The projections of the signal line N3 203 and the signal line N4 204 in the second metal layer M6 1022 and the second metal layer M10 1024 on the same horizontal plane overlap, and the projections of the signal line N7 207 and the signal line N8 208 on the same horizontal plane overlap.

[0047] In another optional case, the projections of the signal lines belonging to the same sub-bus included in each second metal layer overlap on the same horizontal plane. For example, in the second metal layer M4 1021, the second metal layer M6 1022, the second metal layer M8 1023, and the second metal layer M10 1024, the projections of the signal lines N1-N4 201-204 overlap on the same horizontal plane, and the projections of the signal lines N5-N8 205-208 overlap on the same horizontal plane.

[0048] In this way, by arranging the signal lines of the same sub-bus on different second metal layers, and making the vertical physical positions of the signal lines overlap on N second metal layers, the required wiring area of ​​the signal lines in the horizontal direction is reduced, the scribing area of ​​the second metal layer is reduced, and the horizontal area of ​​the bus circuit is effectively reduced while ensuring that the signal lines on two adjacent second metal layers have low crosstalk.

[0049] It should be noted that the signal lines of the same sub-bus on two adjacent second metal layers in the N second metal layers do not overlap in projection on the same horizontal plane. That is, the two signal lines that overlap in the longitudinal physical position in the same sub-bus are arranged on two non-adjacent second metal layers. In this way, since the signal lines on the two adjacent second metal layers are misaligned in the longitudinal physical position, the distance between the W signal lines in the longitudinal direction of the plurality of second metal layers is further increased, and the crosstalk between the signal lines on the two adjacent second metal layers is further effectively reduced.

[0050] In the present application embodiment, Figure 3 As shown, the bus circuit further includes: a driving unit 300. Each signal line includes a plurality of signal line segments connected by at least one driving unit 300. The signal line segments are also called interconnection lines. Figure 3 Two signal line segments (signal line segment 1 and signal line segment 2 ) in one signal line connected to the driving unit 300 are used for schematic illustration.

[0051] The drive unit 200 is also called a drive relay unit. Optionally, the drive unit 200 may be an inverter or a buffer. In an optional case, the drive unit 200 and the signal line are arranged in different interconnection layers in the bus circuit. The signal line segment may be connected to the drive unit through a via. For example, the drive unit may be arranged in an interconnection layer at the bottom of the bus circuit. The inverter may invert the phase of the input signal by 180 degrees. The input signal of an odd number of inverters connected in series is opposite in phase to the output signal, while the input signal of an even number of inverters connected in series is the same in phase as the output signal.

[0052] It should be noted that the driving force of the driving unit has a certain driving range. If too few driving units are inserted into a signal line, the energy of the transmitted signal will be attenuated to a large extent after the signal line performs signal transmission over a long distance, and the signal is easily affected by noise, or even distorted. In addition, the driving unit will also cause the signal it transmits to have a certain delay. Therefore, if too many driving units are inserted into a signal line, the transmission delay of the signal line may be large, thereby failing to meet the transmission delay requirements of the bus. Based on this, it is not difficult to understand that the number of driving units inserted into a signal line in the bus transmission direction, that is, the number of driving units used to connect the signal line segments in a signal line can be determined based on the driving range of the driving unit and the influence of the driving unit on the signal line delay, and the embodiments of the present application do not limit this.

[0053] For example, assume that 8 signal lines N1-N8 are divided into 2 sub-buses G1-G2 in groups of 4. Sub-bus G1 includes signal lines N1-N4; sub-bus G2 includes signal lines N5-N8. Each signal line includes two signal line segments connected by one driving unit.

[0054] Wherein, the signal line N1 includes two signal line segments connected by a driving unit D1 301. The signal line N2 includes two signal line segments connected by a driving unit D2 302. The signal line N3 includes two signal line segments connected by a driving unit D3 303. The signal line N4 includes two signal line segments connected by a driving unit D4 304. The signal line N5 includes two signal line segments connected by a driving unit D5 305. The signal line N6 includes two signal line segments connected by a driving unit D6 306. The signal line N7 includes two signal line segments connected by a driving unit D7 307. The signal line N8 includes two signal line segments connected by a driving unit D8 308. And it is assumed that the four second metal layers used to lay out the signal lines include: a second metal layer M4 1021, a second metal layer M6 1022, a second metal layer M8 1023, and a second metal layer M10 1024.

[0055] like Figure 4 and Figure 5 As shown, two signal line segments of signal line N1 201 and two signal line segments of signal line N5 205 are arranged in the second metal layer M4 1021; two signal line segments of signal line N3 301 and two signal line segments of signal line N7 701 are arranged in the second metal layer M6 1022; two signal line segments of signal line N2 202 and two signal line segments of signal line N6 206 are arranged in the second metal layer M8 1023; two signal line segments of signal line N4 204 and two signal line segments of signal line N8 208 are arranged in the second metal layer M10 1024.

[0056] In some embodiments of the present application, among the multiple driving units corresponding to the W signal lines, the projection of the first driving unit on the plane where the second driving unit is located is misaligned with the second driving unit. Among them, a signal line segment connected to the first driving unit and a signal line segment connected to the second driving unit are arranged on two adjacent second metal layers. That is, the projections of the driving units respectively connected to the two signal line segments arranged on two adjacent second metal layers on the same plane do not overlap.

[0057] For example, please continue to refer to Figure 4 and Figure 5 , the two signal line segments arranged on the second metal layer M4 1021 and the second metal layer M6 1022 respectively connect the drive unit D1 (i.e., the first drive unit) 301 and the drive unit D3 (i.e., the second drive unit) 303, and the drive unit D5 (i.e., the first drive unit) 305 and the drive unit D7 (i.e., the second drive unit) 307 are staggered. The two signal line segments arranged on the second metal layer M8 1023 and the second metal layer M10 1024 respectively connect the drive unit D2 (i.e., the first drive unit) 302 and the drive unit D4 (i.e., the second drive unit) 304, and the drive unit D6 (i.e., the first drive unit) 306 and the drive unit D8 (i.e., the second drive unit) 308 are staggered. It should be noted that, Figure 5 Only one signal line segment included in each signal line is shown for schematic illustration.

[0058] In this way, since the projection of the first driving unit on the plane where the second driving unit is located is misaligned with the second driving unit. Therefore, for two signal line segments arranged on two adjacent second metal layers, the projection of one signal line segment on the plane where the other signal line segment is located is at least separated from the signal line segment by a misalignment distance, and the misalignment distance refers to the distance between the projection of the first driving unit on the plane where the second driving unit is located and the second driving unit. The unit height of the driving unit is much larger than the minimum width of the signal line, that is, the minimum line width of the signal line. Therefore, the arrangement of the first driving unit and the second driving unit makes the distance between the two signal line segments arranged on the two adjacent second metal layers larger, thereby effectively reducing the crosstalk between the signal line segments on the two adjacent second metal layers, reducing the crosstalk between the signal lines on the two adjacent second metal layers, and making the crosstalk between the signal lines of the entire bus circuit lower.

[0059] The present application further schematically illustrates the bus circuit in the first optional case with the following examples. Assume that the bus circuit is arranged on a 1P13M chip, and the bus circuit includes 13 metal layers. When N is 4, the second metal layer for arranging W signal lines may include a metal layer M4 located at the 4th layer to a metal layer M10 located at the 10th layer. Assuming that W is a positive integer of 4, the W signal lines are divided into groups of 4 signal lines to obtain W / 4 sub-buses. The W / 4 sub-buses include, in sequence: signal lines N1-N4, signal lines N5-N10, ..., signal lines Ni-3-Ni, ..., signal lines Nw-3-Nw.

[0060] Among them, the signal line N1 includes two signal line segments connected by the driving unit D1. The signal line N2 includes two signal line segments connected by the driving unit D2. The signal line N3 includes two signal line segments connected by the driving unit D3. The signal line N4 includes two signal line segments connected by the driving unit D4... The signal line Ni-3 includes two signal line segments connected by the driving unit Di-3. The signal line Ni-2 includes two signal line segments connected by the driving unit Di-2. The signal line Ni-1 includes two signal line segments connected by the driving unit Di-1. The signal line Ni includes two signal line segments connected by the driving unit Di... The signal line Nw-3 includes two signal line segments connected by the driving unit Dw-3. The signal line Nw-2 includes two signal line segments connected by the driving unit Dw-2. The signal line Nw-1 includes two signal line segments connected by the driving unit Dw-1. The signal line Nw includes two signal line segments connected by the driving unit Dw.

[0061] like Figure 6As shown, the second metal layer M4 includes signal lines N1, signal lines N5, ..., signal lines Ni-3, ..., and signal lines Nw-3 arranged in parallel along the bus transmission direction. The second metal layer M8 includes signal lines N2, signal lines N6, ..., signal lines Ni-2, ..., and signal lines Nw-2 arranged in parallel along the bus transmission direction. The second metal layer M6 includes signal lines N3, signal lines N7, ..., signal lines Ni-1, ..., and signal lines Nw-1 arranged in parallel along the bus transmission direction. The second metal layer M10 includes signal lines N4, signal lines N8, ..., signal lines Ni, ..., and signal lines Nw arranged in parallel along the bus transmission direction. Among them, the projections of the signal lines (signal lines N1 and signal lines N2, signal lines N5 and signal lines N6, signal lines Ni-3 and signal lines Ni-2, signal lines Nw-3 and signal lines Nw-2) belonging to the same sub-bus on the second metal layer M4 and the second metal layer M8 overlap on the same horizontal plane. The projections of the signal lines (signal lines N3 and N4, signal lines N7 and N8, signal lines Ni-1 and Ni, signal lines Nw-1 and Nw) belonging to the same sub-bus on the second metal layer M6 and the second metal layer M10 overlap on the same horizontal plane. It should be noted that Figure 6 Only one signal line segment included in each signal line is shown for schematic illustration.

[0062] In the embodiment of the present application, the longitudinal coding method may include a longitudinal coding method within a sub-bus and a longitudinal coding method between sub-buses. Among them, the longitudinal coding method within a sub-bus may be used to encode multiple signal lines. For example, the longitudinal coding method within a sub-bus is used to obtain a sub-bus longitudinal coding circuit corresponding to each sub-bus. The sub-bus longitudinal coding circuit is as follows: Figure 5 and Figure 6 The sub-bus longitudinal coding circuit 001 shown in FIG. Moreover, the sub-bus longitudinal coding method is adopted, and the sub-bus longitudinal coding circuit 001 corresponding to each sub-bus is arranged in parallel in sequence to obtain the sub-bus longitudinal coding circuit, that is, the bus circuit. The bus circuit is as shown in FIG. Figure 5 or Figure 6 shown.

[0063] The second optional situation: using vertical coding and horizontal coding to lay out the signal lines to obtain a bus circuit.

[0064] The bus circuit includes a driving unit. Each of the W signal lines includes a plurality of signal line segments connected by at least one driving unit. It is not difficult to understand that one driving unit is used to connect two signal line segments. One signal line includes o+1 signal line segments connected by o driving units, where o is a positive integer.

[0065] Wherein, the multiple signal line segments of each signal line can be arranged in parallel on a second metal layer along the bus transmission direction. Alternatively, the multiple signal line segments of each signal line can be arranged in parallel on multiple second metal layers along the bus transmission direction. For example, W signal lines include signal lines N1-N4. The second metal layer for arranging the signal lines includes second metal layers M4, M6, M8, and M10. Wherein, the second metal layers M4, M6, M8, and M10 are stacked in sequence.

[0066] In an alternative case, Figure 4 and Figure 5 As shown, two signal line segments of signal line N1 201 are arranged in the second metal layer M4 1021; two signal line segments of signal line N3 203 are arranged in the second metal layer M6 1022; two signal line segments of signal line N2 202 are arranged in the second metal layer M8 1023; two signal line segments of signal line N4 204 are arranged in the second metal layer M10 1024.

[0067] Alternatively, if Figure 7 and 8 As shown, the two signal line segments of the signal line N1 201 are respectively arranged in the second metal layer M4 1021 and the second metal layer M6 1022; the two signal line segments of the signal line N3 203 are respectively arranged in the second metal layer M6 1022 and the second metal layer M8 1023; the two signal line segments of the signal line N2 202 are respectively arranged in the second metal layer M8 1023 and the second metal layer M10 1024; the two signal line segments of the signal line N4 are respectively arranged in the second metal layer M10 1024 and the second metal layer M4 1021.

[0068] It should be noted that the first driving unit and the second driving unit in the plurality of driving units corresponding to the W signal lines may be arranged as described above, that is, the projection of the first driving unit on the plane where the second driving unit is located is offset from the second driving unit.

[0069] Optionally, the W signal lines can be divided into at least two sub-buses, each sub-bus including at least one signal line. The end signal line segment of each signal line in the same sub-bus is arranged in parallel on different second metal layers along the bus transmission direction. The first signal line segment and the second signal line segment of each signal line in the W signal lines are arranged on two different second metal layers. The first signal line segment and the second signal line segment are connected to the same driving unit. The end signal line segment is a signal line segment in the signal line that is not connected to the driving unit at one end.

[0070] By way of example, it is assumed that 8 signal lines N1-N8 are divided into 2 sub-buses. The 2 sub-buses include a first sub-bus and a second sub-bus. The first sub-bus includes signal lines N1-N4. The second sub-bus includes signal lines N5-N8. Among them, the signal line N1 includes three signal line segments connected by two driving units D1 301. The signal line N2 includes three signal line segments connected by two driving units D2 302. The signal line N3 includes three signal line segments connected by two driving units D3 303. The signal line N4 includes three signal line segments connected by two driving units D4 304. The signal line N5 includes three signal line segments connected by two driving units D5 305. The signal line N6 includes three signal line segments connected by two driving units D6 306. The signal line N7 includes three signal line segments connected by two driving units D7 307. The signal line N8 includes three signal line segments connected by two driving units D8 308.

[0071] like Fig. 9 As shown, the three signal line segments of the signal line N1 201 and the signal line N5 205 are sequentially arranged in the second metal layer M4 1021, the second metal layer M8 1023 and the second metal layer M10 102. The three signal line segments of the signal line N2 202 and the signal line N6 206 are sequentially arranged in the second metal layer M8 1023, the second metal layer M4 1021 and the second metal layer M6 1022. The three signal line segments of the signal line N3 203 and the signal line N7 207 are sequentially arranged in the second metal layer M6 1022, the second metal layer M10 1024 and the second metal layer M4 1021. The three signal line segments of the signal line N4 204 and the signal line N8 208 are sequentially arranged in the second metal layer M10 1024, the second metal layer M6 1022 and the second metal layer M8 1023.

[0072] It is not difficult to understand that if Fig.10 As shown, it is assumed that a signal line N includes n+1 signal line segments J connected by n driving units D1-Dn. The delay time T of the signal line satisfies:

[0073]

[0074] Among them, T Ji is the delay time of the ith signal segment, T Diis the delay time of the ith driving unit. However, in actual applications, the characteristic parameters of multiple metal layers are usually not completely consistent. Therefore, if a signal line is only arranged on one metal layer, the difference in the characteristic parameters of multiple second metal layers makes the transmission performance of the W signal lines very different, resulting in a large transmission delay difference between the W signal lines. For example, the signal line Ni is arranged on the second metal layer M4 in parallel along the bus transmission direction, and the signal line Ni+1 is arranged on the second metal layer M10 in parallel along the bus transmission direction. The metal thickness of the second metal layer M4 is different from that of the second metal layer M10, resulting in a large difference in resistance between the parasitic resistance of the signal line Ni and the parasitic resistance of the signal line Ni+1, and a large transmission delay difference between the signal line Ni and the signal line Ni+1. As a result, at the receiving end of the bus, the signal transmitted by the signal line Ni and the signal transmitted by the signal line Ni+1 have a large difference in phase difference due to the transmission delay.

[0075] Based on this, a setting method in which multiple signal line segments of each signal line are distributed in multiple second metal layers is adopted. Compared with a setting method in which each signal line is distributed in one second metal layer, this avoids the large difference in transmission performance of the W signal lines due to differences in characteristic parameters of the multiple second metal layers, resulting in a large transmission delay difference between the W signal lines, thereby ensuring the consistency of the transmission delay of the W signal lines.

[0076] Further optionally, the W signal lines may be divided into groups of N signal lines to obtain □W / N□ sub-buses, and the number of the second metal layers is N, where N is a positive integer.

[0077] Wherein, when W / N is an integer, each second metal layer includes W / N end signal line segments arranged in parallel along the bus transmission direction, and the end signal line segments included in each second metal layer belong to different sub-buses. When W / N is a non-integer, each second metal layer includes at least □W / N□ end signal line segments arranged in parallel along the bus transmission direction, and each second metal layer in W%N second metal layers includes □W / N□+1 end signal line segments arranged in parallel along the bus transmission direction, and the end signal line segments included in each second metal layer belong to different sub-buses.

[0078] For an example, please refer to Figure 7 and Figure 8 In the bus circuit shown, the second metal layer M4 1021 includes the end signal line segments of the signal line N1 and the signal line N5. The second metal layer M6 1022 includes: the end signal line segments of the signal line N3 and the signal line N7. The second metal layer M8 1023 includes the end signal line segments of the signal line N2 and the signal line N6. The second metal layer M101024 includes the end signal line segments of the signal line N4 and the signal line N8.

[0079] As another example, assume that W is 8 and N is 3. W signal lines N1-N8 are divided into three sub-buses G1-G3. Sub-bus G1 includes signal lines N1-N3; sub-bus G2 includes signal lines N4-N6; sub-bus G3 includes signal lines N7-N8. And the second metal layer includes second metal layers M4, M6, and M8. The second metal layers M4, M6, and M8 are stacked in sequence.

[0080] like Fig.11 As shown, the second metal layer M4 1021 includes the end signal line segments of the signal line N1, the signal line N4 and the signal line N7. The second metal layer M6 1022 includes the end signal line segments of the signal line N2, the signal line N5 and the signal line N8. The second metal layer M8 1023 includes the end signal line segments of the signal line N3 and the signal line N6.

[0081] Furthermore, the three signal line segments of the signal line N1, the signal line N4 and the signal line N7 are sequentially distributed in the second metal layer M4 1021, the second metal layer M6 1022 and the second metal layer M8 1023. The three signal line segments of the signal line N2, the signal line N5 and the signal line N8 are sequentially distributed in the second metal layer M6 1022, the second metal layer M8 1023 and the second metal layer M4 1021. The three signal line segments of the signal line N3 and the signal line N6 are sequentially distributed in the second metal layer M8 1023, the second metal layer M4 1021 and the second metal layer M6 1022.

[0082] In some embodiments of the present application, the first signal line segment and the second signal line segment can be cyclically arranged in multiple second metal layers along the stacking direction of the multiple metal layers. The first target metal layer can be spaced apart from the second target metal layer by a target number of second metal layers. Among them, the first target metal layer is the second metal layer on which the first signal line segment is arranged. The second target metal layer is the second metal layer on which the second signal line segment is arranged. 0≤X<Y-2, X is the target number, and Y is the total number of second metal layers. It should be noted that the second metal layer spaced between the second metal layer on which the first signal line segment is arranged and the second metal layer on which the second signal line segment is arranged refers to: taking the second metal layer on which the first signal line segment is arranged as the starting point and the second metal layer on which the second signal line segment is arranged as the end point, and the second metal layer between the starting point and the end point in the stacking direction of the multiple metal layers.

[0083] For example, it is assumed that 8 signal lines N1-N8 are divided into 2 sub-buses. The first sub-bus includes signal lines N1-N4. The second sub-bus includes signal lines N5-N8. Each signal line includes n+1 signal line segments connected by n driving units. And the second metal layer includes second metal layers M4, M6, M8, and M10. The second metal layers M4, M6, M8, and M10 are stacked in sequence.

[0084] like Fig.12 As shown, when the target number X is 1, n+1 signal line segments of the signal line N1 and the signal line N5 are sequentially arranged on the second metal layer M4 1021, the second metal layer M8 1024, the second metal layer M4 1023, the second metal layer M8 1022, ...

[0085] The n+1 signal line segments of the signal line N3 and the signal line N7 are sequentially arranged on the second metal layer M6 1022 , the second metal layer M10 1021 , the second metal layer M6 1024 , the second metal layer M10 1024 . . . . .

[0086] The n+1 signal line segments of the signal line N2 and the signal line N6 are sequentially arranged on the second metal layer M8 1023 , the second metal layer M4 1022 , the second metal layer M8 1021 , the second metal layer M4 1024 . . . .

[0087] The n+1 signal line segments of the signal line N3 and the signal line N7 are sequentially arranged on the second metal layer M101024, the second metal layer M61024, the second metal layer M101022, the second metal layer M61021, . . . . .

[0088] Further optionally, the target number can be 0. When the first signal line segment is not arranged in the lowest layer among the plurality of second metal layers, the second target metal layer is adjacent to the first target metal layer, and the second target metal layer is close to the lowest layer. When the first signal line segment is arranged in the lowest layer, the second signal line segment is arranged in the top layer among the plurality of second metal layers.

[0089] As an example, Fig.13 As shown, the signal line Ni includes n+1 signal line segments connected by n driving units Di. The n+1 signal line segments of the signal line N1 are sequentially arranged on the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024, the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024...

[0090] For example, Fig.14As shown, when the target number X is 0, for the first sub-bus including signal lines N1-N4, the n+1 signal line segments of the signal line N1 are sequentially arranged in the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024, the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024.... The three signal line segments of the signal line N2 are sequentially arranged in the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102.... The n+1 signal line segments of the signal line N3 are sequentially arranged in the second metal layer M6 1022, the second metal layer M8 1024 and the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 1022, the second metal layer M8 1024, the second metal layer M10 1021, the second metal layer M4 1022.... The n+1 signal line segments of the signal line N4 are sequentially arranged in the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024, the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024....

[0091] like Fig.15 As shown, in Fig.14On the basis of the first sub-bus including signal lines N1-N4 and the second sub-bus including signal lines N5-N8. The n+1 signal line segments of the signal line N5 are sequentially arranged in the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024, the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024... The n+1 signal line segments of the signal line N6 are sequentially arranged in the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102... The n+1 signal line segments of the signal line N7 are sequentially arranged in the second metal layer M6 1022, the second metal layer M8 1024, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 1022, the second metal layer M8 1024, the second metal layer M10 1021, the second metal layer M4 1022.... The n+1 signal line segments of the signal line N8 are sequentially arranged in the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024, the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024....

[0092] It can be seen from the above that when the target number X is 0, the signal lines N1-N4 and the signal lines N5-N8 are respectively arranged in sequence at M4-M8-M6-M10, M8-M4-M10-M6, M6-M10-M8-M4, M10-M6-M4-M8, M4-M8-M6-M10, M8-M4-M10-M6, M6-M10-M8-M4, M10-M6-M4-M8, .... It is not difficult to understand that multiple signal line segments in any signal line can be evenly distributed in multiple second metal layers.

[0093] In this way, since the end signal line segments of each signal line are distributed in different second metal layers, and the two signal line segments connected to the same driving unit in each signal line are cyclically arranged in two adjacent second metal layers along the stacking direction of multiple metal layers. Therefore, the multiple signal line segments of each signal line Ni in the W signal lines can be evenly distributed in multiple second metal layers. Therefore, even if the characteristic parameters of multiple second metals are usually not completely consistent in actual applications, since the multiple signal line segments of each signal line can be evenly distributed in multiple second metal layers. Therefore, the transmission performance of each signal line is almost the same, which makes the transmission performance of the W signal lines almost non-different. Therefore, the transmission delay between the W signal lines is almost the same, which effectively guarantees the consistency of the transmission delay of the W signal lines.

[0094] In some embodiments of the present application, a bus circuit is further provided. The bus on the bus circuit is divided into a plurality of sub-buses in the bus width expansion direction. Each sub-bus is divided into a plurality of bus segments in the bus transmission direction. The a-th bus segment along the bus transmission direction of each sub-bus includes: the a-th signal line segment among the plurality of signal line segments arranged along the bus transmission direction in each signal line of the sub-bus.

[0095] In any bus segment of each sub-bus, the signal lines of the sub-bus are distributed on multiple metal layers spaced apart in one of multiple preset coding modes. The distribution of multiple preset coding modes on all bus segments enables each signal line of the bus to have a balanced delay. The coding refers to the distribution of the signal lines in the bus segment on the metal layer. Each signal line having a balanced delay means that the delay of each signal line is approximately equal.

[0096] Further optionally, the bus circuit includes: a plurality of metal layers. The plurality of metal layers at least include: a first metal layer and a plurality of second metal layers. The first metal layer and the second metal layer are arranged in an alternating manner. In any section of each sub-bus, the signal lines of the sub-bus are distributed in a plurality of second metal layers in one of a plurality of preset coding modes. On the second metal layer, the projections of the signal lines on two adjacent second metal layers on the same horizontal plane do not overlap.

[0097] For example, Fig. 9 As shown, the first sub-bus and the second sub-bus are divided into three bus segments in the bus transmission direction. The first bus segment S11 of the first sub-bus includes: the first signal line segment from signal line N1 201 to signal line N4 204; the second bus segment S12 of the first sub-bus includes: the second signal line segment from signal line N1 201 to signal line N4 204; the third bus segment S13 of the first sub-bus includes: the third signal line segment from signal line N1 201 to signal line N4 204.

[0098] The first bus segment S21 of the second sub-bus includes: the first signal line segment from signal line N5 205 to signal line N8 208; the second bus segment S22 of the second sub-bus includes: the second signal line segment from signal line N5 205 to signal line N8 208; the third bus segment S23 of the second sub-bus includes: the third signal line segment from signal line N5 205 to signal line N8 208.

[0099] Among them, the first signal line segment from signal line N1 201 to signal line N4 204 in the first bus segment S11 of the first sub-bus, the second signal line segment from signal line N1 201 to signal line N4 204 in the second bus segment S12 of the first sub-bus, and the third signal line segment from signal line N1 201 to signal line N4 204 in the third bus segment S13 of the first sub-bus are distributed on the second metal layers M4, M6, M8, and M10 arranged at intervals in one of a plurality of preset encoding methods.

[0100] The first signal line segment from signal line N5 205 to signal line N8 208 in the first bus segment S21 of the second sub-bus, the second signal line segment from signal line N5 205 to signal line N8 208 in the second bus segment S22 of the second sub-bus, and the third signal line segment from signal line N5 205 to signal line N8 208 in the third bus segment S23 of the second sub-bus are distributed on the second metal layers M4, M6, M8, and M10 arranged at intervals in one of a plurality of preset encoding methods.

[0101] In an optional implementation, at the same position in the bus transmission direction, the signal lines in the bus segments of multiple sub-buses are distributed on multiple spaced metal layers in the same coding manner.

[0102] Optionally, the same position in the bus transmission direction may refer to the position of the bus segments with the same arrangement order in the multiple bus segments arranged along the bus transmission direction of each sub-bus. Based on this, at the same position in the bus transmission direction, the signal lines in the bus segments of the multiple sub-buses are distributed on multiple spaced metal layers in the same coding manner, which may refer to: among the multiple bus segments arranged along the bus transmission direction of the multiple sub-buses, the bus segments of each sub-bus with the same arrangement order are distributed on multiple spaced metal layers in the same coding manner.

[0103] As in the above example, the signal lines in the first bus segment S11 of the first sub-bus and the first bus segment S21 of the second sub-bus are arranged in the second metal layer M4, M8, M6, and M10 in sequence. The signal lines in the second bus segment S12 of the first sub-bus and the second bus segment S22 of the second sub-bus are arranged in the second metal layer M8, M4, M10, and M6 in sequence. The signal lines in the third bus segment S13 of the first sub-bus and the third bus segment S23 of the second sub-bus are arranged in the second metal layer M10, M6, M4, and M8 in sequence. In this way, the encoding method of each sub-bus in the bus circuit is the same, which reduces the encoding complexity of the bus circuit.

[0104] Further optionally, for each sub-bus, the encoding method of the bus segment can be repeated periodically along the bus transmission direction.

[0105] The encoding method may define an encoding cycle. For each sub-bus, the encoding method at the bus end may be repeated along the bus transmission direction according to the encoding cycle. For example, Fig.14 As shown, one sub-bus includes signal lines N1 to N4.

[0106] In the first encoding cycle T1, the signal lines N1 to N4 in the first bus segment of the sub-bus are sequentially distributed in the second metal layer M4, M8, M6, and M10. The signal lines N1 to N4 in the second bus segment of the sub-bus are sequentially distributed in the second metal layer M6, M10, M8, and M4. The signal lines N1 to N4 in the third bus segment of the sub-bus are sequentially distributed in the second metal layer M8, M4, M10, and M6. The signal lines N1 to N4 in the fourth bus segment of the sub-bus are sequentially distributed in the second metal layer M10, M6, M4, and M8.

[0107] In the second encoding cycle T2, the signal lines N1 to N4 in the 5th bus segment of the sub-bus are sequentially distributed in the second metal layer M4, M8, M6, and M10. The signal lines N1 to N4 in the 6th bus segment of the sub-bus are sequentially distributed in the second metal layer M6, M10, M8, and M4. The signal lines N1 to N4 in the 7th bus segment of the sub-bus are sequentially distributed in the second metal layer M8, M4, M10, and M6. The signal lines N1 to N4 in the 8th bus segment of the sub-bus are sequentially distributed in the second metal layer M10, M6, M4, and M8.

[0108] In some embodiments of the present application, in each cycle of the encoding method, the number of signal line segments distributed on the same metal layer for each signal line of the bus is the same. Further, optionally, in each cycle, each bus segment of the same sub-bus is distributed on multiple metal layers spaced apart in different encoding methods. For example, different encoding methods may refer to different distribution orders of signal lines on metal layers. For example, Fig.14 As shown, the encoding modes corresponding to the four bus segments in the first encoding period T1 are distributed in different orders, namely M4-M8-M6-M10, M6-M10-M8-M4, M8-M4-M10-M6, and M10-M6-M4-M8.

[0109] In an optional implementation, the bus circuit further includes: a driving unit. In a plurality of bus segments arranged in a bus transmission direction, the same signal line in each two adjacent bus segments is connected by a driving unit, and the same signal line is connected to a plurality of driving units.

[0110] The projection of the first driving unit on the plane where the second driving unit is located is misaligned with the second driving unit. The metal layer where the signal line connected to the first driving unit is located and the metal layer between the metal layer where the signal line connected to the second driving unit is located do not have signal lines arranged thereon. For example, a signal line segment connected to the first driving unit and a signal line segment connected to the second driving unit are arranged on two adjacent second metal layers.

[0111] The present application further schematically illustrates the bus circuit in the second optional case with the following example. Assume that the bus circuit is arranged on a 1P13M chip, and the bus circuit includes 13 metal layers. When N is 4, the second metal layer for arranging W signal lines may include a metal layer M4 located at the 4th layer to a metal layer M10 located at the 10th layer. Assuming that W is a positive integer of 4, the W signal lines are divided into groups of 4 signal lines to obtain W / 4 sub-buses. The W / 4 sub-buses include, in sequence: signal lines N1-N4, signal lines N5-N10, ..., signal lines Ni-3-Ni, ..., signal lines Nw-3-Nw.

[0112] Each signal line Ni includes n+1 signal line segments Jy connected by n driving units Dix, 1≤i≤W, 1≤x≤n, 1≤y≤n+1.

[0113] like Fig.16As shown, the n+1 signal line segments of the signal line N1, the signal line Ni-3 and the signal line Nw-3 are sequentially arranged in the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024, the second metal layer M4 1021, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1024.... The n+1 signal line segments of the signal line N2, the signal line Ni-2 and the signal line Nw-2 are sequentially arranged in the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102, the second metal layer M8 1023, the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 102.... The n+1 signal line segments of the signal line N3, the signal line Ni-1 and the signal line Nw-1 are sequentially arranged in the second metal layer M6 1022, the second metal layer M8 1024 and the second metal layer M10 1021, the second metal layer M4 1022, the second metal layer M6 1022, the second metal layer M8 1024, the second metal layer M10 1021, the second metal layer M4 1022.... The n+1 signal line segments of the signal line N4, the signal line Ni and the signal line Nw are sequentially arranged in the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024, the second metal layer M10 1024, the second metal layer M4 1022, the second metal layer M6 1023, the second metal layer M8 1024....

[0114] The projections of the signal lines (signal line N1 and signal line N2, signal line N5 and signal line N6, signal line Ni-3 and signal line Ni-2, signal line Nw-3 and signal line Nw-2) belonging to the same sub-bus on the second metal layer M4 and the second metal layer M8 overlap on the same horizontal plane. The projections of the signal lines (signal line N3 and signal line N4, signal line N7 and signal line N8, signal line Ni-1 and signal line Ni, signal line Nw-1 and signal line Nw) belonging to the same sub-bus on the second metal layer M6 and the second metal layer M10 overlap on the same horizontal plane.

[0115] In the embodiment of the present application, the horizontal coding method may include a horizontal coding method within a sub-bus and a horizontal coding method between sub-buses. On the basis of using the vertical coding method to encode the bus, a horizontal coding method within a sub-bus may be used to encode the signal line segments connecting different drive units in the same signal line. For example, a sub-bus horizontal coding method is used to obtain a sub-bus horizontal coding circuit corresponding to each sub-bus. The sub-bus horizontal coding circuit is as follows: Fig.16The sub-bus horizontal coding circuit 002 shown in FIG. Moreover, the sub-bus horizontal coding method is adopted, and multiple sub-bus horizontal coding circuits 002 corresponding to each sub-bus are arranged in sequence to obtain the sub-bus horizontal coding circuit, that is, the bus circuit. The bus circuit is as shown in FIG. Figures 7 to 16 shown.

[0116] like Figures 7 to 16 As shown, an embodiment of the present application provides a bus circuit, in which the bus is divided into a plurality of sub-buses in the bus width expansion direction, and each of the sub-buses is divided into a plurality of bus segments in the bus transmission direction (for example, Figure 7 bus segment 002 in ).

[0117] In any bus segment of each sub-bus, the signal lines of the sub-bus are distributed on multiple spaced metal layers in one of multiple preset coding modes. Coding here refers to the distribution of the signal lines in the bus segment on the metal layer.

[0118] exist Figure 7-16 In the example, the length of each bus segment is substantially the same; at the same position in the bus transmission direction, the signal lines in the bus segments of multiple sub-buses are distributed on multiple spaced metal layers in the same encoding method; for each sub-bus, the encoding method of the bus segments is periodically repeated along the bus transmission direction.

[0119] Those skilled in the art will understand that the encoding method of the bus segment changes or repeats in the vertical direction (bus bit width direction) and the horizontal direction (bus transmission direction), so that the routing of each signal line in the bus is evenly distributed on metal layers with different widths and thicknesses, so that each signal line has a balanced delay.

[0120] In other embodiments, the length of the bus segment may vary in the horizontal or vertical direction, and the spatial distribution of the encoding method is not limited by the above embodiments, as long as the distribution on all bus segments allows each signal line of the bus to have a balanced delay.

[0121] In summary, for a bus with a bit width of W including W signal lines, the bus circuit provided by the embodiment of the present application includes multiple metal layers. The multiple metal layers include at least: a first metal layer and multiple second metal layers, and the first metal layer and the second metal layer are arranged in an alternating and stacked manner. W signal lines are arranged in parallel in the multiple second metal layers along the bus transmission direction, and W is a positive integer greater than 2. In the bus circuit, since the multiple second metal layers are separated by a first metal layer, there is a large distance between two adjacent metal layers where the signal lines are arranged, so that the crosstalk between the signal lines on the two adjacent second metal layers can be effectively reduced, thereby making the crosstalk between the signal lines of the entire bus circuit lower.

[0122] In the embodiment of the present application, a multi-layer metal wire wiring method is used to encode the bus to obtain the bus circuit provided in the embodiment of the present application, for example Figures 1 to 16 The bus circuit is also called a bus encoding circuit, which can reduce the crosstalk between signal lines to a certain extent and ensure the consistency of the transmission delay of W signal lines in the bus.

[0123] Please refer to Fig.17 , which shows a flow chart of a bus circuit wiring method provided in an embodiment of the present application. A bus with a bit width of W includes W signal lines, where W is a positive integer greater than 2, and the bus circuit includes: multiple metal layers, the multiple metal layers include at least a first metal layer and multiple second metal layers, and the first metal layers and the second metal layers are arranged in an alternating manner. The bus circuit can be the bus circuit provided in an embodiment of the present application, for example Figures 1 to 16 The bus circuit is shown.

[0124] like Fig.17 As shown, the method includes:

[0125] Step 1701: at least one signal line among W signal lines is arranged in parallel on multiple second metal layers along a bus transmission direction, so that the W signal lines are arranged in parallel on multiple second metal layers along the bus transmission direction.

[0126] In some embodiments of the present application, a multi-layer metal wiring method can be used to encode the bus in a vertical encoding manner to obtain the bus provided in the embodiments of the present application. Figures 1 to 6 Optionally, the process of encoding the bus in a longitudinal encoding manner may include the following steps a1 to a2.

[0127] In step a1, W signal lines are divided into at least two sub-buses, each sub-bus including at least one signal line.

[0128] In step a2, signal lines in the same sub-bus are arranged in parallel on a plurality of second metal layers along a bus transmission direction, so that the signal lines included in each second metal layer belong to different sub-buses.

[0129] In an optional implementation, the process of dividing W signal lines into at least two sub-buses may include: dividing the W signal lines into groups of N signal lines to obtain □W / N□ sub-buses, where the number of the second metal layers is N, and N is a positive integer.

[0130] The signal lines in the same sub-bus are arranged in parallel on multiple second metal layers along the bus transmission direction, including: when W / N is an integer, W / N signal lines are arranged in parallel on each of the N second metal layers along the bus transmission direction, and the W / N signal lines belong to different sub-buses;

[0131] When W / N is a non-integer, □W / N□+1 signal lines are arranged in parallel along the bus transmission direction on (NW%N) of the N second metal layers, and □W / N□ signal lines are arranged in parallel along the bus transmission direction on the remaining second metal layers among the N second metal layers, and the W / N signal lines belong to different sub-buses.

[0132] Optionally, projections of signal lines belonging to the same sub-bus included in at least two of the N second metal layers overlap on the same horizontal plane.

[0133] In the embodiment of the present application, the longitudinal coding method may include a longitudinal coding method within a sub-bus and a longitudinal coding method between sub-buses. Among them, the longitudinal coding method within a sub-bus may be adopted to arrange the signal lines within the same sub-bus in each sub-bus in parallel along the bus transmission direction on multiple second metal layers. For example, the longitudinal coding method within the sub-bus is adopted to obtain a sub-bus longitudinal coding circuit corresponding to each sub-bus. The sub-bus longitudinal coding circuit is as follows: Figure 5 and Figure 6 The sub-bus longitudinal coding circuit 001 shown in FIG. Moreover, the sub-bus longitudinal coding method is adopted, and the sub-bus longitudinal coding circuit 001 corresponding to each sub-bus is arranged in parallel in sequence to obtain the sub-bus longitudinal coding circuit, that is, the bus circuit. The bus circuit is as shown in FIG. Figure 5 or Figure 6 shown.

[0134] In some embodiments of the present application, a multi-layer metal wiring method can be used to encode the bus in a spatial encoding manner to obtain the bus provided in the embodiments of the present application. Figures 7 to 16 The bus circuit shown in FIG. 1 includes a longitudinal coding method and a transverse coding method. Optionally, the process of encoding the bus using the spatial coding method may include the following steps b1 to b2.

[0135] Optionally, the bus circuit also includes a driving unit, each of the signal lines includes a plurality of signal line segments connected by at least one driving unit, a projection of a first driving unit among the plurality of driving units on a plane where a second driving unit is located is offset from the second driving unit, and a signal line segment connected to the first driving unit and a signal line segment connected to the second driving unit are arranged in two adjacent second metal layers.

[0136] In step b1, at least one signal line segment of at least one of the W signal lines is arranged parallel to the bus transmission direction on multiple second metal layers, so that multiple signal line segments of each signal line of the W signal lines are arranged parallel to the bus transmission direction on multiple second metal layers.

[0137] In an optional implementation, before step b1, the method further includes: dividing the W signal lines into at least two sub-buses, each of the sub-buses including at least one signal line.

[0138] The step of arranging at least one signal line segment of at least one signal line among the W signal lines in parallel along the bus transmission direction on the plurality of second metal layers respectively includes: arranging at least one signal line segment of at least one signal line among the W signal lines in parallel along the bus transmission direction on the plurality of second metal layers respectively according to a target rule,

[0139] Among them, the target rules include: the end signal line segments of the signal lines of the same sub-bus are arranged in parallel on different second metal layers along the bus transmission direction, the first signal line segment and the second signal line segment of each signal line are arranged on two different second metal layers, the first signal line segment and the second signal line segment are connected to the same driving unit, and the end signal line segment is a signal line segment at one end of the signal line connected to the driving unit.

[0140] Optionally, the process of dividing the W signal lines into at least two sub-buses may include: dividing the W signal lines into groups of N signal lines to obtain □W / N□ sub-buses, the number of the second metal layers is N, and N is a positive integer. Based on this, the target rule also includes: when W / N is an integer, each of the second metal layers includes W / N end signal line segments arranged in parallel along the bus transmission direction;

[0141] When W / N is a non-integer, each of the second metal layers includes at least □W / N□ end signal line segments arranged in parallel along the bus transmission direction, and each of the W%N second metal layers includes □W / N□+1 end signal line segments arranged in parallel along the bus transmission direction.

[0142] Optionally, the target rule further includes: when the first signal line segment is arranged in the lowest layer of the plurality of second metal layers, the second target metal layer is adjacent to the first target metal layer, and the second target metal layer is close to the lowest layer, the first target metal layer is the second metal layer arranged with the first signal line segment, and the second target metal layer is the second metal layer arranged with the second signal line segment;

[0143] When the first signal line segment is arranged at the lowest layer, the second signal line segment is arranged at the top layer of the plurality of second metal layers.

[0144] In an embodiment of the present application, the horizontal coding method may include a horizontal coding method within a sub-bus and a horizontal coding method between sub-buses. On the basis of encoding the bus by the vertical coding method, a horizontal coding method within a sub-bus may be adopted to arrange at least one signal line segment of at least one of the W signal lines in parallel along the bus transmission direction on multiple second metal layers. For example, a sub-bus horizontal coding method is adopted to obtain a sub-bus horizontal coding circuit corresponding to each sub-bus. The sub-bus horizontal coding circuit is a sub-bus horizontal coding circuit 002 as shown in 16. In addition, a horizontal coding method is adopted between sub-buses to arrange multiple sub-bus horizontal coding circuits 002 corresponding to each sub-bus in sequence to obtain a horizontal coding circuit between sub-buses, that is, a bus circuit. The bus circuit is as shown in FIG. Figures 7 to 16 shown.

[0145] It should be noted that the specific execution process of each step in the embodiment of the method can refer to the above example, and this embodiment will not go into details.

[0146] In summary, for a bus with a bit width of W including W signal lines, the bus circuit provided by the embodiment of the present application includes multiple metal layers. The multiple metal layers include at least: a first metal layer and multiple second metal layers, and the first metal layer and the second metal layer are arranged in an alternating and stacked manner. W signal lines are arranged in parallel in the multiple second metal layers along the bus transmission direction, and W is a positive integer greater than 2. In the bus circuit, since the multiple second metal layers are separated by a first metal layer, there is a large distance between two adjacent metal layers where the signal lines are arranged, so that the crosstalk between the signal lines on the two adjacent second metal layers can be effectively reduced, thereby making the crosstalk between the signal lines of the entire bus circuit lower.

[0147] The present application also provides a chip, which includes the bus circuit provided in the present application. For example, the chip includes Figures 1 to 16 Any of the bus circuits shown.

[0148] Fig.18 1 is a block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device 1800 may be a mobile phone, a computer, a digital broadcast terminal, a message transceiver device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc. The electronic device 1800 also includes a chip provided in an embodiment of the present application.

[0149] Reference Fig.18, the electronic device 1800 may include one or more of the following components: a processing component 1802 , a memory 1804 , a power component 1806 , a multimedia component 1808 , an audio component 1810 , an input / output (I / O) interface 1812 , a sensor component 1814 , and a communication component 1816 .

[0150] The processing component 1802 generally controls the overall operation of the electronic device 1800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1802 may include one or more processors 1820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1802 may include one or more modules to facilitate the interaction between the processing component 1802 and other components. For example, the processing component 1802 may include a multimedia module to facilitate the interaction between the multimedia component 1808 and the processing component 1802.

[0151] The memory 1804 is configured to store various types of data to support operations on the electronic device 1800. Examples of such data include instructions for any application or method operating on the electronic device 1800, contact data, phone book data, messages, pictures, videos, etc. The memory 1804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0152] The power supply component 1806 provides power to the various components of the electronic device 1800. The power supply component 1806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1800.

[0153] The multimedia component 1808 includes a screen that provides an output interface between the electronic device 1800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1808 includes a front camera and / or a rear camera. When the electronic device 1800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0154] The audio component 1810 is configured to output and / or input audio signals. For example, the audio component 1810 includes a microphone (MIC), and when the electronic device 1800 is in an operation mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1804 or sent via the communication component 1816. In some embodiments, the audio component 1810 also includes a speaker for outputting audio signals.

[0155] I / O interface 1812 provides an interface between processing component 1802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0156] The sensor assembly 1814 includes one or more sensors for providing various aspects of status assessment for the electronic device 1800. For example, the sensor assembly 1814 can detect the open / closed state of the electronic device 1800, the relative positioning of components, such as the display and keypad of the electronic device 1800, and the sensor assembly 1814 can also detect the position change of the electronic device 1800 or a component of the electronic device 1800, the presence or absence of user contact with the electronic device 1800, the orientation or acceleration / deceleration of the electronic device 1800, and the temperature change of the electronic device 1800. The sensor assembly 1814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0157] The communication component 1816 is configured to facilitate wired or wireless communication between the electronic device 1800 and other devices. The electronic device 1800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0158] In an exemplary embodiment, the electronic device 1800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processing circuits (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0159] In this embodiment, the chip also includes a bus circuit provided in the embodiment of the present application.

[0160] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0161] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0162] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0163] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0164] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0165] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0166] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0167] The above is a detailed introduction to a current source module and device, a chip and a storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A bus circuit, characterized in that: The bus with a bit width of W includes: W signal lines, where W is a positive integer greater than 2, and the bus circuit includes: A plurality of metal layers, the plurality of metal layers at least comprising: a first metal layer and a plurality of second metal layers, the first metal layer and the second metal layer being alternately stacked; The W signal lines are arranged in parallel on the plurality of second metal layers along a bus transmission direction.

2. The bus circuit according to claim 1, characterized in that: The W signal lines are divided into at least two sub-buses, each of the sub-buses includes at least one signal line, and the signal lines included in each of the plurality of second metal layers belong to different sub-buses.

3. The bus circuit according to claim 2, characterized in that: The W signal lines are divided into groups of N signal lines to obtain W / N sub-buses, the number of the second metal layers is N, and N is a positive integer; When W / N is an integer, each of the second metal layers includes W / N signal lines arranged in parallel along the bus transmission direction; When W / N is a non-integer, each of the second metal layers includes at least W / N signal lines arranged in parallel along the bus transmission direction, and each of the W%N second metal layers includes W / N+1 signal lines arranged in parallel along the bus transmission direction.

4. The bus circuit according to claim 3, characterized in that: The projections of the signal lines belonging to the same sub-bus included in at least two of the N second metal layers overlap on the same horizontal plane.

5. The bus circuit according to claim 1, characterized in that: The bus circuit further includes: a driving unit, Each of the signal lines includes a plurality of signal line segments connected by at least one driving unit, and the plurality of signal line segments of each signal line are respectively arranged in parallel on a plurality of the second metal layers along a bus transmission direction, a projection of a first driving unit among the plurality of driving units on a plane where a second driving unit is located is offset from the second driving unit, and a signal line segment connected to the first driving unit and a signal line segment connected to the second driving unit are arranged on two adjacent second metal layers.

6. The bus circuit according to claim 5, characterized in that: The W signal lines are divided into at least two sub-buses, each of which includes at least one signal line. The end signal line segments of the signal lines of the same sub-bus are arranged in parallel on different second metal layers along the bus transmission direction, the first signal line segment and the second signal line segment of each signal line are arranged on two different second metal layers, the first signal line segment and the second signal line segment are connected to the same driving unit, and the end signal line segment is a signal line segment at one end of the signal line that is not connected to the driving unit.

7. The bus circuit according to claim 6, characterized in that: The W signal lines are divided into groups of N signal lines to obtain W / N sub-buses, the number of the second metal layers is N, and N is a positive integer; When W / N is an integer, each of the second metal layers includes W / N end signal line segments arranged in parallel along the bus transmission direction; When W / N is a non-integer, each of the second metal layers includes at least W / N end signal line segments arranged in parallel along the bus transmission direction, and each of the W%N second metal layers includes W / N+1 end signal line segments arranged in parallel along the bus transmission direction.

8. The bus circuit according to claim 6 or 7, characterized in that: When the first signal line segment is not arranged in the lowest layer of the plurality of second metal layers, the second target metal layer is adjacent to the first target metal layer, and the second target metal layer is close to the lowest layer, the first target metal layer is the second metal layer arranged with the first signal line segment, and the second target metal layer is the second metal layer arranged with the second signal line segment; When the first signal line segment is arranged at the lowest layer, the second signal line segment is arranged at the top layer of the plurality of second metal layers.

9. A bus circuit wiring method, characterized in that: A bus with a bit width of W includes W signal lines, where W is a positive integer greater than 2, and the bus circuit includes: a plurality of metal layers, where the plurality of metal layers include at least a first metal layer and a plurality of second metal layers, and the first metal layers and the second metal layers are arranged in an alternating and stacked manner; the method includes: At least one signal line among the W signal lines is arranged in parallel along a bus transmission direction on each of the plurality of second metal layers, so that the W signal lines are arranged in parallel along the bus transmission direction on the plurality of second metal layers.

10. A bus circuit, characterized in that: The bus is divided into a plurality of sub-buses in the bus width expansion direction, and each of the sub-buses is divided into a plurality of bus segments in the bus transmission direction; In any bus segment of each of the sub-buses, the signal lines of the sub-buses are distributed on a plurality of spaced metal layers in one of a plurality of preset coding modes; The distribution of the preset multiple encoding modes on all the bus segments enables each signal line of the bus to have a balanced delay.

11. The bus circuit according to claim 10, characterized in that: At the same position in the bus transmission direction, the signal lines in the bus segments of the plurality of sub-buses are distributed on a plurality of spaced-apart metal layers in the same coding manner.

12. The bus circuit according to claim 10 or 11, characterized in that: For each sub-bus, the encoding method of the bus segment is repeated periodically along the bus transmission direction.

13. The bus circuit according to claim 12, characterized in that: In each cycle of the encoding mode, each signal line of the bus has the same number of signal line segments distributed on the same metal layer.

14. The bus circuit according to claim 10, characterized in that: The bus circuit further includes: a driving unit, In the plurality of bus segments arranged along the bus transmission direction, the same signal line in every two adjacent bus segments is connected by a driving unit, and in the plurality of driving units connected to the same signal line, a projection of a first driving unit on a plane where a second driving unit is located is offset from that of the second driving unit, and a metal layer between a metal layer where the signal line connected to the first driving unit is located and a metal layer where the signal line connected to the second driving unit is located has no signal line arranged thereon.

15. The bus circuit according to claim 10, characterized in that: The bus circuit comprises: a plurality of metal layers, the plurality of metal layers at least comprising: a first metal layer and a plurality of second metal layers, the first metal layer and the second metal layer being arranged in an alternating and stacked manner; In any section of each of the sub-buses, the signal lines of the sub-buses are distributed on a plurality of the second metal layers in one of a plurality of preset encoding modes, and projections of the signal lines on two adjacent second metal layers on the same horizontal plane do not overlap.

16. A chip, characterized in that: The chip includes the bus circuit described in any one of claims 1 to 8, or the bus circuit described in any one of claims 10 to 15.

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