Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory blocks, and each memory block comprises a plurality of memory strings; each memory string comprises an upper selection tube, a memory unit and a lower selection tube which are sequentially connected in series between a bit line and a source line; wherein all the lower selection tubes in the same storage block form a lower selection tube set; the peripheral circuit is configured to: perform a program operation on memory cells in the memory block; and performing erasing operation on at least part of the lower selection tubes in the lower selection tube set.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and an operating method thereof, and a memory system. Background Art

[0002] With the continuous development of semiconductor technology, current memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, by arranging storage units three-dimensionally on a substrate to improve integration density.

[0003] Therefore, there is still a need to improve the memory and the operation method thereof to increase the integration density thereof. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, and a memory system.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] The present disclosure provides a memory, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory blocks, each of the memory blocks comprises a plurality of memory strings; each of the memory strings comprises an upper selection tube, a memory cell and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set;

[0007] The peripheral circuit is configured as:

[0008] Performing a programming operation on the storage cells in the storage block;

[0009] An erasing operation is performed on at least part of the lower selection tubes in the lower selection tube set.

[0010] In some embodiments, in the same storage block, the upper selection tubes in different storage strings are electrically isolated from each other and the multiple lower selection tubes with the same distance from the source line are connected to each other; the lower selection tube set includes multiple first lower selection tube sets, each of the first lower selection tube sets includes multiple lower selection tubes with the same distance from the source line and the multiple lower selection tubes have different threshold voltages;

[0011] The peripheral circuit is specifically configured as follows:

[0012] Based on the fact that a plurality of lower selection tubes in the first lower selection tube set have different threshold voltages, a programming operation and a verification operation are performed on the storage cells in the storage block.

[0013] In some embodiments, the peripheral circuit is specifically configured as follows:

[0014] performing an erasing operation on all lower selection tubes in the first lower selection tube set;

[0015] Performing a programming operation on at least one lower selection tube in the first lower selection tube set that is closest to the source line, so that all lower selection tubes in the first lower selection tube set that is closest to the source line have a preset threshold voltage;

[0016] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0017] In some embodiments, the peripheral circuit is specifically configured as follows:

[0018] Performing an erasing operation on all lower selection tubes in the first lower selection tube set, so that at least one lower selection tube in the first lower selection tube set that is closest to the source line has a preset threshold voltage;

[0019] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0020] In some embodiments, the peripheral circuit is specifically configured as follows:

[0021] performing a single-level cell (SLC) programming operation on the remaining lower selection tubes in the first lower selection tube set;

[0022] The lower selection tubes with a preset threshold voltage in the first lower selection tube set are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

[0023] In some embodiments, the lower selection tube set further includes at least one second lower selection tube set located between the source line and the first lower selection tube set, and each of the second lower selection tube sets includes a plurality of lower selection tubes at the same distance from the source line;

[0024] In a programming operation on a memory cell in the memory block, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0025] In some embodiments, the peripheral circuit is specifically configured as follows:

[0026] performing an erasing operation on all lower selection tubes in the second lower selection tube set;

[0027] performing a programming operation on all the lower selection tubes in the second lower selection tube set;

[0028] During the programming operation on the remaining lower selection tubes in the first lower selection tube set, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0029] In some embodiments, the lower selection tube set also includes multiple first dummy unit sets, each of the first dummy unit sets includes multiple first dummy units with the same distance as the source lines, and the first dummy unit sets are located between different first lower selection tube sets or between the first lower selection tube set and the second lower selection tube set.

[0030] In some embodiments, the peripheral circuit is specifically configured as follows:

[0031] An erasing operation is performed on all first dummy cells in the first dummy cell set.

[0032] In some embodiments, when the first dummy unit set is located between different first lower selection tube sets, the peripheral circuit is specifically configured as follows:

[0033] Performing a programming operation on all first dummy cells in the first dummy cell set so that the first dummy cells in the first dummy cell set have a target threshold voltage;

[0034] In the case where the first dummy unit set is located between the first lower selection tube set and the second lower selection tube set, the peripheral circuit is specifically configured as follows:

[0035] A programming operation is performed on all the first dummy cells in the first dummy cell set, so that all the first dummy cells in the first dummy cell set have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set with the preset threshold voltage are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erase operation.

[0036] In some embodiments, the memory string further includes a plurality of second dummy cells located between the memory cell and the lower selection tube, the memory block includes a plurality of second dummy cell sets, and each of the second dummy cell sets includes a plurality of second dummy cells having the same distance as the source line;

[0037] The peripheral circuit is specifically configured as follows:

[0038] Performing an erasing operation on all second dummy cells in the second dummy cell set;

[0039] A programming operation is performed on all the second dummy cells in the second dummy cell set so that the second dummy cells in the second dummy cell set have a target threshold voltage.

[0040] In a second aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0041] The memory as described in the above technical solution; and

[0042] A controller is coupled to the memory and configured to control the memory.

[0043] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory, wherein the memory includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory strings; each of the memory strings includes an upper selection tube, a storage unit, and a lower selection tube sequentially connected in series between a bit line and a source line; wherein all the lower selection tubes in the same memory block form a lower selection tube set;

[0044] The operation method comprises:

[0045] Performing a programming operation on the storage cells in the storage block;

[0046] An erasing operation is performed on at least part of the lower selection tubes in the lower selection tube set.

[0047] In some embodiments, in the same storage block, the upper selection tubes in different storage strings are electrically isolated from each other and the multiple lower selection tubes with the same distance from the source line are connected to each other; the lower selection tube set includes multiple first lower selection tube sets, each of the first lower selection tube sets includes multiple lower selection tubes with the same distance from the source line and the multiple lower selection tubes have different threshold voltages;

[0048] The performing a programming operation on the storage cells in the storage block comprises:

[0049] Based on the fact that a plurality of lower selection tubes in the first lower selection tube set have different threshold voltages, a programming operation and a verification operation are performed on the storage cells in the storage block.

[0050] In some embodiments, performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set includes:

[0051] performing an erasing operation on all lower selection tubes in the first lower selection tube set;

[0052] After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes:

[0053] Performing a programming operation on at least one lower selection tube in the first lower selection tube set that is closest to the source line, so that all lower selection tubes in the first lower selection tube set that is closest to the source line have a preset threshold voltage;

[0054] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0055] In some embodiments, performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set includes:

[0056] Performing an erasing operation on all lower selection tubes in the first lower selection tube set, so that at least one lower selection tube in the first lower selection tube set that is closest to the source line has a preset threshold voltage;

[0057] After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes:

[0058] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0059] In some embodiments, performing a programming operation on the remaining lower selection tubes in the first lower selection tube set includes:

[0060] performing a single-level cell (SLC) programming operation on the remaining lower selection tubes in the first lower selection tube set;

[0061] The lower selection tubes with a preset threshold voltage in the first lower selection tube set are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

[0062] In some embodiments, the lower selection tube set further includes at least one second lower selection tube set located between the source line and the first lower selection tube set, and each of the second lower selection tube sets includes a plurality of lower selection tubes at the same distance from the source line;

[0063] In a programming operation on a memory cell in the memory block, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0064] In some embodiments, performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set includes:

[0065] performing an erasing operation on all lower selection tubes in the second lower selection tube set;

[0066] After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes:

[0067] performing a programming operation on all the lower selection tubes in the second lower selection tube set;

[0068] The performing a programming operation on the remaining lower selection tubes in the first lower selection tube set so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage includes:

[0069] During the programming operation on the remaining lower selection tubes in the first lower selection tube set, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0070] In some embodiments, the lower selection tube set also includes multiple first dummy unit sets, each of the first dummy unit sets includes multiple first dummy units with the same distance as the source lines, and the first dummy unit sets are located between different first lower selection tube sets or between the first lower selection tube set and the second lower selection tube set.

[0071] In some embodiments, performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set includes:

[0072] An erasing operation is performed on all first dummy cells in the first dummy cell set.

[0073] In some embodiments, when the first dummy unit set is located between different first lower selection tube sets, after performing the erasing operation on at least part of the lower selection tubes in the lower selection tube sets, the operating method further includes:

[0074] Performing a programming operation on all first dummy cells in the first dummy cell set so that the first dummy cells in the first dummy cell set have a target threshold voltage;

[0075] In the case where the first dummy unit set is located between the first lower selection tube set and the second lower selection tube set, after performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operating method further includes:

[0076] A programming operation is performed on all the first dummy cells in the first dummy cell set, so that all the first dummy cells in the first dummy cell set have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set with the preset threshold voltage are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erase operation.

[0077] In some embodiments, the memory string further includes a plurality of second dummy cells located between the memory cell and the lower selection tube, the memory block includes a plurality of second dummy cell sets, and each of the second dummy cell sets includes a plurality of second dummy cells having the same distance as the source line;

[0078] While performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further comprises:

[0079] Performing an erasing operation on all second dummy cells in the second dummy cell set;

[0080] After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes:

[0081] A programming operation is performed on all the second dummy cells in the second dummy cell set so that the second dummy cells in the second dummy cell set have a target threshold voltage.

[0082] The embodiment of the present disclosure provides a memory and an operation method thereof, and a memory system. The memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory strings; each of the memory strings includes an upper selection tube, a memory cell, and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set; the peripheral circuit is configured to: perform a programming operation on the memory cells in the memory block; and perform an erasing operation on at least some of the lower selection tubes in the lower selection tube set. In the embodiment of the present disclosure, after completing the programming operation on the memory cells in the memory block, an erasing operation can be performed on at least some of the lower selection tubes in the lower selection tube set, so that some of the lower selection tubes can be readjusted later to form a lower selection tube with a preset threshold voltage, which is used for shutting off in the programming operation and generating a gate induced drain leakage current in the erasing operation, and the remaining lower selection tubes can be used to store data later, thereby improving the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1A A schematic diagram of the structure of a lower selection tube provided in some embodiments;

[0084] Figure 1B A schematic diagram of a circuit of a lower selection tube provided in some embodiments;

[0085] Figure 2A A schematic diagram of the structure of the lower selection tube provided in the embodiment of the present disclosure;

[0086] Figure 2B A schematic diagram of the circuit of the lower selection tube provided in the embodiment of the present disclosure;

[0087] Figure 3 A schematic diagram of the structure of a lower selection tube with different threshold voltages provided in an embodiment of the present disclosure;

[0088] Figure 4 A waveform diagram of a programming operation on a word line provided in an embodiment of the present disclosure;

[0089] Figure 5 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0090] Figure 6 A schematic diagram of a memory including a memory cell array provided for an embodiment of the present disclosure;

[0091] Figure 7 A cross-sectional schematic diagram of a memory cell array including a memory string provided in an embodiment of the present disclosure;

[0092] Figure 8 A schematic diagram of the structure of a lower selection tube assembly provided in an embodiment of the present disclosure;

[0093] Fig. 9 Provides a waveform diagram of erasing and programming operations on the lower selection tube set for the embodiment of the present disclosure;

[0094] Fig.10 A waveform diagram of performing a programming operation on a first set of dummy cells is provided for an embodiment of the present disclosure;

[0095] Fig.11 A schematic diagram of operating a lower selection tube set provided by an embodiment of the present disclosure;

[0096] Fig.12 A schematic diagram of the structure of a memory system provided by an embodiment of the present disclosure;

[0097] Fig.13 A schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0098] Fig.14A A schematic diagram of a memory card having a memory provided by an embodiment of the present disclosure;

[0099] Fig. 14B A schematic diagram of a solid-state drive with a memory provided for an embodiment of the present disclosure;

[0100] Fig.15 A flowchart of a memory operation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0101] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0102] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0103] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0104] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0105] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0106] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0107] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0108] With the continuous development of memory (e.g., 3D NAND memory) technology, the programming time (i.e., Tprog) required by the design is getting shorter and shorter, but at the same time, the size of the metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) circuit design is getting smaller and smaller. The memory may include a memory cell array and a peripheral circuit coupled to the memory cell array. When the area of ​​the charge pump (Pump) in the peripheral circuit is reduced, the ability of the charge pump to ramp the voltage of the memory cell array, i.e., ramp up (Ramp Up) and ramp down (Ramp Down), is affected, thereby causing the peripheral circuit to weaken its driving ability for the memory cell array, which in turn leads to an increase in programming time.

[0109] refer to Figure 1A and Figure 1B , Figure 1A A schematic diagram of the structure of the lower selection tube provided in some embodiments, Figure 1B The following is a schematic diagram of the circuit of the lower selection tube provided in some embodiments. Figure 1A As shown, a storage block (Block) 100 includes: a plurality of storage strings (String) connected in parallel between a bit line (Bit Line, BL) and a source line (Source Line, SL); wherein each storage string includes: a lower selection tube 104, a memory cell (Memory Cell, MC) and an upper selection tube 102 connected in series in sequence between the bit line and the source line; wherein the lower selection tube 104 is located between the source line and the storage cell, and may also be referred to as a source select transistor (Source Selective Transistor, SST); the storage cell is located between the lower selection tube 104 and the upper selection tube 102, and the upper selection tube 102 is located between the storage cell and the bit line, and may also be referred to as a drain select transistor (Drain Selective Transistor, DST). Multiple memory cells located at the same level in different memory strings in the same memory block 100 are interconnected to form a word line (Word Line, WL) 106, that is, multiple memory cells located at the same layer are connected to each other; multiple upper selection tubes 102 located at the same level in different memory strings in the same memory block 100 are electrically isolated from each other, that is, multiple upper selection tubes 102 located at the same layer are electrically isolated from each other; multiple lower selection tubes 104 located at the same level in different memory strings in the same memory block 100 are electrically isolated from each other, that is, multiple lower selection tubes 104 located at the same layer are electrically isolated from each other.

[0110] like Figure 1A As shown, the multiple upper selection tubes 102 at the same level are electrically isolated from each other through the drain selection gate isolation structure 112 ; the multiple lower selection tubes 104 at the same level are electrically isolated from each other through the source selection gate isolation structure 114 . Figure 1A Two lower selection tubes 104 located at the same level are shown, and are electrically connected to a first driver 108 and a second driver 110 respectively.

[0111] It should be noted that the same level refers to the same height in the direction perpendicular to the substrate. The multiple lower selection tubes located at the same level refer to the multiple lower selection tubes with the same distance from the source line; or the multiple lower selection tubes located at the same level refer to the multiple lower selection tubes with the same distance from the bit line.

[0112] For example, Figure 1BAs shown, the storage block 100 may include two finger storage areas (Finger), namely, Finger1 and Finger2; wherein adjacent finger storage areas are electrically isolated from each other through a source selection gate isolation structure 114; the upper selection tubes 102 in the two finger storage areas in the same storage block 100 are electrically isolated from each other, and the lower selection tubes 104 in the two finger storage areas in the same storage block 100 are electrically isolated from each other. Each finger storage area includes two storage strings, namely, Str0 and Str1 (or, Str2 and Str3); wherein the upper selection tubes 102 in the two storage strings in the same finger storage area are electrically isolated from each other, and the lower selection tubes 104 in the two storage strings in the same finger storage area are connected to each other. In addition, Figure 1B The lower selection tubes 104 in the same memory block 100 are shown to be connected to a common source line (Array Common Source, ACS).

[0113] refer to Figure 2A and Figure 2B , Figure 2A A schematic diagram of the structure of the lower selection tube provided in the embodiment of the present disclosure is shown in FIG. Figure 2B The following is a schematic diagram of the circuit of the lower selection tube provided in the embodiment of the present disclosure. Figure 2A As shown, the memory block 200 includes: a plurality of memory strings connected in parallel between the bit line and the source line; wherein each memory string includes: a lower selection tube 204, a memory cell and an upper selection tube 202 connected in series in sequence between the bit line and the source line. A plurality of memory cells located at the same level in different memory strings in the same memory block 200 are interconnected to form a word line 206, that is, a plurality of memory cells located at the same layer are interconnected; a plurality of upper selection tubes 102 located at the same level in different memory strings in the same memory block 200 are electrically isolated from each other, that is, a plurality of upper selection tubes 102 located at the same layer are electrically isolated from each other; a plurality of lower selection tubes 104 located at the same level in different memory strings in the same memory block 200 are interconnected, that is, a plurality of lower selection tubes 104 located at the same layer are electrically isolated from each other. Figure 2A It is shown that the lower selection tubes at the same level are commonly connected to the first driver 208 , and the lower selection tubes at another level are commonly connected to the second driver 210 .

[0114] For example, Figure 2B As shown, the upper selection tubes 202 in two finger storage areas in the same storage block 200 are electrically isolated from each other, and the lower selection tubes 204 in two finger storage areas in the same storage block 200 are connected to each other. The upper selection tubes 202 in two storage strings in the same finger storage area are electrically isolated from each other, and the lower selection tubes 204 in two storage strings in the same finger storage area are connected to each other.

[0115] In the embodiment of the present disclosure, each storage string may include a plurality of lower selection tubes connected in series, at least one of the plurality of lower selection tubes has a first threshold voltage, and the remaining lower selection tubes of the plurality of lower selection tubes have a second threshold voltage different from the first threshold voltage. Some of the plurality of lower selection tubes located at the same level in the same storage block have the first threshold voltage, and the remaining lower selection tubes of the plurality of lower selection tubes have the second threshold voltage.

[0116] refer to Figure 3 , Figure 3 The schematic diagram of the structure of the lower selection tube with different threshold voltages provided by the embodiment of the present disclosure. Figure 3 As shown, each storage string includes two lower selection tubes connected in series, and the storage strings Str0 and Str1 each include a first lower selection tube 204a and a second lower selection tube 204b connected in series; wherein the first lower selection tube 204a and the second lower selection tube 204b have different threshold voltages. For example, the first lower selection tube 204a has a first threshold voltage V1, the second lower selection tube 204b has a second threshold voltage V2, and the first threshold voltage V1 is less than the second threshold voltage V2.

[0117] The storage strings Str2 and Str3 each include a third lower selection tube 204c and a fourth lower selection tube 204d connected in series; the third lower selection tube 204c and the fourth lower selection tube 204d have different threshold voltages. For example, the third lower selection tube 204c has a second threshold voltage V2, and the fourth lower selection tube 204d has a first threshold voltage V1. The first lower selection tube 204a and the third lower selection tube 204c located at the same level are connected to each other, and the first lower selection tube 204a and the third lower selection tube 204c have different threshold voltages; the second lower selection tube 204b and the fourth lower selection tube 204d located at the same level are connected to each other, and the second lower selection tube 204b and the fourth lower selection tube 204d have different threshold voltages.

[0118] In the embodiment of the present disclosure, the lower selection transistors can have different threshold voltages in units of storage strings or finger storage areas. Figure 3As shown, taking the finger storage area as a unit so that the lower selection tubes have different threshold voltages as an example, a voltage greater than the second threshold voltage V2 can be applied to the first lower selection tube 204a and the third lower selection tube 204c located at the same level, so that the first lower selection tube 204a and the third lower selection tube 204c are both turned on; and a voltage greater than the first threshold voltage V1 and less than the second threshold voltage V2 can be applied to the second lower selection tube 204b and the fourth lower selection tube 204d located at the same level, so that the fourth lower selection tube 204d is turned on and the second lower selection tube 204b is turned off; in this way, the storage strings str2 and str3 in the storage area Finger2 can be turned on and the storage strings str0 and str1 in the finger storage area Finger1 are turned off.

[0119] Similarly, a voltage greater than the first threshold voltage V1 and less than the second threshold voltage V2 may be applied to the first lower selection tube 204a and the third lower selection tube 204c located at the same level, so that the first lower selection tube 204a is turned on and the third lower selection tube 204c is turned off; and a voltage greater than the second threshold voltage V2 may be applied to the second lower selection tube 204b and the fourth lower selection tube 204d located at the same level, so that both the second lower selection tube 204b and the fourth lower selection tube 204d are turned on; in this way, the storage strings str0 and str1 in the finger storage area Finger1 may be turned on and the storage strings str2 and str3 in the finger storage area Finger2 are turned off. By using the lower selection tubes with different threshold voltages, different finger storage areas (or storage strings) can be selectively turned on.

[0120] Figure 3 It is shown that all the lower selection tubes of the storage block have two threshold voltages, namely, the first threshold voltage V1 and the second threshold voltage V2. In fact, the disclosed embodiment does not specifically limit the number of threshold voltages of all the lower selection tubes, and a suitable number of threshold voltages can be selected according to actual conditions.

[0121] refer to Figure 4 , Figure 4 The waveform diagram of programming operation on word line provided by the embodiment of the present disclosure. Figure 4 As shown, each storage string includes an upper selection tube, a storage unit and a lower selection tube which are connected in series in sequence between a bit line and a source line; wherein a plurality of upper selection tubes located at the same level are electrically isolated from each other and together form an upper selection tube set 212; a plurality of storage units located at the same level are interconnected to form a word line 206; a plurality of lower selection tubes located at the same level are interconnected, and all lower selection tubes in the same storage block together form a lower selection tube set 218.

[0122] The storage string also includes: a top dummy cell located between the upper selection tube and the storage cell and a bottom dummy cell located between the lower selection tube and the storage cell; wherein, multiple top dummy cells located at the same level are interconnected to form a top dummy word line 214, and multiple bottom dummy cells located at the same level are interconnected to form a bottom dummy word line 216 (i.e., a second dummy cell set 226).

[0123] Exemplarily, all lower selection tubes in the same memory block form a lower selection tube set 218. The lower selection tube set 218 may include multiple first lower selection tube sets 220, each of which includes multiple lower selection tubes at the same distance from the source line and have different threshold voltages. One first lower selection tube set 220 corresponds to a layer of multiple lower selection tubes located at the same level and connected to each other, and the threshold voltages of the multiple lower selection tubes included in one first lower selection tube set 220 are different.

[0124] In some embodiments, the multiple lower selection tubes included in the first lower selection tube set 220 can have different threshold voltages through programming operations. The multiple lower selection tubes included in the first lower selection tube set 220 can be used for selective conduction in verification operations and read operations, wherein the first lower selection tube set 220 can also be called a bottom selective gate cut (BSG Cut) or an electrical selection tube.

[0125] Exemplarily, the lower selection tube set 218 may also include at least one second lower selection tube set 222, each second lower selection tube set 222 including a plurality of lower selection tubes that are at the same distance from the source line and are interconnected; wherein the second lower selection tube set 222 is located between the source line and the first lower selection tube set 220.

[0126] In some embodiments, the multiple lower selection tubes included in the second lower selection tube set 222 can be implemented to have a preset threshold voltage through a programming operation. The multiple lower selection tubes included in the second lower selection tube set 222 can be used for shutting down in a programming operation and generating a gate-induced drain leakage current (Gate-induced Drain Leakage) in an erase operation, wherein the second lower selection tube set can also be called a common bottom selection tube (Bottom Selective Gate, BSG), that is, a common BSG.

[0127] Exemplarily, the lower selection tube set 218 may also include multiple first dummy unit sets 224, each first dummy unit set 224 includes multiple first dummy units that are at the same distance from the source line and are interconnected; wherein the first dummy unit set 224 is located between different first lower selection tube sets 220 or between the first lower selection tube set 220 and the second lower selection tube set 222. Figure 4 It is illustrated that the first dummy unit set 224 is located between different first lower selection tube sets 220 .

[0128] In some embodiments, based on the fact that the plurality of lower selection tubes in the first lower selection tube set 220 have different threshold voltages, a program operation and a verification operation are performed on the memory cells in the memory block 200 .

[0129] like Figure 4 As shown, the storage string where the storage cell to be programmed is located is the selected string, and the other storage strings are non-selected strings; the word line where the storage cell to be programmed is located is the selected word line, and the other word lines are non-selected word lines; the bit line connected to the selected string is the selected bit line, and the other bit lines are non-selected bit lines. In the programming operation, a bit line programming voltage, such as a ground voltage Vss, is applied to the selected bit line, and a programming inhibiting voltage, such as a high voltage Vdd or Vcc, is applied to the non-selected bit line; a conduction voltage, such as a high voltage Vcc, is applied to the upper selection tube of the selected string, and a cutoff voltage, such as a ground voltage Vss, is applied to the upper selection tube of the non-selected string; a word line programming voltage, such as a programming voltage Vpgm, is applied to the selected word line, and a pass voltage, such as a pass voltage Vpass, is applied to the non-selected word line, the top dummy word line and the bottom dummy word line (i.e., the second dummy cell set); at this time in the programming operation, a cutoff voltage, such as a ground voltage Vss, is applied to the first lower selection tube set, the second lower selection tube set and the first dummy cell set in the lower selection tube set; and the ground voltage Vss is also applied to the source line.

[0130] In the verification operation, a verification voltage, such as a verification voltage Vpv, is applied to the selected word line; at this time, different voltages can be applied to the multiple lower selection transistors in the selection string based on the different threshold voltages of the multiple lower selection transistors in the selection string. Return to Reference Figure 3 If the finger storage area Finger1 is the selection finger storage area, based on the different threshold voltages of the first lower selection tube 204a and the second lower selection tube 204b, the voltage applied to the first lower selection tube 204a (i.e., Low Vpass) ensures that the first lower selection tube 204a is turned on, and the voltage applied to the second lower selection tube 204b (i.e., High Vpass) ensures that the second lower selection tube 204b is turned on, so that the channel of the selection string can be turned on.

[0131] In a storage block, based on the different threshold voltages of multiple lower selection tubes in a storage string, during the programming-verification operation of the storage cell, the threshold voltage and bias voltage combination between different layers is used to achieve selective shutdown of different storage strings or storage areas, thereby reducing the load (Loading) of the driving capability of the peripheral circuit, reducing the time for the voltage ramp up or ramp down of the storage array, and thus reducing the programming time. However, setting multiple first lower selection tube sets in the storage block may waste storage space.

[0132] In view of this, the embodiments of the present disclosure provide a memory and an operation method thereof. In the embodiments of the present disclosure, after completing the programming operation of the storage cells in the storage block, at least part of the lower selection tubes in the lower selection tube set can be erased, so that some of the lower selection tubes can be re-trimmed to form a normal BSG, which can be used for shutting off in the programming operation and generating gate induced drain leakage current in the erase operation, and the remaining lower selection tubes can be used as storage cells for storing data. In this way, the storage density can be improved while reducing the programming time by using electrical selection tubes.

[0133] refer to Figure 5 and Figure 6 , Figure 5 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure, Figure 6 A schematic diagram of a memory including a memory cell array provided in an embodiment of the present disclosure. Figure 5 and Figure 6 As shown, the embodiment of the present disclosure provides a memory 300, which includes: a memory cell array 302 and a peripheral circuit 304 coupled to the memory cell array 302; the memory cell array 302 includes a plurality of memory blocks 306, each memory block 306 includes a plurality of memory strings 310; each memory string 310 includes an upper selection tube 314, a memory cell 308 and a lower selection tube 312 which are sequentially connected in series between a bit line 322 and a source line 316; wherein all the lower selection tubes 312 in the same memory block 306 form a lower selection tube set;

[0134] The above peripheral circuit 304 is configured as follows:

[0135] Performing a programming operation on the memory cells in the memory block 306;

[0136] An erasing operation is performed on at least part of the lower selection tubes in the lower selection tube set 218 .

[0137] In the embodiment of the present disclosure, after completing the programming operation on the storage cells in the storage block, the erasing operation can be performed on at least part of the lower selection tubes in the lower selection tube set, so that some of the lower selection tubes can be subsequently adjusted to form lower selection tubes with a preset threshold voltage, which are used as ordinary BSGs, that is, used for shutting off in the programming operation and generating gate induced drain leakage current in the erasing operation, and the remaining lower selection tubes can be subsequently used as storage cells, that is, storing data, thereby improving the storage density.

[0138] like Figure 6 As shown, the memory 300 may include a memory cell array 302 and a peripheral circuit 304 coupled to the memory cell array 302. The memory cell array 302 may be a NAND flash memory cell array, wherein the memory cells 308 are provided in the form of an array of memory strings 310, each memory string 310 being formed on a substrate ( Figure 6 In some embodiments, each memory string 310 includes a plurality of memory cells 308 coupled in series and stacked vertically. Each memory cell 308 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 308. Each memory cell 308 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0139] In some embodiments, each memory cell 308 may be a single-level cell (SLC) having two possible storage states and thus may store one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erased state, and the second storage state is a programmed state. In some embodiments, each memory cell 308 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC may have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00", where the threshold voltage distributions of the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is an erased state, and the second, third, and fourth storage states are all programmed states. Similarly, TLC may have 8 storage states, including an erased state and 7 programmed states; QLC may have 16 storage states, including an erased state and 15 programmed states.

[0140] like Figure 6 As shown, each storage string 310 may include a lower selection tube 312 at its source terminal and an upper selection tube 314 at its drain terminal. The lower selection tube 312 and the upper selection tube 314 can be configured to activate the selected storage string 310 (column of the array) during read and program operations. In some embodiments, the sources of the storage strings 310 in the same storage block 306 are coupled through the same source line 316 (e.g., a common SL). In other words, in some embodiments, all storage strings 310 in the same storage block 306 have a common source line. In some embodiments, the drain of the upper selection tube 314 of each storage string 310 is coupled to the corresponding bit line 322, which can be connected via an output bus ( Figure 6 (not shown) to read or write data from the bit line 322.

[0141] like Figure 6As shown, the memory string 310 can be organized into a plurality of memory blocks 306, each of which can have a source line 316 (e.g., a common SL coupled to ground). In some embodiments, each memory block 306 is a basic unit for an erase operation, that is, all memory cells 308 on the same memory block 306 are erased at the same time. In order to erase the memory cells 308 in the selected memory block, the source lines 316 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 308 of adjacent memory strings 310 can be coupled by word lines 324, which select which row of memory cells 308 is affected by the read and program operations. In some embodiments, each word line 324 is coupled to a memory page 326 of memory cells 308. Each word line 324 may include a plurality of control gates (gate electrodes) at each memory cell 308 in a corresponding memory page 326 and a gate line coupling the control gates.

[0142] It should be noted that Figure 6 The illustrated storage page is a physical page, which refers to a layer of storage cells on the physical level. The basic data unit for programming and reading operations is a logical page. For SLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 1 logical page. For MLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 2 logical pages. For TLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 3 logical pages. For QLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 4 logical pages.

[0143] refer to Figure 7 , Figure 7 A cross-sectional schematic diagram of a memory cell array including a memory string provided in an embodiment of the present disclosure. Figure 7As shown, the memory string 310 can extend vertically through the memory stack layer 330 above the substrate 328. The substrate 328 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0144] The memory stack 330 may include alternating gate conductive layers 332 and gate dielectric layers 334. The number of pairs of gate conductive layers 332 and gate dielectric layers 334 in the memory stack 330 may determine the number of memory cells 308 in the memory cell array 302. The gate conductive layers 332 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 332 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 332 includes a doped polysilicon layer. Each gate conductive layer 332 may include a control gate surrounding the memory cell 308, and may extend laterally at the top of the memory stack 330 as a drain select gate line 320, extend laterally at the bottom of the memory stack 330 as a source select gate line 318, or extend laterally between the drain select gate line 320 and the source select gate line 318 as a word line 324.

[0145] like Figure 7 As shown, the memory string 310 includes a channel structure extending vertically through the memory stack layer 330. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the memory layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0146] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in substrate 328, and the source terminal of memory string 310 may contact the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string further includes a channel plug at the drain terminal of the memory string 310. It should be understood that although in Figure 7 Not shown, but additional components of the memory cell array 302 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0147] Return to reference Figure 6 , the peripheral circuit 304 may be coupled to the memory cell array 302 via the bit lines 322, the word lines 324, the source lines 316, the source select gate lines 318, and the drain select gate lines 320. The peripheral circuit 304 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 302 by applying and sensing voltage and / or current signals to and from each target memory cell 308 via the bit lines 322, the word lines 324, the source lines 316, the source select gate lines 318, and the drain select gate lines 320. The peripheral circuit 304 may include various types of peripheral circuits formed using Metal Oxide Semiconductor (MOS) technology.

[0148] refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of the lower selection tube set provided in the embodiment of the present disclosure. Figure 8 As shown in Figure (a), the lower selection tube set 218 may include multiple first lower selection tube sets 220, each of which includes multiple lower selection tubes with the same distance from the source line and have different threshold voltages. Each first lower selection tube set 220 corresponds to a layer of lower selection tubes.

[0149] Figure 8 Figure (a) shows two first lower selection tube assemblies 220. Figure 8 Figure (b) shows eight first lower selection tube assemblies 220. In fact, the embodiment of the present disclosure has no special limitation on the number of first lower selection tube assemblies, and a suitable number of first lower selection tube assemblies can be provided according to actual conditions.

[0150] refer to Fig. 9 , Fig. 9 The waveform diagram of erasing and programming operations on the lower selection tube set is provided for the embodiment of the present disclosure. Figure 8 and Fig. 9As shown, after the programming operation is completed on all the storage cells of the storage block, an erase operation is performed on at least part of the lower selection tubes in the lower selection tube set; wherein, the basic unit of the erase operation is the storage block, and in the process of selecting the voltage of the source line of the storage block to increase from the ground voltage Vss to the erase voltage Vers, after a preset time, the upper selection tube set 212, the top dummy word line 214, the word line 206, the bottom dummy word line 216 (i.e., the second dummy cell set 226), the first lower selection tube set 220, the first dummy cell set 224 and the second lower selection tube set 222 of the selected storage block are changed from applying a first voltage (e.g., the ground voltage Vss) to floating (Float); here, the preset time can be set according to actual needs. When the voltage of the source line of the selected storage block reaches the erase voltage Vers, the voltages of the upper selection tube set 212, the top dummy word line 214, the word line 206, the bottom dummy word line 216 (i.e., the second dummy cell set 226), the first lower selection tube set 220, the first dummy cell set 224 and the second lower selection tube set 222 in the corresponding storage block will be stabilized at a second voltage due to coupling; the second voltage is also called the Hold and Release (H&R) voltage.

[0151] It should be understood that the voltage difference between the source line of the selected storage block and the corresponding upper selection tube set, top dummy word line, word line, bottom dummy word line (i.e., second dummy unit set), first lower selection tube set, first dummy word line set and second lower selection tube set, is the effective erase voltage; when the erase voltage on the source line of the selected storage block remains unchanged, the longer the preset time length, the longer the voltage on the upper selection tube set, top dummy word line, word line, bottom dummy word line (i.e., second dummy unit set), first lower selection tube set, first dummy word line set and second lower selection tube set in the storage block is forced to be maintained at the first voltage, and thus the shorter the coupling time on the source line, the smaller the final stable second voltage on the corresponding upper selection tube set, top dummy word line, word line, bottom dummy word line (i.e., second dummy unit set), first lower selection tube set, first dummy word line set and second lower selection tube set, and the larger the voltage value of the effective erase voltage. Therefore, the erase depth can be adjusted by changing the preset time length and adjusting / changing the voltage value of the effective erase voltage.

[0152] like Fig. 9As shown, in the case where the lower selection tube set includes the first lower selection tube set, after the programming operation is completed for all the storage cells of the storage block, the purpose of performing the erase operation is to perform the erase operation on the first lower selection tube set, and not to perform the erase operation on the word line. Therefore, in the erase operation, the voltage on the first lower selection tube set is forced to be maintained at the preset time of the first voltage for a longer period of time, the final stable second voltage on the first lower selection tube set is smaller, and the voltage value of the effective erase voltage is larger; while the voltage on the word line is forced to be maintained at the preset time of the first voltage for a shorter period of time, the final stable second voltage on the word line is larger, and the voltage value of the effective erase voltage is smaller; in this way, it is possible to achieve a larger erase depth for the first lower selection tube set and a smaller erase depth for the word line.

[0153] It should be noted that if Fig. 9 As shown, the voltage waveform diagram of the erase operation on the first lower selection tube set includes a solid line and a dotted line. The solid line refers to the application of a low bias voltage (Low Bias) to the first lower selection tube set, and the dotted line refers to the first lower selection tube set reaching a release voltage due to coupling. If the first lower selection tube set is subsequently used as a storage unit, the voltage indicated by the solid line is used. If the first lower selection tube set does not need to be subsequently used as a storage unit, the voltage indicated by the dotted line is used. In other words, if the first lower selection tube set is subsequently used as a storage unit, the erase depth of the first lower selection tube set is greater. In this way, it is possible to avoid insufficient erase depth of the lower selection tubes in the first lower selection tube set, which affects the subsequent storage function.

[0154] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0155] Performing an erasing operation on all lower selection tubes in the first lower selection tube set 218;

[0156] Performing a programming operation on the lower selection tubes in at least one first lower selection tube set 220 closest to the source line, so that the lower selection tubes in at least one first lower selection tube set 220 closest to the source line all have a preset threshold voltage;

[0157] The programming operation is performed on the remaining lower selection tubes in the first lower selection tube set 220 so that the remaining lower selection tubes in the first lower selection tube set 220 have a target threshold voltage.

[0158] Here, after the erasing operation is performed on all lower selection tubes in the first lower selection tube set, readjustment may be performed; wherein the erasing depth of all first lower selection tube sets in the erasing operation is the same, and the readjustment refers to readjustment of the threshold voltage of the lower selection tube.

[0159] In the process of performing an erase operation and readjustment on all first lower selection tube sets, all first lower selection tube sets can be divided into two parts, the first part is arranged adjacent to the source line, and can be used as a normal BSG after performing an erase operation and readjustment on the first part; the second part is arranged adjacent to the first part, and can be used as a storage unit after performing an erase operation on the second part. The embodiment of the present disclosure has no special limitation on the number of first lower selection tube sets included in the first part and the number of first lower selection tube sets included in the second part.

[0160] In some embodiments, re-adjusting the first part means that a programming operation can be performed on the first lower selection tube set included in the first part, so that the lower selection tubes in the first lower selection tube set included in the first part all have a preset threshold voltage; in this way, the lower selection tubes included in the first part can be used as ordinary BSGs, that is, used for shutoff in programming operations and for generating gate induced drain leakage current in erase operations. In other words, the first lower selection tube set needs to be used as an ordinary BSG before an erase operation and a programming operation.

[0161] like Fig. 9 As shown in the dotted line box, applying the programming voltage Vpgm to some of the lower selection tubes refers to performing programming operations on some of the lower selection tubes so that these lower selection tubes have a preset threshold voltage. In this way, these lower selection tubes can be used as ordinary BSGs.

[0162] In some embodiments, the second part can be used as a storage unit after performing an erase operation, which means that the first lower selection tube set included in the second part can be erased and then programmed, so that the lower selection tubes in the first lower selection tube set included in the second part have a target threshold voltage; thus, the lower selection tubes included in the second part can be used as storage units. In other words, the first lower selection tube set can be used as a storage unit only by performing an erase operation.

[0163] like Fig. 9 As shown, applying a programming voltage Vpgm to part of the bottom dummy word line (i.e., the second dummy cell set) and part of the lower selection tubes refers to performing a programming operation on part of the second dummy cell set and part of the lower selection tubes, that is, the second dummy cell set and part of the lower selection tubes can be used as storage cells. Fig. 9 It is indicated that the lower selection tube responsible for shutting down refers to the lower selection tube that has been adjusted to a normal BSG.

[0164] The embodiments of the present disclosure do not specifically limit the range of the preset threshold voltage. The lower selection tubes used as ordinary BSGs have preset threshold voltages. These lower selection tubes can realize the functions of shutting off in programming operations and generating gate induced drain leakage current in erase operations. The embodiments of the present disclosure do not specifically limit the range of the target threshold voltage. The lower selection tubes used as storage cells have target threshold voltages. These lower selection tubes can perform programming operations to store data.

[0165] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0166] Performing an erasing operation on all lower selection tubes in the first lower selection tube set 220, so that at least one lower selection tube in the first lower selection tube set 220 closest to the source line has a preset threshold voltage;

[0167] The programming operation is performed on the remaining lower selection tubes in the first lower selection tube set 220 so that the remaining lower selection tubes in the first lower selection tube set 220 have a target threshold voltage.

[0168] Here, in the process of performing an erase operation on the lower selection tubes in all the first lower selection tube sets, the entire first lower selection tube set can be divided into two parts, the first part is arranged adjacent to the source line; the second part is arranged adjacent to the first part; wherein the erase depths of the first part and the second part are different; more specifically, the erase depth of the first part is less than the erase depth of the second part. After performing an erase operation on the lower selection tubes in all the first lower selection tube sets, the lower selection tubes included in the first part have a preset threshold voltage, so that the lower selection tubes included in the first part can be used as a normal BSG, that is, used for shutoff in a programming operation and for generating a gate induced drain leakage current in an erase operation. In other words, converting the first lower selection tube set to be used as a normal BSG only requires an erase operation. At this time, there is no need Fig. 9 The process of applying voltage shown in the dotted line box means that a normal BSG can be obtained without further adjustment.

[0169] In some embodiments, a programming operation is performed on the first lower selection tube set included in the second part, so that the lower selection tubes in the first lower selection tube set included in the second part have a target threshold voltage; thus, the lower selection tubes included in the second part can be used as storage units. In other words, the first lower selection tube set only needs to be erased to be used as a storage unit.

[0170] The embodiment of the present disclosure has no special limitation on the number of first lower selection tube sets included in the first part and the number of first lower selection tube sets included in the second part. The embodiment of the present disclosure has no special limitation on the range of the preset threshold voltage. The lower selection tubes used as ordinary BSG have a preset threshold voltage. These lower selection tubes can realize the functions of shutting off in programming operations and generating gate induced drain leakage current in erase operations. The embodiment of the present disclosure has no special limitation on the range of the target threshold voltage. The lower selection tubes used as storage units have a target threshold voltage. These lower selection tubes can perform programming operations to store data.

[0171] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0172] Performing a single-level cell SLC programming operation on the remaining lower selection tubes in the first lower selection tube set 220;

[0173] The lower selection tubes with a preset threshold voltage in the first lower selection tube set 220 are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

[0174] Here, the first lower selection tube set is used as a storage unit, and a programming operation can be performed on this part of the storage units later, so that the storage units have a target threshold voltage. More specifically, an SLC programming operation can be performed on this part of the storage units, so that the storage units have a target threshold voltage.

[0175] like Figure 8 As shown in FIG. (a), the lower selection tube set 218 may further include at least one second lower selection tube set 222, each of which includes a plurality of lower selection tubes with the same distance as the source lines; wherein the second lower selection tube set 222 is located between the source lines and the first lower selection tube set 220. wherein each second lower selection tube set 222 corresponds to a layer of lower selection tubes.

[0176] Figure 8 Figures (a) and (b) both illustrate two second lower selection tube sets 222, which are located between the source line and the first lower selection tube set 220. The disclosed embodiment has no special limitation on the number of second lower selection tube sets, which can be flexibly selected according to actual conditions.

[0177] In some embodiments, the lower selection tube set 218 further includes at least one second lower selection tube set 222 located between the source line and the first lower selection tube set 220, and each second lower selection tube set 222 includes a plurality of lower selection tubes at the same distance as the source line;

[0178] During the programming operation of the memory cells in the memory block 200 , a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set 222 .

[0179] refer to Figure 4 In the process of programming the memory cells in the memory block, a turn-off voltage, such as a ground voltage Vss, is applied to the second lower selection tube set 222 in the lower selection tube set. That is, the second lower selection tube set 222 refers to a common BSG, which is used for turning off in the programming operation and generating a gate induced drain leakage current in the erase operation.

[0180] In some embodiments, the above peripheral circuit is specifically configured as follows:

[0181] Performing an erasing operation on all lower selection tubes in the second lower selection tube set 222;

[0182] Performing a programming operation on all lower selection tubes in the second lower selection tube set 222;

[0183] During the programming operation on the remaining lower selection tubes in the first lower selection tube set 220 , a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set 222 .

[0184] Here, after the lower selection tubes in all the second lower selection tube sets are erased, they can be readjusted. Here, the lower selection tubes in all the second lower selection tube sets are readjusted, that is, the lower selection tubes in all the second lower selection tube sets are programmed, so that the lower selection tubes in all the second lower selection tube sets have a preset threshold voltage. That is, the lower selection tubes in all the second lower selection tube sets can continue to be used as ordinary BSGs, that is, used for shutting off in a programming operation and generating a gate induced drain leakage current in an erase operation.

[0185] In addition, it should be noted that it is also possible not to perform the erasing operation on the lower selection tubes in the second lower selection tube set (or the erasing depth in the erasing operation is small), and to readjust the lower selection tubes in part of the first lower selection tube set, that is, to use the lower selection tubes in part of the first lower selection tube set as ordinary BSG. Here, considering that after the first lower selection tube set is erased, the lower selection tubes in the second lower selection tube set may not be effectively turned off, therefore, it is necessary to readjust the part of the first lower selection tube set that has been erased to form an ordinary BSG.

[0186] like Fig. 9As shown, in the case where the lower selection tube set includes a second lower selection tube set, the voltage on the second lower selection tube set is forced to remain at the first voltage for a shorter preset period of time, the final stable second voltage on the second lower selection tube set is larger, and the voltage value of the effective erasing voltage is smaller; in this way, a smaller erasing depth for the second lower selection tube set can be achieved.

[0187] like Figure 8 As shown in Figures (a) and (b), in some embodiments, the lower selection tube set 218 may also include multiple first dummy unit sets 224, each first dummy unit set 224 includes multiple first dummy units that are at the same distance from the source line and are interconnected; wherein the first dummy unit set 224 is located between different first lower selection tube sets 220 or between the first lower selection tube set 220 and the second lower selection tube set 222.

[0188] Figure 8 The middle figure (a) shows that a first dummy unit set 224 is located between different first lower selection tube sets 220; Figure 8 Figure (b) shows that two first dummy unit sets 224 are located between different first lower selection tube sets 220, and three first dummy unit sets 224 are located between different first lower selection tube sets 220. The disclosed embodiment has no special restrictions on the number of first dummy unit sets and the arrangement relationship between the first dummy unit sets and the first lower selection tube sets, and can be flexibly selected according to actual conditions. In the disclosed embodiment, the first dummy unit sets are arranged between different first lower selection tube sets, which can buffer the potential difference formed in the verification operation to cause hot carrier injection (Hot Carrier Injection, HCI), thereby causing the threshold voltage of the lower selection tube in the first lower selection tube set to drift.

[0189] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0190] An erase operation is performed on all first dummy cells in the first dummy cell set 224 .

[0191] like Fig. 9As shown, the voltage waveform diagram of the erase operation on the first dummy cell set includes a solid line and a dotted line, the solid line refers to the application of a low bias voltage to the first dummy cell set, and the dotted line refers to the first dummy cell set reaching a release voltage due to coupling. If the first dummy cell set is subsequently used as a storage cell, the voltage indicated by the solid line is used, and if the first dummy cell set does not need to be subsequently used as a storage cell, the voltage indicated by the dotted line is used. In other words, if the first dummy cell set is subsequently used as a storage cell, the erase depth of the first dummy cell set is greater. In this way, it is possible to avoid insufficient erase depth of the first dummy cell in the first dummy cell set, which affects the subsequent storage function.

[0192] In some embodiments, when the first dummy unit set 224 is located between different first lower selection tube sets 220, the peripheral circuit 304 is specifically configured as follows:

[0193] Performing a programming operation on all first dummy cells in the first dummy cell set 224 so that the first dummy cells in the first dummy cell set 224 have a target threshold voltage;

[0194] In the case where the first dummy unit set 224 is located between the first lower selection tube set 220 and the second lower selection tube set 222, the above peripheral circuit 304 is specifically configured as follows:

[0195] A programming operation is performed on all the first dummy cells in the first dummy cell set 224, so that all the first dummy cells in the first dummy cell set 224 have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set 224 with the preset threshold voltage are used for shutting off in the programming operation and generating gate induced drain leakage current in the erasing operation.

[0196] In some embodiments, the first dummy cell set may be located between different first lower selection tube sets, and the first dummy cell set may be used as a storage cell after an erase operation is performed on the first dummy cell set. Using the first dummy cell set as a storage cell after an erase operation means that the first dummy cell included in the first dummy cell set may be erased and then programmed, so that the first dummy cell included in the first dummy cell set has a target threshold voltage; in this way, the first dummy cell included in the first dummy cell set may be used as a storage cell. Here, the first dummy cell set may be used as a storage cell only by performing an erase operation.

[0197] refer to Fig.10 , Fig.10 The present disclosure provides a waveform diagram of programming operation on the first dummy cell set. Fig.10As shown, applying the programming voltage Vpgm to a portion of the first dummy cell set refers to performing a programming operation on the first dummy cell set so that the portion of the first dummy cell set has a target threshold voltage; thus, the portion of the first dummy cell set can be used as a memory cell.

[0198] In some embodiments, the first dummy cell set may be located between the first lower selection tube set and the second lower selection tube set, and the first dummy cell set may be used as a normal BSG after an erase operation is performed on the first dummy cell set. The first dummy cell set may be used as a normal BSG after an erase operation is performed on the first dummy cell set, which means that an erase operation may be performed on the first dummy cell included in the first dummy cell set and then a programming operation may be performed, so that the first dummy cell included in the first dummy cell set has a preset threshold voltage; in this way, the first dummy cell included in the first dummy cell set may be adjusted as a normal BSG. Here, the first dummy cell set may be used as a normal BSG after an erase operation is performed.

[0199] like Figure 8 As shown in Figure (a), the storage string also includes: a bottom dummy cell (i.e., a second dummy cell) located between the lower selection tube and the storage cell; the storage block includes a plurality of second dummy cell sets 226, each of which includes a plurality of second dummy cells that are at the same distance from the source line and are interconnected. Each second dummy cell set 226 corresponds to a layer of second dummy cells.

[0200] Figure 8 Figure (a) shows two second dummy unit sets 226. In fact, the embodiment of the present disclosure has no special limitation on the number of second dummy unit sets, and a suitable number of second dummy unit sets can be set according to actual conditions.

[0201] In some embodiments, the above peripheral circuit is specifically configured as follows:

[0202] Performing an erase operation on all second dummy cells in the second dummy cell set 226;

[0203] The programming operation is performed on the second dummy cells in all the second dummy cell sets 226 so that the second dummy cells in the second dummy cell sets 226 have a target threshold voltage.

[0204] Here, the second dummy cell set can be used as a storage cell after an erase operation is performed on it. The second dummy cell set used as a storage cell after an erase operation means that the second dummy cells included in the second dummy cell set can be erased and then programmed, so that the second dummy cells included in the second dummy cell set have a target threshold voltage; in this way, the second dummy cells included in the second dummy cell set can be used as storage cells. Here, the second dummy cell set can be used as a storage cell only by performing an erase operation.

[0205] like Fig. 9 As shown, applying a programming voltage Vpgm to part of the bottom dummy word line (i.e., the second dummy cell set) and part of the lower selection tubes refers to performing a programming operation on part of the second dummy cell set and part of the lower selection tubes, that is, the second dummy cell set and part of the lower selection tubes can be used as storage cells.

[0206] As mentioned above, the storage block includes a lower selection tube set and a second dummy unit set located between the lower selection tube set and the word line; wherein the lower selection tube set includes a first lower selection tube set, a second lower selection tube set and a first dummy unit set. Fig.11 , which explains in detail how to operate on the lower selection tube set.

[0207] like Fig.11 As shown, in step S1101, a programming operation is performed on the memory cells in the memory block, that is, a programming operation is performed on the word lines in the memory block. During the programming operation, the process of applying voltage to the lower selection tube set and the second dummy cell set can refer to Figure 4 The relevant description will not be repeated here.

[0208] In step S1102, it is determined whether the programming operation of all the memory cells in the memory block is completed, that is, it is determined whether the programming operation of all the word lines in the memory block is completed; if yes, step S1103 is executed; if not, step S1101 is continued to be executed. That is to say, step S1103 can be executed only after the programming operation of all the word lines in the memory block is completed.

[0209] In step S1103, an erase operation is performed on all lower selection tube sets and at least part of the second dummy cell set; wherein the lower selection tube set includes the first lower selection tube set, the second lower selection tube set and the first dummy cell set.

[0210] Here, after the erase operation is performed on the entire lower selection tube set and at least a part of the second dummy cell set, the entire lower selection tube set and at least a part of the second dummy cell set can be divided into two parts, the first part is arranged adjacent to the source line, and the first part can be readjusted after the erase operation so that the first part can be used as a normal BSG; the second part is arranged adjacent to the first part, and after the erase operation is performed, the second part can be used as a storage unit.

[0211] In step S1104 , a fixed number of layers is selected for readjustment so that some lower selection transistors have a preset threshold voltage.

[0212] Here, after the erase operation, the second lower selection tube set can be readjusted and continue to be used as a normal BSG; the second lower selection tube set and part of the first lower selection tube set can be readjusted and used as a normal BSG; the second lower selection tube set and part of the first dummy unit set can also be readjusted and used as a normal BSG; the second lower selection tube set, part of the first lower selection tube set and part of the first dummy unit set can also be readjusted and used as a normal BSG.

[0213] Here, the fixed number of layers refers to the fixed number of layers closest to the source line. For example, if the source line is set to layer 0, then from bottom to top, they are layer 1, 2, 3, 4, ..., n. At this time, you can choose to use layer 1, or layer 1 and layer 2, or layer 1 to layer 3, or layer 1 to layer 4 as ordinary BSG. In other words, the fixed number of layers that are adjacent to and continuously set to the source line can be readjusted and used as ordinary BSG.

[0214] In step S1105, other number of layers are selected as storage units.

[0215] Here, after the erase operation is performed, other layers can be selected as storage units; thus, programming operations can be performed on the other layers.

[0216] refer to Fig.12 , Fig.12 Schematic diagram of the structure of the memory system provided by the embodiment of the present disclosure. Fig.12 As shown, an embodiment of the present disclosure provides a memory system, which includes: a memory as in the above technical solution; and a controller coupled to the memory and configured to control the memory.

[0217] In some embodiments, the controller 402 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0218] In some embodiments, the controller 402 is designed to operate in a high duty cycle environment (Solid State Drive, SSD) or embedded Multi-Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptops, etc. and enterprise storage arrays.

[0219] The controller 402 may be configured to control the operation of the memory 300, such as read, erase, and program operations. The controller 402 may also be configured to manage various functions regarding data stored or to be stored in the memory 300, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. In some embodiments, the controller 402 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 300.

[0220] The controller 402 may also perform any other suitable functions, such as formatting the memory 300. The controller 402 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 402 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0221] The controller 402 and one or more memories 300 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash storage (UFS) package or eMMC package). That is, the memory system 400 can be implemented and packaged into different types of terminal electronic products.

[0222] refer to Fig.13 , Fig.13 Schematic diagram of an electronic device provided by an embodiment of the present disclosure. Fig.13 As shown, an embodiment of the present disclosure provides an electronic device 500 , which includes: a memory system 400 as in the above technical solution; and a host 502 coupled to the memory system 400 .

[0223] In some embodiments, the electronic device 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0224] like Fig.13 As shown, the electronic device 500 may include a host 502 and a memory system 400, wherein the memory system 400 has one or more memories 300 and a controller 402. The host 502 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 502 may be configured to send data to the memory 300 or receive data from the memory 300.

[0225] In some embodiments, the controller 402 is coupled to the memory 300 and the host 502, and is configured to control the memory 300. The controller 402 may manage data stored in the memory 300, and communicate with the host 502.

[0226] refer to Fig.14A , Fig.14A Schematic diagram of a memory card with a memory provided by an embodiment of the present disclosure. Fig.14AAs shown, the controller 402 and the single memory 300 may be integrated into a memory card 404. The memory card 404 may include a Personal Computer Memory Card International Association (PCMCIA) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro), an SD (e.g., SD, miniSD, microSD, SDHC) card, UFS, etc. The memory card 404 may also include a processor that connects the memory card 404 to a host (e.g., Fig.13 A memory card connector 406 is coupled to a host 502 in the memory card connector.

[0227] refer to Fig. 14B , Fig. 14B A schematic diagram of a solid-state drive with a memory provided by an embodiment of the present disclosure. Fig. 14B As shown, the controller 402 and the plurality of memories 300 may be integrated into a solid-state drive 408. The solid-state drive 408 may also include a computer that connects the solid-state drive 408 to a host (e.g., Fig.13 The solid-state drive connector 410 is coupled to the host 502 in the memory card. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 408 is greater than the storage capacity and / or operating speed of the memory card 404.

[0228] refer to Fig.15 , Fig.15 The flowchart of the memory operation method provided by the embodiment of the present disclosure is as follows. Fig.15 As shown, an embodiment of the present disclosure provides an operation method of a memory, the memory includes a plurality of memory blocks, each memory block includes a plurality of memory strings; each memory string includes an upper selection tube, a memory unit and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set; the above operation method includes:

[0229] Step S1501: performing a programming operation on the memory cells in the memory block;

[0230] Step S1502: performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set.

[0231] In the embodiment of the present disclosure, after completing the programming operation on the storage cells in the storage block, the erasing operation can be performed on at least part of the lower selection tubes in the lower selection tube set, so that some of the lower selection tubes can be readjusted subsequently to form lower selection tubes with preset threshold voltages for shutting off in the programming operation and generating gate induced drain leakage current in the erasing operation, and the remaining lower selection tubes can be used to store data subsequently, thereby improving the storage density.

[0232] In some embodiments, in the same memory block, upper selection tubes in different memory strings are electrically isolated and multiple lower selection tubes with the same distance from the source line are connected to each other; the lower selection tube set includes multiple first lower selection tube sets, each of the first lower selection tube sets includes multiple lower selection tubes with the same distance from the source line, and the multiple lower selection tubes have different threshold voltages;

[0233] Step S1501 includes:

[0234] Based on the fact that the plurality of lower selection tubes in the first lower selection tube set have different threshold voltages, a programming operation and a verification operation are performed on the memory cells in the memory block.

[0235] In some embodiments, step S1502 includes:

[0236] Performing an erasing operation on all lower selection tubes in the first lower selection tube set;

[0237] After step S1502, the above operation method further includes:

[0238] Performing a programming operation on the lower selection tubes in at least one first lower selection tube set closest to the source line, so that the lower selection tubes in at least one first lower selection tube set closest to the source line all have a preset threshold voltage;

[0239] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0240] In the embodiment of the present disclosure, after the lower selection tubes in the first lower selection tube set are erased, some of the lower selection tubes can be readjusted to form a normal BSG; wherein the lower selection tubes used as the normal BSG have a preset threshold voltage; and the remaining lower selection tubes can be used as storage units.

[0241] In some embodiments, step S1502 includes:

[0242] Performing an erasing operation on all lower selection tubes in the first lower selection tube set, so that at least one lower selection tube in the first lower selection tube set that is closest to the pole line has a preset threshold voltage;

[0243] After step S1502, the above operation method further includes:

[0244] A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

[0245] In the disclosed embodiment, the erasing depths of the lower selection tubes in the first lower selection tube set can be controlled to be different. After the erasing operation is performed on some lower selection tubes, normal BSG can be formed without further adjustment; the remaining lower selection tubes can be used as storage units.

[0246] In some embodiments, performing a programming operation on the remaining lower selection tubes in the first lower selection tube set includes:

[0247] performing a single-level cell (SLC) programming operation on the remaining lower selection tubes in the first lower selection tube set;

[0248] The lower selection tubes with a preset threshold voltage in the first lower selection tube set are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

[0249] In some embodiments, the lower selection tube set further includes at least one second lower selection tube set located between the source line and the first lower selection tube set, and each second lower selection tube set includes a plurality of lower selection tubes at the same distance from the source line;

[0250] In a programming operation on a memory cell in a memory block, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0251] In some embodiments, step S1502 includes:

[0252] Performing an erasing operation on all lower selection tubes in the second lower selection tube set;

[0253] After step S1502, the above operation method further includes:

[0254] Performing a programming operation on all lower selection tubes in the second lower selection tube set;

[0255] Performing a programming operation on the remaining lower selection tubes in the first lower selection tube set so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage, comprising:

[0256] In the programming operation for the remaining lower selection tubes in the first lower selection tube set, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

[0257] In the disclosed embodiment, the second lower selection tube set is a common BSG, and the common BSG is responsible for shutting down during the programming operation of the memory cell.

[0258] In some embodiments, the lower selection tube set also includes multiple first dummy unit sets, each first dummy unit set includes multiple first dummy units with the same distance between the source lines, and the first dummy unit sets are located between different first lower selection tube sets or between the first lower selection tube set and the second lower selection tube set.

[0259] In some embodiments, step S1502 includes:

[0260] An erasing operation is performed on the first dummy cells in all the first dummy cell sets.

[0261] In some embodiments, when the first dummy unit set is located between different first lower selection tube sets, after step S1502, the operation method further includes:

[0262] Performing a programming operation on all first dummy cells in the first dummy cell set so that the first dummy cells in the first dummy cell set have a target threshold voltage;

[0263] In the case where the first dummy unit set is located between the first lower selection tube set and the second lower selection tube set, after step S1502, the operation method further includes:

[0264] A programming operation is performed on all the first dummy cells in the first dummy cell set, so that all the first dummy cells in the first dummy cell set have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set with the preset threshold voltage are used for shutting off in the programming operation and generating gate induced drain leakage current in the erasing operation.

[0265] In some embodiments, the memory string further includes a plurality of second dummy cells located between the memory cell and the lower selection tube, the memory block includes a plurality of second dummy cell sets, and each second dummy cell set includes a plurality of second dummy cells having the same distance as the source line;

[0266] At the same time as step S1502, the above operation method further includes:

[0267] Performing an erasing operation on the second dummy cells in all the second dummy cell sets;

[0268] After step S1502, the above operation method further includes:

[0269] A program operation is performed on the second dummy cells in all the second dummy cell sets so that the second dummy cells in the second dummy cell sets have a target threshold voltage.

[0270] The embodiment of the present disclosure provides a memory and an operation method thereof, and a memory system. The memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory strings; each of the memory strings includes an upper selection tube, a memory cell, and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set; the peripheral circuit is configured to: perform a programming operation on the memory cells in the memory block; and perform an erasing operation on at least some of the lower selection tubes in the lower selection tube set. In the embodiment of the present disclosure, after completing the programming operation on the memory cells in the memory block, an erasing operation can be performed on at least some of the lower selection tubes in the lower selection tube set, so that some of the lower selection tubes can be readjusted later to form a lower selection tube with a preset threshold voltage, which is used for shutting off in the programming operation and generating a gate induced drain leakage current in the erasing operation, and the remaining lower selection tubes can be used to store data later, thereby improving the storage density.

[0271] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0272] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory comprises: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory blocks, each of the memory blocks comprises a plurality of memory strings; each of the memory strings comprises an upper selection tube, a memory cell and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set; The peripheral circuit is configured as: Performing a programming operation on the storage cells in the storage block; An erasing operation is performed on at least part of the lower selection tubes in the lower selection tube set.

2. The memory according to claim 1, characterized in that: In the same storage block, the upper selection tubes in different storage strings are electrically isolated from each other and the multiple lower selection tubes with the same distance from the source line are connected to each other; the lower selection tube set includes multiple first lower selection tube sets, each of the first lower selection tube sets includes multiple lower selection tubes with the same distance from the source line and the multiple lower selection tubes have different threshold voltages; The peripheral circuit is specifically configured as follows: Based on the fact that a plurality of lower selection tubes in the first lower selection tube set have different threshold voltages, a programming operation and a verification operation are performed on the storage cells in the storage block.

3. The memory according to claim 2, characterized in that: The peripheral circuit is specifically configured as follows: performing an erasing operation on all lower selection tubes in the first lower selection tube set; Performing a programming operation on at least one lower selection tube in the first lower selection tube set that is closest to the source line, so that all lower selection tubes in the first lower selection tube set that is closest to the source line have a preset threshold voltage; A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

4. The memory according to claim 2, characterized in that: The peripheral circuit is specifically configured as follows: Performing an erasing operation on all lower selection tubes in the first lower selection tube set, so that at least one lower selection tube in the first lower selection tube set that is closest to the source line has a preset threshold voltage; A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

5. The memory according to claim 3 or 4, characterized in that: The peripheral circuit is specifically configured as follows: performing a single-level cell (SLC) programming operation on the remaining lower selection tubes in the first lower selection tube set; The lower selection tubes with a preset threshold voltage in the first lower selection tube set are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

6. The memory according to claim 5, characterized in that: The lower selection tube set further includes at least one second lower selection tube set located between the source line and the first lower selection tube set, each of the second lower selection tube sets includes a plurality of lower selection tubes at the same distance from the source line; In a programming operation on a memory cell in the memory block, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

7. The memory according to claim 6, characterized in that: The peripheral circuit is specifically configured as follows: performing an erasing operation on all lower selection tubes in the second lower selection tube set; performing a programming operation on all the lower selection tubes in the second lower selection tube set; During the programming operation on the remaining lower selection tubes in the first lower selection tube set, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

8. The memory according to claim 7, characterized in that: The lower selection tube set also includes multiple first dummy unit sets, each of the first dummy unit sets includes multiple first dummy units with the same distance as the source lines, and the first dummy unit sets are located between different first lower selection tube sets or between the first lower selection tube set and the second lower selection tube set.

9. The memory according to claim 8, characterized in that: The peripheral circuit is specifically configured as follows: An erasing operation is performed on all first dummy cells in the first dummy cell set.

10. The memory according to claim 9, characterized in that: In the case where the first dummy unit set is located between different first lower selection tube sets, the peripheral circuit is specifically configured as follows: Performing a programming operation on all first dummy cells in the first dummy cell set so that the first dummy cells in the first dummy cell set have a target threshold voltage; In the case where the first dummy unit set is located between the first lower selection tube set and the second lower selection tube set, the peripheral circuit is specifically configured as follows: A programming operation is performed on all the first dummy cells in the first dummy cell set, so that all the first dummy cells in the first dummy cell set have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set with the preset threshold voltage are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erase operation.

11. The memory according to claim 2, characterized in that: The memory string further includes a plurality of second dummy cells located between the memory cell and the lower selection tube, the memory block includes a plurality of second dummy cell sets, and each of the second dummy cell sets includes a plurality of second dummy cells having the same distance as the source line; The peripheral circuit is specifically configured as follows: Performing an erasing operation on all second dummy cells in the second dummy cell set; A programming operation is performed on all the second dummy cells in the second dummy cell set so that the second dummy cells in the second dummy cell set have a target threshold voltage.

12. A memory system, characterized in that: The memory system comprises: The memory as claimed in any one of claims 1 to 11; and A controller is coupled to the memory and configured to control the memory.

13. A method for operating a memory, characterized in that: The memory comprises a plurality of memory blocks, each of which comprises a plurality of memory strings; each of which comprises an upper selection tube, a memory unit and a lower selection tube connected in series between a bit line and a source line in sequence; wherein all the lower selection tubes in the same memory block form a lower selection tube set; The operation method comprises: Performing a programming operation on the storage cells in the storage block; An erasing operation is performed on at least part of the lower selection tubes in the lower selection tube set.

14. The memory operation method according to claim 13, characterized in that: In the same storage block, the upper selection tubes in different storage strings are electrically isolated from each other and the multiple lower selection tubes with the same distance from the source line are connected to each other; the lower selection tube set includes multiple first lower selection tube sets, each of the first lower selection tube sets includes multiple lower selection tubes with the same distance from the source line and the multiple lower selection tubes have different threshold voltages; The performing a programming operation on the storage cells in the storage block comprises: Based on the fact that a plurality of lower selection tubes in the first lower selection tube set have different threshold voltages, a programming operation and a verification operation are performed on the storage cells in the storage block.

15. The memory operation method according to claim 14, characterized in that: The step of performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set comprises: performing an erasing operation on all lower selection tubes in the first lower selection tube set; After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes: Performing a programming operation on at least one lower selection tube in the first lower selection tube set that is closest to the source line, so that all lower selection tubes in the first lower selection tube set that is closest to the source line have a preset threshold voltage; A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

16. The memory operation method according to claim 14, characterized in that: The step of performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set comprises: Performing an erasing operation on all lower selection tubes in the first lower selection tube set, so that at least one lower selection tube in the first lower selection tube set that is closest to the source line has a preset threshold voltage; After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes: A programming operation is performed on the remaining lower selection tubes in the first lower selection tube set, so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage.

17. The memory operation method according to claim 15 or 16, characterized in that: The performing a programming operation on the remaining lower selection tubes in the first lower selection tube set includes: performing a single-level cell (SLC) programming operation on the remaining lower selection tubes in the first lower selection tube set; The lower selection tubes with a preset threshold voltage in the first lower selection tube set are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erasing operation.

18. The memory operation method according to claim 17, characterized in that: The lower selection tube set further includes at least one second lower selection tube set located between the source line and the first lower selection tube set, each of the second lower selection tube sets includes a plurality of lower selection tubes at the same distance from the source line; In a programming operation on a memory cell in the memory block, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

19. The memory operating method according to claim 18, characterized in that: The step of performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set comprises: performing an erasing operation on all lower selection tubes in the second lower selection tube set; After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes: performing a programming operation on all the lower selection tubes in the second lower selection tube set; The performing a programming operation on the remaining lower selection tubes in the first lower selection tube set so that the remaining lower selection tubes in the first lower selection tube set have a target threshold voltage includes: During the programming operation on the remaining lower selection tubes in the first lower selection tube set, a turn-off voltage is applied to the lower selection tubes in the second lower selection tube set.

20. The memory operating method according to claim 19, characterized in that: The lower selection tube set also includes multiple first dummy unit sets, each of the first dummy unit sets includes multiple first dummy units with the same distance as the source lines, and the first dummy unit sets are located between different first lower selection tube sets or between the first lower selection tube set and the second lower selection tube set.

21. The memory operation method according to claim 20, characterized in that: The step of performing an erasing operation on at least part of the lower selection tubes in the lower selection tube set comprises: An erasing operation is performed on all first dummy cells in the first dummy cell set.

22. The memory operating method according to claim 21, characterized in that: In the case where the first dummy unit set is located between different first lower selection tube sets, after performing the erasing operation on at least part of the lower selection tubes in the lower selection tube sets, the operating method further includes: Performing a programming operation on all first dummy cells in the first dummy cell set so that the first dummy cells in the first dummy cell set have a target threshold voltage; In the case where the first dummy unit set is located between the first lower selection tube set and the second lower selection tube set, after performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operating method further includes: A programming operation is performed on all the first dummy cells in the first dummy cell set, so that all the first dummy cells in the first dummy cell set have a preset threshold voltage; wherein the first dummy cells in the first dummy cell set with the preset threshold voltage are used for shutting off in a programming operation and generating a gate induced drain leakage current in an erase operation.

23. The memory operation method according to claim 14, characterized in that: The memory string further includes a plurality of second dummy cells located between the memory cell and the lower selection tube, the memory block includes a plurality of second dummy cell sets, and each of the second dummy cell sets includes a plurality of second dummy cells having the same distance as the source line; While performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes: Performing an erasing operation on all second dummy cells in the second dummy cell set; After performing the erasing operation on at least part of the lower selection tubes in the lower selection tube set, the operation method further includes: A programming operation is performed on all the second dummy cells in the second dummy cell set so that the second dummy cells in the second dummy cell set have a target threshold voltage.

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