Memory, method of operating memory, system, and storage medium

Abstract

The application provides a memory, an operating method of the memory, a system and a storage medium, and relates to the technical field of storage. The memory comprises a peripheral circuit and a memory cell array; the peripheral circuit comprises a plurality of page buffers and a logic control circuit; the page buffer comprises a first bit line connection point, a second bit line connection point, a first switch device and a second switch device; the first bit line connection point and the second bit line connection point are used for connecting bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are connected to a power supply end through independent pre-charging circuits respectively, and the first bit line connection point and the second bit line connection point are connected to latches in the page buffer respectively; the pre-charging circuit is a circuit for pre-charging the bit lines by the page buffer; the first switch device connects the first bit line connection point and the second bit line connection point; and the second switch device is located on the pre-charging circuit corresponding to the second bit line connection point.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a method for operating the memory, a system, and a storage medium. Background Technology

[0002] In memory products such as NAND flash memory, page buffers are important circuits used to implement data sensing and storage.

[0003] In related technologies, page buffers are connected to bit lines in the memory cell array. They sense stored data by sensing / amplifying signals from the bit lines and write data by controlling the voltage of the bit lines. Summary of the Invention

[0004] This application provides a memory, a method for operating the memory, a system, and a storage medium that can reduce the overall size of the page buffer in the memory while keeping the number of bit lines in the memory constant, and increase the number of bit lines in the memory while keeping the die size of the memory constant. The technical solution is as follows:

[0005] On one hand, a memory is provided, the memory including peripheral circuitry and a memory cell array; the peripheral circuitry includes a plurality of page buffers, and control logic circuitry coupled to the plurality of page buffers and configured to control the plurality of page buffers; the page buffers include a first bit line connection point, a second bit line connection point, a first switching device, and a second switching device;

[0006] The first bit line connection point and the second bit line connection point are used to connect the bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are respectively connected to the power supply through independent precharge circuits, and the first bit line connection point and the second bit line connection point are respectively connected to the latches in the page buffer; the precharge circuit is a circuit in which the page buffer precharges the bit lines; the first switching device is connected to the first bit line connection point and the second bit line connection point; the second switching device is located on the precharge circuit corresponding to the second bit line connection point.

[0007] In an optional embodiment, the control logic circuit is configured to disconnect the first switching device and turn on the second switching device when a programming operation is performed through the page buffer; the control logic circuit is also configured to turn on the first switching device and disconnect the second switching device when a read operation is performed through the page buffer.

[0008] In an optional embodiment, a third switching device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first bit line connection point.

[0009] In an optional embodiment, the control logic circuit is configured to disconnect the third switching device during a programming operation via the page buffer; and the control logic circuit is configured to turn on the third switching device during a read operation via the page buffer.

[0010] In an optional embodiment, the first bit line connection point is connected to N bit lines out of the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to the other N bit lines out of the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are sequentially adjacent, and the bit lines connected by the first bit line connection point and the second bit line connection point are sequentially staggered.

[0011] In an optional embodiment, the control logic circuit is configured to apply a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0012] In an optional embodiment, the control logic circuit is configured to, when programming the 2×N bit-line-coupled memory cells through the page buffer, sequentially apply programming pulse voltages to the 2×N bit lines through the first bit line connection point and the second bit line connection point, according to the arrangement order of the 2×N bit lines; wherein, the time intervals for applying programming pulse voltages to adjacent bit lines overlap, so as to apply bias voltages to adjacent bit lines during the programming operation of a bit-line-coupled memory cell.

[0013] In an optional embodiment, for the 4×N bit lines in the memory cell array that are sequentially adjacent to the two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the reverse of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

[0014] On the other hand, a method for operating a memory is provided, the method being executed by control logic circuitry in the peripheral logic circuitry of the memory, the memory being a memory as shown in any of the above embodiments, the method comprising: during a programming operation via the page buffer, disconnecting the first switching device and turning on the second switching device; during a read operation via the page buffer, turning on the first switching device and disconnecting the second switching device.

[0015] In an optional embodiment, a third switching device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first bit line connection point.

[0016] In an optional embodiment, the method further includes: disconnecting the third switching device during a programming operation via the page buffer; and turning the third switching device on during a read operation via the page buffer.

[0017] In an optional embodiment, the first bit line connection point is connected to N bit lines out of the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to the other N bit lines out of the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are sequentially adjacent, and the bit lines connected by the first bit line connection point and the second bit line connection point are sequentially staggered.

[0018] In an optional embodiment, the method further includes: applying a bias voltage to a second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0019] In an optional embodiment, applying a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer includes: when programming the memory cell coupled to the 2×N bit lines through the page buffer, applying programming pulse voltages sequentially to the 2×N bit lines through the first bit line connection point and the second bit line connection point, according to the arrangement order of the 2×N bit lines; wherein, the time intervals for applying programming pulse voltages to two adjacent bit lines overlap, so as to apply bias voltages to adjacent bit lines during the programming operation of a memory cell coupled to one bit line.

[0020] In an optional embodiment, for the 4×N bit lines in the memory cell array that are sequentially adjacent to the two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the reverse of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

[0021] On the other hand, a storage system is provided, the storage system comprising: one or more memories as described in any of the above embodiments, and a controller coupled to the memories and configured to control the memories.

[0022] On the other hand, a computer system is provided, the computer system comprising: a host; one or more memories as described in any of the above embodiments; and a controller coupled to the memories and configured to control the memories.

[0023] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a control logic unit, implement the memory operation method as described in any of the above embodiments.

[0024] The technical solution provided in this application may include the following beneficial effects:

[0025] For multiple page buffers in the peripheral circuitry of the memory, each page buffer includes two bit line connection points, each with an independent precharge circuit. These two bit line connection points are connected to the bit lines in the memory cell array and the latches in the page buffer, respectively. Furthermore, these two bit line connection points are connected via a first switching device, and a second switching device is also provided on the precharge circuit of one of the bit line connection points. In this scheme, when the two bit line connection points in the page buffer separately perform precharge of the bit lines during programming, they can share a portion of the circuit structure in the page buffer. Specifically, for example, during the precharge phase of programming, the first switching device is turned off, while the second switching device is turned on, allowing the two bit line connection points to respectively... Each bit line is precharged through its own precharge circuit. During the read process, the second switching device is disconnected, and the memory cell coupled to either bit line is read through the connection of the first switching device. This allows the two bit line connection points to share the circuit structure of the sensing part. Through the above scheme, two or more bit line connection points can be integrated into a page buffer and share part of the circuit structure in the page buffer. It is not necessary to set a page buffer for each bit line connection point. This reduces the overall size of the page buffer in the memory while keeping the number of bit lines in the memory constant, and increases the number of bit lines in the memory while keeping the size of the memory die constant, thereby improving storage capacity and performance. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the structure of a memory card involved in this application;

[0029] Figure 3 This is a schematic diagram of the structure of a solid-state driver involved in this application;

[0030] Figure 4 This is a block diagram of a memory illustrated in an exemplary embodiment of this application;

[0031] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application;

[0032] Figure 6 This is a perspective view of a portion of a three-dimensional storage array structure shown in an exemplary embodiment of this application;

[0033] Figure 7 This is a schematic diagram showing the connection between a NAND flash memory cell array and a page buffer;

[0034] Figure 8 This is a schematic diagram of the connection between another type of NAND flash memory cell array and page buffer;

[0035] Figure 9 This is a framework diagram of a memory provided in an exemplary embodiment of this application;

[0036] Figure 10 This is a schematic diagram of the structure of a page buffer according to an embodiment of this application;

[0037] Figure 11 This is a schematic diagram of another page buffer structure involved in an embodiment of this application;

[0038] Figure 12 This is a schematic diagram of another page buffer structure involved in an embodiment of this application;

[0039] Figure 13 This is a schematic diagram of another page buffer structure according to an embodiment of this application;

[0040] Figure 14 This is a schematic diagram of another page buffer structure according to an embodiment of this application;

[0041] Figure 15 This is a schematic diagram of another page buffer structure according to an embodiment of this application;

[0042] Figure 16 This is a circuit diagram of a page buffer according to an exemplary embodiment of this application;

[0043] Figure 17 This is a schematic diagram illustrating the connection between a page buffer and a bit line according to an embodiment of this application;

[0044] Figure 18 This is an execution timing diagram of a programming operation involved in an embodiment of this application;

[0045] Figure 19 This is a schematic diagram illustrating the connection between a page buffer and a bit line according to an embodiment of this application;

[0046] Figure 20 This is an execution timing diagram of another programming operation involved in an embodiment of this application;

[0047] Figure 21 This is a flowchart of a memory operation method provided in an exemplary embodiment of this application;

[0048] Figure 22 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application. Detailed Implementation

[0049] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0050] The computer system provided in this application embodiment may include a host and a storage system. The storage system may include 3D memory, such as 3D NAND flash memory.

[0051] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1 As shown, the computer system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100. The controller 200 may also be referred to as a memory controller.

[0052] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0053] The controller 200 can also communicate with external devices according to specific communication protocols. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. The interface protocol can be the Universal Serial Bus (USB) protocol, the Multi-Media Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-E protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Drive Interface (ESDI) protocol, the Integrated Development Environment (IDE) protocol, the FireWire protocol, etc.

[0054] In an optional embodiment, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices can be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In this scenario, such as... Figure 1 As shown, the computer system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0055] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0056] As an example, Figure 2 This is a schematic diagram of the structure of a memory card involved in this application. Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 40. The memory card 40 may include PCMCIA (PC) cards, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 40 may also include a connector 410 for coupling the memory card 40 to the host.

[0057] As another example Figure 3 This is a schematic diagram of the structure of a solid-state drive involved in this application. Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 50. The solid-state drive 50 may also include a connector 510 for coupling the solid-state drive 50 to the host. The storage capacity and / or operating speed of the solid-state drive 50 is greater than that of the memory card 40.

[0058] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0059] Figure 4 This is a block diagram illustrating a memory according to an exemplary embodiment of this application. (Reference) Figure 4 The memory 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, a control logic unit 412, a register 414, and data input / output circuitry 416. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0060] Page buffer 404 can be configured to read data from memory cell array 401 and program (write) data to memory cell array 401 according to control signals from control logic unit 412. In one example, page buffer 404 can store data to be programmed into selected pages of memory cell array 401 (write data). In another example, page buffer 404 can output read data during a programming verification operation to ensure that data has been correctly programmed into the corresponding memory cell coupled to the selected word line of memory cell array 401. Column decoder 406 can operate in response to control signals provided by control logic unit to select one or more NAND memory strings in memory cell array 401. Row decoder can operate in response to control signals provided by control logic unit and select / deselect selected rows of memory cell array 401. Row decoder can also be configured to supply voltage generated from voltage generator 410 to selected and unselected word lines of memory cell array 401. As described in detail below, row decoder / word line driver 408 is configured to perform erase operations on memory cells coupled to one or more selected word lines of memory cell array 401. Voltage generator 410 can use external or internal power supply voltages to generate various voltages required by the memory, such as programming voltage, read voltage, pass voltage, verification voltage, bit line voltage, and combinations thereof.

[0061] Control logic unit 412 may be coupled to voltage generator 410, page buffer 404, column decoder 406, row decoder 408, and data input / output circuitry 416, and is configured to control the operation of each peripheral circuit. Control logic unit can generate operation signals in response to commands or control signals from the memory controller. Register 414 may be coupled to control logic unit 412 and includes a status register, command register, and address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Data input / output circuitry 416 may be coupled to control logic unit 412 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 412, as well as to buffer status information received from control logic unit 412 and relay it to the host. Data input / output circuitry 416 may also be coupled to column decoder and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 401.

[0062] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application. Figure 5As shown, memory 500 may include a memory cell array device 501 and peripheral circuitry 502 coupled to the memory cell array device 501. The memory cell array device 501 may be a NAND flash memory cell array, wherein memory cells 506 are provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In some embodiments, each memory cell 506 is a single-level cell (SLC) having two possible memory states and capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 506 is a multilevel cell capable of storing more than a single bit of data in more than two memory states. For example, each cell can store two bits (i.e., Multi-Level Cell (MLC)), three bits (i.e., Triple-Level Cell (TLC)), or four bits (i.e., Quad-Level Cell (QLC)).

[0063] like Figure 5 As shown, each NAND memory string 508 may include at least one source select transistor 510 at its source end and at least one drain select transistor 512 at its drain end. The source select transistor 510 and drain select transistor 512 may be configured to activate a selected NAND memory string 508 during read and program operations. In some embodiments, the sources of NAND memory strings 508 in the same block 504 are coupled via the same source line (SL). According to some embodiments, the drain select transistor 512 of each NAND memory string 508 is coupled to a corresponding bit line 516. In some embodiments, each NAND memory string 508 is configured to be selected or deselected by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding drain select transistor 512 via one or more drain select lines 515 and / or by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding source select transistor 510 via one or more source select lines 515.

[0064] like Figure 5As shown, the memory cell array may include multiple blocks. In some embodiments, each block 504 is a basic data unit for erase operations, that is, all memory cells 506 on the same block 504 are erased simultaneously.

[0065] Figure 6 This is a perspective view of a portion of a three-dimensional memory array structure illustrated in an exemplary embodiment of this application. The memory cell array structure 600 includes a substrate 630 and a stacked structure above the substrate 630. The stacked structure includes alternately stacked gate conductive layers and interlayer dielectric layers. The substrate 630 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The gate conductive layers may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer includes a doped polycrystalline silicon layer. The gate conductive layers may include multiple word lines 633, at least one source select line 632, and at least one drain select line 634.

[0066] like Figure 6 As shown, the memory cell array 600 includes a plurality of channel structures 612 extending vertically through the memory stack structure 635. In some embodiments, the channel structure 612 includes a memory film 637 and a channel 638. Figure 6 As shown, according to some embodiments, a well 644 (e.g., a P-well and / or an N-well) is formed in the substrate 630, and the source ends of the memory cell array are in contact with the well 644. It should be understood that, although... Figure 6 Additional components that may form the memory cell array 600, but not shown in the diagram, include (but are not limited to) gate line slits / source contacts, local contacts, interconnect layers, etc.

[0067] For any technical details not disclosed in the above memory-related hardware embodiments, please refer to the descriptions of the computer system embodiments and method embodiments of this application for understanding.

[0068] Please refer to Figure 7 It shows a schematic diagram of the connection between a NAND flash memory cell array and a page buffer. For example... Figure 7 As shown, the memory cell array 71 contains several bit lines, namely BL0 to BLK. Correspondingly, the page buffer 72 contains K+1 page buffers, namely page buffer 720 to page buffer 72K. Each bit line is connected to an independent page buffer.

[0069] Please refer to Figure 8This illustrates a connection diagram of another NAND flash memory cell array and page buffer. (See diagram for example.) Figure 8 As shown, the memory cell array 81 contains several bit lines, BL0 to BLK, and the page buffer 82 contains k+1 page buffers, 820 to 82k, where the value of k is less than the value of K. Figure 8 In the structure shown, the bit line BL[0 K] is connected to the page buffer via switching device 83, and... Figure 7 Compared to the architecture shown, this reduces the number of page buffers. For example, two or more bit lines can be connected to the same page buffer, which reduces the number of page buffers used. Figure 8 The NAND shown can also be called X-NAND.

[0070] exist Figure 7 or Figure 8 In the NAND flash memory shown, each page buffer has only one bit line connection point. Conversely, for multiple bit line connection points, a separate page buffer is required. However, because the page buffer circuitry is relatively large, typically occupying about 20% to 40% of the die size, the number of page buffers in NAND flash memory is usually limited, which affects the capacity and performance of NAND flash. Specifically, when the number of page buffers is limited, the number of bit lines connected to the page buffers is limited, thus limiting the storage capacity of the NAND flash memory; furthermore, when the number of page buffers is limited, the concurrency of the programming process is limited, thereby limiting the write speed of NAND flash.

[0071] In response, the solutions shown in the subsequent embodiments of this application provide a new circuit structure for a page buffer and an operation method based on this circuit structure, which can reduce the overall size of the page buffer in the memory while keeping the number of bit lines in the memory constant, and increase the number of bit lines in the memory while keeping the size of the memory die constant.

[0072] Please refer to Figure 9 This is a framework diagram of a memory provided in an exemplary embodiment of this application. The memory may be as follows: Figure 1 The memory 100 in the system 10 shown, or, could be Figure 4 or Figure 5 The memory 400 or memory 500 shown. For example... Figure 9 As shown, the memory includes peripheral circuitry 910 and a memory cell array 920.

[0073] like Figure 9As shown, the peripheral circuit 910 includes a plurality of page buffers 912, and a control logic circuit 914 coupled to the plurality of page buffers 912 and configured to control the plurality of page buffers 912.

[0074] like Figure 9 As shown, the page buffer 912 includes a first bit line connection point 912a, a second bit line connection point 912b, a first switching device 912c, and a second switching device 912d.

[0075] The bit line connection point mentioned above refers to the point where the page buffer 192 is connected to the bit line BL.

[0076] The first switching device 912c and the second switching device 912d mentioned above can be metal-oxide-semiconductor field-effect transistors (MOSFETs), which can be simply referred to as MOS transistors.

[0077] like Figure 9 As shown, the first bit line connection point 912a and the second bit line connection point 912b are used to connect the bit lines in the memory cell array 920; the first bit line connection point 912a and the second bit line connection point 912b are respectively connected to the power supply terminal 912f through an independent precharge circuit 912e, and the first bit line connection point 912a and the second bit line connection point 912b are respectively connected to the latch 912g in the page buffer 912; the precharge circuit 912e is the circuit for the page buffer 912 to precharge the bit lines.

[0078] like Figure 9 As shown, the first switching device 912c is connected to the first bit line connection point 912a and the second bit line connection point 912b; the second switching device 912d is located on the pre-charge circuit 912e corresponding to the second bit line connection point 912b.

[0079] In summary, the solution shown in this application embodiment, for multiple page buffers in the peripheral circuit of the memory, each page buffer includes two bit line connection points, each with an independent precharge circuit. These two bit line connection points are respectively connected to the bit lines in the memory cell array and the latches in the page buffer. Furthermore, these two bit line connection points are connected via a first switching device, and a second switching device is also provided on the precharge circuit of one of the bit line connection points. In the above solution, when the two bit line connection points in the page buffer respectively perform precharge of the bit lines during programming, they can share part of the circuit structure in the page buffer. Specifically, for example, during the precharge stage of programming, the first switching device is disconnected, while the second switching device is connected, allowing the two... Each bit line connection point precharges the bit line through its own precharge circuit. During the read process, the second switching device is disconnected, and the first switching device is connected to read the memory cell coupled to either bit line. This allows the two bit line connection points to share the circuit structure of the sensing part. Through the above scheme, two or more bit line connection points can be integrated into a page buffer and share part of the circuit structure in the page buffer. It is not necessary to set a page buffer for each bit line connection point. This reduces the overall size of the page buffer in the memory while keeping the number of bit lines in the memory constant, and increases the number of bit lines in the memory while keeping the size of the memory die constant, thereby improving storage capacity and performance.

[0080] Among them, Figure 9 In the circuit structure shown, a page buffer 912 includes two bit line connection points, optionally one based on... Figure 9 As shown in the circuit structure, a page buffer 912 can also contain two or more bit line connection points. For example, a page buffer 912 can contain one first bit line connection point 912a and two or more second bit line connection points 912b.

[0081] For example, based on Figure 9 The circuit structure shown, taking a page buffer 912 containing one first bit line connection point 912a and two second bit line connection points 912b as an example, please refer to [reference needed]. Figure 10 The diagram illustrates a structural schematic of a page buffer according to an embodiment of this application. Figure 10As shown, a page buffer 912 includes a first bit line connection point 912a and two second bit line connection points 912b. The two second bit line connection points 912b are connected to the first bit line connection point 912a through a first switching device 912c (that is, there are two first switching devices 912c). The two second bit line connection points 912b and the first bit line connection point 912a each have an independent pre-charge circuit (that is, there are three independent pre-charge circuits). The pre-charge circuits 912e corresponding to the two second bit line connection points 912b each have a second switching component 912d (that is, there are two second switching components 912d).

[0082] in, Figure 10 The following is an example of a page buffer containing one first bit line connection point 912a and two second bit line connection points 912b. Optionally, a page buffer may also have three or more second bit line connection points 912b.

[0083] In one possible implementation, based on Figure 9 or Figure 10 The circuit architecture shown allows the control logic circuit 914 to ensure the accurate execution of programming and reading operations by controlling the on / off states of the first switching device 912c and the second switching device 912d during the programming and reading processes.

[0084] Specifically, the control logic circuit 914 is configured to disconnect the first switching device 912c and connect the second switching device 912d when programming is performed through the page buffer 912;

[0085] The control logic circuit 914 is configured to turn on the first switching device 912c and turn off the second switching device 912d when a read operation is performed through the page buffer 912.

[0086] For example, in Figure 9 In the circuit structure shown, when the first switching device 912c is off and the second switching device 912d is on, the independent pre-charge circuits of the first bit line connection point 912a and the second bit line connection point 912b can be in a conducting state. At the same time, the independent pre-charge circuits of the first bit line connection point 912a and the second bit line connection point 912b can not interfere with each other. At this time, programming operations are performed through the page buffer 912, and the bit lines in the memory cell array 920 can be pre-charged simultaneously through the two bit line connection points, thereby realizing concurrent programming operations on memory cells with different bit line couplings in the memory cell array 920.

[0087] For example, in Figure 9In the circuit structure shown, when the first switching device 912c is turned on and the second switching device 912d is turned off, the pre-charging circuit of the second bit line connection point 912b is turned off, while the pre-charging circuit of the first bit line connection point 912a can be turned on. At the same time, since the first switching device 912c between the first bit line connection point 912a and the second bit line connection point 912b is turned on, the two bit line connection points can share a pre-charging circuit (that is, the pre-charging circuit of the first bit line connection point 912a). At this time, if the circuits between the two bit line connection points and the bit lines in the memory cell array 920 are turned on in sequence, different bit lines in the memory cell array 920 can be pre-charged in sequence through the pre-charging circuit of the first bit line connection point 912a, and thus the memory cells coupled to the bit lines of the memory cell array 920 can be sensed / read in sequence through the two bit line connection points.

[0088] The process of precharging different bit lines in the memory cell array 920 through the pre-charging circuit of the first bit connection point 912a, thereby enabling the sensing / reading of memory cells coupled to the bit lines of the memory cell array 920 through the two bit connection points in sequence, can be achieved by sequentially connecting the two bit connection points to the bit lines.

[0089] For example, based on Figure 9 Please refer to the proposed solution. Figure 11 This illustrates a schematic diagram of another page buffer structure according to an embodiment of this application. Figure 11As shown, the page buffer also includes a fourth switching device 912h and a fifth switching device 912i. The fourth switching device 912h is located in the circuit between the first bit line connection point 912a and the first switching device 912c, and in the circuit between the first bit line connection point 912a and the power supply terminal 912f, but outside the circuit between the first switching device 912c and the power supply terminal 912f. Correspondingly, the fifth switching device 912i is located in the circuit between the second bit line connection point 912b and the first switching device 912c, and in the circuit between the second bit line connection point 912a and the power supply terminal 912f. The circuit between contact 912b and power supply terminal 912f is located outside the circuit between the first switching device 912c and power supply terminal 912f. During the read operation, the control logic circuit 914 first connects the first switching device 912c and disconnects the second switching device 912d. When reading through the first line connection point 912a, the fourth switching device 912h is connected and the fifth switching device 912i is disconnected. At this time, the first line connection point 912a can be connected through the pre-charge circuit corresponding to the first line connection point 912a. The bit lines are pre-charged. After pre-charging, the sense amplification circuit in the page buffer and the sense latch in the latch 912g can sense / read the memory cell coupled to the bit line connected to the first bit line connection point 912a. Correspondingly, when reading through the second bit line connection point 912b, the fourth switch device 912h is disconnected and the fifth switch device 912i is connected. At this time, the pre-charging circuit corresponding to the first bit line connection point 912a can pass through the first switch device 912c and the second bit line connection point 912b to sense / read the memory cell coupled to the bit line connected to the first bit line connection point 912a. The bit line connected to the bit line at bit line connection point 912b is precharged. After precharging, the memory cell coupled to the bit line connected to the second bit line connection point 912b can be sensed / read through the sense amplification circuit in the page buffer and the sense latch in the latch 912g. In other words, during the read operation, the first bit line connection point and the second bit line connection point can share a precharge circuit. Correspondingly, they also share the circuits corresponding to the sense amplification circuit and the sense latch, so that the two bit line connection points can share the circuits in the page buffer used for sensing / reading.

[0090] Among them, the above Figure 11 The page buffer structure shown is illustrated using an example of a page buffer containing one first bit line connection point 912a and one second bit line connection point 912b. Optionally, the page buffer may also contain two or more second bit line connection points 912b.

[0091] For example, consider a page buffer containing one first bit line connection point 912a and two second bit line connection points 912b. Please refer to [reference needed]. Figure 12 This illustrates a schematic diagram of another page buffer structure according to an embodiment of this application. Figure 12 As shown, for the two second bit line connection points 912b in the page buffer, each second bit line connection point 912b corresponds to a fifth switching device 912i. Each fifth switching device 912i is located in the circuit between the corresponding second bit line connection point 912b and the first switching device 912c, and in the circuit between the corresponding second bit line connection point 912b and the power supply terminal 912f, and is located outside the circuit between the first switching device 912c and the power supply terminal 912f. During the read operation, the control logic circuit 914 first connects all the first switching devices 912c and disconnects all the second switching devices 912d. When reading through the first bit line connection point 912a, the fourth switching device 912h is connected. Connect and disconnect all fifth switching devices 912i; when reading through a certain second bit line connection point 912b, disconnect the fourth switching device 912h, connect the fifth switching device 912i corresponding to the current second bit line connection point 912b, and disconnect the fifth switching device 912i corresponding to another second bit line connection point 912b. At this time, the bit line connected to the current second bit line connection point 912b can be precharged through the precharge circuit corresponding to the first bit line connection point 912a. After the precharge is completed, the memory cell coupled to the bit line connected to the current second bit line connection point 912b can be sensed / read through the sensing amplification circuit in the page buffer and the sensing latch in the latch 912g.

[0092] Similarly, in Figure 12 Based on the circuit structure shown, if a page buffer contains three or more second bit line connection points 912b, when reading through one of the second bit line connection points 912b, the fifth switching device 912i corresponding to the current second bit line connection point 912b is connected, and the fourth switching device 912h and the fifth switching device 912i corresponding to the other second bit line connection points 912b are disconnected.

[0093] In one possible implementation of this application, a third switching device 912j is provided between the first line connection point and the sensing latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first line connection point.

[0094] In this embodiment of the application, during the read operation, since two or more bit line connection points share the pre-charge circuit corresponding to the first bit line connection point for pre-charging, that is, the page buffer needs to have a circuit between the first bit line connection point and the sensing latch. However, during the programming process, the circuit between the first bit line connection point and the sensing latch needs to be disconnected. In this embodiment of the application, a third switching device 912j can be set between the first bit line connection point and the sensing latch in the page buffer.

[0095] It should be noted that the aforementioned third switching device 912j is also located on the circuit of sensing latch → first switching device 912c → second bit line connection point 912b.

[0096] Meanwhile, the aforementioned third switching device 912j is also located between the first line connection point and other circuit elements in the page buffer used for sensing / reading.

[0097] In one possible implementation of this application, the control logic circuit 914 is configured to disconnect the third switching device 912j when a programming operation is performed through the page buffer 912; the control logic circuit 914 is configured to turn on the third switching device 912j when a read operation is performed through the page buffer 912.

[0098] In this embodiment of the application, during the programming operation, the control logic circuit 914 can control the third switching device 912j to be turned off, thereby avoiding the programming process from affecting the sensing latch and other circuit elements used for sensing / reading; correspondingly, during the read operation, the control logic circuit 914 can control the third switching device 912j to be turned on, so that the sensing latch and other circuit elements used for sensing / reading can correctly perform read operations on the currently connected bit-line coupled memory cells.

[0099] For example, in Figure 11 Based on this, please refer to Figure 13 This illustrates a schematic diagram of another page buffer structure according to an embodiment of this application. Figure 13 As shown, the latch 912g of the page buffer 912 includes a sensing latch 912k and other latches (e.g., an LVT latch). Corresponding to this sensing latch, it also includes a grounded capacitor element 912m. When the fourth switching device 912h is turned on, both the sensing latch 912k and the capacitor element 912m can be connected to the first bit line connection point 912a. When the first switching device 912c is turned on, the sensing latch 912k and the capacitor element 912m can also be connected to the corresponding second bit line connection point 912b. To avoid the read operation affecting the sensing latch 912k and the capacitor element 912m, in Figure 13 In this configuration, a third switch 912j is positioned between the sensing latch 912k / capacitor element 912m and the two bit line connection points. During programming, the third switch 912j is disconnected to prevent programming operations from affecting the sensing latch 912k and capacitor element 912m; during read operations, the third switch 912j is turned on, allowing read operations to be performed through the sensing latch 912k and capacitor element 912m.

[0100] In the above Figure 13 In this configuration, capacitor element 912m is a grounded capacitor. Optionally, capacitor element 912m may not be grounded; for example, it may be connected to any fixed potential. Furthermore, capacitor element 912m may be a pre-designed and manufactured capacitor, or it may be a parasitic capacitance.

[0101] Among them, the above Figure 13 The page buffer structure shown still applies to cases where a page buffer contains two or more second bit line connection points 912b. For example, please refer to... Figure 14 This illustrates a schematic diagram of another page buffer structure according to an embodiment of this application. Figure 14 As shown, when the fourth switching device 912h is turned on, the sensing latch 912k and the capacitor element 912m can both be connected to the first bit line connection point 912a. When a certain first switching device 912c is turned on, the sensing latch 912k and the capacitor element 912m can also be connected to the second bit line connection point 912b corresponding to that first switching device 912c. To avoid the reading operation affecting the sensing latch 912k and the capacitor element 912m, in Figure 14 In this circuit, a third switching device 912j is provided between the sensing latch 912k / capacitor element 912m and the three bit line connection points.

[0102] In one possible implementation of this application, a sixth switch device 912p and a seventh switch device 912q are further provided on the pre-charge circuit corresponding to the second bit line connection point 912b, between the second switch device 912d and the power supply terminal 912f. The sixth switch device 912p is controlled to be turned on or off by a register 912g. For example, when the register 912g has sufficient voltage output, the sixth switch device 912p is turned on. Specifically, at least during programming, the register 912g will control the sixth switch device 912p to be turned on. The seventh switch device 912q can be controlled by the control logic circuit 914. The control logic circuit can control the connection or disconnection of the seventh switch 912q. For example, outside of the programming process, when the register 912g has sufficient voltage output, the sixth switch 912p will be turned on. If the control logic circuit 914 is controlling the page buffer to perform a read operation at this time, the power supply terminal 912f will affect the capacitor element 912m. In response, the control logic circuit 914 can control the seventh switch 912q to turn off to ensure the correct execution of the read operation. However, during the programming process, when it is necessary to precharge the bit line connected to the second bit line connection point 912b, the control logic circuit 914 can control the seventh switch 912q to turn on to ensure successful precharging.

[0103] For example, please refer to Figure 15This illustrates a schematic diagram of another page buffer structure according to an embodiment of this application. Figure 15 As shown, in the pre-charge circuit corresponding to the second bit line connection point 912b, a sixth switching device 912p and a seventh switching device 912q are sequentially arranged near the power supply terminal 912f. The on / off state of the sixth switching device 912p is controlled by register 912g. Furthermore, the seventh switching device 912q is controlled by control logic circuit 914. During the programming operation, in the pre-charging stage of the bit line through the second bit line connection point 912b, register 912g outputs a voltage, controlling the sixth switching device 912p to turn on. Simultaneously, control logic circuit 914 controls... The seventh switch 912q, the second switch 912d, and the fifth switch 912i corresponding to the second bit line connection point 912b are turned on. At this time, the pre-charging circuit from the power supply terminal 912f to the second bit line connection point 912b is turned on, which can realize pre-charging. During the read operation, the register 912g may have a voltage output, that is, the sixth switch 912p may be in the on state. At this time, the control logic circuit 914 needs to control the seventh switch 912q to turn off in order to prevent the voltage output from the power supply terminal 912f from being applied to the capacitor element 912m.

[0104] Among them, the pre-charging circuit corresponding to the first line connection point 912a has two switching devices with the same function and connection method as the sixth switching device 912p and the seventh switching device 912q, which will not be described in detail here.

[0105] In addition, the aforementioned sixth switching device 912p and seventh switching device 912q are also applicable to the circuit structure of multiple second bit line connection points 912b. That is, when the page buffer 912 contains two or more second bit line connection points 912b, the aforementioned sixth switching device 912p and seventh switching device 912q are respectively included in the pre-charge circuit corresponding to each second bit line connection point 912b.

[0106] Based on the above Figures 9 to 15 Please refer to the proposed solution. Figure 16 This document illustrates a circuit diagram of a page buffer according to an exemplary embodiment of this application. Taking a page buffer containing two bit line connection points as an example, the positions of the first bit line connection point 912a, the second bit line connection point 912b, the first switching device 912c, the second switching device 912d, the precharge circuit 912e, the power supply terminal 912f, the fourth switching device 912h, the fifth switching device 912i, the third switching device 912j, the sensing latch 912k, the capacitor element 912m, the sixth switching device 912p, and the seventh switching device 912q are as follows: Figure 16 As shown.

[0107] exist Figure 16 In this circuit, the first switching device 912c can be turned on by the SW1 signal, the second switching device 912d can be turned on by the VSOBLK_1 signal, the third switching device 912j can be turned on by the VSOBLK_0 signal, the fourth switching device 912h can be turned on by the VPASS_HV0 signal, the fifth switching device 912i can be turned on by the VPASS_HV1 signal, and the seventh switching device 912q can be turned on by the EN_4BL_B signal.

[0108] Specifically, for the first line connection point 912a, the switching device corresponding to the sixth switching device 912p is the eighth switching device 912s, and the switching device corresponding to the seventh switching device 912q is the ninth switching device 912t. The ninth switching device 912t can be turned on by the VBLCLAMP signal.

[0109] Based on the above Figures 5 to 16 In any of the schemes shown, in the memory involved, two bit line connection points can each connect to multiple bit lines.

[0110] In one possible implementation of this application, the first bit connection point is connected to N bit lines out of the 2×N bit lines included in the memory cell array, and the second bit connection point is connected to the other N bit lines out of the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent to each other in sequence, and the bit lines connected by the first bit connection point and the second bit connection point are arranged alternately in sequence.

[0111] Please refer to Figure 17 This illustrates a schematic diagram of the connection between a page buffer and a bit line according to an embodiment of this application. Figure 17 As shown, the memory cell array contains at least 2×N sequentially adjacent bit lines, numbered BL0 to BL2N-1. The first bit line connection point 912a and the second bit line connection point 912b are connected to N bit lines via switching devices 922. Furthermore, the bit lines connected by the first and second bit line connection points are arranged in an alternating pattern. That is, in the aforementioned 2×N bit lines, in every two adjacent bit lines, one bit line is connected to the first bit line connection point 912a via switching device 922, and the other bit line is connected to the second bit line connection point 912b via switching device 922. Specifically, for example, in... Figure 17 In the middle, the first line connection point 912a is connected to BL0, BL2, ... BL2N-2 through switching device 922, and the second line connection point 912b is connected to BL1, ... BL2N-3, BL2N-1 through switching device 922.

[0112] The aforementioned switching device 922 can be used to connect a bit line connection point to one of the corresponding N bit lines at the same time point, and disconnect the bit line connection point from the other N-1 bit lines among the corresponding N bit lines. Different bit line connection points can simultaneously connect to their respective corresponding bit lines.

[0113] In one possible implementation of this application, the control logic circuit 914 is configured to apply a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer 912; wherein the first bit line and the second bit line are two adjacent bit lines in 2×N bit lines.

[0114] The page buffer involved in the above embodiments of this application, and the connection relationship between the two bit line connection points in the page buffer and the bit lines in the memory cell array, can be used to remove the BL-BL coupling during programming operations.

[0115] Specifically, parasitic capacitance is an unavoidable and generally unwanted type of capacitance that exists between various parts of electronic components or circuits simply because they are close to each other. When two conductors with different voltages are placed together, the electric field between them causes charge to be stored on these two conductors; this effect is called capacitance. In high-density memory cell arrays, the bit lines may be very long and the spacing between them may be very tight. When the bit lines are close together, mutual capacitance will occur between them. This mutual capacitance is like a parasitic presence between wirings, and therefore can be called parasitic capacitance, also known as stray capacitance. Due to the existence of parasitic capacitance between bit lines, when the page buffer performs programming operations on multiple bit lines sequentially, it may cause bit line-to-bit line coupling problems; for example, as mentioned above... Figure 17 For example, at time 1, the page buffer programs BL0. After programming BL0, at time 2, the page buffer programs BL1. Since BL0 and BL1 are adjacent bit lines and are close together, parasitic capacitance exists between them. When the page buffer programs BL1, coupling occurs between BL1 and BL0, causing changes to the data already stored in the memory cell of BL0, resulting in data errors. Similarly, at time 3, after programming BL1, the page buffer programs BL2. Since BL1 and BL2 are adjacent bit lines and are close together, parasitic capacitance exists. When the page buffer programs BL2, coupling occurs between BL1 and BL2, causing changes to the data already stored in the memory cell of BL1, resulting in data errors.

[0116] Regarding the above issues, based on the above in this application Figure 17 The bit line connection method shown is such that, since two adjacent bit lines are connected to different bit line connection points in a page buffer, and each bit line connection point has its own independent precharge circuit, when the page buffer performs a programming operation on the memory cell coupled to the first bit line through one bit line connection point, since the adjacent second bit line is connected to another bit line connection point, the page buffer can apply a bias voltage to the second bit line through the precharge circuit corresponding to the other bit line connection point, thereby suppressing the coupling between the first bit line and the second bit line.

[0117] For example, in Figure 17 At time 1, the page buffer begins programming BL0 through the first bit connection point. During this programming operation, the page buffer can apply a bias voltage to BL1 through the second bit connection point, thereby suppressing the coupling between BL0 and BL1. Similarly, at time 2, the page buffer begins programming BL1 through the second bit connection point. During this programming operation, the page buffer can apply a bias voltage to BL0 through the first bit connection point, thereby suppressing the coupling between BL0 and BL1.

[0118] In one possible implementation of this application, the control logic circuit is configured to apply programming pulse voltages sequentially to the 2×N bit lines through the first bit line connection point and the second bit line connection point, according to the arrangement order of the 2×N bit lines, when programming a memory cell coupled to 2×N bit lines via a page buffer; wherein the time intervals for applying programming pulse voltages to two adjacent bit lines overlap, so as to apply bias voltages to adjacent bit lines during the programming operation of a memory cell coupled to a bit line.

[0119] In the above embodiment, the page buffer begins programming BL0 through the first bit connection point. During this programming operation, the page buffer applies a bias voltage to BL1 through the second bit connection point. If the bias voltage applied to BL1 through the second bit connection point is only used to eliminate the coupling between BL0 and BL1, the page buffer will be unable to perform programming operations through the second bit connection point. This will affect the concurrent performance of the programming operation, resulting in excessively long programming time and thus affecting the data write rate.

[0120] To address this, the solution presented in this application provides a timing design for programming memory cells coupled to adjacent bit lines via two bit line connection points. Specifically, when the page buffer programs the memory cell coupled to the first bit line via the first bit line connection point, after the programming operation begins but before it ends, the page buffer begins programming the memory cell coupled to the second bit line adjacent to the first bit line via the second bit line connection point. Since the programming operation to the memory cell coupled to the first bit line has not yet ended and a programming pulse voltage is still being applied to the first bit line via the first bit line connection point, the programming pulse voltage (i.e., the aforementioned bias voltage) applied by the page buffer to the second bit line via the second bit line connection point will not cause coupling between the first and second bit lines. Correspondingly, when the page buffer finishes programming the memory cell coupled to the first bit line through the first bit line connection point, it can start programming the memory cell coupled to the next adjacent third bit line through the first bit line connection point. At this time, the programming operation on the memory cell coupled to the second bit line has not yet ended, and a programming pulse voltage is still being applied to the second bit line through the second bit line connection point. Therefore, the programming pulse voltage (i.e., the aforementioned bias voltage) applied by the page buffer to the third bit line through the first bit line connection point will not cause coupling between the second and third bit lines, and so on. Through the execution timing of the above programming operation, the scheme shown in this application can suppress the coupling between adjacent bit lines without affecting the concurrent performance of programming operations performed through two bit line access points.

[0121] Please refer to the following: Figure 18 This illustrates an execution timing diagram of a programming operation according to an embodiment of this application. Figure 18 As shown, the first bit line connection point and the second bit line connection point in the page buffer are connected according to... Figure 17 The connection method shown takes four bit lines as an example. Assume the first bit line connection point is connected to BL0, BL2, BL4, and BL6 respectively via switch devices 0, 2, 4, and 6; the second bit line connection point is connected to BL1, BL3, BL5, and BL7 respectively via switch devices 1, 3, 5, and 6; where BL0~BL7 correspond to the programmable data D0~D7 respectively. Figure 18 As shown, the time intervals corresponding to switching devices 0 through 7 are the turn-on times for each of them, and the time intervals corresponding to D0 through D7 are the loading times for each of them. Figure 18As can be seen, the turn-on times of the switching devices corresponding to two adjacent bit lines are interleaved according to the order from BL 0 to BL 7, thereby ensuring that when programming begins on one bit line, the programming operation on the adjacent previous bit line has not yet ended, thus suppressing the coupling between the two bit lines.

[0122] pass Figure 17 The bit line connection method shown and Figure 18 The programming operation timing shown can guarantee the suppression of coupling between the eight bit lines BL0 to BL7. However, when there is an adjacent bit line (such as BL8) after BL7, since BL8 is the bit line corresponding to other page buffers, when other page buffers start programming the memory cell coupled to BL8, if BL7 is not currently being programmed, the programming operation of BL8 will cause BL8 to couple to BL7. If BL7 has already completed its programming operation, the data in BL7 will be changed, resulting in data errors. In response, the solution shown in this embodiment can coordinate the programming operations of the two page buffers through control logic circuits, so that the programming operations of different page buffers on the memory cells coupled to BL7 and BL8 are performed at the same time or overlap.

[0123] In one possible implementation of this application, for 4×N bit lines in the memory cell array that are sequentially adjacent to two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the reverse of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

[0124] Specifically, for a series of consecutive 4×N bit lines, the two parts of these 4×N bit lines will be connected to different page buffers, for example, please refer to... Figure 19 This illustrates a schematic diagram of the connection between a page buffer and a bit line according to an embodiment of this application. Figure 19 As shown, the memory cell array contains at least 4×N sequentially adjacent bit lines, numbered BL0 to BL4N-1. The first bit line connection point 912a and the second bit line connection point 912b of the page buffer 1 are connected to N bit lines out of the first 2×N bit lines via switching devices 922. Furthermore, the bit lines connected to the first and second bit line connection points are arranged in an alternating pattern. For example, in… Figure 19In the page buffer 1, the first bit line connection point 912a is connected to BL0, BL2, ..., BL2N-2 via switching devices 922, and the second bit line connection point 912b is connected to BL1, ..., BL2N-3, BL2N-1 via switching devices 922. Correspondingly, the first bit line connection point 912a and the second bit line connection point 912b of the page buffer 2 are connected to N bit lines in the last 2×N bit lines via switching devices 922. Furthermore, the bit lines connected by the first and second bit line connection points are arranged in an alternating pattern. For example, in... Figure 19 In the middle, the first bit connection point 912a of page buffer 2 is connected to BL 2N, BL 2N+2, ... BL 4N-2 through switching device 922, and the second bit connection point 912b of page buffer 2 is connected to BL 2N+1, ..., BL 4N-3, BL4N-1 through switching device 922.

[0125] Among them, combined Figure 19 Please refer to Figure 20 This illustrates a timing diagram of the execution of another programming operation involved in an embodiment of this application. For example... Figure 20 As shown, the first bit line connection point and the second bit line connection point in page buffer 1 and page buffer 2 are connected according to... Figure 19 The connection method shown takes four bit lines as an example. Assume the first bit line connection point in page buffer 1 is connected to BL0, BL2, BL4, and BL6 via switches 0, 2, 4, and 6 respectively; the second bit line connection point in page buffer 1 is connected to BL1, BL3, BL5, and BL7 via switches 1, 3, 5, and 6 respectively; the first bit line connection point in page buffer 2 is connected to BL8, BL10, BL12, and BL14 via switches 8, 10, 12, and 14 respectively; and the second bit line connection point in page buffer 2 is connected to BL9, BL11, BL13, and BL15 via switches 9, 11, 13, and 15 respectively. The data to be programmed corresponding to BL0~BL15 are D0~D15 respectively. Figure 20 As shown, the time intervals corresponding to switching devices 0 to 15 are the turn-on times of each of them, and the time intervals corresponding to D0 to D15 are the loading times of each of them; from Figure 20As can be seen, the turn-on times of the switching devices corresponding to two adjacent bit lines are interleaved in the order from BL0 to BL7, and the turn-on times of the switching devices corresponding to two adjacent bit lines are interleaved in the order from BL15 to BL8. This ensures that when programming begins on one bit line, the programming operation on the adjacent previous bit line has not yet ended. At the same time, the two page buffers can perform programming operations synchronously, and the programming operation times of BL7 and BL8 are the same, thereby suppressing the coupling between any two adjacent bit lines in each bit line corresponding to the two page buffers.

[0126] Figure 21 This is a flowchart illustrating an exemplary embodiment of a memory operation method provided in this application. The method is applied to a memory and executed by control logic circuitry in the memory's peripheral logic circuitry; wherein the memory can be, for example... Figure 9 , Figure 17 or Figure 19 The memory shown; as Figure 21 As shown, the method includes the following.

[0127] Step 2101: When performing programming operations through the page buffer, disconnect the first switching device and connect the second switching device.

[0128] Step 2102: When performing a read operation through the page buffer, turn on the first switching device and turn off the second switching device.

[0129] In one possible implementation of this application, a third switching device is provided between the first line connection point and the latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first line connection point.

[0130] In one possible implementation of this application, the method further includes: disconnecting the third switching device when performing a programming operation through the page buffer; and turning on the third switching device when performing a read operation through the page buffer.

[0131] In one possible implementation of this application, the first bit connection point is connected to N bit lines out of the 2×N bit lines included in the memory cell array, and the second bit connection point is connected to the other N bit lines out of the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent to each other in sequence, and the bit lines connected by the first bit connection point and the second bit connection point are arranged alternately in sequence.

[0132] In one possible implementation of this application, the method further includes: applying a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer; wherein the first bit line and the second bit line are two adjacent bit lines in 2×N bit lines.

[0133] In one possible implementation of this application, during the programming operation of the memory cell coupled to the first bit line via the page buffer, applying a bias voltage to the second bit line includes: when programming the memory cell coupled to 2×N bit lines via the page buffer, applying programming pulse voltages sequentially to the 2×N bit lines through the first bit line connection point and the second bit line connection point, according to the arrangement order of the 2×N bit lines; wherein, the time intervals for applying programming pulse voltages to two adjacent bit lines overlap, so as to apply bias voltages to adjacent bit lines during the programming operation of a memory cell coupled to one bit line.

[0134] In one possible implementation of this application, for 4×N bit lines in the memory cell array that are sequentially adjacent to two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the reverse of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

[0135] Figure 22 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 22 As shown, the storage system 2200 includes: one or more memories 2210, and,

[0136] A controller 2220 is coupled to memory 2210 and configured to control memory 2210.

[0137] Storage system 2200 may be all or part of a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0138] Optionally, the storage system 2200 may include a host and a storage subsystem, the storage subsystem having one or more memories 2210 and a controller 2220. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 2210. Alternatively, the host may be configured to receive data from the memory 2210.

[0139] According to some implementations, controller 2220 is also coupled to a host. Controller 2220 can manage data stored in memory 2210 and communicate with the host.

[0140] In some implementations, the controller 2220 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0141] In some implementations, the controller 2220 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0142] Controller 2220 can be configured to control operations of memory 2210, such as read, erase, and program operations. Controller 2220 can also be configured to manage various functions relating to data stored or to be stored in memory 2210, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 2220 is also configured to process error correction codes (ECC) relating to data read from or written to memory 2210.

[0143] The controller 2220 can also perform any other suitable functions, such as formatting the memory 2210. The controller 2220 can communicate with external devices according to a specific communication protocol.

[0144] The controller 2220 and one or more memories 2210 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash memory (UFS) package or an eMMC package). That is, the memory system 2200 can be implemented and packaged into different types of end electronic products.

[0145] Schematic illustration: the controller 2220 and a single memory 2210 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0146] Schematic, the controller 2220 and multiple memories 2210 may be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0147] The aforementioned memory 2210 can be implemented as follows: Figure 9 , Figure 17 or Figure 19 The memory shown.

[0148] It is understandable that the control logic circuit in memory 2210 can perform the above-described actions. Figure 21 All or part of the steps in the scheme shown.

[0149] This application provides a computer system, which includes: a host; one or more such as Figure 9 , Figure 17 or Figure 19 The memory shown; and the controller coupled to the memory and configured to control the memory.

[0150] This application provides a computer-readable storage medium storing instructions that, when executed on the control logic circuit of a controller, implement the following: Figure 21 The illustrated embodiment provides a method for operating a memory. Optionally, the memory may be as follows: Figure 9 , Figure 17 or Figure 19 Any of the memory shown.

[0151] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0152] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0153] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes peripheral circuitry and a memory cell array; The peripheral circuitry includes multiple page buffers and control logic circuitry coupled to the multiple page buffers and configured to control the multiple page buffers. The page buffer includes a first bit line connection point, a second bit line connection point, a first switching device, and a second switching device; The first bit line connection point and the second bit line connection point are used to connect the bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are respectively connected to the power supply through independent pre-charge circuits, and the first bit line connection point and the second bit line connection point are respectively connected to the latches in the page buffer; the pre-charge circuit is a circuit in which the page buffer pre-charges the bit lines; The first switching device is connected to the first bit line connection point and the second bit line connection point; The second switching device is located on the pre-charge circuit corresponding to the second bit line connection point; The first bit line connection point is connected to N bit lines out of the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to the other N bit lines out of the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are sequentially adjacent, and the bit lines connected by the first bit line connection point and the second bit line connection point are sequentially staggered.

2. The memory according to claim 1, characterized in that, The control logic circuit is configured to disconnect the first switching device and connect the second switching device when a programming operation is performed through the page buffer. The control logic circuit is configured to turn on the first switching device and turn off the second switching device when a read operation is performed through the page buffer.

3. The memory according to claim 2, characterized in that, A third switching device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first bit line connection point.

4. The memory according to claim 3, characterized in that, The control logic circuit is configured to disconnect the third switching device when a programming operation is performed through the page buffer; The control logic circuit is configured to turn on the third switching device when a read operation is performed through the page buffer.

5. The memory according to any one of claims 1 to 4, characterized in that, The control logic circuit is configured to apply a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer. The first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

6. The memory according to claim 5, characterized in that, The control logic circuit is configured to, when performing programming operations on the 2×N bit-line-coupled memory cells through the page buffer Through the first bit line connection point and the second bit line connection point, programming pulse voltages are sequentially applied to the 2×N bit lines according to the arrangement order of the 2×N bit lines; Among the 2×N bit lines, the time intervals for applying programming pulse voltage to two adjacent bit lines overlap, so that during the programming operation of a memory cell coupled to a bit line, a bias voltage is applied to the adjacent bit lines of the bit line.

7. The memory according to claim 6, characterized in that, For the 4×N bit lines in the memory cell array that are sequentially adjacent to the two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the opposite of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

8. A method for operating a memory, characterized in that, The method is executed by control logic circuitry in the peripheral logic circuitry of the memory, the memory being the memory as described in claim 1, and the method includes: When programming via the page buffer, the first switching device is disconnected and the second switching device is turned on; During a read operation via the page buffer, the first switching device is turned on and the second switching device is turned off.

9. The method according to claim 8, characterized in that, A third switching device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switching device is located outside the pre-charge circuit corresponding to the first bit line connection point.

10. The method according to claim 9, characterized in that, The method further includes: The third switching device is disconnected during programming operations via the page buffer; When a read operation is performed through the page buffer, the third switching device is turned on.

11. The method according to any one of claims 8 to 10, characterized in that, During the programming operation of the memory cell coupled to the first bit line through the page buffer, a bias voltage is applied to the second bit line. The first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

12. The method according to claim 11, characterized in that, The process of applying a bias voltage to the second bit line during the programming operation of the memory cell coupled to the first bit line through the page buffer includes: When programming the 2×N bit-line coupled memory cells through the page buffer, programming pulse voltages are applied sequentially to the 2×N bit lines through the first bit line connection point and the second bit line connection point, according to the arrangement order of the 2×N bit lines. Among the 2×N bit lines, the time intervals for applying programming pulse voltage to two adjacent bit lines overlap, so that during the programming operation of a memory cell coupled to a bit line, a bias voltage is applied to the adjacent bit lines of the bit line.

13. The method according to claim 12, characterized in that, For the 4×N bit lines in the memory cell array that are sequentially adjacent to the two page buffer vectors, the order in which the programming pulse voltage is applied to the first 2×N bit lines is the opposite of the order in which the programming pulse voltage is applied to the last 2×N bit lines.

14. A storage system, characterized in that, The storage system includes: One or more memories as described in any one of claims 1 to 7, and, A controller coupled to the memory and configured to control the memory.

15. A computer system, characterized in that, The computer system includes: Host; One or more memories as described in any one of claims 1 to 7; and, A controller coupled to the memory and configured to control the memory.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a control logic circuit, implement the memory operation method as described in any one of claims 8 to 13.

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