Packaging structure and forming method thereof

Abstract

The invention provides a packaging structure and a forming method thereof. The packaging structure comprises a condensation rewiring layer, and a vertical interconnection structure, a silicon bridge chip and a condensation flow pipe are arranged in the condensation rewiring layer. Cooling liquid can be introduced into the packaging structure through the condensation flow pipe, heat conduction is conducted through the cooling liquid in the condensation flow pipe, the heat dissipation efficiency of the packaging structure can be effectively improved, and the heat dissipation problem of a high-performance large-power-consumption chip is solved; meanwhile, the technological process is effectively simplified, and the manufacturing cost is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a packaging structure for improving heat dissipation performance and a forming method thereof. Background Art

[0002] The packaging process of integrated circuits is an essential step in the process of converting integrated circuit chips into practical electronic products. It plays the role of interconnection, mechanical support, and protection of electronic modules, and can significantly improve the reliability of chips. For high-end digital chips such as central processing units (CPUs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs) for emerging applications such as artificial intelligence (AI), big data, high-performance computing (HPC), smart cars, and data centers, flip chip ball grid arrays (FCBGA) have begun to become a mainstream method with its unique flip chip packaging mode, which has many advantages such as high computing power, high speed, high bandwidth, low latency, low power consumption, multi-functions, and system-level integration.

[0003] In the new generation of high-speed, highly integrated chips, heat dissipation will be a major challenge. Based on the unique FCBGA flip-chip packaging form, the back of the chip can be exposed to the air, which can directly dissipate heat, or a metal heat sink can be installed on the back of the chip to further enhance the chip's heat dissipation capabilities and greatly improve the chip's stability when running at high speeds.

[0004] However, the existing FCBGA packaging structure still has many problems. Since the front of the chip in the FCBGA packaging structure is bonded to the packaging substrate and there is also a high thermal resistance bonding glue, it is impossible to actively dissipate heat from the bottom, and additional heat dissipation measures are required to keep the temperature of the chip stable, otherwise overheating may occur. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a packaging structure and a forming method thereof to improve the heat dissipation performance of the chip structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a packaging structure, which is characterized by comprising: Providing a temporary slide comprising a first surface and a second surface; forming a condensation redistribution layer on the first surface of the temporary carrier; The step of forming a condensation rewiring layer also includes: forming a vertical interconnection structure on the first surface of the temporary carrier; mounting a silicon bridge chip on the first surface of the temporary carrier; mounting a condensation flow pipe on the first surface of the temporary carrier; forming a first plastic packaging layer on the temporary carrier to cover the vertical interconnection structure, the silicon bridge chip, and the condensation flow pipe; Forming electroplating pads and assembly solder balls on the first surface of the condensation rewiring layer away from the temporary carrier; Providing a first chip and a second chip, flip-chip bonding the first chip and the second chip on the condensation rewiring layer, and electrically connecting the front surfaces of the first chip and the second chip to the condensation rewiring layer through solder balls; The first chip and the second chip are connected via the silicon bridge chip; A second plastic packaging layer is formed to cover the first chip and the second chip.

[0007] Optionally, the method for forming the packaging structure further includes: the condensation flow pipes are evenly arranged in the condensation redistribution layer.

[0008] Optionally, the method for forming the packaging structure further includes: the condensation flow pipes are evenly arranged between the gaps of the vertical interconnection structures and surround the silicon bridge chip.

[0009] Optionally, the method for forming the packaging structure also includes: removing the temporary carrier, forming an electroplated pad on the second surface of the condensation rewiring layer away from the first chip and the second chip, assembling solder balls, and electrically connecting the vertical interconnect structure with the solder balls.

[0010] Optionally, the method for forming the packaging structure further includes: providing a substrate, and bonding the chip packaging structure to the substrate.

[0011] Optionally, the method for forming the packaging structure further includes: providing a liquid inlet pipe and a liquid outlet pipe, which are respectively connected to the liquid inlet and the liquid outlet of the condensing flow tube.

[0012] Optionally, the method for forming the packaging structure further includes: providing a packaging adhesive layer to bond and fix the chip packaging structure, the liquid inlet pipe, the liquid outlet pipe and the substrate.

[0013] Optionally, the method for forming the packaging structure further includes: the material of the packaging glue layer is a high thermal conductivity plastic packaging material with a thermal conductivity greater than 3W / mK.

[0014] Correspondingly, the technical solution of the present invention provides a packaging structure, characterized in that it includes: a condensation rewiring layer, the condensation rewiring layer includes: a vertical interconnection structure, a silicon bridge chip, a condensation flow tube, and a first plastic encapsulation layer, the first plastic encapsulation layer covers the vertical interconnection structure, the silicon bridge chip, and the condensation flow tube; electroplated pads and solder balls located on the first surface of the condensation rewiring layer; a first chip and a second chip, the first chip and the second chip are flip-chip bonded to the condensation rewiring layer through the electroplated pads and solder balls located on the first surface of the condensation rewiring layer; the first chip and the second chip are connected through the silicon bridge chip; a second plastic encapsulation layer covers the first chip and the second chip.

[0015] Optionally, the packaging structure further includes: the condensation flow pipes are evenly arranged in the condensation redistribution layer.

[0016] Optionally, the packaging structure further includes: the condensation flow pipes are evenly arranged between the gaps of the vertical interconnection structures and surround the silicon bridge chip.

[0017] Optionally, the packaging structure further includes: electroplated pads and solder balls located on the second surface of the condensation redistribution layer, and the vertical interconnect structure is electrically connected to the solder balls.

[0018] Optionally, the packaging structure further includes: a substrate, wherein the substrate and the chip packaging structure are bonded to each other.

[0019] Optionally, the packaging structure further includes: a liquid inlet pipe and a liquid outlet pipe, which are respectively connected to the liquid inlet and the liquid outlet of the condensing flow tube.

[0020] Optionally, the packaging structure further includes: a packaging adhesive layer for bonding and fixing the chip packaging structure, the liquid inlet pipe, the liquid outlet pipe and the substrate.

[0021] Optionally, the packaging structure further includes: the material of the packaging glue layer is a high thermal conductivity plastic packaging material with a thermal conductivity greater than 3W / mK.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: In the packaging structure of the technical solution of the present invention, the condensation rewiring layer includes: a vertical interconnection structure, a silicon bridge chip, a condensation flow tube, and a first plastic sealing layer, wherein the first plastic sealing layer covers the vertical interconnection structure, the silicon bridge chip, and the condensation flow tube; a plated pad and a solder ball located on the first surface of the condensation rewiring layer; a first chip and a second chip, wherein the first chip and the second chip are flip-chip bonded on the condensation rewiring layer through the plated pad and the solder ball located on the first surface of the condensation rewiring layer, and the first chip and the second chip are connected through the silicon bridge chip; a second plastic sealing layer covers the first chip and the second chip. Moreover, the condensation flow tube is evenly arranged between the gaps of the vertical interconnection structure and surrounds the silicon bridge chip. The condensation flow tube is directly mounted and buried in the chip packaging structure, and the process is simpler. Compared with the traditional method that requires selective etching in the substrate to form a microchannel structure, the degree of selective etching is difficult to control, and the process complexity is high, the process flow of the condensation flow tube of the present invention is simpler and the cost is lower, and no etching process is required and the chip will not be damaged. The condensing manifold has the function of active heat dissipation, and can effectively extract the heat in the chip packaging structure, so that the chip packaging structure not only dissipates heat from the top through the heat dissipation cover, but also dissipates heat from the bottom through the condensing manifold, effectively improving the heat dissipation efficiency of the packaging structure. Furthermore, the packaging structure also includes a packaging glue layer, and the material of the packaging glue layer is a high thermal conductivity plastic sealing material, which can assist the condensing manifold to further dissipate heat from the bottom of the chip packaging structure, further improving the heat dissipation efficiency of the chip packaging and ensuring the stable operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of a packaging structure in the prior art; Figures 2 to 8 is a structural schematic diagram of each step of a method for forming a packaging structure in one embodiment of the present invention; DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the present disclosure, the exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0026] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0027] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0028] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0031] As described in the background art, the existing FCBGA packaging structure still has many problems, and the active heat dissipation of the FCBGA packaging structure and the temperature stability of the chip still have a lot of room for improvement. The following will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 The present invention is a schematic diagram of a packaging structure in the prior art.

[0033] Please refer to Figure 1 A packaging structure includes: a chip structure 100; an interposer 101, the chip structure 100 is electrically connected to the interposer 101; a driving substrate 102, the interposer 101 is electrically connected to the driving substrate 102; a heat dissipation cover 103, the heat dissipation cover 103 is connected to the interposer 101 to form a cavity (not shown), and the chip structure 100 is located in the cavity; a heat conductive layer 104, the heat conductive layer 104 is located between the chip structure 100 and the heat dissipation cover 103, and the heat conductive layer 104 is respectively connected to the chip structure 100 and the heat dissipation cover 103.

[0034] In the embodiment of the prior art, the chip structure 100 is electrically connected to the interposer 101 by means of a Flip Chip Ball Grid Array (FCBGA), and the heat dissipation cover 103 plays the role of protecting the chip structure 100, providing support for the chip structure 100, and guiding the heat dissipation of the chip structure 100 to relieve the heat dissipation pressure of the heat sink. The connection between the heat dissipation cover 103 and the driving substrate 102 relies on adhesive glue (AD glue) and the heat conductive layer 104, wherein the heat conductive layer 104 uses a thermal interface material (TIM), which is responsible for transferring the heat of the chip structure 100 to the heat dissipation cover 103, and the AD glue mainly provides adhesion to ensure that the heat dissipation cover 103 is tightly connected to the driving substrate 102 and provides a closed environment.

[0035] However, although the intermediate layer 101 and the driving substrate 102 located below have metal connections and have good thermal conductivity, they are coated with AD glue (the thermal conductivity is only 0.5W / mK), so the heat cannot be actively dissipated from the bottom. That is, the heat dissipation of the packaging structure can only rely on the heat dissipation cover 103 located above, which makes the heat dissipation efficiency of the packaging structure limited. Especially in the application scenario of high-power chips, the heat dissipation cover 103 located above is not enough to dissipate the heat, which affects the operation of the chip.

[0036] On this basis, the present invention provides a packaging structure and a method for forming the same, including a condensation rewiring layer, wherein the condensation rewiring layer has a vertical interconnection structure, a silicon bridge chip, and a condensation flow pipe. The cooling liquid can be introduced into the packaging structure through the condensation flow pipe, and the cooling liquid in the condensation flow pipe is used for heat conduction, which can effectively improve the heat dissipation efficiency of the packaging structure and solve the heat dissipation problem of high-performance and high-power consumption chips; at the same time, the process flow is effectively simplified and the manufacturing cost is saved.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 8 It is a structural schematic diagram of each step of a method for forming a packaging structure in one embodiment of the present invention.

[0039] Please refer to the attached Figure 2 , a temporary carrier 200 is provided, which includes a first surface 210 and a second surface 220.

[0040] The temporary carrier 200 is made of materials including silicon, glass, ceramic or organic materials.

[0041] In this embodiment, the temporary carrier 200 is made of silicon.

[0042] A condensation rewiring layer is formed on the first surface 210 of the temporary carrier 200, and the condensation rewiring layer includes: a vertical interconnect structure, a silicon bridge chip, a condensation flow pipe, and a first plastic packaging layer. The method for forming the condensation rewiring layer is as follows: In this embodiment, a vertical interconnect structure 300 is formed on the first surface 210 of the temporary carrier 200 .

[0043] In this embodiment, the vertical interconnection structure 300 is a metal column, and the material of the metal column can be copper, nickel, tin, silver or other metals, preferably copper, that is, a copper column.

[0044] In this embodiment, the vertical interconnect structure 300 may be formed using an electroplating process, and the process steps include: first forming a seed layer on the first surface 210 of the temporary carrier 200, patterning, electroplating metallization, post-processing, etc.

[0045] In this embodiment, after forming the vertical interconnect structure 300, a silicon bridge chip 400 is mounted on the first surface 210 of the temporary carrier 200. The silicon bridge chip 400 is prepared by conventional processes in the prior art and is used to subsequently connect multiple flip chips in a chip packaging structure.

[0046] In the present embodiment, a condensing manifold 500 is mounted on the first surface 210 of the temporary carrier 200. The mounted condensing manifold 500 is a small-sized heat dissipation tube pre-manufactured according to the shape and size of the chip packaging structure and adapted to the layout of the condensation rewiring layer. It has the function of active heat dissipation and is directly mounted and embedded in the chip packaging structure. In the present embodiment, a prefabricated condensing manifold with active heat dissipation is directly mounted and embedded in the chip packaging structure, and the process is simpler. Compared with the traditional method that requires selective etching in the substrate to form a microchannel structure, the degree of selective etching is difficult to control and the process complexity is high. The process flow of the condensing manifold 500 of the present invention is simpler and the cost is lower. At the same time, no etching process is required and the chip will not be damaged.

[0047] In this embodiment, the material of the condensation flow tube 500 can be a quartz tube, a metal tube or the like. The condensation flow tube 500 is loaded with condensate, which has the function of active heat dissipation and can effectively dissipate the heat in the chip packaging structure, thereby effectively improving the heat dissipation efficiency of the packaging structure.

[0048] In this embodiment, a first plastic encapsulation layer 600 is formed on the first surface 210 of the temporary carrier 200, and the first plastic encapsulation layer 600 uniformly covers and envelops the vertical interconnection structure 300, the silicon bridge chip 400, and the condensation flow tube 500. The first plastic encapsulation layer 600 is subjected to a grinding process to be thinned to expose the vertical interconnection structure 300 and the micro-bumps on the surface of the silicon bridge chip 400. For details, please refer to the attached Figure 3 In this embodiment, the grinding process includes: a physical mechanical grinding process, a chemical mechanical grinding process or a wet etching process. The planarization process performed by the grinding process can eliminate or reduce the unevenness of the surface of the first plastic encapsulation layer 600 and improve the yield rate in the production process. In this embodiment, the material of the first plastic encapsulation layer 600 can be one or more of epoxy resin, polyimide (PI), Ajinomoto Build-up Film (ABF), or bismaleimide triazine resin (BT resin), and epoxy resin is preferred.

[0049] In this embodiment, the condensation flow pipes 500 are evenly arranged in the condensation rewiring layer.

[0050] Please refer to the attached Figure 4 , which is a schematic diagram of the top view of the condensation rewiring layer of an embodiment of the present invention, the condensation flow pipe 500 includes a plurality of 90° bends, so that the condensation flow pipe 500 is evenly arranged in the condensation rewiring layer, and further, the condensation flow pipe 500 is evenly arranged between the gaps of the vertical interconnection structure 300 and surrounds the silicon bridge chip 400. The condensation flow pipe 500 has the function of active heat dissipation, and can evenly guide the heat in the chip packaging structure as a whole, effectively improve the heat dissipation efficiency of the packaging structure, and avoid local high heat caused by uneven heat dissipation.

[0051] Please refer to the attached Figure 5 The exposed portion of the vertical interconnect structure 300 is used as a UBM (under bump metallization) structure, and a plating pad and a solder ball assembly are formed on the first surface of the condensation rewiring layer away from the temporary carrier 200. The plating pad adopts a conventional electroplating process, and the solder ball assembly can preferably be a laser solder ball assembly process, which can obtain a smaller and more precise solder ball.

[0052] In this embodiment, a first chip 710 and a second chip 720 are provided. The first chip 710 and the second chip 720 may be high-power chips that need to withstand operating environments such as high current, high voltage and high temperature. The first chip 710 and the second chip 720 may be the same chip, or chips of the same type, or chips of different types, for example, they may be logic chips such as CPU, DSP, GPU, FPGA, or storage chips such as DRAM, Flash, HBM, or other types of chips such as SOC or sensors (such as MEMS sensors, etc.). Please refer to the attached Figure 5 The first chip 710 and the second chip 720 are flip-chip bonded on the condensation rewiring layer. The bonding method can be thermal compression bonding, so that the front surfaces of the first chip 710 and the second chip 720 are electrically connected to the condensation rewiring layer through solder balls.

[0053] In this embodiment, the front surfaces of the first chip 710 and the second chip 720 have micro-bumps, which can be connected to the micro-bumps on the surface of the silicon bridge chip 400 through solder balls, that is, the first chip 710 and the second chip 720 are connected through the silicon bridge chip 400, and finally a silicon bridge interconnection structure is formed.

[0054] Please refer to the attached Figure 6 , a second plastic encapsulation layer 800 is formed on the condensation rewiring layer, the second plastic encapsulation layer 800 uniformly covers and envelops the first chip 710 and the second chip 720, and the second plastic encapsulation layer 800 is subjected to a grinding process to thin the second plastic encapsulation layer 800 until the surfaces of the first chip 710 and the second chip 720 are exposed. In this embodiment, the grinding process includes: a physical mechanical grinding process, a chemical mechanical grinding process, or a wet etching process. By performing a planarization process through a grinding process, the unevenness of the surface of the second plastic encapsulation layer 800 can be eliminated or reduced, thereby improving the yield rate in the production process.

[0055] In this embodiment, the material of the second plastic sealing layer 800 can be one or more of epoxy resin, polyimide (PI), Ajinomoto Build-up Film (ABF), or bismaleimide triazine resin (BT resin), and epoxy resin is preferably used.

[0056] Please refer to the attached Figure 7, remove the temporary carrier 200, and expose the vertical interconnection structure 300 on the surface of the condensation rewiring layer. The exposed part of the vertical interconnection structure 300 is used as a UBM (under bump metallization) structure, and a plating pad and an assembly solder ball are formed on the second surface of the condensation rewiring layer away from the first chip 710 and the second chip 720, and the vertical interconnection structure is electrically connected to the solder ball. In this embodiment, the plating pad adopts a conventional electroplating process, and the assembly solder ball can preferably be a laser assembly solder ball process, which can obtain a smaller and more precise solder ball.

[0057] Please refer to the attached Figure 8 , provide a substrate 1000, and attach the above Figure 7 The chip packaging structure with the temporary carrier removed is bonded to the substrate 1000. In this embodiment, the bonding temperature is usually set at about 245°C to melt the solder balls so as to form a stable connection with the substrate 1000.

[0058] In this embodiment, the substrate 1000 has a built-in circuit structure (not shown), and the chip packaging structure is electrically connected to the substrate 1000 through the solder balls and the vertical interconnection structure 300 .

[0059] In this embodiment, the substrate 1000 may be an interposer substrate, a PCB substrate, an organic ball grid array (BGA) packaging substrate, or a multi-chip module (MCM) substrate, etc.

[0060] Furthermore, a liquid inlet pipe 910 and a liquid outlet pipe 920 are provided, which are respectively connected to the liquid inlet and the liquid outlet of the condensing flow pipe 500. Furthermore, a packaging glue layer 1100 is provided to bond and fix the chip packaging structure, the liquid inlet pipe 910, the liquid outlet pipe 920 and the substrate 1000. The material of the packaging glue layer 1100 adopts a high thermal conductivity plastic sealing material, which is mainly used to protect the chip packaging structure from physical damage, chemical corrosion and environmental factors; at the same time, it can fully fill the gap of the device, which helps to improve the reliability and stability of the device; at the same time, the thermal conductivity is greater than 3W / mK, which has good thermal conductivity compared with the AD glue in the prior art. The packaging glue layer 1100 is formed by heating the high thermal conductivity plastic sealing material to a molten state and then injecting it, and then cooling and solidifying it to enhance the stability of the connection and protect the solder joints.

[0061] In this embodiment, a heat dissipation cover 1200 is provided, and the heat dissipation cover 1200 is connected to the substrate 1000 to form a cavity (not shown), and the chip packaging structure is located in the cavity; a heat conductive layer 1300 is provided, and the heat conductive layer 1300 is located between the chip packaging structure and the heat dissipation cover 1200, and the heat conductive layer 1300 is respectively connected to the chip packaging structure and the heat dissipation cover 1200.

[0062] In this embodiment, the heat dissipation cover 1200 also has a liquid inlet and a liquid outlet (not shown), and the liquid inlet pipe 910 and the liquid outlet pipe 920 are led out and connected to an external pump to drive the condensed liquid in the condensation flow pipe 500 to perform heat exchange. The chip packaging structure not only dissipates heat from the top through the heat dissipation cover 1200, but also dissipates heat from the bottom through the condensation flow pipe 500, thereby improving the heat dissipation efficiency of the chip packaging structure. Furthermore, the material of the packaging glue layer 1100 is a high thermal conductivity plastic sealing material, which can assist the condensation flow pipe 500 to further dissipate heat from the bottom of the chip packaging structure, further improving the heat dissipation efficiency of the chip packaging and ensuring the stable operation of the chip.

[0063] Accordingly, a packaging structure is also provided in the embodiment of the present invention, please continue to refer to Figure 8 , comprising: a condensation rewiring layer, the condensation rewiring layer comprising: a vertical interconnection structure, a silicon bridge chip, a condensation flow tube, and a first plastic encapsulation layer, the first plastic encapsulation layer covers the vertical interconnection structure, the silicon bridge chip, and the condensation flow tube; electroplated pads and solder balls located on the first surface of the condensation rewiring layer; a first chip and a second chip, the first chip and the second chip are flip-chip bonded to the condensation rewiring layer through the electroplated pads and solder balls located on the first surface of the condensation rewiring layer, and the first chip and the second chip are connected through the silicon bridge chip; a second plastic encapsulation layer covers the first chip and the second chip.

[0064] In this embodiment, the vertical interconnection structure is a metal column, and the material of the metal column can be copper, nickel, tin, silver or other metals, preferably copper, that is, a copper column.

[0065] In this embodiment, the silicon bridge chip is prepared by conventional processes in the prior art and is used for subsequently connecting multiple flip chips in a chip packaging structure.

[0066] In this embodiment, the condenser flow tube is a small-sized heat dissipation tube pre-fabricated according to the shape and size of the chip packaging structure and adapted to the layout of the condensation rewiring layer. It has the function of active heat dissipation and is directly mounted and embedded in the chip packaging structure. In this embodiment, a prefabricated condenser flow tube with active heat dissipation is directly mounted and embedded in the chip packaging structure, and the process is simpler. Compared with the traditional method that requires selective etching in the substrate to form a microchannel structure, the degree of selective etching is difficult to control and the process complexity is high. The process flow of the condenser flow tube of the present invention is simpler and the cost is lower. At the same time, no etching process is required and the chip will not be damaged.

[0067] In this embodiment, the material of the condensation flow tube can be a quartz tube, a metal tube or the like. The condensation flow tube is loaded with condensate, which has the function of active heat dissipation and can effectively export the heat in the chip packaging structure, thereby effectively improving the heat dissipation efficiency of the packaging structure.

[0068] In this embodiment, the condensation flow pipes are evenly arranged in the condensation rewiring layer.

[0069] Please refer to the attached Figure 4 , which is a schematic diagram of the top view structure of the condensation rewiring layer of an embodiment of the present invention, the condensation flow pipe includes a plurality of 90° bends, so that the condensation flow pipe is evenly arranged in the condensation rewiring layer, and further, the condensation flow pipe is evenly arranged between the gaps of the vertical interconnection structure and surrounds the silicon bridge chip. The condensation flow pipe has the function of active heat dissipation, and can evenly guide the heat in the chip packaging structure as a whole, effectively improve the heat dissipation efficiency of the packaging structure, and avoid local high heat caused by uneven heat dissipation.

[0070] In this embodiment, it also includes: electroplating pads and solder balls located on the second surface of the condensation rewiring layer, and the vertical interconnection structure is electrically connected to the solder balls.

[0071] Please refer to the attached Figure 8 In this embodiment, it also includes: a substrate, the substrate and the chip packaging structure are bonded to each other. In this embodiment, the bonding temperature is usually set at about 245°C to melt the solder balls so that the substrate and the chip packaging structure form a stable connection.

[0072] In this embodiment, the substrate has a built-in circuit structure (not shown), and the chip packaging structure is electrically connected to the substrate through the solder balls and the vertical interconnection structure.

[0073] In this embodiment, the substrate may be an interposer substrate, a PCB substrate, an organic ball grid array (BGA) packaging substrate, or a multi-chip module (MCM) substrate, etc.

[0074] In this embodiment, it also includes: a liquid inlet pipe and a liquid outlet pipe, which are respectively connected to the liquid inlet and the liquid outlet of the condensing flow tube.

[0075] In this embodiment, it also includes: a packaging glue layer, which bonds and fixes the chip packaging structure, the liquid inlet pipe, the liquid outlet pipe and the substrate. The material of the packaging glue layer is a high thermal conductivity plastic sealing material, which is mainly used to protect the chip packaging structure from physical damage, chemical corrosion and environmental factors; at the same time, it can fully fill the gap of the device, which helps to improve the reliability and stability of the device; at the same time, the thermal conductivity is greater than 3W / mK, which has good thermal conductivity compared with the AD glue in the prior art. The packaging glue layer 1100 is formed by heating the high thermal conductivity plastic sealing material to a molten state and then injecting it, and then cooling and solidifying it to enhance the stability of the connection and protect the solder joints.

[0076] In this embodiment, it also includes: a heat dissipation cover, which is connected to the substrate to form a cavity (not marked), and the chip packaging structure is located in the cavity.

[0077] It further comprises: a heat conducting layer, wherein the heat conducting layer is located between the chip packaging structure and the heat dissipation cover, and the heat conducting layer is connected to the chip packaging structure and the heat dissipation cover respectively.

[0078] In this embodiment, the heat dissipation cover also has a liquid inlet and a liquid outlet (not shown), and the liquid inlet and the liquid outlet are led out and connected to an external pump to drive the condensed liquid in the condenser flow tube to perform heat exchange. The chip packaging structure not only dissipates heat from the top through the heat dissipation cover, but also dissipates heat from the bottom through the condenser flow tube, thereby improving the heat dissipation efficiency of the chip packaging structure. Furthermore, the material of the packaging glue layer is a high thermal conductivity plastic sealing material, which can assist the condenser flow tube to further dissipate heat from the bottom of the chip packaging structure, further improving the heat dissipation efficiency of the chip packaging and ensuring the stable operation of the chip.

[0079] It should be understood that "one embodiment" or "an embodiment" or "this embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0080] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0081] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a packaging structure, characterized in that: include: Providing a temporary slide comprising a first surface and a second surface; forming a condensation redistribution layer on the first surface of the temporary carrier; The step of forming a condensation rewiring layer also includes: forming a vertical interconnection structure on the first surface of the temporary carrier; mounting a silicon bridge chip on the first surface of the temporary carrier; mounting a condensation flow pipe on the first surface of the temporary carrier; forming a first plastic packaging layer on the temporary carrier to cover the vertical interconnection structure, the silicon bridge chip, and the condensation flow pipe; Forming electroplating pads and assembly solder balls on the first surface of the condensation rewiring layer away from the temporary carrier; Providing a first chip and a second chip, flip-chip bonding the first chip and the second chip on the condensation rewiring layer, and electrically connecting the front surfaces of the first chip and the second chip to the condensation rewiring layer through solder balls; The first chip and the second chip are connected via the silicon bridge chip; A second plastic packaging layer is formed to cover the first chip and the second chip.

2. The method for forming a packaging structure according to claim 1, wherein: The condensation flow pipes are uniformly arranged in the condensation redistribution layer.

3. The method for forming a packaging structure according to claim 2, wherein: The condensing flow pipes are evenly arranged between the gaps of the vertical interconnection structure and surround the silicon bridge chip.

4. The method for forming a packaging structure according to any one of claims 1 to 3, characterized in that: The temporary carrier is removed, and electroplating pads are formed on the second surface of the condensation rewiring layer away from the first chip and the second chip, and solder balls are assembled, and the vertical interconnection structure is electrically connected to the solder balls.

5. The method for forming a packaging structure according to claim 4, wherein: A substrate is provided, and the chip packaging structure is bonded to the substrate.

6. The method for forming a packaging structure according to claim 5, wherein: A liquid inlet pipe and a liquid outlet pipe are provided, which are respectively connected to the liquid inlet and the liquid outlet of the condensing flow tube.

7. The method for forming a package structure according to claim 6, wherein: A packaging adhesive layer is provided to bond and fix the chip packaging structure, the liquid inlet pipe, the liquid outlet pipe and the substrate.

8. The method for forming a package structure according to claim 7, wherein: The material of the packaging glue layer is a high thermal conductivity plastic packaging material with a thermal conductivity greater than 3W / mK.

9. A packaging structure, characterized in that: include: A condensation rewiring layer, the condensation rewiring layer comprising: a vertical interconnection structure, a silicon bridge chip, a condensation flow tube, and a first plastic encapsulation layer, the first plastic encapsulation layer covering the vertical interconnection structure, the silicon bridge chip, and the condensation flow tube; electroplated pads and solder balls located on the first surface of the condensation rewiring layer; A first chip and a second chip, wherein the first chip and the second chip are flip-chip bonded on the condensation rewiring layer through electroplated pads and solder balls located on a first surface of the condensation rewiring layer; The first chip and the second chip are connected via the silicon bridge chip; The second plastic packaging layer covers the first chip and the second chip.

10. The packaging structure according to claim 9, characterized in that: The condensation flow pipes are uniformly arranged in the condensation redistribution layer.

11. The packaging structure according to claim 10, characterized in that: The condensing flow pipes are evenly arranged between the gaps of the vertical interconnection structure and surround the silicon bridge chip.

12. The packaging structure according to any one of claims 9 to 11, characterized in that: The electroplating pads and solder balls are located on the second surface of the condensation rewiring layer, and the vertical interconnection structure is electrically connected to the solder balls.

13. The packaging structure according to claim 12, characterized in that: A substrate is bonded to the chip packaging structure.

14. The packaging structure according to claim 13, characterized in that: The liquid inlet pipe and the liquid outlet pipe are respectively connected to the liquid inlet and the liquid outlet of the condensing flow tube.

15. The packaging structure according to claim 14, characterized in that: The packaging adhesive layer is used to bond and fix the chip packaging structure, the liquid inlet pipe, the liquid outlet pipe and the substrate.

16. The packaging structure according to claim 15, characterized in that: The material of the packaging glue layer is a high thermal conductivity plastic packaging material with a thermal conductivity greater than 3W / mK.

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