Three-dimensional optoelectronic integrated package structure and method of manufacturing the same

Abstract

The application provides a three-dimensional optoelectronic integrated packaging structure and a preparation method thereof. The packaging structure comprises a TSV substrate, a rewiring layer, a first electric chip, a second electric chip, a dielectric layer, a conductive column, an optical chip module, a 3D stacked chip and a horizontal storage chip. The optical chip module, the first electric chip and the 3D stacked chip are connected by the TSV substrate and the rewiring layer to form an optical integrated circuit. The 3D stacked chip, the second electric chip and the horizontal storage chip are connected by the TSV substrate and the rewiring layer to form an electric integrated circuit. The transmission distance between the optical integrated circuit and the electric integrated circuit is shortened, the packaging area is reduced, the power consumption is lowered, and high-density integrated packaging of the optical and electric chips is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a three-dimensional optoelectronic integrated packaging structure and a preparation method thereof. BACKGROUND

[0002] With the development of cloud services, Internet of Things (IoT), 5G applications, etc., the quantity of network information presents an explosive growth, and the requirement for data center interconnection bandwidth is rapidly increasing. Integrated circuit packaging technology is continuously developing towards low cost, high reliability, fast transmission and high-density circuits, but the number of input / output (I / O) pins and the total I / O bandwidth of each packaging structure differ in growth rate, resulting in high energy consumption. Light has the performance of small signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS. The introduction of silicon optical technology can increase the bandwidth of I / O to reduce energy consumption. Among them, the integration of light and electricity is crucial, and how to well combine the photonic integrated circuit (PIC) and the electronic integrated circuit (EIC) for packaging is a problem to be solved.

[0003] Most of the existing semiconductor packaging structures directly bond the photonic integrated chip and the electronic integrated chip on the substrate, and are electrically connected with the substrate through wire-bonds or Flip-Chip mode. The direct signal transmission distance of PIC and EIC is too long. Moreover, the silicon optical process node is relatively backward compared with the electrical chip. For example, the current single-chip integrated development silicon optical process node is 45nm and 32nm process, which is far from the process node below 10nm of the electrical chip. Therefore, the existing optoelectronic integrated semiconductor packaging structure is difficult to meet the demand of high-density integrated packaging.

[0004] Therefore, how to provide a three-dimensional optoelectronic integrated packaging structure and a preparation method thereof to shorten the transmission distance of each module, realize high-density integrated packaging of optical chips and electrical chips, and reduce transmission power consumption has become an important problem to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and facilitating the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a three-dimensional optoelectronic integrated packaging structure and a preparation method thereof, which are used to solve the problem that it is difficult to perform high-density integrated packaging of optical chips and electrical chips and the transmission distance of each module is too long in the prior art.

[0007] To achieve the above object and other related objects, the present application provides a preparation method of a three-dimensional optoelectronic integrated packaging structure, comprising the following steps:

[0008] A TSV substrate is provided, a first re-wiring layer is formed on a first surface of the TSV substrate, a TSV metal column is arranged in the TSV substrate, and the first surface of the TSV substrate exposes a top end of the TSV metal column, and the first re-wiring layer is electrically connected with the TSV metal column;

[0009] A first electric chip and a second electric chip are provided, and the first electric chip and the second electric chip are bonded on the first re-wiring layer so that the first electric chip and the second electric chip are electrically connected with the first re-wiring layer, respectively;

[0010] A medium layer covering the first electric chip and the second electric chip is formed on the first re-wiring layer;

[0011] A conductive column is formed in the medium layer, the conductive column penetrates through the medium layer to be electrically connected with the first re-wiring layer, and the medium layer is thinned to expose the conductive column, the first electric chip and the second electric chip;

[0012] A second re-wiring layer is formed on the medium layer, and the second re-wiring layer is electrically connected with a top end of the conductive column;

[0013] A metal bump is formed on the second re-wiring layer, and the metal bump is electrically connected with the second re-wiring layer;

[0014] A support substrate is provided, and the metal bump is bonded with the support substrate;

[0015] The TSV substrate is thinned to expose a bottom end of the TSV metal column, and a third re-wiring layer is formed on a second surface of the TSV substrate, and the third re-wiring layer is electrically connected with the TSV metal column;

[0016] An optical chip module, a 3D stacked chip and a horizontal storage chip are provided, and the optical chip module, the 3D stacked chip and the horizontal storage chip are bonded on the third re-wiring layer, and the optical chip module, the 3D stacked chip and the second electric chip are electrically connected through the third re-wiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal storage chip and the first electric chip are electrically connected through the third re-wiring layer to form an electric integrated circuit.

[0017] Optionally, after the first electric chip and the second electric chip are bonded on the first re-wiring layer, a step of thinning the first electric chip and the second electric chip is further included.

[0018] Optionally, after the optical chip module, the 3D stacked chip and the horizontal storage chip are bonded on the third re-wiring layer, the method further comprises the step of removing the support substrate.

[0019] Optionally, the method of forming the first re-wiring layer comprises a damascene process, the method of forming the second re-wiring layer comprises a damascene process, and the method of forming the third re-wiring layer comprises a damascene process.

[0020] Optionally, a vertical projection of the optical chip module on the third re-wiring layer at least partially overlaps with a vertical projection of the second electrical chip on the third re-wiring layer.

[0021] Optionally, the second electrical chip comprises an ASIC chip, and the ASIC chip is configured to convert electrical signals of the 3D stacked chip into optical signals.

[0022] Optionally, the method further comprises the step of forming a filling layer in a gap between the optical chip module, the 3D stacked chip, the horizontal storage chip and the third re-wiring layer.

[0023] Optionally, after the 3D stacked chip is bonded on the third re-wiring layer, the method further comprises the step of bonding a backplane power supply chip on the 3D stacked chip, and the backplane power supply chip is electrically connected with the 3D stacked chip.

[0024] Optionally, the 3D stacked chip comprises a logic chip and a storage chip, and the storage chip is located on the logic chip and is electrically connected with the logic chip.

[0025] Optionally, before the second re-wiring layer is formed on the medium layer, the method further comprises the step of forming a first heat dissipation layer on an upper surface of the first electrical chip and / or forming a second heat dissipation layer on an upper surface of the second electrical chip.

[0026] Optionally, the number of the horizontal storage chip is one or more, and the number of the first electrical chip is one or more.

[0027] The present application also provides a three-dimensional optoelectronic integrated packaging structure, comprising:

[0028] a TSV substrate, wherein a TSV metal column is arranged in the TSV substrate, a first surface of the TSV substrate exposes a top end of the TSV metal column, and a second surface of the TSV substrate exposes a bottom end of the TSV metal column;

[0029] a first re-wiring layer, which is located on the first surface of the TSV substrate and is electrically connected with the TSV metal column;

[0030] a first and a second electrical chip bonded on the first re-wiring layer and electrically connected with the first re-wiring layer respectively;

[0031] a dielectric layer on the first re-wiring layer and surrounding the first and the second electrical chip;

[0032] a conductive pillar penetrating the dielectric layer and electrically connected with the first re-wiring layer;

[0033] a second re-wiring layer on the dielectric layer and electrically connected with the top end of the conductive pillar;

[0034] a metal bump on the second re-wiring layer and electrically connected with the second re-wiring layer;

[0035] a third re-wiring layer on the second face of the TSV substrate and electrically connected with the bottom end of the TSV metal pillar;

[0036] an optical chip module, a 3D stacked chip and a horizontal memory chip bonded on the third re-wiring layer, the optical chip module, the 3D stacked chip and the second electrical chip electrically connected through the third re-wiring layer to form an optical integrated circuit, the 3D stacked chip, the horizontal memory chip and the first electrical chip electrically connected through the third re-wiring layer to form an electrical integrated circuit.

[0037] Optionally, the vertical projection of the optical chip module on the third re-wiring layer at least partially overlaps with the vertical projection of the second electrical chip on the third re-wiring layer.

[0038] Optionally, the second electrical chip comprises an ASIC chip, which converts the electrical signal of the 3D stacked chip into an optical signal.

[0039] Optionally, further comprising a filling layer in the gap between the optical chip module, the 3D stacked chip and the horizontal memory chip and the third re-wiring layer.

[0040] Optionally, further comprising a backplane power supply chip bonded on the 3D stacked chip and electrically connected with the 3D stacked chip.

[0041] Optionally, the 3D stacked chip comprises a logic chip and a memory chip, the memory chip being on the logic chip and electrically connected with the logic chip.

[0042] Optionally, a first heat dissipation layer and / or a second heat dissipation layer are further included, the first heat dissipation layer is located on the upper surface of the first electric chip, and the second heat dissipation layer is located on the upper surface of the second electric chip.

[0043] Optionally, the number of the horizontal storage chips is one or more, and the number of the first electric chips is one or more.

[0044] As described above, the three-dimensional optoelectronic integrated packaging structure and the preparation method thereof connect the optical chip module, the first electric chip and the 3D stacked chip through the TSV substrate and the rewiring layer to form an optical integrated circuit, and connect the 3D stacked chip, the second electric chip and the horizontal storage chip through the TSV substrate and the rewiring layer to form an electric integrated circuit, thereby shortening the transmission distance between the optical integrated circuit and the electric integrated circuit, reducing the packaging area, reducing the power consumption, and realizing high-density integrated packaging of the optical and electric chips. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A schematic diagram of an optoelectronic integrated packaging structure is shown.

[0046] Figure 2 A process flow diagram of the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0047] Figure 3 A structure schematic diagram after forming the first rewiring layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0048] Figure 4 A structure schematic diagram after bonding the first electric chip and the second electric chip in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0049] Figure 5 A structure schematic diagram after polishing the first electric chip and the second electric chip in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0050] Figure 6 A structure schematic diagram after forming the dielectric layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0051] Figure 7 A structure schematic diagram after forming the conductive column in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0052] Figure 8 A structure schematic diagram after polishing the dielectric layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0053] Figure 9A structure schematic diagram after forming a second re-wiring layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0054] Figure 10 A structure schematic diagram after forming a metal bump in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0055] Figure 11 A structure schematic diagram after forming a support substrate in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0056] Figure 12 A structure schematic diagram after forming a grinding TSV substrate, forming a third re-wiring layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0057] Figure 13 A structure schematic diagram after bonding an optical module chip, a 3D stacked chip and a horizontal storage chip on the third re-wiring layer in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0058] Figure 14 A structure schematic diagram after bonding a backplane power supply chip on the 3D stacked chip in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0059] Figure 15 A structure schematic diagram after removing the support substrate in the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application is shown.

[0060] BRIEF DESCRIPTION OF DRAWINGS

[0061] 11 system board

[0062] 12 electrical chip

[0063] 121 substrate

[0064] 122 logic chip

[0065] 123 HBM chip

[0066] 13 optical chip module

[0067] 131 substrate

[0068] 132 ASIC chip

[0069] 133 optical chip

[0070] 21 TSV base

[0071] 22 TSV metal column

[0072] 23 first re-wiring layer

[0073] 24 first electrical chip

[0074] 25 second electrical chip

[0075] 26 dielectric layer

[0076] 27 conductive pillar

[0077] 28 second re-wiring layer

[0078] 29 first heat dissipation layer

[0079] 210 second heat dissipation layer

[0080] 211 metal bump

[0081] 212 support substrate

[0082] 213 separation layer

[0083] 214 third re-wiring layer

[0084] 215 optical chip module

[0085] 216 3D stacked chip

[0086] 2161 logic chip

[0087] 2162 memory chip

[0088] 217 horizontal memory chip

[0089] 218 filling layer

[0090] 219 backplane power chip

[0091] S1-S9 steps DETAILED DESCRIPTION

[0092] See Figure 1, show as a kind of schematic diagram of optoelectronic integrated package structure, the optoelectronic integrated package structure includes system board 11, electric chip 12 and optical chip module 13, wherein, the electric chip 12 and the optical chip module 13 are all electrically connected with the system board.The electric chip 12 includes logic chip 122 and HBM chip 123, wherein, HBM's Chinese full name is high bandwidth memory, English full name is High Bandwidth Memory, the HBM chip 123 is connected with the logic chip 122 by substrate 121, the optical chip module 13 includes ASIC chip 132 and optical chip 133, wherein, ASIC's Chinese full name is application specific integrated circuit, English full name is Application Specific Integrated Circuit, the ASIC chip 132 is connected with optical chip 133 by substrate 131.It can be seen that, in the optoelectronic integrated semiconductor package structure, the electric chip 12 needs to be connected with the optical chip module 13 through the system board 11, so that the transmission distance between photoelectric signal is too long, the area of package is larger.

[0093] The inventor of the present application proposes a three-dimensional optoelectronic integrated package structure and a preparation method thereof through a large number of analysis and research, realizes short-distance connection of optical integrated circuit and electric integrated circuit, reduces the transmission distance of photoelectric signal, reduces the packaging area, and reduces the power consumption, so as to meet the high-density integrated packaging of optoelectronic chip.

[0094] The embodiments of the present application are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied through different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0095] It should be emphasized that the term "comprises / comprising" is used herein to indicate the presence of a feature, integer, step or component, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0096] Features described and / or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with features in other embodiments, or in place of features in other embodiments.

[0097] As in the detailed description of the embodiments of the present application, for the convenience of description, the schematic diagram showing the structure of the device is partially enlarged without general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application here. In addition, three-dimensional spatial dimensions of length, width and depth should be included in actual manufacture.

[0098] For convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that these spatial relationship words are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0099] In the context of the present application, a structure described as having a first feature "on" a second feature can include embodiments in which the first and second features form direct contact, and can also include embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact.

[0100] It should be noted that the diagrams provided in the embodiments merely schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0101] Referring to Figure 2 , a process flow diagram of a method for manufacturing a three-dimensional optoelectronic integrated package structure of the present application is shown, including the following steps:

[0102] S1: providing a TSV substrate, forming a first re-wiring layer on a first surface of the TSV substrate, the TSV substrate being provided with a TSV metal column, the first surface of the TSV substrate exposing a top end of the TSV metal column, the first re-wiring layer being electrically connected with the TSV metal column;

[0103] S2: providing a first electric chip and a second electric chip, and bonding the first electric chip and the second electric chip on the first re-wiring layer so that the first electric chip and the second electric chip are respectively electrically connected with the first re-wiring layer;

[0104] S3: forming a dielectric layer covering the first electric chip and the second electric chip on the first re-wiring layer;

[0105] S4: forming a conductive column in the dielectric layer, the conductive column penetrating through the dielectric layer to be electrically connected with the first re-wiring layer, and thinning the dielectric layer to expose the conductive column, the first electric chip and the second electric chip;

[0106] S5: forming a second re-wiring layer on the dielectric layer, the second re-wiring layer being electrically connected with a top end of the conductive column.

[0107] S6: forming a metal bump on the second re-distribution layer, the metal bump being electrically connected with the second re-distribution layer;

[0108] S7: providing a support substrate and bonding the metal bump with the support substrate;

[0109] S8: thinning the TSV substrate to expose a bottom end of the TSV metal pillar, forming a third re-distribution layer on a second surface of the TSV substrate, the third re-distribution layer being electrically connected with the TSV metal pillar;

[0110] S9: providing an optical chip module, a 3D stacked chip and a horizontal memory chip, bonding the optical chip module, the 3D stacked chip and the horizontal memory chip on the third re-distribution layer, the optical chip module, the 3D stacked chip and the second electronic chip being electrically connected through the third re-distribution layer to form an optical integrated circuit, the 3D stacked chip, the horizontal memory chip and the first electronic chip being electrically connected through the third re-distribution layer to form an electronic integrated circuit.

[0111] The preparation method of the three-dimensional optoelectronic integrated packaging structure will be described in detail below. Figures 3 to 15 , each step of the preparation method of the three-dimensional optoelectronic integrated packaging structure.

[0112] First, please refer to FIG. 2, and perform step S1: providing a TSV substrate 21, forming a first re-distribution layer 23 on a first surface of the TSV substrate 21, the TSV substrate 21 being provided with a TSV metal pillar 22, the first surface of the TSV substrate 21 exposing a top end of the TSV metal pillar 22, the first re-distribution layer 23 being electrically connected with the TSV metal pillar 22.

[0113] As an example, the TSV substrate 21 can include a wafer-level substrate with a size of 4 inches, 6 inches, 8 inches, 12 inches, etc., to further improve the process efficiency, but the size of the TSV substrate 21 is not limited thereto.

[0114] As an example, the first re-distribution layer 23 can be a re-distribution layer using damascene process, including a dielectric layer and a metal wiring embedded in the dielectric layer, wherein the material of the dielectric layer can include silicon oxide or silicon nitride, etc., and the material of the metal wiring can include copper, aluminum, etc., and a smaller line width and pitch can be obtained through the first re-distribution layer 23 to meet the subsequent high-density connection requirement. The material, number of layers, layout, preparation method, etc. of the first re-distribution layer 23 can be selected as needed, which is not limited here.

[0115] Please refer to FIG. 3 again. Figure 4, the step S2 of providing a first electrical chip 24 and a second electrical chip 25 is performed, and the first electrical chip 24 and the second electrical chip 25 are bonded on the first re-wiring layer 23 so as to be electrically connected with the first re-wiring layer 23 respectively.

[0116] As an example, the second electrical chip 25 comprises an ASIC chip which can convert electrical signals of a subsequent 3D stacked chip 218 (such as a DRAM chip) into optical signals, but the type of the second electrical chip 25 is not limited thereto and can be selected as required. Figure 13 ) into optical signals, but the type of the second electrical chip 25 is not limited thereto and can be selected as required.

[0117] As an example, the bonding is performed by a direct copper-to-copper connection mode instead of a traditional bump or solder ball interconnection, which can simplify the process of the bonding interconnection, reduce the size of the stacking and packaging, reduce the power of the interconnection channel, and improve the heat dissipation capacity.

[0118] As an example, referring to Figure 5 , after the first electrical chip 24 and the second electrical chip 25 are bonded on the first re-wiring layer 23, a step of thinning the first electrical chip 24 and the second electrical chip 25 is further included, and a mechanical grinding, a chemical mechanical grinding, a plasma dry chemical etching, or the like can be used to thin the first electrical chip 24 and the second electrical chip 25 so as to facilitate subsequent processes, which is not limited herein. In the embodiment, a mechanical grinding process is used to achieve a smooth grinding surface. The thickness thinning of the first electrical chip 24 and the second electrical chip 25 can shorten the transmission distance and reduce the thickness of the packaging.

[0119] Referring to Figure 6 , the step S3 of forming a dielectric layer 26 covering the first electrical chip 24 and the second electrical chip 25 on the first re-wiring layer 23 is performed.

[0120] As an example, the material of the dielectric layer 26 can be silicon oxide, but is not limited thereto, and inorganic materials such as silicon nitride or aluminum oxide can also be used as required, which is not limited herein.

[0121] Referring to Figures 7 to 8 , the step S4 of forming a conductive pillar 27 in the dielectric layer 26 is performed, the conductive pillar 27 penetrates through the dielectric layer 26 to be electrically connected with the first re-wiring layer 23, the dielectric layer 26 is thinned to expose the conductive pillar 27, the first electrical chip 24, and the second electrical chip 25, wherein Figure 7 a schematic diagram of a structure obtained after the conductive pillar 27 is formed is shown, Figure 8 a schematic diagram of a structure obtained after the dielectric layer 26 is thinned is shown.

[0122] As an example, forming the conductive pillars 27 can include a step of forming through holes (not shown) through the dielectric layer 26, and a step of metal filling the through holes. The method of punching can include laser punching or mechanical drilling, which can be selected as needed. The method of filling metal can use electroplating, etc. The specific steps for preparing the conductive pillars 27, the size of the conductive pillars 27, and the distribution of the conductive pillars 27 are not limited here and can be selected as needed. The material of the conductive pillars 27 can be copper metal, but is not limited to this and other conductive metal materials can also be used.

[0123] As an example, mechanical grinding, chemical mechanical grinding, plasma dry chemical etching, or other suitable processes can be used to thin the dielectric layer 26 to expose the conductive pillars 27, the first electric chip 24, and the second electric chip 25. Here, the chemical mechanical grinding process is not limited and is used in the embodiment to obtain a relatively flat surface to facilitate subsequent processes.

[0124] Referring again to Figure 9 , the step S5 of forming a second re-wiring layer 28 on the dielectric layer 26 is performed, and the second re-wiring layer 28 is electrically connected to the top end of the conductive pillars 27.

[0125] As an example, the second re-wiring layer 28 can be a re-wiring layer using a damascene process, including a dielectric layer and a metal wiring embedded in the dielectric layer. The material of the dielectric layer can include silicon oxide or silicon nitride, etc. The material of the metal wiring can include copper, aluminum, etc. The material, number of layers, layout, and preparation method of the second re-wiring layer 28 can be selected as needed and are not limited here.

[0126] As an example, before forming the second re-wiring layer 28 on the dielectric layer 26, a step of forming a first heat dissipation layer 29 on the upper surface of the first electric chip 24 and / or a second heat dissipation layer 210 on the upper surface of the second electric chip 25 can be performed to improve heat dissipation and reduce power consumption. In the embodiment, a metal layer, preferably a copper layer, is electroplated on the back inactive area (area without electrical connection) of the first electric chip 24 and the second electric chip 25 to conduct heat for the first electric chip 24 and the second electric chip 25.

[0127] Referring again to Figure 10 , the step S6 of forming a metal bump 211 on the second re-wiring layer 28 is performed, and the metal bump 211 is electrically connected to the second re-wiring layer 28.

[0128] As an example, the metal bump 211 can be a C24 metal bump for facilitating subsequent electrical lead-out, but is not limited thereto, and no further limitation is made herein.

[0129] Referring back to Figure 11 , a step S7 is performed to provide a support substrate 212 and bond the metal bump 211 to the support substrate 212.

[0130] As an example, the support substrate 212 can include a glass substrate, a metal substrate, a semiconductor substrate, etc., so that the support substrate 212 can provide support for subsequent manufacturing processes. In the present embodiment, a separation layer 213 is preferably formed on the surface of the support substrate 212 to facilitate subsequent removal of the support substrate 212. The separation layer 213 can include, but is not limited to, one of a tape and a polymer layer. The separation layer 213 can be a light-heat conversion layer, so that the support substrate 212 can be separated from the metal bump 211 by heating the separation layer 213 by means of a laser, etc., to improve operation convenience.

[0131] Referring back to Figure 12 , a step S8 is performed to thin the TSV base 21 to expose the bottom end of the TSV metal pillar 22, and form a third redistribution layer 214 on the second surface of the TSV base 21, the third redistribution layer 214 being electrically connected to the TSV metal pillar 22.

[0132] As an example, a chemical mechanical polishing process can be used to expose the bottom end of the TSV metal pillar 22 and provide the TSV base 21 with a relatively smooth surface to facilitate subsequent processes. Of course, a mechanical polishing process, etc., can also be used to expose the TSV metal pillar 22, and no further limitation is made herein.

[0133] As an example, the third redistribution layer 214 can be a redistribution layer formed by a damascene process, including a dielectric layer and a metal wiring embedded in the dielectric layer. The dielectric layer can include silicon oxide or silicon nitride, etc., and the metal wiring can include copper, aluminum, etc. The material, number of layers, layout, manufacturing method, etc., of the third redistribution layer 214 can be selected as needed, and no further limitation is made herein.

[0134] Referring back to Figure 13, performing step S9: providing the optical chip module 215, the 3D stacked chip 216 and the horizontal storage chip 217, bonding the optical chip module 215, the 3D stacked chip 216 and the horizontal storage chip 217 on the third re-wiring layer 214, the optical chip module 215, the 3D stacked chip 216 and the second electrical chip 25 being electrically connected through the third re-wiring layer 214 to form an optical integrated circuit, the 3D stacked chip 216, the horizontal storage chip 217 and the first electrical chip 24 being connected through the third re-wiring layer 214 to form an electrical integrated circuit.

[0135] Specifically, the optical chip module 215 is electrically connected with the second electrical chip 25 through the third re-wiring layer 214, the TSV metal column 22 and the first re-wiring layer 23, the second electrical chip 25 is electrically connected with the 3D stacked chip 216 through the first re-wiring layer 23, the TSV metal column 22 and the third re-wiring layer 214, and in this way, an optical integrated circuit is formed, the 3D stacked chip 216 is electrically connected with the first electrical chip 24 through the third re-wiring layer 214, the TSV metal column 22 and the first re-wiring layer 23, the first electrical chip 24 is electrically connected with the horizontal storage chip 217 through the first re-wiring layer 23, the TSV metal column 22 and the third re-wiring layer 214, and in this way, an electrical integrated circuit is formed.

[0136] As an example, the vertical projection of the optical chip module 215 on the third re-wiring layer 214 at least partially overlaps with the vertical projection of the second electrical chip 25 on the third re-wiring layer 214.

[0137] As an example, the vertical projection of the 3D stacked chip 216 on the third re-wiring layer 214 at least partially overlaps with the vertical projection of the first electrical chip 24 on the third re-wiring layer 214, and the vertical projection of the 3D stacked chip 216 on the second re-wiring layer 28 at least partially overlaps with the vertical projection of the second electrical chip 25 on the third re-wiring layer 214.

[0138] As an example, the vertical projection of the horizontal storage chip 217 on the third re-wiring layer 214 at least partially overlaps with the vertical projection of the first electrical chip 24 on the third re-wiring layer 214.

[0139] As an example, the optical chip module 215, the 3D stacked chip 216 and the horizontal storage chip 217 are all electrically connected with the second re-wiring layer 28 in a flip-chip manner, and the types of the optical chip module 215, the 3D stacked chip 216 and the horizontal storage chip 217 are not limited here.

[0140] As an example, a filling layer 218 is formed between the optical chip module 215, the 3D stacked chip 216, the horizontal storage chip 217 and the second re-wiring layer 28 to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas and the like. The material of the filling layer 218 can be selected as needed, and can be an insulating material, which is not limited here.

[0141] As an example, the 3D stacked chip 216 includes a logic chip 2161 and a storage chip 2162, and the storage chip 2162 is located on the logic chip 2161 and is electrically connected to the logic chip 2161, i.e., the storage chip is vertically expanded on the logic chip by 3D stacking.

[0142] As an example, please refer to Figure 14 Further comprising the step of bonding a backplane power supply chip 219 on the 3D stacked chip 216, and the backplane power supply chip 219 is electrically connected to the 3D stacked chip 216.

[0143] As an example, please refer to Figure 15 Further comprising the step of removing the support substrate 212, wherein the support substrate 212 is removed based on the separation layer 213.

[0144] As an example, the number of the horizontal storage chip 217 is one or more, and the number of the second electrical chip 25 is one or more, and the specific number can be determined according to the specific situation, which is not limited here. The number of vertically expanded storage chips on the 3D stacked chip 216 is limited, and horizontally expanding the horizontal storage chip 217 can further improve the storage performance and meet the demand for high performance and high computing power.

[0145] So far, a three-dimensional optoelectronic integrated packaging structure is prepared, and please refer to Figure 15, the three-dimensional optoelectronic integrated package structure comprises a TSV substrate 21, a first re-wiring layer 23, a first electrical chip 24, a second electrical chip 25, a dielectric layer 26, a conductive column 27, a second re-wiring layer 28, a metal bump 211, a third re-wiring layer 214, an optical chip module 215, a 3D stacked chip 216, and a horizontal storage chip 217, wherein the TSV substrate 21 is provided with a TSV metal column 22, the first surface of the TSV substrate 21 exposes the top end of the TSV metal column 22, and the second surface of the TSV substrate 21 exposes the bottom end of the TSV metal column 22; the first re-wiring layer 23 is located on the first surface of the TSV substrate 21 and is electrically connected with the TSV metal column 22; the first electrical chip 24 and the second electrical chip 25 are bonded on the first re-wiring layer 23 and are respectively electrically connected with the first re-wiring layer 23; the dielectric layer 26 is located on the first re-wiring layer 23 and surrounds the first electrical chip 24 and the second electrical chip 25; the conductive column 27 penetrates through the dielectric layer 26 and is electrically connected with the first re-wiring layer 23; the second re-wiring layer 28 is located on the dielectric layer 26 and is electrically connected with the top end of the conductive column 27; the metal bump 211 is located on the second re-wiring layer 28, and the metal bump 211 is electrically connected with the second re-wiring layer 28; the third re-wiring layer 214 is located on the second surface of the TSV substrate 21 and is electrically connected with the bottom end of the TSV metal column 22; the optical chip module 215, the 3D stacked chip 216, and the horizontal storage chip 217 are bonded on the second re-wiring layer 28, the optical chip module 215, the 3D stacked chip 216, and the second electrical chip 25 are electrically connected through the third re-wiring layer 214 to form an optical integrated circuit, and the 3D stacked chip 216, the horizontal storage chip 217, and the first electrical chip 24 are connected through the third re-wiring layer 214 to form an electrical integrated circuit.

[0146] As an example, the first re-wiring layer 23 can be a re-wiring layer adopting a damascene process, the second re-wiring layer 28 can be a re-wiring layer adopting a damascene process, and the third re-wiring layer 214 can be a re-wiring layer adopting a damascene process.

[0147] As an example, the second electrical chip 25 can be an ASIC chip for converting electrical signals of the 3D stacked chip 216 into optical signals.

[0148] As an example, a filling layer 218 is arranged in the gap between the optical chip module 215, the 3D stacked chip 216, and the horizontal storage chip 217 and the second re-wiring layer 28 to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas, etc.

[0149] As an example, a backplane power chip 219 is also included, which is bonded on and electrically connected with the 3D stacked chip 216.

[0150] As an example, the 3D stacked chip 216 includes a logic chip 2161 and a memory chip 2162, and the 3D stacked chip 216 vertically expands the memory chip 2162 on the logic chip 2161 by 23D stacking.

[0151] As an example, the upper surface of the first electronic chip 24 is further provided with a first heat dissipation layer 29, and / or the upper surface of the second electronic chip 25 is further provided with a second heat dissipation layer 210, so as to improve the heat dissipation capacity.

[0152] As an example, the number of the horizontal memory chip 217 is one or more, and the number of the first electronic chip 24 is one or more, and the specific number can be determined according to specific conditions, which is not limited here.

[0153] In summary, the preparation method of the three-dimensional optoelectronic integrated packaging structure of the present application connects the optical chip module, the first electronic chip and the 3D stacked chip through the TSV substrate and the rewiring layer to form an optical integrated circuit, and connects the 3D stacked chip, the second electronic chip and the horizontal memory chip through the TSV substrate and the rewiring layer to form an electrical integrated circuit, thereby shortening the transmission distance between the optical integrated circuit and the electrical integrated circuit, reducing the packaging area, reducing the power consumption, and realizing high-density integrated packaging of the optical and electrical chips. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0154] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for preparing a three-dimensional optoelectronic integrated packaging structure, characterized in that: Providing a TSV substrate, forming a first redistribution layer on a first surface of the TSV substrate, wherein a TSV metal pillar is provided in the TSV substrate, a top of the TSV metal pillar is exposed on the first surface of the TSV substrate, and the first redistribution layer is electrically connected to the TSV metal pillar; Providing a first electrical chip and a second electrical chip, and bonding the first electrical chip and the second electrical chip to the first redistribution layer so that the first electrical chip and the second electrical chip are electrically connected to the first redistribution layer respectively; forming a dielectric layer covering the first electrical chip and the second electrical chip on the first redistribution layer; forming a conductive pillar in the dielectric layer, the conductive pillar penetrating the dielectric layer to be electrically connected to the first redistribution layer, and thinning the dielectric layer to expose the conductive pillar, the first electrical chip, and the second electrical chip; forming a second redistribution layer on the dielectric layer, wherein the second redistribution layer is electrically connected to the top of the conductive pillar; forming a metal bump on the second redistribution layer, wherein the metal bump is electrically connected to the second redistribution layer; Providing a supporting substrate, and bonding the metal bump to the supporting substrate; Thinning the TSV substrate to expose the bottom end of the TSV metal pillar, forming a third redistribution layer on the second surface of the TSV substrate, wherein the third redistribution layer is electrically connected to the TSV metal pillar; An optical chip module, a 3D stacked chip and a horizontal memory chip are provided, and the optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the third rewiring layer. The optical chip module, the 3D stacked chip and the second electrical chip are electrically connected through the third rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal memory chip and the first electrical chip are connected through the third rewiring layer to form an electrical integrated circuit.

2. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: After bonding the first electrical chip and the second electrical chip to the first rewiring layer, the method further includes a step of thinning the first electrical chip and the second electrical chip.

3. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: After bonding the optical chip module, the 3D stacked chip and the horizontal memory chip on the third rewiring layer, the method further includes a step of removing the supporting substrate.

4. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: The first rewiring layer is formed by a damascene process, the second rewiring layer is formed by a damascene process, and the third rewiring layer is formed by a damascene process.

5. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: A vertical projection of the optical chip module on the third redistribution layer at least partially overlaps with a vertical projection of the second electrical chip on the third redistribution layer.

6. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: The second electrical chip includes an ASIC chip, and the ASIC chip is used to convert the electrical signal of the 3D stacked chip into an optical signal.

7. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: The method further includes forming a filling layer in gaps between the optical chip module, the 3D stacked chip, the horizontal memory chip, and the third rewiring layer.

8. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: After bonding the 3D stacked chip to the third rewiring layer, the method further includes bonding a backplane power supply chip to the 3D stacked chip, wherein the backplane power supply chip is electrically connected to the 3D stacked chip.

9. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: The 3D stacked chip includes a logic chip and a memory chip, wherein the memory chip is located on the logic chip and is electrically connected to the logic chip.

10. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: Before forming the second rewiring layer on the dielectric layer, the method further includes forming a first heat dissipation layer on the upper surface of the first electrical chip and / or forming a second heat dissipation layer on the upper surface of the second electrical chip.

11. The method for preparing a three-dimensional optoelectronic integrated packaging structure according to claim 1, wherein: The number of the horizontal storage chips is one or more, and the number of the first electrical chips is one or more.

12. A three-dimensional optoelectronic integrated packaging structure, characterized in that: include: A TSV substrate, wherein a TSV metal column is provided in the TSV substrate, a top end of the TSV metal column is exposed on a first surface of the TSV substrate, and a bottom end of the TSV metal column is exposed on a second surface of the TSV substrate; a first redistribution layer, located on a first surface of the TSV substrate and electrically connected to the TSV metal pillar; A first electrical chip and a second electrical chip are bonded to the first redistribution layer and are electrically connected to the first redistribution layer respectively; a dielectric layer located on the first redistribution layer and surrounding the first electrical chip and the second electrical chip; a conductive pillar, the conductive pillar penetrating the dielectric layer and electrically connected to the first rewiring layer; a second redistribution layer, located on the dielectric layer and electrically connected to the top of the conductive pillar; a metal bump, located on the second redistribution layer and electrically connected to the second redistribution layer; a third redistribution layer, located on the second surface of the TSV substrate and electrically connected to the bottom end of the TSV metal pillar; An optical chip module, a 3D stacked chip and a horizontal memory chip, wherein the optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the third rewiring layer, the optical chip module, the 3D stacked chip and the second electrical chip are electrically connected through the third rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal memory chip and the first electrical chip are connected through the third rewiring layer to form an electrical integrated circuit.

13. The three-dimensional optoelectronic integrated packaging structure according to claim 12, characterized in that: A vertical projection of the optical chip module on the third redistribution layer at least partially overlaps with a vertical projection of the second electrical chip on the third redistribution layer.

14. The three-dimensional optoelectronic integrated packaging structure according to claim 12, wherein: The second electrical chip includes an ASIC chip, which converts the electrical signal of the 3D stacked chip into an optical signal.

15. The three-dimensional optoelectronic integrated packaging structure according to claim 12, wherein: The system further includes a filling layer, which is located in gaps between the optical chip module, the 3D stacked chip, the horizontal memory chip, and the third rewiring layer.

16. The three-dimensional optoelectronic integrated packaging structure according to claim 12, characterized in that: It also includes a backplane power supply chip, which is bonded to the 3D stacked chip and electrically connected to the 3D stacked chip.

17. The three-dimensional optoelectronic integrated packaging structure according to claim 12, wherein: The 3D stacked chip includes a logic chip and a memory chip, wherein the memory chip is located on the logic chip and is electrically connected to the logic chip.

18. The three-dimensional optoelectronic integrated packaging structure according to claim 12, characterized in that: It also includes a first heat dissipation layer and / or a second heat dissipation layer, wherein the first heat dissipation layer is located on the upper surface of the first electric chip, and the second heat dissipation layer is located on the upper surface of the second electric chip.

19. The three-dimensional optoelectronic integrated packaging structure according to claim 18, characterized in that: The number of the horizontal storage chips is one or more, and the number of the first electrical chips is one or more.

Images