Package architecture with vertically stacked die and voltage regulator

Abstract

An embodiment of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including a voltage regulator circuit unit; and a third IC die having a fifth surface, where the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die through a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die through a second interconnect, and the first IC die is electrically coupled to the second IC die through a conductive path in the third IC die.

Description

Technical Field

[0001] The present disclosure relates to techniques, methods, and apparatuses that relate to a packaging architecture having dies in a vertically stacked arrangement. Background Art

[0002] When electronic circuits are fabricated together on a wafer made of semiconductor material (e.g., silicon), they are called integrated circuits (ICs). Wafers with such ICs are typically cut into a large number of individual dies. The dies may be packaged into an IC package, which contains one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated into an electronic system (e.g., a consumer electronic system) or a server (e.g., a mainframe). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The various embodiments can be easily understood by considering the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are shown by way of example and not by way of limitation in the illustrations of the accompanying drawings.

[0004] Figures 1A-1D is a schematic cross-sectional view of an exemplary IC die according to some embodiments of the present disclosure.

[0005] Figure 2A According to some embodiments of the present disclosure Figure 1A A schematic perspective view of an exemplary IC die is shown in FIG.

[0006] Figure 2B According to some embodiments of the present disclosure Figure 1B A schematic perspective view of an exemplary IC die is shown in FIG.

[0007] Figure 2C According to some embodiments of the present disclosure Figure 1C A schematic perspective view of an exemplary IC die is shown in FIG.

[0008] Figure 2D According to some embodiments of the present disclosure Figure 1D A schematic perspective view of an exemplary IC die is shown in FIG.

[0009] Figure 3A is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0010] Figure 3B yes Figure 3A Schematic cross-sectional view of a portion of an exemplary microelectronic assembly.

[0011] Figure 3C According to some embodiments of the present disclosure Figure 3ASchematic cross-sectional view of a portion of an exemplary microelectronic assembly.

[0012] Figure 3D According to some embodiments of the present disclosure Figure 3A Schematic cross-sectional view of a portion of an exemplary microelectronic assembly.

[0013] Figure 4A According to some embodiments of the present disclosure, Figure 2A Schematic perspective view of an exemplary microelectronic assembly with an exemplary IC die.

[0014] Figure 4B According to some embodiments of the present disclosure, Figure 2B Schematic perspective view of an exemplary microelectronic assembly with an exemplary IC die.

[0015] Figures 5A-5C is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0016] Figure 6 is a simplified flow chart illustrating exemplary operations that may be associated with an embodiment of an exemplary microelectronic assembly.

[0017] Figure 7 is a simplified flow chart illustrating exemplary operations that may be associated with an embodiment of an exemplary microelectronic assembly.

[0018] Figure 8 is a simplified flow chart illustrating exemplary operations that may be associated with an embodiment of an exemplary microelectronic assembly.

[0019] Fig. 9 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0020] Fig.10 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0021] Fig.11 is a block diagram of an exemplary computing device including one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0022] Overview

[0023] For the purpose of illustrating the IC packaging described herein, it is important to understand the phenomena that occur during the assembly and packaging of the IC. The basic information below can be considered as the basis for properly interpreting the present disclosure. Such information is provided for illustrative purposes only and accordingly should not be interpreted in any way that limits the broad scope of the present disclosure and its potential applications.

[0024] The trend in the computer industry is to utilize multiple processors in large servers, which are coupled together in a single package (e.g., a multi-chip module (MCM)). These multiple processors, along with other IC dies containing memory circuits (e.g., cache memory circuits, high bandwidth memory circuits, etc.), are interconnected through high-speed data buses in the package substrate of the MCM, thereby (for example) achieving the overall nature of the processors working together. However, current technology in such MCMs has inherent limitations in its ability to scale for the bandwidth / distance requirements of next-generation servers, which may have signal speeds greater than 10 GHz and / or data speeds of 3-10 terabytes per second. These limitations are primarily associated with bandwidth degradation, signal delays, signal losses, and signal distortions caused by various reasons, one of which is this configuration of multiple processors coupled together in a single package.

[0025] Current packaging architectures (whether 2D, 2.5D or 3D) use multiple IC dies that are oriented parallel to each other and are interconnected together through various interconnects such as copper microbumps, solder balls, etc. In a general sense, any typical IC die is composed of a substrate, an active area including transistors and other active circuit units (circuitry) located in the substrate, and a metallization stack located on the substrate to share contact areas with the active area. The metallization stack is an area in the IC die where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using conductive traces and conductive vias. Common metals for conductive traces and conductive vias are copper and aluminum. The metallization stack typically includes contact pads, an insulating layer (e.g., an interlayer dielectric (ILD) material, such as silicon oxide), a conductive layer including conductive traces, and bonding sites for chip-to-chip or chip-to-package connections. Advanced IC dies may include more than 10 conductive layers located in the metallization stack.

[0026] Conventionally, various such IC dies can be stacked within a package in various ways: (1) back-to-back, where the substrate of one IC die is in direct contact with the substrate of another IC die; (2) back-to-front, where the substrate of one IC die is in direct contact with the metallization stack of another IC die; and (3) front-to-front, where the metallization stacks of two IC dies are in direct contact. In all of these configurations, the IC dies are parallel to each other, where the active circuit elements are arranged in a plane parallel to the contact areas of adjacent IC dies. Such architectures are plagued by certain inherent limitations. For example, computing IC dies that include high-performance computing circuit elements that generate a large amount of heat have to be arranged on top of any such stack to properly dissipate heat. Such arrangements limit the number of high-power computing IC dies that can be placed in a package with a limited (or restricted) footprint.

[0027] Memory IC packages typically require 2 to 3 watts of power delivery and thus typically do not have a large voltage drop, whereas computing systems typically require 100 watts of power delivery. In such computing systems, efficient power delivery is a significant challenge and is critical to achieving the expected performance per watt. An IC package may include a voltage regulator (VR) for managing power delivery to the IC die. Integrating a VR into an IC package having IC dies in a vertically stacked arrangement may be difficult because the available footprint in the IC package is limited. Various of the microelectronic assemblies disclosed herein may exhibit improved power delivery and signal speeds while reducing packaging complexity relative to conventional approaches.

[0028] The microelectronic assembly disclosed herein may include an IC die that is stacked vertically and electrically coupled to a surface of a base IC die at a lateral edge (e.g., back-to-back, back-to-front, or front-to-front stacked and rotated 90 degrees). Specifically, the microelectronic assembly disclosed herein may include an IC die that is coupled to a base IC die through an interconnect on a first surface of the IC die and a second surface of the base IC die, such that the first surface contacts the second surface, and the IC die includes a substrate attached to a metallization stack along an interface orthogonal to the first surface. The metallization stack of the IC die may include multiple layers of conductive traces located in a dielectric material, and the interconnects may be coupled to conductive traces exposed on the first surface. The IC die may be further electrically coupled to a VR circuit unit, which may be a VR die coupled to a surface of the base IC die or may be integrated into the base IC die. In some embodiments, the interconnect may include oxide-oxide bonding and metal-metal bonding including a first bonding pad in the first IC die and a second bonding pad in the second IC die, wherein the first bonding pad includes a conductive trace exposed on the first surface.

[0029] Accordingly, microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include: a first integrated circuit (IC) die having a first surface, a second surface opposite to the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface, the second IC die including a voltage regulator circuit unit; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die through a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die through a second interconnect, and the first IC die is electrically coupled to the second IC die through a conductive path in the third IC die.

[0030] Each of the structures, components, packaging, methods, devices, and systems disclosed herein may have several innovative aspects, no single one of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0031] In the following description, terms commonly used by those skilled in the art may be used to describe various aspects of the exemplary embodiments so as to convey the essence of its functions to those skilled in the art.

[0032] The terms "circuit" and "circuit unit" may refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide the intended functionality. These terms refer to analog circuit units, digital circuit units, hard-wired circuit units, programmable circuit units, microcontroller circuit units, and / or any other type of physical hardware electrical and / or electronic components.

[0033] The term "integrated circuit" refers to an electrical circuit that is integrated into a single piece of semiconductor or similar material.

[0034] In some embodiments, the IC die disclosed herein may include a semiconductor such as a basic single crystal of silicon or germanium as a base material (e.g., substrate, body) on which the integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more of the IC dies may include an alternative material, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium indium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In still further embodiments, the base material may comprise a compound semiconductor, for example, having a first sublattice composed of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice composed of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still further embodiments, the base material may comprise an intrinsic Group IV or Group III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still further embodiments, the die may comprise an amorphous material, for example, a polymer; for example, the base material may comprise an epoxy filled with silicone. In other embodiments, the base material may comprise a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although several examples of materials for the die are described here, any material or structure that can serve as a substrate (e.g., base material) on which IC circuits and structures as described herein are built falls within the spirit and scope of the present disclosure.

[0035] Unless otherwise described, an IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuit units (e.g., an IC that implements one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs that implement logic / computing circuit units (e.g., an IC that implements one or more of I / O functions, arithmetic operations, data pipelining operations, etc.).

[0036] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “die,” and “IC die” are used interchangeably herein.

[0037] The term "optical structure" includes various forms of arrangements made in the IC structure to receive, transform and / or transmit optical signals as described herein. It can include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0038] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials, such as N-type or P-type materials. The PIC may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor materials) or an SOI structure (or more generally a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium aluminum arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, gallium indium arsenide, gallium nitride, gallium indium nitride, aluminum indium nitride, or gallium antimonide or other combinations of III-N or IV group materials. In some embodiments, the PIC may include an amorphous material, such as a polymer. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC can be heterogeneous, including a carrier material (e.g., glass or silicon carbide) as a base material together with a thin semiconductor layer on which the active side including transistors and similar components are located. Although several examples of materials for PICs are described here, any material or structure that can serve as a substrate on which a PIC can be built falls within the spirit and scope of the present disclosure.

[0039] The word "insulation" means "electrical insulation" and the word "conduction" means "conductive conduction" unless otherwise specified. In the case of reference to optical signals and / or devices, components and elements that operate or work with optical signals, the word "conduction" may also mean "optical conduction".

[0040] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0041] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0042] The terms "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refer to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially non-conductive. By way of example and not limitation, they also include organic polymers and plastics and inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride and aluminum oxide or combinations thereof. They may include dielectric materials, high polarizability materials and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and moldings or materials similar to moldings used in packaging applications, including, for example, materials used in organic interposers, package supports and other such components.

[0043] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. In various embodiments, elements associated with an IC may include those elements integrated into the IC in a monolithic form, those elements mounted on the IC, or those elements connected to the IC. The ICs described herein may be analog or digital, and may be used in many applications, such as microprocessors, optoelectronic components, logic blocks, audio amplifiers, and the like, depending on the components associated with the IC. The ICs described herein may be used in a single IC die, or may be used as part of a chipset that performs one or more related functions in a computer.

[0044] In various embodiments of the present disclosure, the transistor described herein may be a field effect transistor (FET), such as a MOSFET. In many embodiments, the FET is a four-terminal device. In a silicon-on-insulator or nanoribbon or gate-all-around (GAA) FET, the FET is a three-terminal device that includes a source, a drain, and a gate terminal and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in and / or on the channel material, and a gate stack, the gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided on a portion of the channel material ("channel portion") between the source region and the drain region, and optionally also includes a gate dielectric material located between the gate electrode material and the channel material.

[0045] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect described herein should be understood with reference to the signal medium associated with the interconnect. Thus, when used with reference to an electronic device (e.g., an IC that operates with electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more elements associated with the IC or / and between various such elements. In such a case, the term "interconnect" can refer to both electrical traces (sometimes referred to as "wires", "conductors", "metal wires" or "trench") and electrical vias (sometimes referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, thereby emphasizing the fact that these elements include conductive materials (e.g., metals). Similarly, when used with reference to a device that also operates optical signals (e.g., a PIC), "interconnect" may also describe any element formed of light-conducting materials for providing an optical connection to one or more elements associated with the PIC. In such a case, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0046] The term "waveguide" refers to any structure that functions to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed from silicon, doped silicon, silicon nitride, glass (e.g., silica (e.g., silicon dioxide or SiO2)), borosilicate (e.g., 70–80 wt% SiO2, 7–13 wt% B2O3, 4–8 wt% Na2O or K2O, and 2–8 wt% Al2O3), and the like. The waveguide can be formed using various techniques including, but not limited to, forming the waveguide in situ. For example, in some embodiments, the waveguide can be formed in situ in glass using low temperature glass-to-glass bonding or by direct laser writing. The waveguide formed in situ can have lower loss characteristics.

[0047] The term "conductive trace" may be used to describe conductive elements that are isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided into the IC die. Within a package substrate and PCB, such insulating materials include organic materials such as Ajinomoto Build-Up Film (ABF), polyimide, or epoxy. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0048] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, the via may be provided substantially perpendicular to the plane of the IC die / chip or to the plane of a support structure on which the IC structure is provided, and the via may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0049] The term "package substrate" may be used to describe any substrate material that helps package any collection of semiconductor die and / or other electrical components (e.g., passive electrical components) together. As used herein, a package substrate may be composed of any material, including but not limited to insulating materials such as fiberglass impregnated with resin (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a build-up layer (e.g., ABF layer).

[0050] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0051] As used herein, the term "pitch" of interconnects refers to the center-to-center distance between adjacent interconnects.

[0052] It should be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, each level of underfill may include the same or different insulating materials. In some embodiments, each level of underfill may include a thermosetting epoxy with silicon oxide particles; in some embodiments, each level of underfill may include any suitable material capable of performing an underfill function (such as supporting the die and reducing thermal stresses acting on the interconnects). In some embodiments, the selection of underfill material may be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of underfill material may be based on material properties and processing conditions, such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of underfill material may be based on both design considerations and processing considerations.

[0053] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or illustrated to avoid obscuring the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may not be photoimageable.

[0054] The terms "substantially," "close," "approximately," "near," and "around" generally mean within + / - 20% of a target value (e.g., within + / - 5% or + / - 10% of a target value), based on the context of the specific values ​​described herein or as known in the art.

[0055] Terms indicating the orientation of elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, are generally meant to be within + / - 5%-20% of the target value, based on the context of specific values ​​described herein or as known in the art.

[0056] The word "connected" refers to a direct connection between the connected objects (which may be one or more of mechanical, electrical and / or thermal connections) without any intermediate devices, while the term "coupled" refers to a direct connection between the connected objects or an indirect connection through one or more passive or active intermediate devices.

[0057] The description uses the phrases "in an embodiment" or "in various embodiments," each of which may refer to one or more of the same embodiment or different embodiments.

[0058] Furthermore, the words "comprising," "including," "having," and the like used in connection with embodiments of the present disclosure are synonymous.

[0059] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0060] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two adjacent features may be in direct contact with the adjacent features, or may have one or more intervening layers.

[0061] As used herein, the term "disposed" refers to position, location, placement, and / or arrangement rather than any particular method of formation.

[0062] When used in connection with a range of measurements, the phrase "between" includes both ends of the range of measurements.

[0063] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0064] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0065] Unless otherwise indicated, the use of ordinal adjectives such as "first", "second", "third", etc. to describe common objects simply indicates that different instances of similar objects are being referenced, and does not imply that the objects described must be in a certain temporal or spatial order in an arranged manner or in any other way.

[0066] In the detailed description below, reference is made to the accompanying drawings which form an integral part thereof, in which embodiments that can be practiced are shown by way of example. It should be understood that other embodiments may be employed and structural and logical changes may be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limiting sense.

[0067] The drawings are not necessarily drawn to scale.

[0068] In the drawings, like reference numerals denote like or similar elements / materials illustrated, and thus, unless otherwise stated, explanations of elements / materials with a given reference numeral provided in the context of one of the drawings apply to other drawings that may illustrate elements / materials with the same reference numeral. In addition, reference numerals in singular or plural form may be used in conjunction with a reference numeral to denote single or multiple instances of the same or similar type, class, or kind of element, respectively.

[0069] Furthermore, in the accompanying drawings, some schematic illustrations of exemplary structures of various devices and components described herein may be illustrated as having exact right angles and straight lines, but it should be understood that such schematic illustrations may not reflect real-life process limitations that may cause the features to appear less than "ideal" when any of the structures described herein are examined using, for example, images of appropriate characterization tools, such as scanning electron microscope (SEM) images, transmission electron microscope (SEM) images, or non-contact surface profilometers. In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, deviations in curvature or profile, pits or scratches, imperfectly straight edges of materials, tilted vias or other openings, unintended rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations or combined dislocations within (multiple) crystal regions, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device fabrication and / or packaging.

[0070] Note that in the drawings, various components (e.g., interconnects) are shown as aligned (at corresponding interfaces) only for ease of illustration; in reality, some or all of them may be misaligned. In addition, there may be other components in the assembly, such as bonding pads, landing pads, metallizations, etc., which are not shown in the drawings to avoid confusion. In addition, the drawings are intended to show the relative arrangement of components within their assemblies, and in general such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal relief). For example, in some other embodiments, the assemblies shown in the drawings may include more dies together with other electrical components. In addition, although some components of the assemblies are shown as planar rectangles or formed by rectangular entities in the drawings, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, which is determined by the manufacturing processes used to make the various components and is sometimes unavoidable due to these manufacturing processes.

[0071] In the drawings, specific numbers and arrangements of structures and components are described for purposes of illustration, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0072] Furthermore, unless otherwise stated, the structures shown in the drawings may take any appropriate form or shape depending on material properties, manufacturing processes and operating conditions.

[0073] For convenience, if there is a collection of drawings designated by different letters (e.g. Figures 1A-1D ), then such a collection may be referred to herein without those letters (e.g., as “FIG. 1”). Similarly, if there is a collection of reference numerals designated with different letters (e.g., 108A, 108B), then such a collection may be referred to herein without those letters (e.g., as “108”).

[0074] Each operation can be described as a discrete action or sequential operation in a manner that is most helpful for understanding the subject matter claimed for protection. However, the description order should not be inferred to imply that these operations are necessarily sequentially related. Specifically, these operations may not be performed in the order of introduction. The described operations may be performed in an order different from the described embodiments. In other embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0075] Exemplary Embodiments

[0076] Figure 1Ais a schematic cross-sectional view of an exemplary IC die 100 according to some embodiments of the present disclosure. In the illustrated embodiment, the IC die 100 includes a metallization stack 102 having a surface 104 and another surface 106 orthogonal thereto. In some embodiments, the surfaces 104 and 106 can be planarized. Generally speaking, IC dies other than the IC die 100 do not have planarized edges along the thickness, for example, the vertical surface corresponding to the surface 104 will be rough after undergoing a dicing operation when singulating the IC die from a wafer. In contrast, the surface 104 of the IC die 100 can be straight and planar, with a surface roughness of less than 10 angstroms and a total thickness variation (TTV) across the surface 104 of less than 3 microns.

[0077] The metallization stack 102 may be located on the substrate 110 (e.g., at the interface 108). The interface 108 may be orthogonal to the surface 104 and parallel to the surface 106 (e.g., located in the xy plane). It should be understood that although the interface 108 is located in the xy plane, the interface 108 may not be exactly planar. The substrate 110 may further include an active area 112. In some embodiments, the active area 112 may include transistors, diodes, and other active circuit units, and may be close to the interface 108. In some other embodiments, there may be no active area 112, or alternatively there may be no transistors, diodes, and other active circuit units in the active area 112. The substrate 110 may have a surface 114, which may be coplanar with the surface 104. In some embodiments, the substrate 110 may include the semiconductor materials listed above in the previous subsection. In other embodiments, the substrate 110 may include glass, ceramics, or other materials that may be suitable for creating functional elements of an IC.

[0078] In various embodiments, the metallization stack 102 may include a dielectric material or multiple layers of dielectric material and a conductive trace 120 passing through the dielectric material. The conductive trace 120 may be parallel to the surface 106, such that the conductive trace 120 is orthogonal to the surface 104. In some embodiments, the dielectric material of the metallization stack 102 may include silicon oxide; in other embodiments, the dielectric material of the metallization stack 102 may include any suitable dielectric material as described in the previous subsection that is used as an interlayer dielectric (ILD) in a typical semiconductor IC die. In many embodiments, the conductive trace 120 may include a conductive material, such as copper. In some embodiments, there may be 2 to 6 layers of conductive traces 120 in the multiple layers of dielectric material. Conductive vias 122 passing through the dielectric material may conductively connect the conductive trace 120 to the active circuit unit in the active area 112. The conductive vias 122 are orthogonal to the conductive trace 120. Conductive traces 120 may extend all the way to surface 104, such that portions of conductive traces 120 are exposed on surface 104; such exposed portions may form bonding portions 124. In various embodiments, there may be several conductive traces 120 between interface 108 and surface 106. One or more of conductive traces 120 may be exposed on surface 104 to serve as bonding portions 124. In some embodiments, the linear dimension (e.g., length, width, or diagonal dimension) of the largest bonding portion 124 may be less than 5 microns. In some embodiments, bonding portions 124 may be spaced apart at a pitch of less than 9 microns. In some embodiments, bonding pads (e.g., similar to conductive bonding pads 308 as shown in FIG. 3) may be formed on bonding portions 124 at surface 104.

[0079] Figure 1B 1 is a schematic cross-sectional view of another exemplary IC die 100 according to some other embodiments of the present disclosure. In some embodiments, the IC die 100 may include metallization stacks 102A and 102B on both sides of a substrate 110. The metallization stack 102A may share an interface 108A with the substrate 110, and the metallization stack 102B may share an interface 108B with the substrate 110. In some embodiments, as Figure 1B, active area 112 may be proximate to interface 108A; in other embodiments, active area 112 may be proximate to interface 108B. Conductive trace 120A and conductive via 122A may be located in metallization stack 102A. Conductive trace 120B and conductive via 122B may be located in metallization stack 102B. In some embodiments, conductive trace 120A may be configured to route signals, while conductive trace 120B may be configured to route power and ground to active area 112. In such embodiments, conductive trace 120B may be thicker than conductive trace 120A (i.e., conductive trace 120A may be thinner than conductive trace 120B). In other embodiments, conductive trace 120A and conductive trace 120B may be configured to route signals, power, and ground without distinguishing between them. In such embodiments, conductive traces 120A and 120B may have similar thicknesses. The TSV 202 passing through the substrate 110 may provide a conductive path between the conductive traces 120A and 120B and / or between the active region 112 and the conductive trace 120B. In some embodiments, the TSV 202 may pass through the active region 112 (eg, Figure 1C ).

[0080] Figure 1C is a schematic cross-sectional view of yet another exemplary IC die 100 according to some embodiments of the present disclosure. Figure 1C The IC die 100 shown in FIG. 1 is an assembly including a first IC die 100A and a second IC die 100B. In the illustrated embodiment, the first IC die 100A is coupled to the second IC die 100B in a front-to-front configuration via an interconnect 305. The first IC die 100A and the second IC die 100B may be selected from the following: Figure 1A. The first IC die 100A may include a metallization stack 102A having a surface 104A and another surface 106A orthogonal thereto. The metallization stack 102A may be coupled to a substrate 110A having an active area 112A along an interface 108A. The substrate 110A may have a surface 114, which may be coplanar with the surface 104A. The metallization stack 102A may include a dielectric material and a conductive trace 120A passing through the dielectric material. The conductive trace 120A may be parallel to the surface 106A, so that the conductive trace 120A is orthogonal to the surface 104A. A conductive via 122A passing through the dielectric material may conductively connect the conductive trace 120A to an active circuit unit in the active area 112A, and one or more conductive vias 122A may further extend through the active area 112A, as shown. The conductive via 122A is orthogonal to the conductive trace 120A. The conductive trace 120A may extend all the way to the surface 104A, such that a portion of the conductive trace 120A is exposed on the surface 104A; such exposed portion may form a bonding portion 124A.

[0081] The second IC die 100B may include a metallization stack 102B having a surface 104B and another surface 106B orthogonal thereto. The metallization stack 102B may be attached to a substrate 110B having an active area 112B along an interface 108B. The substrate 110B may have a surface 114B, which may be coplanar with the surface 104B and with the surfaces 104A, 114A. The metallization stack 102B may include a dielectric material and a conductive trace 120B passing through the dielectric material. The conductive trace 120B may be parallel to the surface 106B so that the conductive trace 120B is orthogonal to the surface 104B. The conductive via 122B passing through the dielectric material may conductively connect the conductive trace 120B to the active circuit unit in the active area 112B, and one or more conductive vias 122B may further extend through the active area 112B, as shown. Conductive via 122B is orthogonal to conductive trace 120B. Conductive trace 120B may extend all the way to surface 104B such that a portion of conductive trace 120B is exposed on surface 104B; such exposed portion may form bonding portion 124B. Conductive via 122A of first IC die 100A may be coupled to conductive via 122B of second IC die 100B via interconnect 305. Interconnect 305 may include any suitable interconnect, such as, for example, a hybrid bond (e.g., a bond pad in dielectric material 115 that will form an oxide-oxide bond as well as a metal-metal bond), as described below with reference to interconnect 304 in FIG. 3 .

[0082] Figure 1D1 is a schematic cross-sectional view of another exemplary IC die 100 according to some embodiments of the present disclosure. The IC die 100 may include a substrate 110 and more than one metallization stack 102. The metallization stack 102A has mutually orthogonal surfaces 104 and 106, as shown in FIG. Figure 1A The metallization stack 102A is located on the substrate 110 along an interface 108A, which is orthogonal to the surface 104 and parallel to the surface 106. The metallization stack 102A may include a dielectric material (e.g., Figure 3B The metallization stack 102A may further include a dielectric material 116 as shown in FIG. 1 and multiple layers of conductive traces 120A in the dielectric material, each layer of conductive traces 120A being parallel to the surface 106 (and the interface 108A) such that the conductive traces 120A are orthogonal to the surface 104. The metallization stack 102A may also include conductive vias 122A passing through the dielectric material, the conductive vias 122A being orthogonal to the conductive traces 120A. Figure 1A As in the embodiment of the present invention, a bonding portion 124 including a portion of the conductive trace 120A exposed on the surface 104 is provided to the surface 104. In various embodiments, the substrate 110 may include a reference Figure 1A Semiconductor materials discussed in the previous subsection. In various embodiments, the active region 112A in the substrate 110 may be disposed on a side of the substrate 110 that is away from the interface 108A.

[0083] In many embodiments, the IC die 100 may include another metallization stack 102B located on the substrate 110 along another interface 108B. In many embodiments, the active area 112A may be proximate to the interface 108B. The metallization stack 102B may include conductive traces 120B and conductive vias (not labeled to avoid cluttering the drawing) located in the dielectric material. The metallization stack 102B may be located on another metallization stack 102C along another interface 108C. The metallization stack 102C may include conductive traces 120C and conductive vias (not labeled to avoid cluttering the drawing). The conductive trace 120C may be conductively coupled to the conductive trace 120B at the interface 108C by an interconnect 128. The interconnect 128 may include any suitable interconnect technology for interconnecting the conductive traces / vias in the stack 102B with the conductive traces / vias in the stack 102C. For example, in some embodiments, interconnect 128 may include a hybrid bonding interface such that some traces or vias in stack 102B are directly bonded to some traces or vias in stack 102C.

[0084] The metallization stack 102C can be substantially similar to the metallization stack 102B, except that the metallization stack 102C can further include optical structures 130 of the photonic IC. For example, the metallization stack 102C can include an optical waveguide. The metallization stack 102C can be attached to another active area 112B along another interface 108D via an interconnect 305. The interconnect 305 can include any suitable interconnect, for example, a hybrid bond (e.g., a bond pad in the dielectric material 115, which will form an oxide-oxide bond and a metal-metal bond), as described below with reference to the interconnect 304 in FIG. 3. The interfaces 108A-108D can be parallel to each other and orthogonal to the surface 104. The active area 112B can include other optical structures 130 of the photonic circuit, for example, electromagnetic radiation sources such as lasers and LEDs and electromagnetic radiation detectors such as electro-optical optical detectors, which are optically coupled to the optical waveguides in the metallization stack 102C. Active region 112B may also include electronic circuitry that may be coupled to conductive traces 120C in metallization stack 102C. In many embodiments, photonic circuitry and electronic circuitry may be fabricated into suitable materials, for example, as discussed in the previous subsection with reference to materials suitable for photonic ICs. In various embodiments, at least some optical structures 130 (e.g., optical waveguides) may be sandwiched between active region 112A and active region 112B.

[0085] The optical structure 130 may include one or more electromagnetic radiation sources that can enable the generation of optical signals and may include a laser, for example, having a wavelength between about 0.8 and 1.7 microns; or an oscillator, for example, that generates electromagnetic radiation with a wavelength on the order of millimeters; or some combination of a laser and an oscillator, for example, that generates electromagnetic energy with a wavelength between 0.8 microns and several millimeters or centimeters. Other optical structures 130 (e.g., electro-optical devices) can enable the reception, conversion, and transmission of optical signals. In some embodiments, the electro-optical device can be any device or component configured to encode information into / onto an electromagnetic signal, such as a modulator, a polarizer, a phase shifter, and a photodetector.

[0086] The optical structure 130 may include a waveguide that can guide optical signals and can also perform coupling, switching, splitting, multiplexing and demultiplexing of optical signals. In some embodiments, the waveguide may include any component that feeds or loads an electromagnetic signal into a propagation medium (e.g., an optical fiber). In some embodiments, the waveguide may be further configured as an optical multiplexer and / or demultiplexer, thereby (for example) performing frequency division multiplexing (FDM) or wavelength division multiplexing (WDM). In some embodiments, the waveguide may include a demultiplexer, such as an arrayed waveguide grating (AWG) demultiplexer, an echelle grating, a single mode waveguide, or a thin film filter (TFF) demultiplexer.

[0087] The waveguide may include any type of planar and non-planar waveguide. In one example, the waveguide may include a silicon photonic waveguide based on a silicon on insulator (SOI) platform, which is configured to guide electromagnetic radiation in any band from about 0.8 microns to about 5 centimeters. In another example, the waveguide may support wavelengths of about 1.2 microns to about 1.7 microns in the near infrared and infrared bands used in data communications and telecommunications. In another example, the waveguide may support wavelengths in the extremely high frequency (EHF) radio / microwave bands of about 1 micron to about 10 microns, and in particular, wavelengths of about 2 millimeters may be used for radar and radio frequency (RF) radio communications.

[0088] In general, the light provided to the optical structure 130 may include any electromagnetic signal having information encoded therein (or in other words, any electromagnetic signal modulated to contain information). Electromagnetic signals are often associated with optical amplitude, phase, and wavelength, and thus the description provided herein relates to "optical" signals (or light) and "optical" components. However, the optical structure 130 as described herein is not limited to operating with electromagnetic signals having a spectrum, and the description provided herein with reference to optical signals and / or optical components is equally applicable to electromagnetic signals of any appropriate wavelength, for example, electromagnetic signals within the near infrared (NIR) and / or infrared (IR) bands and electromagnetic signals within the RF and / or microwave bands.

[0089] In various embodiments, the surface of one or more optical structures 130 (e.g., optical waveguides) in the metallization stack 102C exposed on the side of the IC die 100 opposite the surface 104 can be configured to be coupled to an optical fiber. In many embodiments, the substrate 110 can further include through-substrate vias (TSVs) 202 that conductively couple the conductive traces 120A in the metallization stack 102A with the conductive traces 120B in the metallization stack 102B and / or the active area 112A. In some embodiments, the optical structures 130 can provide optical connections for signal propagation between circuits in the active area 112A (i.e., intra-die connections). In other embodiments, the optical structures 130 can provide optical connections for signal propagation between IC dies 100, for example, through optical fibers (not shown) coupled to the optical structures 130.

[0090] Figure 2A is a simplified perspective view of IC die 100 . Figure 2A shows a 90 degree rotation Figure 1AThe IC die 100 is formed of a substrate 110, such that surfaces 114 and 104 are located at the bottom and surface 106 is located at a side position. The IC die 100 may include a substrate 110, an active area 112, and a metallization stack 102. The IC die 100 may have any suitable size. In various embodiments, the IC die 100 may have a thickness (e.g., z dimension) between 10 microns and 800 microns (e.g., between 10 microns and 100 microns), a width (e.g., y dimension) between 1 mm and 6 mm, and a length (e.g., x dimension) between 10 mm and 33 mm. The substrate 110 of the IC die 100 may be thinned so that the IC die 100 has a desired thickness.

[0091] Figure 2B is a simplified perspective view of IC die 100 . Figure 2B shows a 90 degree rotation Figure 1B The IC die 100 is configured such that the surfaces 114, 104A, and 104B are located at the bottom and the surfaces 106A, 106B are located at the side positions. The IC die 100 may include a substrate 110, an active area 112, and metallization stacks 102A, 102B. The IC die 100 may have any suitable size, including as described above with reference to Figure 2A The substrate 110 may have any suitable thickness (e.g., z-dimension). For example, the substrate 110 may have a thickness of less than between 1 micron and 50 microns (e.g., between 0.25 microns and 5 microns or between 20 microns and 50 microns). In some embodiments, the substrate 110 may be almost completely removed so that the TSVs 202 may be very thin (e.g., having a thickness of less than 1 micron) and may provide direct contact to the transistor source / drain in the active region 112.

[0092] Figure 2C is a simplified perspective view of IC die 100 . Figure 2C shows a 90 degree rotation Figure 1C The IC die 100 is configured such that the surfaces 114A, 114B, 104A, and 104B are located at the bottom and the surfaces 106A, 106B are located at the side positions. The IC die 100 may include substrates 110A, 110B, active areas 112A, 112B, metallization stacks 102A, 102B, and a dielectric 115 having interconnects 305. In various embodiments, the IC die 100 may have a thickness (e.g., z-dimension) between 20 microns and 1600 microns (e.g., between 20 microns and 200 microns), a width (e.g., y-dimension) between 1 mm and 6 mm, and a length (e.g., x-dimension) between 10 mm and 33 mm.

[0093] Figure 2D is a simplified perspective view of IC die 100 . Figure 2Dshows a 90 degree rotation Figure 1D The IC die 100 is configured such that the surfaces 114, 104A, 104B, and 104C are located at the bottom and the surfaces 106A, 106B are located at the side positions. The IC die 100 may include a substrate 110, active areas 112A, 112B, and metallization stacks 102A, 102B, and 102C. The IC die 100 may have any suitable size, including as described above with reference to Figure 2A Dimensions as stated.

[0094] Figures 3A-3D Simplified schematic cross-sectional views of various configurations of a microelectronic assembly 300 are shown according to embodiments of the present disclosure. Figure 3A A microelectronic assembly 300 is shown that includes a plurality of IC dies 100, e.g., 100(1), 100(2), and 100(3), coupled to another IC die 302 via an interconnect 304 such that a surface 104 of any one of the IC dies 100 is in direct contact with a surface 306 of the IC die 302. As described in connection with FIGS. 1-2, the surface 104 is orthogonal to an interface 108 between an active region 112 and a metallization stack 102 of any one of the IC dies 100. In some embodiments, the IC dies 100 may include active circuit elements (e.g., transistors, diodes) located in the active region 112. In other embodiments, one or more of the IC dies 100 may not include active circuit elements located in the active region 112; in such embodiments, the active region 112 may be fused to the substrate 110 (e.g., without the active region 112).

[0095] In various embodiments, IC die 302 may include an interposer with conductive traces, thereby enabling IC die 100 to be conductively coupled to other IC die and / or package substrates, and IC die 302 may not have any active circuit units located therein. In other embodiments, IC die 302 may include active circuit units. In many embodiments, IC die 100 may be conductively coupled through conductive paths in IC die 302. For example, IC die 302 may include an on-chip network, thereby interconnecting the computing circuit units of IC die 100 together. In various embodiments, IC die 100 may be conductively coupled to IC die 302 through interconnect 304 including hybrid bonding. In such a configuration, surface 114 of substrate 110 of IC die 100 may be in direct contact with surface 306 of IC die 302.

[0096] Figure 3B302. FIG. 3 is a schematic cross-sectional view of a detail of a particular one of the interconnects 304 in the microelectronic assembly 300. Note that although only the interconnect 304 is shown, the same structure and description may apply to any other such interconnects, including hybrid bonding, in the microelectronic assembly 300. In a general sense, the interconnect 304 may include metal-metal bonding between the bonding portion 124 of the IC die 100 and the bonding pad 308 of the IC die 302 and dielectric-dielectric bonding (e.g., oxide-oxide bonding) in the dielectric materials 116 and 310 of the IC dies 100 and 302, respectively, at the interface between the surface 104 of the IC die 100 and the surface 306 of the IC die 302. The bonding portion 124 belonging to the IC die 100 may be bonded to the bonding pad 308 of the IC die 302. As indicated in the description of FIG. 1 , bonding portion 124 may include a portion of conductive trace 120 exposed on surface 104; bonding pad 308 may include a conventional conductive structure plated on surface 306. Dielectric material 116 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in IC die 100 may be bonded to dielectric material 310 in IC die 302. In some embodiments, dielectric material 310 in IC die 302 is the same as dielectric material 116 in IC die 100. In various embodiments, dielectric material 310 includes silicon oxide, silicon nitride, silicon carbonitride, and other such inorganic materials commonly used in making semiconductor IC dies. The bonded metal material and dielectric material form interconnect 304 including hybrid bonding, which provides electrical and mechanical coupling between IC die 100 and IC die 302. In various embodiments, interconnect 304 may have a linear dimension of less than 5 microns and a spacing of less than 10 microns between adjacent interconnects.

[0097] Re-watch Figure 3A , IC die 100 can be coupled to IC die 302 such that metallization stack 102 of one of IC die 100 (e.g., 100(1)) can be in direct contact with substrate 110 of an adjacent IC die 100 (e.g., 100(2)). In some such embodiments, IC die 100(1) and 100(2) can be bonded to each other at least via oxide-oxide bonding. In some embodiments, including reference Figure 3BThe depicted metal-metal bonded and oxide-oxide bonded interconnects 304 may be present at the planar contact interface between IC dies 100(1) and 100(2). In some such embodiments, conductive contact between active regions 112 of IC dies 100(1) and 100(2) may be achieved via conductive traces 120 in IC die 100(1), interconnects 304 at the interface between IC dies 100(1) and 100(2), and TSVs 202 in IC die 100(2); in such embodiments, TSVs 202 are in conductive contact with interconnects 304 between IC dies 100(1) and 100(2). In other embodiments (not shown), metallization stacks 102 of IC dies 100(1) and 100(2) may be contacted in a front-to-front configuration. In still other embodiments (not shown), the substrates 110 of the IC dies 100 ( 1 ) and 100 ( 2 ) may be contacted in a back-to-back configuration.

[0098] In various embodiments, the IC die 100 can be arranged in parallel rows so that gaps 312 exist between adjacent IC die 100. In some embodiments, the gaps 312 can be uniform across the microelectronic assembly 300 and can be within a range of about a few millimeters (e.g., less than 5 millimeters); in other embodiments, the gaps 312 can be non-uniform, where some IC die 100 are closer to each other than other IC die 100. In some such embodiments, the IC die 100 can include circuit units that consume power and generate heat during operation. For example, the IC die 100 can include computing circuit units of a microprocessor. The gaps 312 can be configured to flow a cooling fluid therethrough. In some embodiments, the cooling fluid (not shown) can be air; in other embodiments, the cooling fluid can be a liquid coolant.

[0099] In some embodiments, IC die 100 may include computing circuit units, and IC die 302 may include on-chip network circuit units that conductively couple arrays of IC die 100. In some other embodiments, some IC die 100 may include graphics processing circuit units, and other IC die may include computer circuit units, and IC die 302 may include memory circuit units. Among the various IC die 100 and IC die 302, any appropriately configured circuit units may be provided in microelectronic assembly 300 as desired and based on specific needs.

[0100] Figure 3C According to some embodiments of the present disclosure Figure 3ASchematic cross-sectional view of a portion 313 of a microelectronic assembly 300. The IC die 302 may include a metallization stack 314 attached to a substrate 316 having an active area 318. The substrate 316 is attached to the metallization stack 314 along an interface 320 parallel to the surface 306. In some embodiments, the active area 318 includes active circuit units (not shown) including transistors and diodes. In such embodiments, the active area 318 may be proximate to the interface 320. In some embodiments, the active area 318 may not be present. The metallization stack 314 may further include conductive paths (e.g., conductive traces 322 and conductive vias 324) located in the dielectric material. In some embodiments, the dielectric material of the metallization stack 314 is Figure 3B The dielectric material 310 in the conductive pad 308. The conductive trace 322 can be coupled to the bonding pad 308 through the conductive via 324.

[0101] Figure 3D According to some embodiments of the present disclosure Figure 3A Schematic cross-sectional view of a portion 313 of a microelectronic assembly 300. The IC die 302 may be substantially similar to Figure 3C The embodiment of the present invention is similar to that of the present invention, except that the IC die 302 is inverted (e.g., upside down) so that the substrate 316 is close to the surface 104 of the IC die 100. In such an embodiment, the IC die 302 can include an interface layer 326 (e.g., a bonding layer) located on the side of the substrate 316 opposite the metallization stack 314. The interface layer 326 includes the bonding pads 308 and a dielectric material located between (e.g., surrounding) the bonding pads 308, such that the interconnect 304 is formed by metal-to-metal bonding of the bonding portion 124 to the bonding pads 308 and oxide-to-oxide bonding of the dielectric material of the substrate 110 of the IC die 100(3) to the dielectric material of the interface layer 326 of the IC die 302. In some embodiments, the dielectric material of the interface layer 326 is Figure 3B The dielectric material of the interface layer 326 is the same material as the dielectric material 310. In some embodiments, the dielectric material of the interface layer 326 is Figure 3B The same material as the dielectric material 116 of the IC die 100. In various embodiments, the dielectric material of the interface layer 326 may include silicon oxide, silicon nitride, silicon carbonitride, or other such inorganic materials commonly used to make semiconductor IC dies. In such an embodiment, the IC die 302 may further include TSVs 330 located in the substrate 316 between the interface layer 326 and the metallization stack 314. The TSVs 330 may enable electrical connections between the interconnects 304 and the active regions 318 and / or the conductive traces 322 in the IC die 302.

[0102] Figure 4A Yes Figure 2A 3 . A simplified perspective view of an exemplary microelectronic assembly 300 having an IC die 100 is shown. Note that for ease of illustration and to not clutter the drawing, the figure is not drawn to scale and detailed features are not shown. Multiple IC dies 100 (e.g., IC dies 100(1), 100(2), and 100(3)) can be coupled to a surface 306 of an IC die 302 at respective surfaces 104 (e.g., surfaces 104(1), 104(2), and 104(3)). The multiple IC dies 100 can be coupled to the IC die 302 by any suitable interconnects (e.g., interconnect 304 in FIG. 3 ). In many embodiments, the IC die 302 can be of large size, for example, as large as a conventional recticle, which can occupy an area of ​​approximately 850 square millimeters. Although Figure 4A The IC dies 100 are shown having the metallization stacks 102 ( 1 ), 102 ( 2 ), and 102 ( 3 ) facing away from each other, but in some embodiments one or more of the IC dies 100 may have the metallization stacks 102 facing each other.

[0103] Figure 4B Yes Figure 2B 3 . A simplified perspective view of an exemplary microelectronic assembly 300 with an IC die 100 is shown. Note that the figure is not drawn to scale and detailed features are not shown for ease of illustration and to avoid cluttering the drawing. Multiple IC dies 100 (e.g., IC dies 100(1), 100(2), 100(3), and 100(4)) can be coupled to a surface 306 of an IC die 302 at respective surfaces 104A, 104B. The IC dies 100 can be stacked vertically and bonded together, for example, by oxide-oxide bonding or inorganic dielectric-inorganic dielectric bonding. The bonded IC dies 100 in the stacked arrangement can be rotated 90 degrees and electrically coupled to the IC die 302. The multiple IC dies 100 can be coupled to the IC die 302 by any suitable interconnect (e.g., interconnect 304 in FIG. 3 ). Stacking and bonding IC die 100 before coupling IC die 100 to IC die 302 may allow IC die 100 to be more easily handled during assembly operations. Any suitable number of IC die 100 may be stacked and bonded together, for example, between 2 and 100. Although Figure 4B While the IC dies 100 are shown with a particular stacking arrangement (e.g., all facing the same direction), in some embodiments, one or more of the IC dies 100 may have a different stacking arrangement (e.g., one or more of the IC dies 100 may be flipped to face the opposite direction). Figure 4B include Figure 1BIC die 100, but the stack of IC die 100 may include Figures 1A-1D any IC die 100.

[0104] Figure 5A is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in this figure is substantially the same as Figure 3A 1, 2, and 3. The microelectronic assembly 300 is similar to the embodiment of , except that the IC dies 100 are not bonded together (e.g., at the surface 106) but are separated by gaps 312(1) and 312(2), and the microelectronic assembly 300 further includes voltage regulator (VR) dies 350 (e.g., VR dies 350(1), 350(2), and 350(3)) and a package substrate 404. Individual IC dies 100 are coupled to individual VR dies 350 such that each IC die 100 is coupled to a respective VR die 350 and the respective VR die 350 provides regulated power in the range between 0.2 volts (V) and 2 V to the respective IC die 100.

[0105] VR die 350 may include electronic components and circuit units for maintaining a constant voltage. For example, VR die 350 may include a voltage input, a voltage output, an input capacitor, an output capacitor, an inductor, a switching transistor and / or a diode, and a control circuit having a plurality of transistors to perform voltage regulation and control the switching transistor and / or the diode. VR die 350 may be a separate IC die, such as Figure 5A , or may be integrated into a base die (eg, IC die 302), as shown in Figure 5B and Figure 5C . The microelectronic assembly 300 may include a plurality of IC dies 100 and a plurality of VR dies 350, wherein each VR die 350 regulates power delivery to a corresponding IC die 100, the power being at the same or different voltages / frequencies. In various embodiments, the VR die 350 may include various voltage rails configured to provide current at corresponding different voltages. The VR die 350 may be fabricated using a process particularly suitable for a voltage regulator circuit cell, such as a special silicon process or a process using a III-V compound (e.g., gallium nitride or silicon carbide) to support improved power conversion. The VR die 350 may include an active surface (e.g., a first surface) and a back surface (e.g., an opposite second surface), wherein the active surface includes a metallization stack and the back surface includes a substrate.

[0106] The active surface of VR die 350 can be electrically coupled to IC die 302 via interconnects 304 at surface 306. Interconnects 304 can include metal-metal bonds and dielectric-dielectric bonds, for example, as described in reference Figure 3BAs described. In some embodiments, VR die 350 can be electrically coupled to IC die 100 via conductive pathways 323 through IC die 302 and interconnects 304 at surface 104 (e.g., as shown for VR 350(1) and 350(2)). In some embodiments, VR die 350 can be electrically coupled to IC die 100 via interconnects 304 at surface 106 (e.g., as shown for VR 350(1) and 350(3)). The lateral surface of VR die 350 with interconnects 304 can also be planarized. VR die 350 can be electrically coupled to one or more power supplies 325 in package substrate 404 via conductive pathways 323 through IC die 302 and TSV 202 and via interconnects 352. The one or more power supplies 325 in package substrate 404 can be configured to deliver unregulated power at 5V or 2V.

[0107] The package substrate 404 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) through which power, ground, and signals are directed. In some embodiments, the insulating material of the package substrate 404 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Specifically, when the package substrate 404 is formed using a standard printed circuit board (PCB) process, the package substrate 404 may include FR-4, and the conductive paths in the package substrate 404 may be formed by patterned copper sheets separated by build-up layers of FR-4. The conductive paths in the package substrate 404 may be appropriately bordered with a liner material (such as an adhesive liner and / or a barrier liner). In some embodiments, the package substrate 404 may be formed using a photolithographically defined via package process. In some embodiments, the package substrate 404 may be manufactured using a standard organic package manufacturing process, and thus the package substrate 404 may take the form of an organic package. In some embodiments, the package substrate 404 may be a set of redistribution layers formed on a flat carrier, formed by laminating or spin coating on a dielectric material and establishing conductive vias and conductive lines by laser drilling and plating. In some embodiments, the package substrate 404 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for making the package substrate 404 may be used, and for the sake of brevity, such methods will not be further discussed here.

[0108] The IC die 302 may be coupled to the package substrate 404 via the interconnect 352. The interconnect 352 disclosed herein may take any suitable form. When describing the interconnect herein, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts of the first set may be electrically and mechanically coupled to some conductive contacts of the second set via the interconnect. In some embodiments, a set of interconnects 352 may include solder (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the interconnect 352). The interconnect 352 including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth or other alloys. In some embodiments, a set of interconnects 352 may include an anisotropic conductive material, for example, an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include tiny conductive particles embedded in an adhesive or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy or acrylic resin material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include gold coated with nickel or copper coated with silver, which in turn will be coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is fully compressed (e.g., through conductive contacts located on both sides of the anisotropic conductive material), the conductive materials near the compressed area may contact each other, thereby forming a conductive path from one side of the film to the other side in the compressed area.

[0109] In some embodiments, some interconnects in a microelectronic assembly or IC package described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the conductive contacts on both sides of the interconnect may be bonded together (e.g., under elevated pressure and temperature) without the use of an intervening solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the metals bonded together (e.g., between copper pads or copper pillars providing associated conductive contacts). In some embodiments, one side of the interconnect may include a metal pillar (e.g., a copper pillar) and the other side of the interconnect may include a metal contact (e.g., a copper contact) sunk into the dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxide is conductive (e.g., silver). In some embodiments, a metal-to-metal interconnect may include a metal nanostructure (e.g., a nanorod) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be limited to mitigate mechanical failure.

[0110] In some embodiments, a thin solder cap may be used in a metal-to-metal interconnect to provide planarity, and this solder may become an intermetallic compound during processing. In some embodiments, the solder used in some interconnects may have a higher melting point than the solder contained in other interconnects. For example, when forming interconnects in an IC package before forming other interconnects, the solder-based interconnect formed first may use a higher temperature solder (e.g., a melting point above 200 degrees Celsius), while the interconnect formed second may use a lower temperature solder (e.g., a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0111] In some embodiments, the microelectronic assembly 300 may further include an underfill material 127. In some embodiments, the underfill material 127 may extend around the associated interconnect 352 between the bottom surface of the IC die 302 and the top surface of the package substrate 404. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that facilitates soldering the IC die 302 to the package substrate 404 when forming the interconnect 352, then polymerizes the interconnect 352 and encapsulates the interconnect 352. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that can relieve or minimize stress between the IC die 302 and the package substrate 404 caused by uneven thermal expansion within the microelectronic assembly 300.

[0112] In some embodiments, the microelectronic assembly 300 may also include a circuit board (not shown). The package substrate 404 may be coupled to the circuit board via an interconnect (not shown) located at the bottom surface of the package substrate 404. The interconnect may be any suitable interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As is known in the art, the circuit board may include conductive pathways and other conductive contacts for directing power, ground, and signals through the circuit board. In some embodiments, the interconnect may not couple the package substrate 404 to the circuit board, but may couple the package substrate 404 to another IC package, an interposer, or any other suitable component.

[0113] Figure 5B is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in this figure is substantially the same as Figure 5A 302, except that VR die 350 (e.g., VR die 350(1), 350(2), and 350(3)) are integrated into IC die 302. VR die 350 is electrically coupled to a corresponding IC die 100 via interconnects 304 (e.g., at the interface of surface 104 of IC die 100 and surface 306 of IC die 302). Conductive pathways 323 in IC die 302 are not shown to avoid cluttering the drawing.

[0114] Figure 5C is a schematic cross-sectional view of another exemplary microelectronic assembly 300 according to some embodiments of the present disclosure. Figure 5B The embodiment is similar to that of Figure 1B The embodiments shown in Figure 4B As shown, the microelectronic assembly 300 is stacked together, and the microelectronic assembly 300 further includes other IC dies stacked together. Figure 5C As shown in , IC die 302 can be coupled to a stack of other IC dies 402 (e.g., 402(1), 402(2), etc.) such that IC die 302 is the topmost one of the stack of IC dies 402. The bottommost IC die 402 can be coupled to package substrate 404 via interconnect 352. The stack of IC dies 402 (including IC die 302) can include a high bandwidth memory (HMB) circuit unit, and the vertically stacked IC die 100 on IC die 302 can include a computing circuit unit that can be directly interfaced with the HBM circuit unit via interconnect 354 and TSVs 202 in IC die 302 and IC die 402. Interconnect 354 can include any suitable interconnect, such as interconnect 304 or interconnect 352, etc. Various other circuit configurations are also included within the broad scope of the embodiments disclosed herein.

[0115] In various embodiments, any of the features discussed with reference to any of the figures in FIGS. 1-5 herein may be combined with any other features to form a package with one or more IC dies as described herein, for example, to form a modified IC die 100 or a modified microelectronic assembly 300. Some such combinations are described above, but other combinations and modifications are possible in various embodiments. The various different embodiments depicted in the different figures may be appropriately combined within the broad scope of the embodiments based on specific needs.

[0116] Exemplary Methods

[0117] Figure 6 is a simplified flow chart showing exemplary operations that may be associated with fabricating certain embodiments of microelectronic assembly 300. In 602, an IC die 100 having planarized surfaces 104 and 106 (along with other surfaces) may be fabricated. Fabrication of such an IC die 100 may include semiconductor manufacturing operations known in the art. For example, a wafer including a portion of IC die 100 including substrate 110 having TSV 202 is provided, metallization stack 102A is coupled to substrate 110 along interface 108A, and metallization stack 102B is coupled to substrate 110 along interface 108B.

[0118] Accordingly, in some embodiments, for example, Figure 1BAs shown in , the conductive traces 120B in the metallization stack 102B can be thicker than the conductive traces 120A in the metallization stack 102A. In some other embodiments (e.g., Figure 1D ), the metallization stack 102B may additionally include a metallization stack 102C and an active area 112B having an optical structure 130. Exemplary operations may further include stacking a plurality of wafers, dicing the plurality of wafers into stacks of individual IC dies 100, planarizing a surface 104 orthogonal to the interfaces 108A and 108B, and separating individual IC dies 100 from each stack.

[0119] In 604, the IC die 100 (e.g., a first IC die) can be electrically coupled to the surface 306 of the IC die 302 using interconnects 304 including metal-metal bonds and dielectric-dielectric bonds along corresponding lateral surfaces 104 (e.g., planarized surfaces orthogonal to the surface 106) of the IC die 100. In various embodiments, the IC die 302 can include an "interposer" IC die, thereby providing a conductive path between the IC die 100 and the package substrate 404 or other components. As described with reference to FIG. 3, the IC die 302 can include a corresponding substrate 316 attached to a corresponding metallization stack 314 along an interface 320 orthogonal to the interfaces 108A and 108B. The IC die 100 can be one of a plurality of IC dies 100 that can be electrically coupled to the surface 306 of the IC die 302.

[0120] In 606, the VR die 350 can be electrically coupled to the surface 306 of the IC die 302 (e.g., the second die) by means of the interconnect 304 including metal-metal bonding and dielectric-dielectric bonding. In various embodiments, the VR die 350 can include VR circuit units and other components for regulating voltage. In various embodiments, the IC die 302 can provide a conductive path between the IC die 100 and the VR die 350. The VR die 350 can be one of a plurality of VR dies 350 that can be electrically coupled to the surface 306 of the IC die 302. Individual IC dies 100 of the plurality of IC dies 100 can be electrically coupled to individual VR dies 350 of the plurality of VR dies 350 through conductive paths in the IC die 302.

[0121] At 608 , VR die 350 may be electrically coupled to a power source. For example, package substrate 404 having a power source or connection to a power source may be electrically coupled to IC die 302 .

[0122] Figure 7is a simplified flow chart showing exemplary operations that may be associated with fabricating certain embodiments of microelectronic assembly 300. At 702, IC die 100 (eg, a first IC die) having planarized surfaces 104 and 106 (along with other surfaces) may be fabricated. Figure 6 The operations described perform the fabrication of such an IC die 100. The IC die 100 may include a first surface, an opposite second surface 106, and a third surface 104 orthogonal to the first and second surfaces. The IC die 100 may further include conductive traces parallel to the first and second surfaces and the conductive traces are exposed at the third surface 104 (e.g., a side surface) as conductive bonding portions 124. The third surface 104 may include a conductive bonding portion and the second surface 106 may include a first conductive bonding pad.

[0123] In 704, a VR die 350 may be fabricated, which includes a fourth surface (e.g., an active surface) having a second conductive bonding pad and a fifth surface (e.g., a side surface) having a third conductive bonding pad orthogonal to the fourth surface. The fourth surface and the fifth surface of the VR die 350 may be planarized. The VR die 350 may be coupled to the surface 104 of the IC die 100 through interconnects 304 including metal-metal bonding and dielectric-dielectric bonding. Specifically, the third conductive bonding pad on the fifth surface (e.g., the side surface) of the VR die 350 may be electrically coupled to the first conductive bonding pad on the second surface 106 of the IC die 100. In various embodiments, the interconnects 304 formed between the IC die 100 and the VR die 350 may provide a direct communication path between the IC die 100 and the VR die 350. The IC die 100 and the VR die 350 may be one of a plurality of IC dies 100 and a plurality of VR dies 350, respectively. Individual ones of the plurality of IC dies 100 may be electrically coupled to individual ones of the plurality of VR dies 350 through interconnects 304 between third conductive bonding pads on the fifth surface of the VR die 350 and first conductive bonding pads on the surface 106 of the IC die 100 .

[0124] In 706, the conductive bonding portion at the third surface 104 of the IC die 100 (e.g., the first IC die) can be electrically coupled to the fourth conductive bonding pad at the sixth surface (e.g., surface 306) of the IC die 302 (e.g., the second IC die), thereby forming the interconnect 304, and the second conductive bonding pad at the fourth surface (e.g., the active surface) of the VR die 350 can be electrically coupled to the fourth conductive bonding pad at the sixth surface (e.g., surface 306) of the IC die 302, thereby forming the interconnect 304. The interconnect 304 can include metal-metal bonding and dielectric-dielectric bonding. Individual IC dies 100 of the plurality of IC dies 100 can be coupled to individual VR dies 350 of the plurality of VR dies 350, and the plurality of IC dies 100 and the plurality of VR dies 350 can be electrically coupled to the surface 306 of the IC die 302.

[0125] At 708 , VR die 350 may be electrically coupled to a power source. For example, package substrate 404 having a power source or connection to a power source may be electrically coupled to IC die 302 .

[0126] Figure 8 8 is a simplified flow chart showing exemplary operations that may be associated with fabricating certain embodiments of microelectronic assembly 300. At 802, IC die 100 (eg, first IC die) having planarized surfaces 104 and 106 (along with other surfaces) may be fabricated. Figure 6 The operations described perform the fabrication of such an IC die 100. The IC die 100 may include a first surface, an opposite second surface 106, and a third surface 104 orthogonal to the first and second surfaces. The IC die 100 may further include conductive traces parallel to the first and second surfaces and the conductive traces are exposed at the third surface 104 (e.g., a side surface) as conductive bonding portions 124. The third surface 104 may include conductive bonding portions.

[0127] At 804, the IC dies 100 are stacked on the first and second surfaces and the stacked IC dies 100 are bonded together. In some embodiments, the IC dies 100 may be stacked on a carrier, bonded together, and then removed from the carrier. Before or after being stacked and bonded together, the side surfaces 104 of the IC dies 100 may be planarized. In some embodiments, a wafer including the IC dies 100 may be stacked, bonded together, and then singulated and planarized.

[0128] In 806, the conductive bonding portion at the third surface 104 of the IC die 100 (e.g., the first IC die) can be electrically coupled to the second conductive bonding pad at the fourth surface (e.g., surface 306) of the IC die 302 (e.g., the second IC die), thereby forming the interconnect 304. The interconnect 304 can include metal-metal bonding and dielectric-dielectric bonding. The IC die 302 can include a plurality of VR circuit cells 350 and individual IC dies 100 of the plurality of IC dies 100 can be electrically coupled to individual VR circuit cells 350 of the plurality of VR circuit cells 350.

[0129] At 808 , the VR circuit unit 350 in the IC die 302 may be electrically coupled to a power source. For example, a package substrate 404 having a power source or a connection to a power source may be electrically coupled to the IC die 302 .

[0130] although Figure 6-8 Various operations are shown to be performed in a particular order, but this is only illustrative, and the operations discussed herein may be reordered and / or repeated as appropriate. In addition, additional processes not shown may be performed without departing from the scope of the present disclosure. Moreover, the present disclosure may be modified in accordance with the present disclosure. Figure 6-8 Each of the operations discussed in the present invention may be performed to produce other microelectronic packages 300 disclosed herein. Although various operations are illustrated once each, these operations may be repeated as often as desired. For example, one or more operations may be performed in parallel to manufacture and test multiple microelectronic packages substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a particular microelectronic package that may include one or more substrates or other components as described herein.

[0131] also, Figure 6-8 The operations shown in the drawings may be combined or may include more details than described. For example, the operations may be appropriately modified for an IC die 100 that does not have a semiconductor substrate but is fabricated on other materials (e.g., glass or ceramic materials) without departing from the scope of the present disclosure. In addition, the various operations shown and described may further include other manufacturing operations related to the fabrication of other components of the microelectronic assemblies described herein or related to the fabrication of any device that may include a microelectronic assembly as described herein. For example, Figure 6-8 The operations shown may include various cleaning operations, additional surface planarization operations, operations for surface roughening, operations for incorporating desired carrier and / or adhesive layers, and / or operations for incorporating the microelectronic packages described herein into (or in combination with) IC components, computing devices, or any desired structure or device.

[0132] Exemplary Devices and Components

[0133] The packages disclosed herein (eg, any of the embodiments shown in FIGS. 1-5 or any other embodiments described herein) may be included in any suitable electronic component. Figure 9-11 Various examples of packages, components, and devices are shown that may be used in conjunction with or include any of the IC packages disclosed herein.

[0134] Fig. 9 is a side cross-sectional view of an exemplary IC package 2200 that may include an IC package according to any of the embodiments disclosed herein. In some embodiments, IC package 2200 may be a SiP.

[0135] As shown in the figure, package substrate 2252 may be formed of an insulator (e.g., ceramic, build film, epoxy film with filler particles therein, etc.) and may have conductive pathways extending through the insulator between first side 2272 and second side 2274, or between different locations on first side 2272, and / or between different locations on second side 2274. These conductive pathways may take the form of any of the interconnect structures including wires and / or vias.

[0136] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive pathways 2262 passing through the packaging substrate 2252, thereby allowing circuit units within the die 2256 and / or the interposer 2257 to be electrically coupled to individual ones of the conductive contacts 2264 (or to other devices not shown that are included in the packaging substrate 2252).

[0137] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of interposer 2257, first level interconnects 2265, and conductive contacts 2263 of package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, but any suitable first level interconnects 2265 may be employed, such as solder bumps, solder pillars, or bond wires.

[0138] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via the conductive contacts 2254 of the dies 2256, the first level interconnects 2258, and the conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) that pass through the interposer 2257, thereby allowing the circuit units within the dies 2256 to be electrically coupled to the respective conductive contacts in the conductive contacts 2261 (or to other devices not shown contained in the interposer 2257). The first level interconnects 2258 shown in the figure are solder bumps, but any suitable first level interconnects 2258 may be used, such as solder bumps, solder columns, or bonding wires. As used herein, "conductive contacts" may refer to portions of conductive material (e.g., metal) that act as interfaces between different components; the conductive contacts may be recessed into the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and may take any suitable form (e.g., conductive pads or sockets).

[0139] In some embodiments, an underfill material 2266 may be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. An exemplary material that may be used for the underfill material 2266 and the molding 2268 is epoxy, where appropriate. A second level interconnect 2270 may be coupled to the conductive contact 2264. The second level interconnect 2270 shown in this figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 may be employed (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Fig.10 described.

[0140] In various embodiments, any of the dies 2256 may be a microelectronic assembly 300 as described herein. In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuit elements that perform any intended function. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 300 as described herein, one or more of the dies 2256 may be a logic die (e.g., a silicon-based die), and one or more of the dies 2256 may be a memory die (e.g., an HBM), and so on. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the preceding figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0141] Although the IC package 2200 shown in the figure is a flip chip package, other packaging architectures may be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the prior art.

[0142] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be coupled directly to conductive contacts 2263 at first side 2272 by first level interconnects 2265 .

[0143] Fig.10is a cross-sectional side view of an IC device assembly 2300, which includes components that can have one or more microelectronic assemblies 300 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (e.g., which can be a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposite second side 2342 of the circuit board 2302; in general, the components can be disposed on one or both of the sides 2340 and 2342. Specifically, any appropriate component of the components of the IC device assembly 2300 can include any microelectronic component in one or more microelectronic assemblies 300 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 can take the form of any of the IC packages discussed above with reference to the IC device assembly 2300. Fig. 9 The IC package 2200 may be in the form of any of the embodiments discussed.

[0144] In some embodiments, circuit board 2302 may be a PCB that includes multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. One or more of the metal layers may be formed in a desired circuit pattern to (optionally in conjunction with other metal layers) direct electrical signals between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0145] As shown in the figure, in some embodiments, the IC device assembly 2300 can include a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling feature 2316. The coupling feature 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0146] Package-on-interposer structure 2336 may include IC package 2320 coupled to interposer 2304 via coupling feature 2318. Coupling feature 2318 may take any suitable form depending on the intended function, such as the forms discussed above with reference to coupling feature 2316. In some embodiments, IC package 2320 may be or may include IC package 2200, such as described above with reference to FIG. Fig. 9 In some embodiments, the IC package 2320 may include at least one microelectronic assembly 300 as described herein. The microelectronic assembly 300 is not specifically shown in this figure to avoid cluttering the drawing.

[0147] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to the interposer 2304; indeed, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can redistribute connections to a wider spacing or redirect connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 so as to couple it to the circuit board 2302.

[0148] In the embodiment shown in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0149] Interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 2304 may be formed of alternating rigid or flexible materials, which may include materials identical to those used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, which include but are not limited to TSV 2306. Interposer 2304 may further include embedded devices 2314, which include both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 2304. Package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0150] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0151] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together via coupling component 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0152] Fig.11 2400 that may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., Fig. 9 In yet another example, any one or more of the components of the computing device 2400 may include the IC device assembly 2300 (e.g., as shown in Fig.10 shown in ).

[0153] Many components are shown in this figure as being included in computing device 2400, but any one or more of these components may be omitted or duplicated, depending on the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-chip (SoC) die.

[0154] In addition, in various embodiments, the computing device 2400 may not include one or more of the components shown in the figure, but the computing device 2400 may include an interface circuit unit for coupling to the one or more components. For example, the computing device 2400 may not include the display device 2406, but may include a display device interface circuit unit (e.g., a connector and a driver circuit unit), and the display device 2406 may be coupled to the interface circuit unit. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include an audio input or output device interface circuit unit (e.g., a connector and a supporting circuit unit), and the audio input device 2418 or the audio output device 2408 may be coupled to the interface circuit unit.

[0155] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other appropriate processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. This memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0156] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for implementing data transfers to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0157] The communication chip 2412 can implement any of a wide variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision)), LTE plans together with any revisions, updates and / or adaptations thereof (e.g., Advanced LTE plan, Ultra Mobile Broadband (UMB) plan (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, and WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0158] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 2412 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0159] The computing device 2400 may include a battery / power circuit unit 2414. The battery / power circuit unit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit units for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0160] Computing device 2400 may include a display device 2406 (or a corresponding interface circuit unit, as discussed above). For example, display device 2406 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0161] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). For example, audio output device 2408 may include any device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0162] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0163] Computing device 2400 may include GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0164] Computing device 2400 may include other output devices 2410 (or corresponding interface circuit units, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0165] Computing device 2400 may include other input devices 2420 (or corresponding interface circuit units, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a trackpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0166] The computing device 2400 may have any desired form factor, such as a portable or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0167] Selected Examples

[0168] The description of the exemplary embodiments of the present disclosure (including the contents described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may exist within the scope of the present disclosure, which will be recognized by those skilled in the art.

[0169] The following paragraphs provide various examples of the embodiments disclosed herein.

[0170] Example 1 is a microelectronic component, comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite to the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die comprising conductive traces parallel to the first surface and the second surface and the conductive traces exposed at the third surface; a second IC die having a fourth surface, the second IC die comprising a voltage regulator circuit unit; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die through a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die through a second interconnect, and the first IC die is electrically coupled to the second IC die through a conductive path in the third IC die.

[0171] Example 2 may include the subject matter of Example 1, and may further specify that: the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and an individual second IC die of the plurality of second IC dies is electrically coupled to an individual third IC die of the third IC die via a conductive path in the third IC die.

[0172] Example 3 may include the subject matter of Example 2, and may further specify that the plurality of first IC dies are separated from each other by gaps.

[0173] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the first interconnect and the second interconnect include a metal-metal bond and a dielectric-dielectric bond.

[0174] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that: the fifth surface of the third IC die includes conductive contacts, and the first interconnect is formed by electrically coupling individual ones of the conductive contacts at the fifth surface of the third IC die with individual ones of the conductive traces exposed at the third surface of the first IC die.

[0175] Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the second IC die further includes a sixth surface orthogonal to the second surface, and wherein the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die via a third interconnect.

[0176] Example 7 may include the subject matter of Example 6, and may further specify that the third interconnect includes a metal-metal bond and a dielectric-dielectric bond.

[0177] Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the first IC die further includes a metallization stack and a substrate having an interface parallel to the first surface and the second surface.

[0178] Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the first IC die further includes a substrate and two metallization stacks on both sides of the substrate along respective interfaces parallel to the first surface and the second surface.

[0179] Example 10 may include the subject matter of Example 9, and may further specify that one of the two metallization stacks further includes an optical structure.

[0180] Example 11 is a microelectronic component comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite to the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die comprising a conductive trace parallel to the first surface and the second surface, the conductive trace being exposed at the third surface; and a second IC die having a fourth surface having a conductive contact portion, the second IC die comprising a voltage regulator circuit unit, wherein the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die via an interconnect and the first IC die is electrically coupled to the voltage regulator circuit unit in the second IC die.

[0181] Example 12 may include the subject matter of Example 11 and may further specify that: the first IC die is one of a plurality of first IC dies, the voltage regulator circuit unit is one of a plurality of voltage regulator circuit units, and individual first IC dies in the first IC die are electrically coupled to individual voltage regulator circuit units in the plurality of voltage regulator circuit units.

[0182] Example 13 may include the subject matter of Example 12, and may further specify that the plurality of first IC dies are separated from each other by gaps.

[0183] Example 14 may include the subject matter of Example 12, and may further specify that the plurality of first IC dies are bonded together at the respective first and second surfaces.

[0184] Example 15 may include the subject matter of any of Examples 11-14, and may further specify that the interconnect includes metal-to-metal bonding and dielectric-to-dielectric bonding.

[0185] Example 16 may include the subject matter of any of Examples 11-15, and may further specify that the second IC die further includes a fifth surface opposite the fourth surface, and the microelectronic assembly may further include a packaging substrate electrically coupled to the fifth surface of the second IC die, the packaging substrate including a power supply.

[0186] Example 17 may include the subject matter of any of Examples 11-16, and may further specify that the first IC die further includes a substrate and a metallization stack having an interface parallel to the first surface and the second surface.

[0187] Example 18 may include the subject matter of any of Examples 11-16, and may further specify that the first IC die further includes a substrate and two metallization stacks located on both sides of the substrate along respective interfaces parallel to the first surface and the second surface.

[0188] Example 19 is a microelectronic component comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite to the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die comprising a substrate and a metallization stack having an interface parallel to the first surface and the second surface; a second IC die having a fourth surface and comprising a voltage regulator circuit unit; and a third IC die having a fifth surface and comprising a conductive path, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die via a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die via a second interconnect, and the first IC die is electrically coupled to the second IC die via a conductive path in the third IC die.

[0189] Example 20 may include the subject matter of Example 19, and may further specify that: the first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and an individual first IC die of the plurality of first IC dies is electrically coupled to an individual second IC die of the second IC dies via a conductive path in a third IC die.

[0190] Example 21 may include the subject matter of Example 20, and may further specify that the plurality of first IC dies are separated from each other by gaps.

[0191] Example 22 may include the subject matter of any of Examples 19-21, and may further specify that the first interconnect or the second interconnect includes a metal-metal bond and a dielectric-dielectric bond.

[0192] Example 23 may include the subject matter of any of Examples 19-22, and may further specify that the first IC die further includes a conductive trace parallel to the first surface and the second surface, and the conductive trace is exposed at the third surface.

[0193] Example 24 may include the subject matter of any of Examples 19-23, and may further specify that the second IC die further includes a sixth surface orthogonal to the fourth surface, and the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die through a third interconnect.

[0194] Example 25 may include the subject matter of Example 23, and may further specify that the first interconnect is formed by electrically coupling individual ones of the conductive traces exposed at the third surface of the first IC die to individual ones of the conductive bonding pads at the fifth surface of the third IC die.

Claims

1. A microelectronic assembly comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die including conductive traces parallel to the first surface and the second surface, and the conductive traces exposed at the third surface; a second IC die having a fourth surface and comprising a voltage regulator circuit unit; as well as a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die via a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die via a second interconnect, and the first IC die is electrically coupled to the second IC die via a conductive path in the third IC die.

2. The microelectronic assembly according to claim 1, wherein: The first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and individual second IC dies of the plurality of second IC dies are electrically coupled to individual third IC dies of the third IC dies through conductive pathways in the third IC die.

3. The microelectronic assembly according to claim 2, wherein: The plurality of first IC dies are separated from each other by gaps.

4. The microelectronic assembly according to claim 1, wherein: The first interconnect and the second interconnect include metal-metal bonding and dielectric-dielectric bonding.

5. The microelectronic assembly according to claim 1, wherein: The fifth surface of the third IC die includes conductive contacts, and the first interconnect is formed by electrically coupling individual ones of the conductive contacts at the fifth surface of the third IC die with individual ones of the conductive traces exposed at the third surface of the first IC die.

6. The microelectronic assembly according to claim 1, wherein: The second IC die further includes a sixth surface orthogonal to the second surface, and wherein the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die through a third interconnect.

7. The microelectronic assembly according to claim 6, wherein: The third interconnect includes metal-metal bonding and dielectric-dielectric bonding.

8. The microelectronic assembly according to any one of claims 1 to 7, wherein: The first IC die further includes a substrate and a metallization stack having an interface parallel to the first surface and the second surface.

9. The microelectronic assembly according to any one of claims 1 to 7, wherein: The first IC chip further includes a substrate and two metallization stacks located on both sides of the substrate along respective interfaces parallel to the first surface and the second surface.

10. A microelectronic assembly according to claim 9, wherein: One of the two metallization stacks further comprises an optical structure.

11. A computing device comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die including conductive traces parallel to the first surface and the second surface, and the conductive traces exposed at the third surface; as well as A second IC die, the second IC die having a fourth surface, the fourth surface having a conductive contact portion, the second IC die including a voltage regulator circuit unit, wherein the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die through an interconnect, and the first IC die is electrically coupled to the voltage regulator circuit unit in the second IC die.

12. The computing device according to claim 11, wherein: The first IC die is one of a plurality of first IC dies, the voltage regulator circuit unit is one of a plurality of voltage regulator circuit units, and individual first IC dies of the first IC die are electrically coupled to individual voltage regulator circuit units of the plurality of voltage regulator circuit units.

13. The computing device of claim 12, wherein: The plurality of first IC dies are separated from each other by gaps.

14. The computing device of claim 12, wherein: The plurality of first IC dies are bonded together at respective first and second surfaces.

15. The computing device according to any one of claims 11 to 14, wherein: The interconnects include metal-metal bonding and dielectric-dielectric bonding.

16. The computing device according to any one of claims 11 to 14, wherein: The second IC die further includes a fifth surface opposite the fourth surface, and the computing device further includes: A package substrate is electrically coupled to the fifth surface of the second IC die, the package substrate comprising a power source.

17. The computing device according to any one of claims 11 to 14, wherein: The first IC die further includes a substrate and a metallization stack having an interface parallel to the first surface and the second surface.

18. The computing device according to any one of claims 11 to 14, wherein: The first IC chip further includes a substrate and two metallization stacks located on both sides of the substrate along respective interfaces parallel to the first surface and the second surface.

19. An integrated circuit (IC) package, comprising: a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first surface and the second surface, the first IC die comprising a substrate and a metallization stack, and the substrate and the metallization stack having an interface parallel to the first surface and the second surface; a second IC die having a fourth surface and including a voltage regulator circuit unit; as well as A third IC die having a fifth surface and including a conductive path, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die via a first interconnect, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die via a second interconnect, and the first IC die is electrically coupled to the second IC die via the conductive path in the third IC die.

20. The IC package of claim 19, wherein: The first IC die is one of a plurality of first IC dies, the second IC die is one of a plurality of second IC dies, and an individual first IC die of the plurality of first IC dies is electrically coupled to an individual second IC die of the second IC dies through the conductive path in the third IC die.

21. The IC package of claim 20, wherein: The plurality of first IC dies are separated from each other by gaps.

22. The IC package according to any one of claims 19 to 21, wherein: The first interconnect or the second interconnect includes metal-metal bonding and dielectric-dielectric bonding.

23. The IC package according to any one of claims 19 to 21, wherein: The first IC die further includes conductive traces parallel to the first surface and the second surface, and the conductive traces are exposed at the third surface.

24. The IC package according to any one of claims 19 to 21, wherein: The second IC die further includes a sixth surface orthogonal to the fourth surface, and wherein the sixth surface of the second IC die is electrically coupled to the second surface of the first IC die through a third interconnect.

25. The IC package of claim 23, wherein: The first interconnect is formed by electrically coupling individual ones of the conductive traces exposed at the third surface of the first IC die to individual ones of the conductive bond pads at the fifth surface of the third IC die.

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