Method of forming FOWLP with pre-molded embedded discrete electrical components and semiconductor device
Through pre-molded embedded discrete electrical components and FoWLP technology, the problem of complex electrical connections and vulnerability to damage to the layered structure during semiconductor device packaging is solved, and a high-density and low-cost packaging effect is achieved.
Patent Information
- Application Number
- CN202410890705.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-07
- Filing Date
- 2024-07-04
- Publication Date
- 2025-03-07
AI Technical Summary
During the packaging process, existing semiconductor devices have problems such as complex electrical connections and easy damage to layered structures, making it difficult to achieve high-density and low-cost packaging.
Using pre-molded embedded discrete electrical components and FoWLP technology, thin packaging and high-density connections are achieved by deploying discrete electrical components on the carrier and using multiple layers of encapsulation and conductive layers to build complex electrical interconnect structures.
High-density packaging of semiconductor devices is realized, reducing packaging costs, improving the physical and electrical performance of the packaging, and avoiding damage to the layered structure.
Smart Images
Figure CN119581457A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates generally to semiconductor devices, and more particularly to methods and semiconductor devices for forming a FoWLP having pre-molded and embedded discrete electrical components. Background Art
[0002] Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electrical equipment, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive vehicles, industrial controllers, and office equipment.
[0003] Semiconductor devices often include a semiconductor die or substrate with an electrical interconnect structure, such as a redistribution layer (RDL) formed on one or more surfaces of the semiconductor die or substrate to perform the necessary electrical functions. Semiconductor devices are formed on a wafer or panel, such as a molded reconstructed wafer level package (WLP) or a fan-out wafer level package (FoWLP). WLP often uses discrete passive and / or active components for electrical functions, such as radio frequency (RF) signal transmission. These discrete passive and active components are exposed and suffer from delamination at the electrical connection terminals to the RDL due to the circuit topology. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Figure 1a to Figure 1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;
[0005] Figure 2a to Figure 2h illustrates a process for forming a pre-molded embedded discrete electrical component;
[0006] Figure 3 Another pre-molded embedded discrete electrical component is illustrated;
[0007] Figure 4a to Figure 4b Attachment of a pre-molded embedded discrete electrical component to a carrier is illustrated;
[0008] Figure 5a to Figure 5c illustrates another pre-molded embedded discrete electrical component attached to a carrier;
[0009] Figures 6a to 6n A first embodiment of a FoWLP with pre-molded embedded discrete electrical components is illustrated;
[0010] Figures 7a to 7f A second embodiment of a FoWLP with pre-molded embedded discrete electrical components is illustrated;
[0011] Figures 8a to 8e illustrates a third embodiment of a FoWLP with pre-molded embedded discrete electrical components; and
[0012] Fig. 9 A printed circuit board (PCB) is illustrated with different types of packages disposed on a surface of the PCB. DETAILED DESCRIPTION
[0013] The present invention is described in one or more embodiments in the following description with reference to the figures, and similar reference numerals in the figures represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that it is intended to cover substitutions, modifications and equivalents as may be included in the spirit and scope of the present invention as defined by the appended claims (and their equivalents as supported by the following disclosure and drawings). The features shown in the figures are not necessarily drawn to scale. Elements with similar functions in the figures are assigned the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and can refer to both a single semiconductor device and a plurality of semiconductor devices accordingly.
[0014] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the electrical circuit function.
[0015] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of the wafer called saw road or scribe line. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are disposed on a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads in the package. The electrical connection can be made using a conductive layer, a bump, a columnar bump, a conductive paste, or a wiring bond. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.
[0016] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).
[0017] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or inactive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
[0018] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.
[0019] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and their combination, and optional flux solution. For example, bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. Bump material is bonded to conductive layer 112 using suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form ball or bump 114 by heating the material above its melting point. In one embodiment, bump 114 is formed on under bump metallization (UBM), and under bump metallization has a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be compression bonded or thermally compressed bonded to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. Interconnect structure can also use bonding wiring, conductive paste, columnar bump, microbump or other electrical interconnection.
[0020] exist Figure 1c In the process, the semiconductor wafer 100 is singulated into individual semiconductor dies 104 through saw streets 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or known good units (KGD / KGU) after singulation.
[0021] Figure 2a A temporary substrate or carrier 120 is shown, comprising a sacrificial base material such as silicon, polymer, beryllium oxide, glass, metal or other suitable low-cost, rigid material for structural support. The substrate 120 has a major surface 122 and a major surface 124 opposite the surface 122. In one embodiment, the carrier 120 is a support structure having a temporary bonding layer 126 formed on the surface 122 of the carrier. The temporary bonding layer 126 can be a double-sided tape.
[0022] Discrete electrical components 130a-130b are disposed on the surface 122 of the substrate 120. The discrete electrical components 130a-130b may be passive components, such as resistors, capacitors, or inductors. The discrete electrical components 130a-130b may be active components, such as diodes, transistors, or thyristors. Active types of discrete electrical components 130a-130b may be similar to Figure 1a to Figure 1c130a-130b are formed on the wafer. As an active example, a diode with an anode and a cathode can be formed on a substrate 132, which has semiconductor layers of opposite types, namely a P layer and an N layer. For example, the P layer is formed within the surface 134 and the N layer is formed within the surface 135. An electrical terminal 136 is connected to the anode and another electrical terminal 136 is connected to the cathode. The discrete electrical components 130a-130b of the passive type can be wound, layered or otherwise prepared using suitable electrical materials. As a passive example, a capacitor is formed using a layered dielectric material between two metal plates or regions. An electrical terminal 136 is connected to one metal plate and another electrical terminal 136 is connected to another metal plate. Conductive material or solder 138 is deposited on the electrical terminal 136. In one embodiment, the conductive material 138 is a SnAg finish to enable uniform sputtering of the seed layer and plating of Ni / Cu RDL on the SnAg contact terminal.
[0023] Discrete electrical components 130a-130b are positioned over surface 122 of substrate 120 using a pick and place operation. Discrete electrical components 130a-130b are brought into contact with bonding layer 126. Figure 2b Discrete electrical components 130a-130b are illustrated bonded to substrate 120. Conductive material 138 is partially embedded in bonding layer 126.
[0024] exist Figure 2c In the process, an encapsulant or molding compound 140 is deposited on and around the discrete electrical components 130a-130b and the substrate 120 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 140 can be a liquid or granular polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with an appropriate filler. The encapsulant 140 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.
[0025] exist Figure 2d In the process, the carrier 120 and the bonding layer 126 are removed by chemical etching, chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light, or wet stripping to expose the conductive material 138 on the electrical terminals 136 .
[0026] exist Figure 2e In FIG. 1 , the assembly is inverted and the surface 144 of the encapsulant 140 is subjected to a grinding operation using a grinder 146 to planarize the surface 144 and the conductive material 138. Some of the encapsulant 140 remains on the substrate 132.
[0027] exist Figure 2fIn the embodiment, a conductive layer 150 is formed on the conductive material 138 of the electrical terminal 136 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. The conductive layer 150 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 150 makes electrical connections to the discrete electrical components 130a-130b. In one embodiment, the conductive layer 150 is a deposited Cu pad.
[0028] exist Figure 2g In the process, the encapsulant 140 is singulated using a saw blade or laser cutting tool 154 . Figure 2h Discrete electrical components 130a-130b are shown encapsulated in discrete component package 156 after singulation. Conductive layer 150 extends from encapsulant 140 in discrete component package 156. Discrete component package 156 contains discrete electrical components 130a-130b. Discrete electrical components 130a-130b are pre-molded and pre-encapsulated in that the discrete electrical components are embedded within encapsulant 140 prior to the next level of integration, as shown in FIGS. 6-8.
[0029] In another embodiment, Figure 3 The discrete semiconductor package 158 in FIG. 1 shows a conductive layer 150 coplanar with the surface 144 of the encapsulant 140. In this case, the conductive layer 150 will be formed before encapsulation and Figure 2e The grinder 146 in the planarizes the surface 144 and the conductive layer 150. Components having similar functions are assigned the same reference numbers. Discrete component package 158 contains discrete electrical components 130a-130b. Discrete electrical components 130a-130b are pre-molded and pre-encapsulated in that the discrete electrical components are embedded within the encapsulant 140 before the next level of integration, as shown in Figures 6 to 8.
[0030] Figure 4a A temporary substrate or carrier 160 is shown, which includes a sacrificial base material, such as silicon, polymer, beryllium oxide, glass, metal or other suitable low-cost rigid material, for structural support. The substrate 160 has a major surface 162 and a major surface 164 opposite the surface 162. In one embodiment, the carrier 160 is a support structure having a temporary bonding layer 166 formed on the surface 162 of the carrier. The temporary bonding layer 166 can be a double-sided tape.
[0031] Use pick and place operations to move Figure 2h Discrete component package 156 or from Figure 3 The discrete component package 158 is disposed over the surface 162 of the substrate 160. The discrete component package 156 is brought into contact with the bonding layer 166. Figure 4bDiscrete component package 156 is illustrated bonded to substrate 160. Conductive layer 150 is partially embedded in bonding layer 166.
[0032] In another embodiment, Figure 5a Shows similarity to Figure 2a or other suitable preparation processes to form discrete electrical components 170a-170b. The discrete electrical components 170a-170b have a functional area 172, namely an active or passive device, an electrical terminal 174, and a conductive material or solder 175 deposited on the electrical terminal. In one embodiment, the conductive material 175 is a SnAg surface layer to enable uniform sputtering of the seed layer and plating of Ni / Cu RDL on the SnAg contact terminal.
[0033] Conductive layer 176 is formed over conductive material 175 of electrical terminals 174 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 176 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 176 makes electrical connections to discrete electrical components 170a-170b.
[0034] exist Figure 5b In the process, an encapsulant or molding compound 180 is deposited over and around the discrete electrical components 170a-170b using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
[0035] Figure 5c A temporary substrate or carrier 182 is shown, which includes a sacrificial base material, such as silicon, polymer, beryllium oxide, glass, metal or other suitable low-cost rigid material, for structural support. The substrate 182 has a major surface 184 and a major surface 185 opposite the surface 184. In one embodiment, the carrier 182 is a support structure having a temporary bonding layer 186 formed on the surface 184 of the carrier. The temporary bonding layer 186 can be a double-sided tape.
[0036] exist Figure 5c In, similar to Figure 4a to Figure 4b , using a pick and place operation to position discrete electrical components 170a-170b over a surface 184 of a substrate 182. The discrete electrical components 170a-170b are brought into contact with a bonding layer 186. Conductive material 176 is partially embedded in the bonding layer 186. Discrete component package 188 contains discrete electrical components 170a-170b. Discrete electrical components 170a-170b are pre-molded and pre-encapsulated in that the discrete electrical components are embedded within an encapsulant 180 prior to the next level of integration, as shown in FIGS. 6 to 8.
[0037] exist Figure 6a In the process, the encapsulant or molding compound 190 is deposited on the substrate from the mold using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating or other suitable applicators. Figure 2h Discrete component package 156 or from Figure 3 Discrete component package 158 or from Figure 5c The encapsulant 190 is formed over and around the discrete component package 188. The encapsulant 190 may be a liquid or granular polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with an appropriate filler. The encapsulant 190 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.
[0038] The following disclosure is from Figure 2h The discrete component package 156 is described in terms of, but the text applies to Figure 3 Discrete component packages 158 and from Figure 5c The discrete component package is 188. Figure 6b In the process, carrier 160 and bonding layer 166 are removed by chemical etching, CMP, mechanical stripping, mechanical grinding, thermal baking, UV light, or wet stripping to expose conductive layer 150. Encapsulant 190 undergoes an optional grinding operation to planarize surface 191 and conductive layer 150. Some encapsulant 190 remains on substrate 132.
[0039] exist Figure 6c In the embodiment, the assembly is inverted and an insulating or passivation layer 192 is formed over the surface 191 and the conductive layer 150 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 192 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials with similar insulating and structural properties. An etching process or laser direct ablation (LDA) is used to remove portions of the insulating layer 192 to form openings or through holes extending to the conductive layer 150 for further electrical interconnection.
[0040] Conductive layer 194 is formed over insulating layer 192 and into vias to conductive layer 150 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 194 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 194 extends through openings in insulating layer 192 to conductive layer 150 to make electrical connections to discrete electrical components 130a-130b.
[0041] Conductive layer 196 is formed over insulating layer 192 and conductive layer 194 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 196 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.
[0042] An insulating or passivation layer 198 is formed over the insulating layer 192 and the conductive layers 194 and 196 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 198 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 198 to form openings or vias 199 extending to the conductive layer 196 for further electrical interconnection, such as a multi-layer RDL build-up structure or interconnect bumps. The insulating layers 192 and 198 provide isolation around the conductive layers 194 and 196. The conductive layers 194 and 196, in combination with the insulating layers 192 and 198, form the RDL 200. The RDL 200 has a fine line spacing, less than 8 / 8 μm.
[0043] exist Figure 6d In the embodiment, a solder resist or photoresist layer 202 is formed over the RDL 200. Figure 6e In the process, a plurality of openings 203 are formed in the solder resist / photoresist 202 using an etching process or LDA by a laser 204 .
[0044] exist Figure 6f In the embodiment, the opening 203 is filled with a conductive material to form a conductive rod or conductive column 206. Figure 6g In the embodiment of the present invention, the remaining solder resist / photoresist 202 is removed, leaving a conductive rod or conductive column or conductive post 206. The conductive rod or conductive column or conductive post 206 can be Al, Cu, Sn, Ni, Au, Ag, a multi-layer combination or other suitable conductive materials. The conductive column 206 can have a height H1 of 100.0 μm to compensate for thickness variations in different technologies (such as surface mounting and flip chip).
[0045] exist Figure 6h In the embodiment, an electrical component 210 is disposed on the RDL 200 between the conductive pillars 206, wherein the bumps 114 are oriented away from the RDL. The electrical component 210 may be from Figure 1c 1 , with back surface 108 oriented toward RDL 200. Alternatively, electrical component 210 may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).
[0046] The electrical component 210 is positioned over the RDL 200 using a pick and place operation. The electrical component 210 is brought into contact with the insulating layer 198 and secured with an adhesive or other bonding layer 212. Figure 6i An electrical component 210 is illustrated bonded to the RDL 200 using an adhesive or other bonding layer 212 .
[0047] exist Figure 6j In the process, an encapsulant or molding compound 214 is deposited on and around the electrical components 210, the conductive pillars 206, and the RDL 200 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 214 can be a liquid or granular polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with an appropriate filler. The encapsulant 214 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.
[0048] exist Figure 6k In the embodiment of the present invention, the encapsulant 214 is subjected to a grinding operation using a grinder 216 to planarize the surface 218 and expose the conductive pillars 206 and the bumps 114. Some of the encapsulant 214 remains over the electrical component 210. Figure 6l Coplanar surfaces 218 are shown along with exposed conductive pillars 206 and bumps 114 .
[0049] exist Figure 6m In the embodiment, an insulating or passivation layer 220 is formed over the surface 218 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 220 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO and other materials with similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 202 to form openings or through holes extending to the conductive pillars 206 and the bumps 114 for further electrical interconnection.
[0050] Conductive layer 222 is formed over insulating layer 220 and into vias to conductive pillars 206 and bumps 114 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 222 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 222 extends through openings in insulating layer 220 to conductive pillars 206 and bumps 114 to make electrical connections to electrical components 210, RDL 200, and discrete electrical components 130a-130b.
[0051] An insulating or passivation layer 224 is formed over the insulating layer 220 and the conductive layer 222 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 224 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 224 to form openings or vias extending to the conductive layer 222 for further electrical interconnection.
[0052] Conductive layer 226 is formed over insulating layer 224 and conductive layer 222 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 226 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 226 extends through openings in insulating layer 224 to conductive pillars 206 and bumps 114 to make electrical connections to electrical components 210, RDL 200, and discrete electrical components 130a-130b. Insulating layers 220 and 224 provide isolation around conductive layers 222 and 226. Conductive layers 222 and 226, in combination with insulating layers 220 and 224, constitute RDL 228 because they redistribute electrical signals across electrical components 210, encapsulation 140, and conductive pillars 206 and over them. Portions of RDL 200 and 228 may be electrically common or electrically isolated depending on the design and functionality of electrical component 210, discrete electrical components 130a-130b, and other electrical components attached thereto. RDL 228 has a fine line pitch, less than 8 / 8 μm.
[0053] exist Figure 6n In the embodiment of the present invention, the conductive bump material is deposited on the conductive layer 226 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 226 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 230. In another embodiment, a bump 230 is formed on the UBM, and the UBM has a wetting layer, a barrier layer and an adhesive layer. The bump 230 can also be compression bonded or thermally compressed bonded to the conductive layer 226. The bump 230 represents a type of interconnect structure that can be formed on the conductive layer 226. The interconnect structure can also use conductive paste, columnar bumps, micro bumps or other electrical interconnects.
[0054] The combination of discrete electrical components 130a-130b, encapsulant 140, encapsulant 190, RDL 200, conductive pillar 206, electrical component 210, encapsulant 214, and RDL 228 constitutes a fan-out wafer level package (FOWLP) or embedded wafer level ball grid array (eWLB) 232. Package 232 has electrical interconnects between discrete electrical components 130a-130b and electrical component 210 through RDL 200, conductive pillar 206, and RDL 228, as well as external interconnects using bumps 230. Package 232 does not have through silicon vias that could potentially damage electrical component 210. Package 232 has a thin profile, less than 1.0 mm, and RDLs 200 and 228 have fine line pitches, less than 8 / 8 μm. Discrete electrical components 130a-130b are pre-molded and embedded, using multiple encapsulant layers to provide protection on all sides.
[0055] In another embodiment, from Figure 6g Continuing, electrical components 236 are disposed over RDL 200 between conductive pillars 206, with bumps 114 oriented toward the RDL, as in Figure 7a Components having similar functions are assigned the same reference numerals. The electrical component 236 may be from Figure 1c 1 , with bumps 114 oriented toward RDL 200. Alternatively, electrical component 236 may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or IPDs.
[0056] Similar to Figure 6h to Figure 6i , an electrical component 236 is positioned over the RDL 200 using a pick and place operation. The bumps 114 of the electrical component 236 are brought into contact with the conductive layer 196. The bumps 114 are reflowed to form a secure mechanical and electrical connection to the conductive layer 196 of the RDL 200. An underfill material 238, such as an epoxy, is deposited beneath the electrical component 236.
[0057] exist Figure 7b In the process, an encapsulant or molding compound 240 is deposited on and around the electrical components 236, the conductive pillars 206, and the RDL 200 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 240 can be a liquid or granular polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with an appropriate filler. The encapsulant 240 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.
[0058] exist Figure 7cIn the embodiment, encapsulant 240 is subjected to a grinding operation using grinder 242 to planarize surface 244 and expose back surfaces of conductive pillars 206 and electrical components 236 . Figure 7d Surface 244 is shown to be coplanar with surface 246 of exposed conductive pillar 206 .
[0059] exist Figure 7e In the embodiment, an insulating or passivation layer 250 is formed over the surface 244 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 250 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO and other materials with similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 250 to form openings or through holes extending to the conductive pillars 206 for further electrical interconnection.
[0060] Conductive layer 252 is formed over insulating layer 250 and into vias to conductive pillars 206 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 252 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 252 extends through openings in insulating layer 250 to conductive pillars 206 to make electrical connections to electrical components 236, RDL 200, and discrete electrical components 130a-130b.
[0061] An insulating or passivation layer 254 is formed over the insulating layer 250 and the conductive layer 252 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 254 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 254 to form openings or vias extending to the conductive layer 252 for further electrical interconnection.
[0062] Conductive layer 256 is formed over insulating layer 254 and conductive layer 252 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 256 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 256 extends through openings in insulating layer 254 to conductive pillars 206 so as to be electrically connected to electrical components 236, RDL 200, and discrete electrical components 130a-130b. Insulating layers 250 and 254 provide isolation around conductive layers 252 and 256. Conductive layers 252 and 256, in combination with insulating layers 250 and 254, constitute RDL 258 because they redistribute electrical signals across electrical components 236, encapsulation 240, and conductive pillars 206 and over them. Portions of RDL 200 and 258 may be electrically common or electrically isolated depending on the design and functionality of electrical component 236, discrete electrical components 130a-130b, and other electrical components attached thereto. RDL 258 has a fine line pitch, less than 8 / 8 μm.
[0063] exist Figure 7f In the embodiment of the present invention, the conductive bump material is deposited on the conductive layer 256 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 256 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 260. In another embodiment, a bump 260 is formed on the UBM, and the UBM has a wetting layer, a barrier layer and an adhesive layer. The bump 260 can also be compression bonded or thermally compressed bonded to the conductive layer 256. The bump 260 represents a type of interconnect structure that can be formed on the conductive layer 256. The interconnect structure can also use conductive paste, columnar bumps, microbumps or other electrical interconnects.
[0064] The combination of discrete electrical components 130a-130b, encapsulant 140, encapsulant 190, RDL 200, conductive pillar 206, electrical component 236, encapsulant 240, and RDL 258 constitutes FoWLP or eWLB 262. Package 262 has electrical interconnects between discrete electrical components 130a-130b and electrical component 236 through RDL 200, conductive pillar 206, and RDL 258, as well as external interconnects using bumps 260. Package 262 does not have through-silicon vias that could potentially damage electrical component 236. Package 262 has a thin profile, less than 1.0 mm, and RDL 200 and 258 have a fine line pitch, less than 8 / 8 μm. Discrete electrical components 130a-130b are pre-molded and embedded, with multiple encapsulant layers providing protection on all sides.
[0065] In another embodiment, from Figure 7b Continuing, the top surface 246 of the conductive pillar 206 extends above the back surface 108 of the electrical component 236, as shown in FIG. Figure 8a As shown in Figure 8b In the embodiment, the encapsulant 240 is subjected to a grinding operation using a grinder 266 to planarize the surface 244 and expose the conductive pillars 206 . Figure 8c A surface 244 is shown that is coplanar with a surface 246 of the exposed conductive pillar 206. A portion of the encapsulant 240 remains over the back surface 108 of the electrical component 236.
[0066] exist Figure 8d In the embodiment, an insulating or passivation layer 270 is formed over the surface 244 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 270 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO and other materials with similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 270 to form openings or through holes extending to the conductive pillars 206 for further electrical interconnection.
[0067] Conductive layer 272 is formed over insulating layer 270 and into vias to conductive pillars 206 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 272 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 272 extends through openings in insulating layer 270 to conductive pillars 206 to make electrical connections to electrical components 236, RDL 200, and discrete electrical components 130a-130b.
[0068] An insulating or passivation layer 274 is formed over the insulating layer 270 and the conductive layer 272 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 274 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. An etching process or LDA is used to remove portions of the insulating layer 274 to form openings or vias extending to the conductive layer 272 for further electrical interconnection.
[0069] Conductive layer 276 is formed over insulating layer 274 and conductive layer 272 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 276 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 276 extends through openings in insulating layer 274 to conductive pillars 206 so as to be electrically connected to electrical components 236, RDL 200, and discrete electrical components 130a-130b. Insulating layers 270 and 274 provide isolation around conductive layers 272 and 276. Conductive layers 272 and 276, in combination with insulating layers 270 and 274, constitute RDL 278 because they redistribute electrical signals across electrical components 236, encapsulation 240, and conductive pillars 206 and over them. Portions of RDL 200 and 278 may be electrically common or electrically isolated depending on the design and functionality of electrical component 236, discrete electrical components 130a-130b, and other electrical components attached thereto. RDL 278 has a fine line pitch, less than 8 / 8 μm.
[0070] exist Figure 8e In the embodiment of the present invention, the conductive bump material is deposited on the conductive layer 276 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 276 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 280. In another embodiment, a bump 280 is formed on the UBM, and the UBM has a wetting layer, a barrier layer and an adhesive layer. The bump 280 can also be compression bonded or thermally compressed bonded to the conductive layer 276. The bump 280 represents a type of interconnect structure that can be formed on the conductive layer 276. The interconnect structure can also use conductive paste, columnar bumps, microbumps or other electrical interconnects.
[0071] The combination of discrete electrical components 130a-130b, encapsulant 140, encapsulant 190, RDL 200, conductive pillar 206, electrical component 236, encapsulant 240, and RDL 278 constitutes FoWLP or eWLB 282. Package 282 has electrical interconnects between discrete electrical components 130a-130b and electrical component 236 through RDL 200, conductive pillar 206, and RDL 278, as well as external interconnects using bumps 280. Package 282 does not have through-silicon vias that could potentially damage electrical component 236. Package 282 has a thin profile, less than 1.0 mm, and RDL 200 and 278 have a fine line pitch, less than 8 / 8 μm. Discrete electrical components 130a-130b are pre-molded and embedded, with multiple encapsulant layers providing protection on all sides.
[0072] Fig. 9 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with multiple semiconductor packages, including FoWLP 232, FoWLP 262, and FoWLP 282, disposed on a surface of PCB 402. Electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages depending on the application.
[0073] The electrical device 400 can be an independent system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 can be a subcomponent of a larger system. For example, the electrical device 400 can be a part of a flat panel, a cellular phone, a digital camera, a communication system, or other electrical equipment. Alternatively, the electrical device 400 can be a graphics card, a network interface card, or other signal processing cards that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are crucial for the product to be accepted by the market. The distance between semiconductor devices can be reduced to achieve higher density.
[0074] exist Fig. 9 In the PCB 402, PCB 402 provides a general base for structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 404 are formed on the surface or in various layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.
[0075] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is directly mechanically and electrically disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including a bond wiring package 406 and a flip chip 408. Additionally, several types of second level packaging disposed on PCB 402 are shown, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or a SIP module 418, a quad flat package (QFN) 420, a quad flat package 422, an embedded wafer level ball grid array (eWLB) 424, and a wafer level chip size package (WLCSP) 426. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages and other electrical components configured with any combination of first-level packaging styles and second-level packaging styles can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-made components into electrical devices and systems. Because semiconductor packages include complex functionality, electrical devices can be manufactured using less expensive components and assembly line manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for consumers.
[0076] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.
Claims
1. A semiconductor device, comprising: Pre-molded discrete electrical components; a first encapsulant deposited over the pre-molded discrete electrical component; a first conductive layer formed over the first encapsulant and the pre-molded discrete electrical components; an electrical component disposed over the first conductive layer; a second encapsulant deposited over the electrical component and the first conductive layer; as well as A second conductive layer is formed on the second encapsulant. 2 . The semiconductor device according to claim 1 , further comprising a conductive pillar formed between the first conductive layer and the second conductive layer through the second encapsulant.
3. The semiconductor device of claim 1 , wherein the pre-molded discrete electrical component comprises: Discrete components; as well as A third encapsulant is deposited around the discrete components.
4. The semiconductor device according to claim 3, wherein the discrete components include: Discrete devices; an electrical terminal coupled to the discrete device; a surface layer formed over the electrical terminals; as well as A third conductive layer is formed on the surface layer. 5 . The semiconductor device of claim 1 , wherein the interconnect structure formed on the electrical component is oriented toward the first conductive layer or the second conductive layer.
6. A semiconductor device comprising: Semiconductor packaging; as well as A pre-molded discrete electrical component that is disposed over a semiconductor package.
7. The semiconductor device according to claim 6, wherein the semiconductor package comprises: a first encapsulant deposited over the pre-molded discrete electrical component; a first conductive layer formed over the first encapsulant and the pre-molded discrete electrical components; an electrical component disposed over the first conductive layer; a second encapsulant deposited over the electrical component and the first conductive layer; as well as A second conductive layer is formed on the second encapsulant. 8 . The semiconductor device according to claim 7 , further comprising a conductive pillar formed between the first conductive layer and the second conductive layer through the second encapsulant. 9 . The semiconductor device of claim 7 , wherein the interconnect structure formed on the electrical component is oriented toward the first conductive layer or the second conductive layer.
10. The semiconductor device of claim 6, wherein the pre-molded discrete electrical component comprises: Discrete components; as well as An encapsulant is deposited around the discrete components.
11. A method for manufacturing a semiconductor device, comprising: Providing pre-molded discrete electrical components; as well as A semiconductor package is formed wherein the pre-molded discrete electrical components are disposed over the semiconductor package.
12. The method of claim 11 , wherein forming a semiconductor package comprises: depositing a first encapsulant over the pre-molded discrete electrical component; forming a first conductive layer over the first encapsulant and the pre-molded discrete electrical components; disposing an electrical component over the first conductive layer; depositing a second encapsulant over the electrical component and the first conductive layer; as well as A second conductive layer is formed over the second encapsulant. 13 . The method of claim 12 , further comprising forming a conductive pillar between the first conductive layer and the second conductive layer through the second encapsulant.
14. The method of claim 12, further comprising orienting an interconnect structure of the electrical component toward the first conductive layer or the second conductive layer.
15. The method of claim 11, wherein providing a pre-molded discrete electrical component comprises: Provide discrete components; as well as An encapsulant is deposited around the discrete components.