Semiconductor package structure and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure includes a plurality of semiconductor chips stacked; at least one semiconductor chip includes a plurality of stress detection structures arranged in different directions; the stress detection structures are located in an interconnection structure of the semiconductor chip; the plurality of semiconductor chips include a lead-out structure passing through the at least one semiconductor chip and connected with the stress detection structures; the lead-out structure leads the stress detection structures out to a top or a bottom of the plurality of semiconductor chips.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular, to a semiconductor package structure and a manufacturing method thereof. BACKGROUND

[0002] Three-dimensional chip stacking interconnection technology can increase the bandwidth between chips and improve computing performance. Chip stacking brings great challenges to heat dissipation and stress reliability. Three-dimensional chip stacking has the characteristics of heterogeneity. The thermal expansion coefficients of different materials are quite different, and stress is easily generated in the high-low temperature cycle process, which affects the performance of the chip. It is necessary to obtain the stress situation of the internal specific position of the chip in the three-dimensional chip stacking. SUMMARY

[0003] Therefore, embodiments of the present application provide a semiconductor package structure and a manufacturing method thereof.

[0004] In a first aspect, embodiments of the present application provide a semiconductor package structure, which includes a plurality of semiconductor chips stacked; at least one semiconductor chip includes a plurality of stress detection structures arranged in a plurality of different directions; the stress detection structures are located in an interconnection structure of the semiconductor chip; the plurality of semiconductor chips includes a lead-out structure passing through at least one semiconductor chip and connected with the stress detection structure; the lead-out structure leads out the stress detection structure to the top or bottom of the plurality of semiconductor chips.

[0005] In some embodiments, the plurality of stress detection structures includes a plurality of corresponding meander-shaped wires; the plurality of meander-shaped wires includes a first meander-shaped wire extending in a first direction and a second meander-shaped wire extending in a second direction; the first direction and the second direction extend and intersect in an interconnection layer of the interconnection structure; a first end of the first meander-shaped wire and a first end of the second meander-shaped wire are connected to a common end, and the common end, a second end of the first meander-shaped wire and a second end of the second meander-shaped wire are connected to a common pad, a first pad and a second pad of the lead-out structure.

[0006] In some embodiments, the plurality of meander-shaped wires further includes a third meander-shaped wire extending in the first direction and a fourth meander-shaped wire extending in the second direction; the first meander-shaped wire to the fourth meander-shaped wire are arranged circumferentially around the common end in an interconnection layer of the interconnection structure; a first end of the third meander-shaped wire and a first end of the fourth meander-shaped wire are connected to the common end, and a second end of the third meander-shaped wire and a second end of the fourth meander-shaped wire are connected to a third pad and a fourth pad of the lead-out structure.

[0007] In some embodiments, the plurality of folded wires further comprises a fifth folded wire and a seventh folded wire extending along a third direction, and a sixth folded wire and an eighth folded wire extending along a fourth direction; the first to eighth folded wires are arranged along a common end in an interconnect layer of the interconnect structure; first ends of the fifth to eighth folded wires are connected to the common end, and the common end is connected to a common pad of the lead-out structure; second ends of the fifth to eighth folded wires are connected to fifth to eighth pads of the lead-out structure, respectively.

[0008] In some embodiments, the outer contour of the folded wire is a quadrilateral or a triangle.

[0009] In some embodiments, the stress detection structure is located in a first interconnect layer of the interconnect structure; the first interconnect layer is located close to a side of the substrate of the semiconductor chip in the interconnect structure.

[0010] In some embodiments, the lead-out structure comprises a dummy through-silicon via, a dummy via, and a lead-out pad; the dummy through-silicon via passes through at least one semiconductor chip; the dummy via is located in the interconnect structure of the semiconductor chip, and is connected between the dummy through-silicon via and the lead-out pad, and is connected between the dummy through-silicon via and the stress detection structure; the lead-out pad is located on the top or bottom of the plurality of semiconductor chips, and is used to receive or output a stress test signal, which is applied to the lead-out pad from outside of the plurality of semiconductor chips, or is output from the lead-out pad to outside of the plurality of semiconductor chips.

[0011] In some embodiments, the semiconductor package structure further comprises a bonding structure located between two adjacent semiconductor chips; the lead-out structure comprises a dummy bonding via and a dummy bonding pad connected to each other and penetrating through the bonding structure; the dummy bonding via and the dummy bonding pad are connected between the dummy through-silicon via and the dummy via.

[0012] In a second aspect, the embodiments of the present application provide a method for manufacturing a semiconductor package structure, the method comprising: forming a first semiconductor chip; the first semiconductor chip comprising a plurality of stress detection structures and a corresponding plurality of first lead-out structures arranged along a plurality of different directions; the first lead-out structures being located on and connected with the stress detection structures; the stress detection structures being located in an interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip being located on a substrate of the first semiconductor chip; forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip comprising a plurality of second lead-out structures passing through a substrate of the second semiconductor chip and connected with the corresponding first lead-out structures; the first lead-out structures and the second lead-out structures leading the stress detection structures to a top of the plurality of semiconductor chips; or, forming a first semiconductor chip; the first semiconductor chip comprising a plurality of first lead-out structures; the first lead-out structures passing through a substrate of the first semiconductor chip and an interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip being located on the substrate of the first semiconductor chip; forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip comprising a plurality of stress detection structures and a corresponding plurality of second lead-out structures arranged along a plurality of different directions; the second lead-out structures being located under and connected with the stress detection structures; the second lead-out structures passing through a substrate of the second semiconductor chip and connected with the corresponding first lead-out structures; the stress detection structures being located in an interconnection structure of the second semiconductor chip; the interconnection structure of the second semiconductor chip being located on the substrate of the second semiconductor chip; the first lead-out structures and the second lead-out structures leading the stress detection structures to a bottom of the plurality of semiconductor chips.

[0013] In some embodiments, forming the first semiconductor chip comprising a plurality of stress detection structures and a corresponding plurality of first lead-out structures arranged along a plurality of different directions comprises: forming a first layer of interconnection layers of the interconnection structure of the first semiconductor chip on a substrate of the first semiconductor chip; the first layer of interconnection layers comprising a first metal interconnection layer of the first semiconductor chip and the stress detection structures; or, forming the second semiconductor chip comprising a plurality of stress detection structures and a corresponding plurality of second lead-out structures arranged along a plurality of different directions comprises: forming a first layer of interconnection layers of the interconnection structure of the second semiconductor chip on a substrate of the second semiconductor chip; the first layer of interconnection layers comprising a first metal interconnection layer of the second semiconductor chip and the stress detection structures.

[0014] In some embodiments, forming the second semiconductor chip on the first semiconductor chip comprises: connecting the first semiconductor chip and the second semiconductor chip by a bonding process.

[0015] In the embodiments of the present application, at least one semiconductor chip of the plurality of semiconductor chips arranged in a stack is provided with a plurality of stress detection structures arranged in different directions, the stress detection structures are located in the interconnection structure of the semiconductor chip and are led to the top or bottom of the plurality of semiconductor chips through the lead-out structure passing through the at least one semiconductor chip and connected with the stress detection structures, the stress conditions of the positions where the plurality of stress detection structures are located in the interconnection structure are tested, and the stress distribution in the plurality of semiconductor chips arranged in a stack is detected. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A cross-sectional schematic view of a semiconductor package structure provided by an embodiment of the present application;

[0017] Figure 2 A cross-sectional schematic view of a semiconductor package structure provided by an embodiment of the present application;

[0018] Figure 3 A planar schematic view of a zigzag-shaped wire as a stress detection structure provided by an embodiment of the present application;

[0019] Figure 4 A planar schematic view of a zigzag-shaped wire as a stress detection structure provided by an embodiment of the present application;

[0020] Figure 5 A planar schematic view of a plurality of zigzag-shaped wires extending in different directions as stress detection structures provided by an embodiment of the present application;

[0021] Figure 6 A planar schematic view of a plurality of zigzag-shaped wires extending in different directions as stress detection structures provided by an embodiment of the present application;

[0022] Figure 7A A planar schematic view of two quadrilateral zigzag-shaped wires extending in each different direction as stress detection structures provided by an embodiment of the present application;

[0023] Figure 7B A planar schematic view of two quadrilateral zigzag-shaped wires extending in each different direction as stress detection structures provided by an embodiment of the present application;

[0024] Figure 8A A planar schematic view of two triangular zigzag-shaped wires extending in each different direction as stress detection structures provided by an embodiment of the present application;

[0025] Figure 8B A planar schematic view of two triangular zigzag-shaped wires extending in each different direction as stress detection structures provided by an embodiment of the present application;

[0026] Figure 9AThe third planar schematic diagram of the stress detection structure provided in the embodiments of this application shows two triangular polygonal wires extending in different directions as stress detection structures.

[0027] Figure 9B The fourth planar schematic diagram of the stress detection structure provided in the embodiments of this application shows two triangular polygonal wires extending in different directions as stress detection structures.

[0028] Figure 10 One of the schematic flowcharts of a method for manufacturing a semiconductor packaging structure provided in an embodiment of this application;

[0029] Figures 11A-11C for Figure 10 A cross-sectional schematic diagram of the manufacturing method shown;

[0030] Figure 12 A second schematic flowchart illustrating the manufacturing method of the semiconductor packaging structure provided in this application embodiment;

[0031] Figures 13A-13C for Figure 12 A cross-sectional schematic diagram of the manufacturing method shown. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] In related technologies, the surface stress distribution of a wafer can be obtained through finite element simulation or theoretical formulas. For example, strain gauges can be embedded at the junction of the passivation layer and electrical insulation layer of a chip package or between multiple redistribution layers, and electrically connected to the chip package via solder balls to obtain the stress conditions at specific internal locations. However, measuring stress inside a wafer is very difficult. Due to their millimeter-scale size, package-level strain gauges are limited to measuring the internal stress of chip packages, and their testing techniques cannot be applied to the interior of chips in three-dimensional chip stacks (e.g., high-bandwidth memory (HBM)).

[0036] In view of this, embodiments of this application provide a semiconductor packaging structure and a method for manufacturing the same.

[0037] Figure 1 This is one of the cross-sectional schematic diagrams of the semiconductor packaging structure provided in the embodiments of this application. Figure 2 This is a second cross-sectional schematic diagram of the semiconductor packaging structure provided in the embodiments of this application.

[0038] In a first aspect, embodiments of this application provide a semiconductor packaging structure, with reference to... Figure 1 and Figure 2 The semiconductor package structure 300 includes a plurality of semiconductor chips stacked together (e.g., a first semiconductor chip 100 and a second semiconductor chip 200); at least one semiconductor chip (e.g., the first semiconductor chip 100 or the second semiconductor chip 200) includes a plurality of stress detection structures SS12 arranged in a plurality of different directions; the stress detection structures SS12 are located in the interconnect structure of the semiconductor chips; the plurality of semiconductor chips include an outgoing structure SS10 that passes through at least one semiconductor chip and is connected to the stress detection structures; the outgoing structure SS10 leads the stress detection structures SS12 to the top (also referred to as the top surface) SUR2 or the bottom (also referred to as the bottom surface) SUR1 of the plurality of semiconductor chips.

[0039] For ease of description, the first and second directions in this embodiment are represented as two intersecting directions parallel to the top / bottom surface of the semiconductor chip, for example, the first and second directions are orthogonal; the fifth direction is a direction perpendicular to the top / bottom surface of the semiconductor chip or a stacking direction of multiple semiconductor chips. For example, the first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the fifth direction can be represented as the Z direction in the figures.

[0040] It should be noted that, Figure 1 The semiconductor package structure 300 shown has a lead-out structure SS10 that leads the stress detection structure SS12 to the top SUR2 of multiple semiconductor chips. Figure 2The semiconductor package structure 300 shown has a lead-out structure SS10 that leads the stress detection structure SS12 to the bottom SUR1 of multiple semiconductor chips; wherein the top SUR2 and the bottom SUR1 are two opposite ends of the multiple semiconductor chips along the stacking direction.

[0041] It should be noted that the materials for the stress detection structure SS12 and the lead-out structure SS10 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicides, nitrides, or any combination thereof. For example, the materials for the stress detection structure SS12 and the lead-out structure SS10 may include copper and copper alloys.

[0042] It should be noted that in this article, the term "dummy" is used to refer to a component that is distinct from the functional circuitry of a semiconductor chip. For example, a "dummy through-silicon via" is not used to implement the functions of a semiconductor chip, such as to implement the lead-out of the stress detection structure SS12. In contrast, the term "through-silicon via" (TSV) is used to refer to a component that is not functionally related to a semiconductor chip. Figure 1 and Figure 2 (Not shown) can be understood as the electrical connection used to form the functional circuit of a semiconductor chip, which can be used to realize the various functions of the semiconductor chip.

[0043] refer to Figure 1 and Figure 2 , substrate ( Figure 1 and Figure 2 (Not shown) is used as the substrate for this semiconductor package structure and can be a printed circuit board (PCB), glass substrate, ceramic substrate, or a board with wiring. The semiconductor chip can be a memory chip or a logic chip. The logic chip can be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC). The memory chip can be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or it can be a non-volatile memory chip, such as a resistive random access memory (RRAM) chip.

[0044] In some embodiments, the semiconductor package structure 300 includes a plurality of semiconductor chips stacked on a substrate, the plurality of semiconductor chips including a first semiconductor chip 100 and a second semiconductor chip 200 stacked sequentially. The first semiconductor chip 100 includes a logic chip, and the second semiconductor chip 200 includes a memory chip. The first semiconductor chip 100 and at least one second semiconductor chip 200 on the first semiconductor chip 100 can constitute HBM DRAM. Although a semiconductor package structure 300 with one first semiconductor chip 100 and one second semiconductor chip 200 stacked sequentially on a substrate is shown in this example embodiment, the number of second semiconductor chips 200 that can be stacked on the first semiconductor chip 100 is not limited thereto. For example, two, three, or more than three second semiconductor chips 200 (e.g., four chips) can be stacked on the first semiconductor chip 100.

[0045] In some embodiments, the circuitry of the first semiconductor chip 100 and / or the circuitry of the second semiconductor chip 200 are functional circuits led out by interconnect structures located in an insulating layer (also referred to below as a dielectric layer). Figure 1 and Figure 2 (Not shown). Functional circuitry may include a wide variety of active and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design. Functional circuitry may include NMOS or PMOS devices. The insulating layer material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The interconnect layer material includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicides, nitrides, or any combination thereof.

[0046] For example, the substrate material of the first semiconductor chip 100 may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrate, etc.; the substrate may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Functional circuits and interconnect structures for leading out functional circuits on the substrate of the first semiconductor chip 100 can be formed in the substrate of the first semiconductor chip 100 through one or more patterning processes. The interconnect layers in the interconnect structure of the first semiconductor chip 100 include dielectric layers (…). Figure 1 and Figure 2 (not shown) and conductive components formed in the dielectric layer ( Figure 1 and Figure 2(Not shown). The dielectric layer is an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD), which can be formed of a dielectric material. The material of the dielectric layer can include dielectric materials with a dielectric constant (k value) lower than 3.8. The material of the conductive component can include metals such as copper or tungsten.

[0047] In some embodiments, at least two of the multiple semiconductor chips include multiple stress detection structures SS12 arranged in multiple different directions. Figure 1 and Figure 2 (Not shown). For example, each semiconductor chip includes multiple stress detection structures arranged in multiple different directions, all of which extend towards the top SUR2, or all of which extend towards the bottom SUR1. In some embodiments, at least two of the multilayer interconnect layers of the semiconductor chip include multiple stress detection structures SS12 arranged in multiple different directions (in this case). Figure 1 and Figure 2 (Not shown). For example, the first interconnect layer M1, the second interconnect layer M2, and the third interconnect layer M3 of the first semiconductor chip 100 are each provided with multiple stress detection structures SS12 arranged in multiple different directions (in this case). Figure 1 and Figure 2 (Not shown).

[0048] In the following explanation, ... Figure 1 The semiconductor package structure 300 shown is described in detail, but this exemplary description is not intended to limit the embodiments of this application.

[0049] In some embodiments, the stress detection structure may be located in the substrate of the semiconductor chip or in the interconnect structure of the semiconductor chip. For example, the stress detection structure is located in an interconnect layer in the interconnect structure. In some embodiments, the stress detection structure is located in a first interconnect layer M1 of the interconnect structure; the first interconnect layer M1 is located on the side of the interconnect structure closer to the substrate of the semiconductor chip.

[0050] In some embodiments, the stress detection structure may be a resistor or a capacitor. For example, the stress detection structure may be a linear resistor. Exemplarily, the stress detection structure may be a zigzag wire made of P-type or N-type semiconductor material located in the substrate, or the stress detection structure may be a zigzag wire made of conductive components located in the interconnect layer.

[0051] Figure 2 The polygonal conductor provided in this application is one of the planar schematic diagrams of a stress detection structure. Figure 1The second planar schematic diagram of the polygonal conductor as a stress detection structure provided in the embodiments of this application is shown.

[0052] like Figure 3 and Figure 4 As shown, a zigzag-shaped conductor can be fabricated in at least one interconnect layer of a semiconductor chip's interconnect structure using semiconductor manufacturing technology to serve as a stress detection structure SS12. When the wafer (which can be understood as a semiconductor packaging structure in the process) warps, stress is generated at the location of the stress detection structure SS12, and the stress on the zigzag conductor causes a change in its resistance. According to the resistance law R = ρL / S (hereinafter referred to as Formula 1), the resistance R of the zigzag conductor is directly proportional to its length L and resistivity ρ, and inversely proportional to its cross-sectional area S, where ρ is the resistivity of the material used to make the zigzag conductor, L is the length of the zigzag conductor, S is the cross-sectional area of ​​the zigzag conductor, and R is the resistance value of the zigzag conductor. From the resistance R = ρL / S of the polygonal conductor, we know that the length L can be calculated using the cross-sectional area S and the Poisson's ratio of the material of the polygonal conductor. There is a linear relationship between the length L and the stress. Therefore, the length change ΔL of the polygonal conductor before and after being subjected to stress can be characterized by the resistance change ΔR of the polygonal conductor before and after being subjected to stress. The resistance change ΔR can be expressed as a linear function of the circumferential stress of the polygonal conductor. In other words, by measuring the resistance change ΔR of the polygonal conductor before and after being subjected to stress, we can characterize the stress at the location of the polygonal conductor.

[0053] The stress at a given location can be calculated using the formula Ks*ε=ΔR / R (hereinafter referred to as Formula 2). The sign of the stress indicates whether the location is under tension or compression. Here, Ks is the sensitivity coefficient of the stress detection structure, ε is the stress at the location of the stress detection structure, ΔR is the change in resistance of the stress detection structure before and after being subjected to stress, and R is the initial resistance of the stress detection structure before being subjected to stress. The stress ε at the location of the broken-line conductor, the change in resistance ΔR of the broken-line conductor, the initial resistance R, and the sensitivity coefficient Ks have a linear relationship as shown in Formula 2. By measuring the initial resistance R of the stress detection structure before being subjected to stress and the final resistance R' of the stress detection structure after being subjected to stress, the resistance change ΔR=(R'-R) can be obtained. The stress at that location can be calculated using Formula 2, and the sign of the stress indicates whether the location is under tension or compression.

[0054] refer to Figure 3 and Figure 4Before the stress detection structure is subjected to stress, the initial resistance R can be obtained by applying a test voltage to the first and second terminals of the stress detection structure SS12. After the stress detection structure is subjected to stress, the final resistance R' can be obtained by applying a test voltage to the first and second terminals of the stress detection structure SS12. The first and second terminals of the stress detection structure SS12 can be led out through one lead-out pad and another lead-out pad, respectively, which receive the test voltage.

[0055] refer to Figure 3 and Figure 4 In some embodiments, the outer contour of the polygonal conductor is a quadrilateral or a triangle.

[0056] Figure 3 The multiple polygonal wires extending in different directions provided in the embodiments of this application are one of the planar schematic diagrams of the stress detection structure. Figure 4 The second schematic diagram shows multiple polygonal wires extending in different directions as a stress detection structure, provided in the embodiments of this application.

[0057] In some embodiments, by arranging multiple stress detection structures extending in different directions, the stress distribution magnitude in different stress detection directions can be obtained. These different stress detection directions can be any different direction within a plane, ranging from 0 degrees to 180 degrees, and the arrangement of these different stress detection directions can be adaptively set according to actual process requirements. For example, refer to... Figure 5 By arranging multiple stress detection structures along the X direction (0 degrees) and Y direction (90 degrees), the stress distribution in the 0-degree and 90-degree directions can be obtained. For example, refer to... Figure 6 By arranging multiple stress detection structures along the fourth direction D4 (indicated as 45 degrees) and the Y direction (indicated as 90 degrees), the stress distribution magnitude in the 45-degree and 90-degree directions can be obtained.

[0058] In some embodiments, by arranging multiple stress detection structures extending in different directions, they can be closely arranged in the same direction to achieve a minimum footprint. For example, refer to... Figure 5 Two stress detection structures with a quadrilateral outer contour of a polygonal conductor can be arranged adjacent to each other along the X-direction. These two quadrilateral stress detection structures are squares extending along the X and Y directions, respectively, and they function as a single unit, also extending into a square along the X and Y directions. This minimizes the occupied area along the X and Y directions. For example, refer to... Figure 6The outer contour of the broken-line conductor is a triangle. Two stress detection structures can be arranged adjacent to each other in the X direction. Although one of the two stress detection structures in the triangle intersects both the X and Y directions, the two stress detection structures in the triangle as a whole are still a square extending along the X and Y directions, which can obtain the minimum occupied area in the X and Y directions.

[0059] Figure 5 The two quadrilateral polygonal wires extending in each different direction provided in the embodiments of this application are one of the planar schematic diagrams of the stress detection structure. Figure 6 The second planar schematic diagram of the stress detection structure provided in the embodiments of this application shows two quadrilateral broken-line wires extending in different directions.

[0060] refer to Figure 7A In some embodiments, the plurality of stress detection structures include a plurality of corresponding polygonal conductors; the plurality of polygonal conductors include a first polygonal conductor extending along a first direction and a second polygonal conductor extending along a second direction; the first direction and the second direction extend and intersect in an interconnect layer of the interconnect structure; a first end of the first polygonal conductor and a first end of the second polygonal conductor are connected to a common end, and the common end, the second end of the first polygonal conductor, and the second end of the second polygonal conductor are connected to a common pad P0, a first pad P1, and a second pad P2 of the lead-out structure. In some embodiments, the plurality of polygonal conductors further include a third polygonal conductor extending along the first direction and a fourth polygonal conductor extending along the second direction; the first to fourth polygonal conductors are arranged circumferentially along the common end in an interconnect layer of the interconnect structure; the first end of the third polygonal conductor and the first end of the fourth polygonal conductor are connected to the common end, and the second end of the third polygonal conductor and the second end of the fourth polygonal conductor are connected to a third pad P3 and a fourth pad P4 of the lead-out structure.

[0061] The first to fourth zigzag traverses are arranged circumferentially along the common end. That is, the zigzag traverses extending along the first direction (the first or third zigzag traverse) and the zigzag traverses extending along the second direction (the second or fourth zigzag traverse) are arranged alternately in the circumferential direction. The four zigzag traverses arranged symmetrically in the circumferential direction can occupy a smaller area as a whole, and the environment in which each zigzag traverse is located is symmetrical. At the same time, two zigzag traverses are set in each direction that are symmetrical about the environment of the common end, which can avoid the large measurement fluctuations caused by setting only one zigzag traverse in each direction.

[0062] refer to Figure 7BIn some embodiments, the plurality of zigzag conductors further include a fifth zigzag conductor and a seventh zigzag conductor extending along a third direction, and a sixth zigzag conductor and an eighth zigzag conductor extending along a fourth direction; the first zigzag conductor to the eighth zigzag conductor are arranged circumferentially along a common terminal in an interconnect layer of the interconnect structure; the first ends of the fifth zigzag conductor to the eighth zigzag conductor are connected to the common terminal, the common terminal is connected to the common pad P10 of the lead-out structure, and the second ends of the fifth zigzag conductor to the eighth zigzag conductor are respectively connected to the fifth pad P5 to the eighth pad P8 of the lead-out structure.

[0063] Combination Figure 7A and Figure 7B Ten pads, including common pad P0, common pad P10, and pads P1 through P8, are used to lead out eight polygonal conductors. This allows for the measurement of stress distribution in four different directions: X (0 degrees), D4 (45 degrees), Y (90 degrees), and D3 (135 degrees). This enables the detection of stress distribution in more directions while maintaining a smaller footprint for the multiple polygonal conductors as a whole.

[0064] Figure 7A The two triangular polygonal wires extending in each different direction provided in the embodiments of this application are one of the planar schematic diagrams of the stress detection structure. Figure 7B The second planar schematic diagram of the stress detection structure is provided for each of the two triangular broken-line conductors extending in different directions in the embodiments of this application. Figure 8A The third planar schematic diagram of the stress detection structure is provided for each of the two triangular broken-line conductors extending in different directions in the embodiments of this application. Figure 8B The fourth planar schematic diagram of the stress detection structure is provided for each of the two triangular broken-line conductors extending in different directions in the embodiments of this application.

[0065] Four polygonal conductors are considered as a whole. If the overall shape (square) and the direction of extension of the polygonal conductors remain unchanged, compared to... Figure 9A , Figure 9B The broken line shape shown has been changed to a triangle.

[0066] Assuming the four polygonal conductors are treated as a whole, and given that the overall shape (rhombus) and the direction of extension of the polygonal conductors remain unchanged, compared to... Figure 7A , Figure 8A The broken line shape shown has been changed to a triangle.

[0067] Four broken-line conductors are considered as a whole. With the overall shape (square) and the individual shapes (triangles) within this whole remaining unchanged, compared to... Figure 7B ,Figure 8B The extension direction of the broken-line conductor shown changes to the third direction D3 and the fourth direction D4.

[0068] Assuming the four polygonal conductors form a whole, and that the overall shape (rhombus) and the individual shapes (triangles) within that whole remain unchanged, compared to... Figure 8A , Figure 9A The extension direction of the broken-line conductor shown changes to the first direction X and the second direction Y.

[0069] In some embodiments, combined with Figure 8B and Figure 9B Or, combining 8A and Figure 7A Ten pads, including common pad P0, common pad P10, and pads P1 through P8, are used to draw eight polygonal conductors, allowing for the measurement of stress distribution in four different directions (X direction (0 degrees), fourth direction D4 (45 degrees), Y direction (90 degrees), and third direction D3 (135 degrees)). Furthermore, two groups of four polygonal conductors extend as a whole along the first and second directions, forming eight polygonal conductors. These eight conductors, as a whole, still extend along the first and second directions, resulting in a compact structure. This allows for the detection of stress distribution in more directions while occupying a smaller area with multiple polygonal conductors as a whole.

[0070] Similarly, in some embodiments, combined with Figure 9A and Figure 9A , or, combined Figure 7B and Figure 9B This allows us to obtain eight polygonal conductors extending along the third and fourth directions.

[0071] To clearly show the relative positional relationship between the two ends (the first end and the second end) of the polygonal conductor and the lead-out pads, Figure 8B The 10 pads shown are common pad P0, common pad P10, and first pad P1 to eighth pad P8. Parts of these 10 pads are schematically projected onto the plane containing the corresponding multiple polygonal conductors. The shape and size of these 10 pads are not used to limit the actual shape and size of the lead-out pads.

[0072] refer to Figure 9B and Figures 5-9B In some embodiments, the lead-out structure SS10 includes a dummy silicon via SS16 and a dummy through-hole (SSD). Figure 1 and Figure 2(Not shown) and lead-out pad SS18; wherein, a dummy through-silicon via SS16 passes through at least one semiconductor chip; a dummy via is located in the interconnect structure of the semiconductor chip, connecting the dummy through-silicon via SS16 and the lead-out pad SS18, and connecting the dummy through-silicon via SS16 and the stress detection structure SS12; the lead-out pad SS18 is located at the top or bottom of the plurality of semiconductor chips, for receiving or outputting stress test signals, the stress test signals being applied to the lead-out pad from the outside of the plurality of semiconductor chips, or being output from the lead-out pad to the outside of the plurality of semiconductor chips.

[0073] It should be noted that dummy vias can be located between interconnect layers in an interconnect structure to enable connections between the interconnect layers. For example, the two ends of the stress detection structure SS12 can be led out to the corresponding dummy through-silicon vias SS16 through dummy vias connecting the interconnect layers.

[0074] In some embodiments, the first end (or second end) of the stress sensing structure, the corresponding dummy through-silicon via (TSV), and the corresponding dummy via at least partially overlap with the lead-out pad in the plane containing the lead-out pad. Thus, the lead-out structure SS10 extends in the stacking direction of the multiple semiconductor chips, avoiding the introduction of measurement errors due to its extension in the plane containing the first and second directions. For example, if the stress sensing structure SS12 is a component that senses stress changes, and the direction in which it is subjected to stress lies in the plane containing the first and second directions, the stress should not be affected by stress on other non-sensing parts (lead-out structure SS10) in the plane containing the first and second directions; or, compared to the stress affecting the sensing part (stress sensing structure SS12) in the plane containing the first and second directions, the stress affecting the non-sensing part (lead-out structure SS10) in the plane containing the first and second directions can be ignored. In other words, by extending the lead-out structure SS10 in the stacking direction and avoiding its extension in the plane containing the first and second directions, the introduction of measurement errors can be reduced or avoided.

[0075] In some embodiments, the semiconductor package structure further includes a bonding structure located between two adjacent semiconductor chips; the lead-out structure includes dummy bonding vias and dummy bonding pads SS14 located in the bonding structure and interconnected and penetrating the bonding structure; the dummy bonding vias and dummy bonding pads SS14 are connected between the dummy through-silicon via SS16 and the dummy via.

[0076] The bonding structure includes a first bonding structure 106 located on the first semiconductor chip 100 and a second bonding structure 206 located on the second semiconductor chip 200. The second semiconductor chip 200 can be disposed on the first semiconductor chip 100 by a bonding process, such as a hybrid bonding process, to connect the dummy silicon via SS16 and the stress detection structure SS12, thereby enabling the stress detection structure SS12 to be brought out.

[0077] In various embodiments of this application, at least one of the stacked semiconductor chips is provided with multiple stress detection structures arranged in multiple different directions. The stress detection structures are located in the interconnect structure of the semiconductor chips and are led out to the top or bottom of the multiple semiconductor chips through the lead-out structure that passes through at least one semiconductor chip and is connected to the stress detection structure. The stress conditions at the locations of the multiple stress detection structures in the interconnect structure of the middle layer of the semiconductor chips are used to test the stress distribution in the stacked semiconductor chips.

[0078] Figure 1 This is one of the schematic flowcharts of a method for manufacturing a semiconductor packaging structure provided in an embodiment of this application. Figure 2 for Figure 10 A cross-sectional schematic diagram of the manufacturing method shown. Figures 11A-11C This is a second schematic flowchart illustrating the manufacturing method of the semiconductor packaging structure provided in this application embodiment. Figure 10 for Figure 12 A cross-sectional schematic diagram of the manufacturing method shown.

[0079] Secondly, embodiments of this application provide a method for manufacturing a semiconductor packaging structure, see below. Figures 13A-13C The manufacturing method includes the following steps: S101, forming a first semiconductor chip; the first semiconductor chip includes a plurality of stress detection structures arranged along a plurality of different directions and a plurality of corresponding first lead-out structures; the first lead-out structures are located on and connected to the stress detection structures; the stress detection structures are located in the interconnect structure of the first semiconductor chip; the interconnect structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; S102, forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip includes a second lead-out structure passing through the substrate of the second semiconductor chip and connected to the corresponding first lead-out structure; the first lead-out structure and the second lead-out structure lead the stress detection structures to the top of the plurality of semiconductor chips.

[0080] In some embodiments, a first semiconductor chip is formed including a plurality of stress detection structures arranged in a plurality of different directions and a plurality of corresponding first lead-out structures, including: forming a first interconnect layer of interconnect structure of the first semiconductor chip on a substrate of the first semiconductor chip; the first interconnect layer includes a first metal interconnect layer of the first semiconductor chip and stress detection structures.

[0081] refer to Figure 12 A functional circuit is formed in the substrate 102 of the first semiconductor chip 100. Figure 10 (Not shown). An insulating layer and an interconnect structure 104 for functional circuits are formed on a substrate 102 of the first semiconductor chip 100. In some embodiments, a first interconnect layer M1, a second interconnect layer M2, and a third interconnect layer M3 are sequentially formed on the interconnect structure 104. A stress detection structure SS12 can be formed during the photolithography etching process that forms the first interconnect layer M1. An insulating layer is formed on the interconnect structure 104, and a first bonding structure 106 connected to the interconnect structure 104 is formed in the insulating layer. The first bonding structure 106 includes a first dummy bonding pad SS13. For example, the first dummy bonding pad SS13 can be a via dummy via (…). Figure 11A (Not shown) is connected to the stress detection structure SS12. For example, the two ends of the stress detection structure SS12 can be led out to the corresponding first dummy bonding pad SS13 through dummy vias connecting the interconnect layers.

[0082] In some embodiments, the stress detection structure SS12 can be measured during fabrication (at which point it is located on the surface of the semiconductor chip) to calibrate its sensitivity coefficient Ks. In some embodiments, during fabrication of the stress detection structure SS12, a test voltage can be received by two first dummy bonding pads SS13 connected to both ends of the stress detection structure SS12 to test the first resistance R1 of the stress detection structure SS12 and the first lead-out structure.

[0083] refer to Figure 11A A functional circuit is formed in the substrate 202 of the second semiconductor chip 200. Figure 11A (Not shown). An insulating layer is formed on the substrate 202 of the second semiconductor chip 200, and interconnect structures 204 for functional circuits and dummy silicon vias SS16 extending through the substrate 202 are formed in the insulating layer. An insulating layer is formed on the interconnect structure 204, and an interconnect structure 208 connected to the interconnect structure 204 is formed in the insulating layer. The interconnect structure 208 includes an interconnect pad SS18. A second bonding structure 206 is formed under the substrate 202 of the second semiconductor chip 200. The second bonding structure 206 includes a second dummy bonding pad SS15. For example, the second dummy bonding pad SS15 can be a via dummy through-hole (…). Figure 11B (Not shown) is connected to one end of the corresponding dummy silicon via SS16, and the other end of the dummy silicon via SS16 is connected through a dummy via ( Figure 11B (Not shown) Connect to the corresponding lead-out pad SS18.

[0084] In some embodiments, the second resistance R2 of the second lead structure can be obtained by receiving test voltage through two pairs of pads connected to both ends of the stress detection structure SS12 (where each pair of pads corresponds to a second dummy bonding pad SS15 and a lead-out pad SS18).

[0085] refer to Figure 11B A bonding process, such as hybrid bonding, is used to bond the first semiconductor chip and the second semiconductor chip together. The lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the top SUR2 of multiple semiconductor chips. The first bonding structure 106 and the second bonding structure 206 constitute the bonding structure 302, and the first dummy bonding pad SS13 and the second dummy bonding pad SS15 constitute the dummy bonding pad SS14. For example, one end of the dummy bonding pad SS14 can be a through-hole (dummy via). Figure 11B (Not shown) is connected to one end of the corresponding dummy silicon via SS16, and the other end of the dummy bonding pad SS14 can be connected to a dummy via ( Figure 11C (Not shown) is connected to the corresponding stress detection structure SS12.

[0086] In some embodiments, a test voltage can be received through two lead-out pads SS18 connected to both ends of the stress detection structure SS12 to test the final resistance R' of the lead-out structure. As mentioned above, compared to the stress affecting the sensing part (stress detection structure SS12) in the plane containing the first and second directions, the stress affecting the non-sensing part (lead-out structure SS10) in the plane containing the first and second directions can be ignored. The resistance of the first lead-out structure (included in the first resistance R1) and the second resistance R2 of the second lead-out structure are negligible in terms of stress before and after bonding (which can be exemplified as before and after being subjected to stress). That is, the resistance values ​​of the first lead-out structure and the second resistance R2 of the second lead-out structure remain unchanged before and after bonding. It can be obtained that the resistance change of the stress detection structure before and after being subjected to stress is ΔR = (R' - (R1 + R2)) (hereinafter referred to as Formula 3). According to Formula 3, the stress at this position can be calculated, and the sign of the stress can be used to determine whether the position is subjected to tension or compression.

[0087] This application provides another method for manufacturing a semiconductor packaging structure, see below. Figure 11CThe manufacturing method includes the following steps: S201, forming a first semiconductor chip; the first semiconductor chip includes a plurality of first lead-out structures; the first lead-out structures pass through the substrate of the first semiconductor chip and the interconnect structure of the first semiconductor chip; the interconnect structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; S202, forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip includes a plurality of stress detection structures arranged along a plurality of different directions and corresponding plurality of second lead-out structures; the second lead-out structures are located below the stress detection structures and connected to the stress detection structures; the second lead-out structures pass through the substrate of the second semiconductor chip and are connected to the corresponding first lead-out structures; the stress detection structures are located in the interconnect structure of the second semiconductor chip; the interconnect structure of the second semiconductor chip is located on the substrate of the second semiconductor chip; the first lead-out structures and the second lead-out structures lead the stress detection structures to the bottom of the plurality of semiconductor chips.

[0088] In some embodiments, a second semiconductor chip is formed including a plurality of stress detection structures arranged in a plurality of different directions and a plurality of corresponding second lead-out structures, including: forming a first interconnect layer of interconnect structure of the second semiconductor chip on a substrate of the second semiconductor chip; the first interconnect layer includes a first metal interconnect layer of the second semiconductor chip and stress detection structures.

[0089] refer to Figure 11C A functional circuit is formed in the substrate 102 of the first semiconductor chip 100. Figure 12 (Not shown). An insulating layer is formed on the substrate 102 of the first semiconductor chip 100, and an interconnect structure 104 for functional circuits is formed in the insulating layer. An insulating layer is formed on the interconnect structure 104, and a first bonding structure 106 connected to the interconnect structure 104 is formed in the insulating layer. The first bonding structure 106 includes a first dummy bonding pad SS13. A dummy silicon via SS17 penetrating the substrate 102 is formed under the substrate 102 of the first semiconductor chip 100, and an exit structure 108 is formed under the substrate 102 of the first semiconductor chip 100 and connected to the dummy silicon via SS17. The exit structure 108 includes an exit pad SS18. For example, the first dummy bonding pad SS13 can be a via-hole dummy via ( Figure 13A (Not shown) is connected to one end of the corresponding dummy through-silicon via SS17, and the other end of the dummy through-silicon via SS17 is connected through a dummy via ( Figure 13A (Not shown) Connect to the corresponding lead-out pad SS18.

[0090] In some embodiments, the second resistance R2 of the first lead-out structure can be obtained by receiving test voltage through two pairs of pads (one pair of pads corresponds to a first dummy bonding pad SS13 and a lead-out pad SS18) at both ends of the stress detection structure SS12.

[0091] refer to Figure 13A A functional circuit is formed in the substrate 202 of the second semiconductor chip 200. Figure 13A (Not shown). An insulating layer and an interconnect structure 204 for functional circuits are formed on the substrate 202 of the second semiconductor chip 200. In some embodiments, a first interconnect layer M1, a second interconnect layer M2, and a third interconnect layer M3 are sequentially formed in the interconnect structure 104. A stress detection structure SS12 can be formed during the photolithography etching process that forms the first interconnect layer M1. A dummy silicon via SS16 penetrating the substrate 202 is formed under the substrate 202 of the second semiconductor chip 200. A second bonding structure 206 is formed under the substrate 202 of the second semiconductor chip 200 and connected to the dummy silicon via SS16. The second bonding structure 206 includes a second dummy bonding pad SS15. For example, one end of the dummy silicon via SS16 can be connected to the corresponding stress detection structure SS12, and the other end of the dummy silicon via SS16 can be a dummy via (…). Figure 13B (Not shown) is connected to the corresponding second dummy bonding pad SS15.

[0092] In some embodiments, the stress detection structure SS12 can be measured during fabrication (at which point it is located on the surface of the semiconductor chip) to calibrate its sensitivity coefficient Ks. In some embodiments, during fabrication of the stress detection structure SS12, a test voltage can be received through two second dummy bonding pads SS15 connected to both ends of the stress detection structure SS12 to test the first resistance R1 of the stress detection structure SS12 and the second lead-out structure.

[0093] refer to Figure 13B A bonding process, such as a hybrid bonding process, is used to bond the first semiconductor chip and the second semiconductor chip together. The lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the bottom SUR1 of multiple semiconductor chips. The first bonding structure 106 and the second bonding structure 206 constitute the bonding structure 302, and the first dummy bonding pad SS13 and the second dummy bonding pad SS15 constitute the dummy bonding pad SS14. For example, one end of the dummy bonding pad SS14 can be a through-hole (dummy via). Figure 13B (Not shown) is connected to one end of the corresponding dummy silicon via SS16, and the other end of the dummy bonding pad SS14 can be connected to a dummy via ( Figure 13C (Not shown) is connected to one end of the corresponding dummy silicon via SS17, and the other end of the dummy silicon via SS17 is a through-hole dummy via ( Figure 13C Figure 13C Figure 13C (Not shown) Connect to the corresponding lead-out pad SS18.

[0094] In some embodiments, a test voltage can be received through two lead-out pads SS18 connected to both ends of the stress detection structure SS12 to test the final resistance R' of the lead-out structure. As mentioned above, the resistance change ΔR of the stress detection structure before and after being subjected to stress can be obtained. The stress at this location can be calculated according to Formula 3. The sign of the stress can be used to determine whether the location is under tension or compression.

[0095] The semiconductor packaging structure obtained by the manufacturing method of the semiconductor packaging structure provided in the second aspect of this application is similar to the semiconductor packaging structure provided in the first aspect above. For technical features not disclosed in detail in the embodiments of this application, please refer to the semiconductor packaging structure in the above embodiments for understanding. Here, they will not be repeated.

[0096] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A semiconductor package structure, comprising: A plurality of semiconductor chips are stacked; At least one of the semiconductor chips includes a plurality of stress detection structures arranged in a plurality of different directions; the stress detection structures are located in an interconnection structure of the semiconductor chip; The plurality of semiconductor chips includes a plurality of lead-out structures passing through at least one of the semiconductor chips and connected to the stress detection structures; the lead-out structures lead the stress detection structures out to a top or a bottom of the plurality of semiconductor chips; The lead-out structures include dummy through-silicon vias, dummy through-holes, and lead-out pads; wherein, The dummy through-silicon vias pass through at least one of the semiconductor chips; The dummy through-holes are located in the interconnection structure of the semiconductor chip; The lead-out pads are located at the top or the bottom of the plurality of semiconductor chips for receiving or outputting stress test signals, which are applied to the lead-out pads from outside of the plurality of semiconductor chips or output from the lead-out pads to outside of the plurality of semiconductor chips; The semiconductor package structure further includes a bonding structure located between two adjacent semiconductor chips; The lead-out structures include dummy bonding through-holes and dummy bonding pads connected to each other and passing through the bonding structure; The dummy bonding through-holes and the dummy bonding pads are connected between the dummy through-silicon vias and the dummy through-holes.

2. The semiconductor package structure of claim 1, wherein, The plurality of stress detection structures includes a plurality of corresponding zigzag-shaped wires; the plurality of zigzag-shaped wires includes a first zigzag-shaped wire extending in a first direction and a second zigzag-shaped wire extending in a second direction; the first direction and the second direction extend and intersect in an interconnection layer of the interconnection structure; First ends of the first zigzag-shaped wire and the second zigzag-shaped wire are connected to a common end, and the common end, second ends of the first zigzag-shaped wire and the second zigzag-shaped wire are connected to common pads, first pads and second pads of the lead-out structures.

3. The semiconductor package structure of claim 2, wherein, The plurality of zigzag-shaped wires further includes a third zigzag-shaped wire extending in the first direction and a fourth zigzag-shaped wire extending in the second direction; the first to fourth zigzag-shaped wires are arranged circumferentially around the common end in an interconnection layer of the interconnection structure; First ends of the third zigzag-shaped wire and the fourth zigzag-shaped wire are connected to the common end, and second ends of the third zigzag-shaped wire and the fourth zigzag-shaped wire are connected to third pads and fourth pads of the lead-out structures.

4. The semiconductor package structure of claim 3, wherein, The plurality of zigzag-shaped wires further includes a fifth zigzag-shaped wire and a seventh zigzag-shaped wire extending in a third direction, and a sixth zigzag-shaped wire and an eighth zigzag-shaped wire extending in a fourth direction; The first to eighth zigzag-shaped wires are arranged circumferentially around the common end in an interconnection layer of the interconnection structure; First ends of the fifth to eighth zigzag-shaped wires are connected to the common end, and the common end is connected to common pads of the lead-out structures, and second ends of the fifth to eighth zigzag-shaped wires are respectively connected to fifth to eighth pads of the lead-out structures.

5. The semiconductor package structure of claim 2 or 3, wherein, The outer contour of the fold line-shaped wire is quadrilateral or triangular; and the outer contour of the plurality of fold line-shaped wires is square.

6. The semiconductor package structure of claim 1, wherein, The stress detection structure is located in a first layer interconnection layer of the interconnection structure; the first layer interconnection layer is located on a side close to a substrate of the semiconductor chip in the interconnection structure.

7. A method of manufacturing a semiconductor package structure, characterized by, Comprising: forming a first semiconductor chip; The first semiconductor chip comprises a plurality of stress detection structures arranged in a plurality of different directions and a corresponding plurality of first lead-out structures; The first lead-out structure is located on the stress detection structure and is connected with the stress detection structure; The stress detection structure is located in the interconnection structure of the first semiconductor chip; The interconnection structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; Forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip comprises a second lead-out structure passing through the substrate of the second semiconductor chip and connected with the corresponding first lead-out structure; the first lead-out structure and the second lead-out structure lead the stress detection structure out to the top of the plurality of semiconductor chips; Or, forming a first semiconductor chip; the first semiconductor chip comprises a plurality of first lead-out structures; the first lead-out structure passes through the substrate of the first semiconductor chip and the interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; Forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip comprises a plurality of stress detection structures arranged in a plurality of different directions and a corresponding plurality of second lead-out structures; the second lead-out structure is located below the stress detection structure and is connected with the stress detection structure; the second lead-out structure passes through the substrate of the second semiconductor chip and is connected with the corresponding first lead-out structure; The stress detection structure is located in the interconnection structure of the second semiconductor chip; The interconnection structure of the second semiconductor chip is located on the substrate of the second semiconductor chip; the first lead-out structure and the second lead-out structure lead the stress detection structure out to the bottom of the plurality of semiconductor chips.

8. The manufacturing method according to claim 7, wherein Forming the first semiconductor chip comprising a plurality of stress detection structures arranged in a plurality of different directions and a corresponding plurality of first lead-out structures, comprising: forming a first layer interconnection layer of the interconnection structure of the first semiconductor chip on the substrate of the first semiconductor chip; the first layer interconnection layer comprises the first metal interconnection layer of the first semiconductor chip and the stress detection structure; Or, Forming the second semiconductor chip comprising a plurality of stress detection structures arranged in a plurality of different directions and a corresponding plurality of second lead-out structures, comprising: forming a first layer interconnection layer of the interconnection structure of the second semiconductor chip on the substrate of the second semiconductor chip; the first layer interconnection layer comprises the first metal interconnection layer of the second semiconductor chip and the stress detection structure.

9. The production method according to claim 7, wherein Forming a second semiconductor chip on the first semiconductor chip, comprising: using a bonding process to bond and connect between the first semiconductor chip and the second semiconductor chip.

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