Semiconductor Structure and Method for Preparing the Same

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate, the top of the substrate has an ion doping region, and the ion doping region includes a first detection region and a second detection region that are exactly the same; a first resistance detection structure, including: a first blocking structure, the first detection region is completely covered by the first blocking structure; a first electrode for obtaining a first resistance of the first detection region; a second resistance detection structure, including: a second blocking structure, a part of the second detection region is covered by the second blocking structure, and an oxide layer is formed on the surface of another part of the second detection region; a second electrode for obtaining a second resistance of the second detection region. By forming a first resistance detection structure without an oxide layer and a second resistance detection structure with an oxide layer on the surface of the ion doping region, the oxidation enhanced diffusion effect of the doped ions is characterized according to the difference in the measured resistance values of the two, thereby improving the performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a preparation method thereof. Background Art

[0002] In integrated circuit manufacturing, wafers are ion-doped by means such as ion implantation, and the doped ions are diffused through heat treatment. Among them, the oxidation enhanced diffusion effect (OED) is an important factor affecting ion diffusion. During the oxidation process, the diffusion movement of ions is achieved through two mechanisms: vacancy and interstitial, and the interstitial mechanism may play a more important role. Taking the diffusion of boron ions in a silicon substrate as an example, when silicon is oxidized, a large number of interstitial silicon atoms are generated near the Si / SiO 2 interface. While these excess interstitial silicon atoms diffuse into the silicon body, they continuously recombine with vacancies, causing the concentration of these excess interstitial silicon atoms to decrease with depth. However, near the surface, the excess interstitial silicon atoms can interact with substitutional boron, causing the originally substitutional boron atoms to become interstitial boron. When there is no vacancy in the neighboring lattice of interstitial boron, interstitial boron moves in an interstitial manner; if a vacancy appears in the neighboring lattice of interstitial boron, interstitial boron can enter the vacancy and become substitutional boron. In this way, boron ions move in an alternative substitutional-interstitial manner, and their diffusion rate is faster than that from substitutional to substitutional alone.

[0003] However, due to the different oxidation enhanced diffusion effects of different doped ions and the different influences of different processes on the oxidation enhanced diffusion effect of doped ions, it is impossible to estimate the distribution of doped ions. When the distribution of doped ions does not match the expectation, the performance and reliability of the device are severely affected. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a semiconductor structure, including:

[0005] A substrate, the top of the substrate has an ion-doped region, and the ion-doped region includes a first detection region and a second detection region that are exactly the same;

[0006] A first resistance detection structure, including:

[0007] A first blocking structure, the first detection region is completely covered by the first blocking structure;

[0008] A first electrode, used to obtain the first resistance of the first detection region;

[0009] A second resistance detection structure, including:

[0010] A second blocking structure, a part of the second detection region is covered by the second blocking structure, and an oxide layer is formed on the surface of another part of the second detection region;

[0011] A second electrode for obtaining a second resistance of the second detection region.

[0012] In one embodiment, a heat treatment process is performed on the first detection region and the second detection region to diffuse doping ions.

[0013] In one embodiment, when the first resistance is less than the second resistance, the doping ions have an oxidation-enhanced diffusion effect.

[0014] In one embodiment, a first process treatment is performed on the first resistance detection structure and the second resistance detection structure, and the second resistance has a first difference from the first resistance; a second process treatment is performed on the first resistance detection structure and the second resistance detection structure, and the second resistance has a second difference from the first resistance; when the second difference is greater than the first difference, the oxidation-enhanced diffusion index value of the second process treatment is greater than that of the first process treatment.

[0015] In one embodiment, the ion doping region includes an electrode lead-out region for leading out an electrode, and the ion doping concentration of the electrode lead-out region is greater than that of the ion doping region.

[0016] In one embodiment, the electrode lead-out region includes a first electrode lead-out region for leading out a first electrode, and the first electrode lead-out region is provided at both ends of the first detection region; the electrode lead-out region includes a second electrode lead-out region for leading out a second electrode, and the second electrode lead-out region is provided at both ends of the second detection region.

[0017] In one embodiment, the second blocking structure includes a plurality of sub-blocking structures arranged at intervals, the sizes of the plurality of sub-blocking structures are the same, and the spacing between adjacent sub-blocking structures is equal.

[0018] On the other hand, the present invention provides a method for manufacturing a semiconductor structure, including the following steps:

[0019] Provide a substrate and form an ion doping region on the top of the substrate;

[0020] Perform a first lithography process to form completely identical first blocking structures and transition blocking structures on the ion doping region respectively, the first blocking structures cover the first detection regions, and the transition blocking structures cover the second detection regions;

[0021] Perform a second lithography process to remove a part of the transition blocking structure to form a second blocking structure, exposing a part of the upper surface of the second detection region;

[0022] Form an oxide layer on the exposed upper surface of the second detection region;

[0023] Form a first electrode and a second electrode. The first electrode is used to obtain a first resistance of a first detection region, and the second electrode is used to obtain a second resistance of a second detection region.

[0024] In one embodiment, before forming the first electrode and the second electrode, it further includes: performing an ion implantation process to form an electrode lead-out region for leading out an electrode in an ion-doped region, and the ion doping concentration of the electrode lead-out region is greater than that of the ion-doped region.

[0025] In one embodiment, before obtaining the first resistance of the first detection region and the second resistance of the second detection region, it further includes: performing a heat treatment process on the first detection region and the second detection region to enable the doped ions to diffuse.

[0026] According to the semiconductor structure and its preparation method provided by the present invention, by forming a first resistance detection structure without an oxide layer and a second resistance detection structure with an oxide layer on the surface of the ion-doped region, and according to the difference in the measured resistance values of the two, the oxidation enhanced diffusion effect of the doped ions or the influence of different process steps on the oxidation enhanced diffusion effect of the doped ions is characterized, thereby improving the performance and reliability of the semiconductor structure. Description of the Drawings

[0027] To better describe and illustrate the embodiments and / or examples of those applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments and / or examples, and the currently understood best mode of these applications.

[0028] Figure 1 It is a schematic flow chart of a preparation method of a semiconductor structure provided in an embodiment;

[0029] Figure 2 It is a schematic cross-sectional structure diagram of the obtained structure after forming an ion-doped region in step S101 of the preparation method of the semiconductor structure provided in an embodiment;

[0030] Figure 3 It is a schematic cross-sectional structure diagram of the obtained structure after performing a first lithography process in step S102 of the preparation method of the semiconductor structure provided in an embodiment;

[0031] Figure 4 It is a schematic cross-sectional structure diagram of the obtained structure after performing a second lithography process in step S103 of the preparation method of the semiconductor structure provided in an embodiment;

[0032] Figure 5Schematic cross-sectional view of the structure obtained after performing an oxidation process in step S104 of the method for preparing a semiconductor structure provided in an embodiment;

[0033] Figure 6 Schematic cross-sectional view of the structure obtained after forming a first electrode and a second electrode in step S105 of the method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 7A Schematic cross-sectional view of the first resistance detection structure provided in an embodiment;

[0035] Figure 7B Schematic cross-sectional view of the second resistance detection structure provided in an embodiment;

[0036] Figure 8 Schematic diagram of the distribution of doped ions below the first barrier structure and the second barrier structure provided in an embodiment.

[0037] Description of reference numerals:

[0038] 200, substrate; 210, ion-doped region; 221, first barrier structure; 2220, transition barrier structure; 222, second barrier structure; 230, oxide layer; 241, first electrode; 242, second electrode. Detailed implementation manners

[0039] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of this application.

[0042] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of this application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0044] The embodiments of the present application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present application.

[0045] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0046] In view of the above problems, the present invention provides a method for manufacturing a semiconductor structure, as Figure 1 shown, including the following steps:

[0047] Step S101: Provide a substrate and form an ion-doped region on the top of the substrate;

[0048] Step S102: Perform a first lithography process to form identical first barrier structures and transition barrier structures on the ion-doped region respectively. The first barrier structure covers the first detection region, and the transition barrier structure covers the second detection region;

[0049] Step S103: Perform a second lithography process to remove a part of the transition barrier structure to form a second barrier structure, exposing a part of the upper surface of the second detection region;

[0050] Step S104: Form an oxide layer on the exposed upper surface of the second detection region;

[0051] Step S105: Form a first electrode and a second electrode. The first electrode is used to obtain the first resistance of the first detection region, and the second electrode is used to obtain the second resistance of the second detection region.

[0052] First, with reference to Figure 2 shown, perform Step S101 to provide a substrate 200 and form an ion-doped region 210 on the top of the substrate 200.

[0053] In one embodiment, the substrate 200 can be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0054] In one embodiment, the substrate 200 for forming the first resistance detection structure and the second resistance detection structure respectively may be the same substrate or two completely identical substrates, for example, two substrates obtained by processing two wafers of the same batch through the same process. For example, the substrate 200 is a P-type substrate.

[0055] In one embodiment, an ion implantation process is used to form an ion-doped region 210 on the top of the substrate 200. The doping ions for ion implantation can be N-type doping ions or P-type doping ions. Among them, the N-type doping ions include but are not limited to phosphorus ions, and the P-type doping ions include but are not limited to boron ions. The parameters of the ion implantation process, such as the ion implantation dose, ion implantation energy, and ion implantation angle, etc., can be set as needed and are not limited here.

[0056] Next, referring to Figure 3 as shown, step S102 is performed, and a first lithography process is performed to respectively form completely identical first barrier structures 221 and transition barrier structures 2220 on the ion-doped region 210. The first barrier structure 221 covers the first detection region, and the transition barrier structure 2220 covers the second detection region.

[0057] In one embodiment, when the substrate 200 for forming the first resistance detection structure and the second resistance detection structure respectively is the same substrate, first a barrier material layer is formed on the surface of the substrate 200. The barrier material layer includes but is not limited to a polysilicon layer, a silicon nitride layer, etc. It should be noted that the barrier material layer does not use an oxide material. The method for forming the barrier material layer can be chemical vapor deposition (CVD), such as one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). Next, a patterned mask layer is formed on the barrier material layer using a photomask. At least two regions with the same length and width are designed on the photomask so that the formed patterned mask layer includes two mask regions with the same length and width. Then, the barrier material layer is etched using the patterned mask layer as a mask to transfer the pattern of the mask layer to the barrier material layer, forming first barrier structures 221 and transition barrier structures 2220 with exactly the same length, width, and height. Specifically, the method for etching the barrier material layer includes an anisotropic dry etching process. The dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method can be used, or more than one etching method can also be used.

[0058] In one embodiment, when the substrates 200 for forming the first resistance detection structure and the second resistance detection structure respectively are two substrates, the first barrier structure 221 and the transition barrier structure 2220 can be formed on the surfaces of the two substrates in sequence. For example, first perform the following processing on the first substrate: form a barrier material layer on the substrate surface, and the barrier material layer includes but is not limited to a polysilicon layer, a silicon nitride layer, etc. It should be noted that the oxide material is not used for the barrier material layer. Next, use a photomask to form a patterned mask layer on the barrier material layer, and the formed patterned mask layer includes a mask region. Then, use the patterned mask layer as a mask to etch the barrier material layer to transfer the pattern of the mask layer to the barrier material layer, forming the first barrier structure 221. Then perform the same processing on the second substrate to form the transition barrier structure 2220 on the surface of the second substrate.

[0059] Next, refer to Figure 4 as shown, perform step S103, perform a second lithography process to remove a part of the transition barrier structure 2220 to form the second barrier structure 222, exposing a part of the upper surface of the second detection region.

[0060] In one embodiment, use a photomask to form a patterned mask layer on the transition barrier structure 2220. For example, at least multiple regions with the same length and width are designed on the photomask, so that the formed patterned mask layer includes multiple mask regions with the same length and width. Then, use the patterned mask layer as a mask to etch the transition barrier structure 2220 to transfer the pattern of the mask layer to the transition barrier structure 2220, forming the second barrier structure 222 composed of multiple sub-barrier structures. For the convenience of subsequent resistance measurement and analysis, the sizes of the multiple sub-barrier structures are the same, and the spacing between adjacent sub-barrier structures is equal.

[0061] Next, refer to Figure 5 as shown, perform step S104 to form an oxide layer 230 on the exposed upper surface of the second detection region. Further, before step S105, it also includes a heat treatment process for the first detection region and the second detection region to enable the diffusion of doped ions.

[0062] In one embodiment, a thermal oxidation process can be performed to promote the diffusion of doped ions while forming the oxide layer 230. Specifically, the thermal oxidation process is a dry oxygen oxidation process, or the thermal oxidation process includes a dry oxygen oxidation process performed first and a wet oxygen oxidation process performed later. The dry oxygen oxidation has a slow growth rate, but good denseness, strong impurity masking ability, and uniform growth. By first using dry oxygen oxidation and then using wet oxygen oxidation, the advantages of dry oxygen oxidation are retained, and the oxidation time is shortened.

[0063] In one embodiment, the formation of the oxide layer 230 and the promotion of the diffusion of doping ions through heat treatment can also be carried out in steps. For example, first, the oxide layer 230 is formed by a process familiar to those skilled in the art, such as chemical vapor deposition (CVD). Then, the process steps in the semiconductor manufacturing process are used as the heat treatment process to evaluate the influence of the process steps in the semiconductor manufacturing process on the enhanced diffusion effect of doping ions in oxidation.

[0064] Next, referring to Figure 6 As shown, step S105 is performed to form the first electrode 241 and the second electrode 242. The first electrode 241 is used to obtain the first resistance of the first detection region, and the second electrode 242 is used to obtain the second resistance of the second detection region. Further, before forming the first electrode and the second electrode, it also includes: performing an ion implantation process to form an electrode lead-out region for leading out the electrode in the ion doping region, and the ion doping concentration of the electrode lead-out region is greater than that of the ion doping region.

[0065] In one embodiment, an ion implantation process is used to form an electrode lead-out region in the ion doping region. The electrode lead-out region is usually arranged at both ends of the first detection region and the second detection region. The ions used to form the electrode lead-out region are usually the same as the doping ions in the ion doping region. For example, when the doping ions in the ion doping region are boron ions, the doping ions in the electrode lead-out region are also boron ions, and the boron ion concentration in the electrode lead-out region is much greater than that in the ion doping region. By forming an ion heavily doped electrode lead-out region in the ion doping region, the resistance of the electrode lead-out region can be reduced or even ignored, so as to reduce the influence of electrode lead-out on resistance measurement.

[0066] In one embodiment, first, an interlayer dielectric layer (not shown) covering the first barrier structure 221 and the second barrier structure 222 is formed. Through holes are formed in the interlayer dielectric layer to expose a part of the upper surface of the ion doping region. Ion implantation is performed on the exposed upper surface of the ion doping region through the through holes to form an electrode lead-out region. The ions implanted are the same as the doping ions in the ion doping region. The parameters of the ion implantation process, such as the ion implantation dose, ion implantation energy, and ion implantation angle, can be set as needed and are not limited here. A metal layer is deposited in the through holes to form an electrode. The materials of the electrode include, but are not limited to, conductive materials such as aluminum and copper. Physical vapor deposition, chemical vapor deposition, or atomic layer deposition and other process technologies familiar to those skilled in the art can be used to deposit the metal layer, which will not be elaborated here.

[0067] Through the above steps, first electrodes 241 are formed at both ends of the first detection region to obtain a first resistance of the first detection region; second electrodes 242 are formed at both ends of the second detection region to obtain a second resistance of the second detection region. When the substrate 200 for separately forming the first resistance detection structure and the second resistance detection structure is the same substrate, the first electrodes 241 and the second electrodes 242 are formed simultaneously, as Figure 6 shown. When the substrates 200 for separately forming the first resistance detection structure and the second resistance detection structure are two substrates, the first electrodes 241 and the second electrodes 242 can be separately formed by performing the same steps, as Figure 7A and Figure 7B shown.

[0068] So far, the introduction of the related steps of the preparation method of the semiconductor structure according to the embodiment of the present invention has been completed. It can be understood that the preparation method of the semiconductor structure in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of the present manufacturing method.

[0069] On the other hand, the present invention also provides a semiconductor structure, as Figure 6 or Figures 7A - 7B shown, including:

[0070] A substrate 200, on the top of which there is an ion-doped region 210, and the ion-doped region 210 includes completely identical first and second detection regions;

[0071] A first resistance detection structure, including:

[0072] A first blocking structure 221, and the first detection region is completely covered by the first blocking structure;

[0073] First electrodes 241 for obtaining a first resistance of the first detection region;

[0074] A second resistance detection structure, including:

[0075] A second blocking structure 222, a part of the second detection region is covered by the second blocking structure, and an oxide layer 230 is formed on the surface of another part of the second detection region;

[0076] Second electrodes 242 for obtaining a second resistance of the second detection region.

[0077] In one embodiment, the substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0078] In one embodiment, the substrate 200 for forming the first resistance detection structure and the second resistance detection structure respectively may be the same substrate or two completely identical substrates, for example, two substrates obtained by processing two wafers of the same batch through the same process. For example, the substrate 200 is a P-type substrate.

[0079] In one embodiment, the doping ions in the ion doping region 210 may be N-type doping ions or P-type doping ions. Among them, the N-type doping ions include but are not limited to phosphorus ions, and the P-type doping ions include but are not limited to boron ions. The ion doping region 210 includes a first detection region and a second detection region that are completely identical. Specifically, the lengths and widths of the first detection region and the second detection region are the same. The doping ions and doping concentrations of the first detection region and the second detection region are the same.

[0080] In one embodiment, the materials of the first blocking structure 221 and the second blocking structure 222 include but are not limited to polysilicon, silicon nitride, etc. It should be noted that the first blocking structure 221 and the second blocking structure 222 do not use oxide materials. The first blocking structure 221 completely covers the first detection region, and the length range of the first blocking structure includes 5 μm to 10 μm, such as 5 μm, 7.5 μm or 10 μm. The second blocking structure 222 is composed of multiple sub-blocking structures and covers a part of the second detection region. The sizes of the multiple sub-blocking structures are the same, the spacing between adjacent sub-blocking structures is equal, and the length range of the sub-blocking structure includes 0.3 μm to 0.8 μm, such as 0.3 μm, 0.5 μm or 0.8 μm.

[0081] In one embodiment, the oxide layer 230 includes but is not limited to silicon oxide, and the oxide layer 230 covers the surface of the spacing region in the second detection region that is not covered by the second blocking structure 222. By providing the oxide layer 230 on a part of the surface of the second detection region, an oxide is provided for the oxidation enhanced diffusion effect of the doping ions.

[0082] In one embodiment, first electrodes 241 are formed at both ends of the first detection region for obtaining the first resistance of the first detection region; second electrodes 242 are formed at both ends of the second detection region for obtaining the second resistance of the second detection region. The materials of the electrodes include but are not limited to conductive materials such as aluminum and copper.

[0083] In one embodiment, the ion doping region 210 further includes an electrode lead-out region, and the ion doping concentration of the electrode lead-out region is greater than the ion doping concentration of the ion doping region. Specifically, the first electrode lead-out region is used to lead out the first electrode 241, and the second electrode lead-out region is used to lead out the second electrode. By forming an ion heavily doped electrode lead-out region in the ion doping region, the resistance of the electrode lead-out region can be reduced or even ignored, so as to reduce the influence of electrode lead-out on resistance measurement.

[0084] In one embodiment, when the first resistance is less than the second resistance, it indicates that the doped ions have an oxidation-enhanced diffusion effect. For example, when the doped ions are X ions, by using a thermal oxidation process when forming the oxide layer 230 or performing a heat treatment process after forming the oxide layer 230, the X ions are diffused in the substrate 200. When the first resistance is less than the second resistance, it means that the presence of the oxide layer 230 promotes the diffusion of X ions in the substrate 200. Therefore, the X ions have an oxidation-enhanced diffusion effect.

[0085] In one embodiment, taking X ions as an example, along Figure 7A the distribution of X ions at the cross-section of the dashed line A-a in Figure 8 is shown by curve ① (red curve) in Figure 7B the distribution of X ions at the cross-section of the dashed line B-b in Figure 8 is shown by curve ② (green curve) in

[0086] In one embodiment, the first process treatment is performed on the first resistance detection structure and the second resistance detection structure, and the second resistance has a first difference from the first resistance; the second process treatment is performed on the first resistance detection structure and the second resistance detection structure, and the second resistance has a second difference from the first resistance; when the second difference is greater than the first difference, the oxidation-enhanced diffusion index value of the second process treatment is greater than that of the first process treatment. Specifically, taking the doped ions as X ions as an example, when two identical semiconductor structures use different process steps in the semiconductor manufacturing process as heat treatment processes respectively, for example, when the semiconductor structure is treated by the first process (such as an annealing process), the second resistance has a first difference R1 from the first resistance, and when the identical semiconductor structure is treated by the second process (such as a heating process), the second resistance has a second difference R2 from the first resistance. When R1 > R2, it indicates that the first process (such as an annealing process) has a more obvious effect on the oxidation-enhanced diffusion effect of X ions than the second process (such as a heating process), that is, the oxidation-enhanced diffusion index value of the second process treatment is greater than that of the first process treatment. Further, by comparing the magnitudes of the oxidation-enhanced diffusion index values of different process steps, the influence of each process step in the semiconductor manufacturing process on the oxidation-enhanced diffusion effect of the doped ions can be evaluated.

[0087] The specific structure of the semiconductor structure can be referred to the description in the corresponding part above. For the sake of brevity, it will not be elaborated here.

[0088] According to the semiconductor structure and its manufacturing method provided by the present invention, by forming a first resistance detection structure without an oxide layer and a second resistance detection structure with an oxide layer on the surface of the ion doping region, according to the difference in the measured resistance values of the two, the oxidation enhanced diffusion effect of the doping ions or the influence of different process steps on the oxidation enhanced diffusion effect of the doping ions is characterized, thereby improving the performance and reliability of the semiconductor structure.

[0089] Please note that the above embodiments are for illustrative purposes only and do not imply a limitation to this application.

[0090] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0091] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0092] The above-described embodiments only represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the top of the substrate has an ion-doped region, and the ion-doped region includes a first detection region and a second detection region that are completely identical; The first resistance detection structure includes: a first blocking structure, wherein the first detection area is completely covered by the first blocking structure; a first electrode, used to obtain a first resistance of the first detection area; The second resistance detection structure includes: The second blocking structure includes a plurality of adjacent sub-blocking structures formed by removing a portion of a transition blocking structure identical to the first blocking structure through a photolithography process, a portion of the second detection area is covered by the second blocking structure, and an oxide layer is formed on a surface of the second detection area exposed between the plurality of adjacent sub-blocking structures; a second electrode, used to obtain a second resistance of the second detection area; The semiconductor structure is used to: perform a heat treatment process on the first detection region and the second detection region to diffuse the doped ions, and when the first resistance is smaller than the second resistance, the doped ions have an oxidation-enhanced diffusion effect; The semiconductor structure is used to: perform a first process on the first resistor detection structure and the second resistor detection structure, and the second resistor has a first difference with the first resistor; perform a second process on the first resistor detection structure and the second resistor detection structure, and the second resistor has a second difference with the first resistor; when the second difference is greater than the first difference, the oxidation enhanced diffusion index value of the second process is greater than the oxidation enhanced diffusion index value of the first process.

2. The semiconductor structure according to claim 1, characterized in that: The first blocking structure and the transition blocking structure have the same length, width and height.

3. The semiconductor structure according to claim 1, characterized in that: The materials of the first barrier structure and the second barrier structure include at least one of polysilicon and silicon nitride, and the first barrier structure and the second barrier structure do not use oxide materials.

4. The semiconductor structure according to claim 1, characterized in that The substrate used to form the first resistance detection structure and the second resistance detection structure respectively is the same substrate, or two completely identical substrates.

5. The semiconductor structure according to claim 1, characterized in that: The ion doping region includes an electrode lead-out region, the electrode lead-out region is used to lead out an electrode, and the ion doping concentration of the electrode lead-out region is greater than the ion doping concentration of the ion doping region.

6. The semiconductor structure according to claim 5, characterized in that: The electrode lead-out area includes a first electrode lead-out area for leading out a first electrode, and the first electrode lead-out area is arranged at both ends of the first detection area; the electrode lead-out area includes a second electrode lead-out area for leading out a second electrode, and the second electrode lead-out area is arranged at both ends of the second detection area.

7. The semiconductor structure according to claim 1, characterized in that: The second blocking structure includes a plurality of sub-blocking structures that are spaced apart from each other. The plurality of sub-blocking structures have the same size and the intervals between adjacent sub-blocking structures are equal.

8. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, and forming an ion doping region on the top of the substrate; Performing a first photolithography process to form a completely identical first blocking structure and a transition blocking structure on the ion-doped region, respectively, wherein the first blocking structure covers the first detection region, and the transition blocking structure covers the second detection region; Performing a second photolithography process to remove a portion of the transition blocking structure to form a second blocking structure including a plurality of sub-blocking structures, wherein a portion of the upper surface of the second detection region is exposed between adjacent sub-blocking structures; forming an oxide layer on the exposed upper surface of the second detection area; forming a first electrode and a second electrode, wherein the first electrode is used to obtain a first resistance of the first detection area, and the second electrode is used to obtain a second resistance of the second detection area; The semiconductor structure is used to: perform a heat treatment process on the first detection region and the second detection region to diffuse the doped ions, and when the first resistance is smaller than the second resistance, the doped ions have an oxidation-enhanced diffusion effect; The semiconductor structure is used to: perform a first process on the first resistance detection structure and the second resistance detection structure, the second resistance having a first difference with the first resistance; Performing a second process on the first resistance detection structure and the second resistance detection structure, wherein the second resistance has a second difference with the first resistance; When the second difference is greater than the first difference, the oxidation enhanced diffusion index value of the second process is greater than the oxidation enhanced diffusion index value of the first process.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: Before forming the first electrode and the second electrode, the method further includes: An ion implantation process is performed to form an electrode lead-out region for leading out an electrode in the ion doping region, wherein the ion doping concentration of the electrode lead-out region is greater than the ion doping concentration of the ion doping region.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: A thermal oxidation process is used to promote diffusion of doping ions while forming the oxide layer. The thermal oxidation process includes a dry oxygen oxidation process performed first and a wet oxygen oxidation process performed later.

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