A backflow protection circuit and system for ESD

Abstract

The present application provides an anti-backflow ESD protection circuit and system, which relates to the field of ESD protection technology. The anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein the source and drain are shared between multiple MOS tubes. The anti-backflow ESD protection circuit and system provided by the present application have the advantage of reducing the layout area occupied while meeting the ESD requirements.

Description

Technical Field

[0001] The present application relates to the field of ESD protection technology, and in particular to an anti-backflow ESD protection circuit and system. Background Art

[0002] ESD (Electrostatic Discharge) is the main factor that causes most electronic devices or circuit systems to be damaged by excessive electrical stress. This damage can cause permanent damage to the integrated circuit, thus affecting the circuit function and causing the electronic product to malfunction. However, the generation of ESD is mostly caused by human or environmental factors, but it is difficult to completely avoid it. Therefore, in addition to strengthening the control of static electricity accumulation in the workplace, it is necessary to add a structure with ESD protection to the integrated circuit to ensure the safety of the integrated circuit in the case of ESD.

[0003] Furthermore, when a bus is shared between two or more electronic systems, when a chip is connected to the bus, the chip may lose power while the bus is still at a high level because the other system is powered on. If there is no ESD protection circuit to prevent backflow, the input and output interface will charge the chip power supply through the ESD protection device, which may cause damage to the chip itself and affect the bus equipment or the other party's electronic system, causing greater losses.

[0004] Therefore, when a bus is shared between two or more electronic systems, an ESD protection circuit is generally required to be provided. However, the current ESD protection circuit has the problem of occupying a large layout area. Summary of the invention

[0005] The purpose of the present application is to provide an ESD protection circuit and system to solve the problem that the ESD protection circuit in the prior art occupies a large layout area.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] On the one hand, an embodiment of the present application provides an ESD protection circuit for backflow prevention, wherein the ESD protection circuit for backflow prevention includes a plurality of MOS tubes and a plurality of resistors, wherein the plurality of MOS tubes are connected in parallel, the source and drain of each MOS tube are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein,

[0008] Multiple MOS tubes share a source and a drain.

[0009] Optionally, the fork index of each of the MOS tubes is an odd number, and the fork index of each of the MOS tubes is less than or equal to 5.

[0010] Optionally, when the fork index of each MOS tube is the same, the multiple resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to twice the resistance of the first resistor, and N is the number of MOS tubes; wherein,

[0011] The sources or drains of two adjacent MOS tubes share a first resistor, and the sources or drains of the first MOS tube and the last MOS tube are connected to the second resistor.

[0012] Optionally, when the number of the MOS tubes is an odd number, the source of the first MOS tube is connected to the second resistor, and connected to the first port through the second resistor;

[0013] The drain of the last MOS tube is connected to the second resistor, and is connected to the second port through the second resistor;

[0014] The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0015] Optionally, in the case where the fork indexes of the plurality of MOS tubes are different, when the number of the MOS tubes is an odd number, the plurality of MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the plurality of resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to the resistance of the first resistor*(M1+M2) / M3, N is the total number of MOS tubes, M1 and M2 represent the fork indexes of the first MOS tube and the second MOS tube respectively, and M3 represents the fork index of the first MOS tube; wherein,

[0016] The sources or drains of two adjacent MOS tubes share a first resistor, and the sources or drains of the first MOS tube and the last MOS tube are connected to the second resistor.

[0017] Optionally, the source of the first MOS tube is connected to the second resistor, and is connected to the first port through the second resistor;

[0018] The drain of the last MOS tube is connected to the second resistor, and is connected to the second port through the second resistor;

[0019] The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0020] Optionally, in the case where the fork indexes of the plurality of MOS tubes are different, when the number of the MOS tubes is an even number, the plurality of MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the plurality of resistors include N-1 first resistors, a third resistor and a fourth resistor, the resistance value of the third resistor is equal to the resistance value of the first resistor*(M1+M2) / M3, the resistance value of the fourth resistor is equal to the resistance value of the first resistor*(M1+M2) / M4, N is the total number of MOS tubes, M1 and M2 represent the fork indexes of the first MOS tube and the second MOS tube respectively, M3 represents the fork index of the first MOS tube, and M4 represents the fork index of the last MOS tube; wherein,

[0021] The sources or drains of two adjacent MOS tubes share a first resistor, the source or drain of the first MOS tube is connected to the third resistor, and the source or drain of the last MOS tube is connected to the fourth resistor.

[0022] Optionally, the source of the first MOS tube is connected to the third resistor, and is connected to the first port through the third resistor;

[0023] The source of the last MOS tube is connected to the fourth resistor, and is connected to the first port through the fourth resistor;

[0024] The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0025] Optionally, the plurality of MOS transistors are formed by adopting an interdigitated electrode structure.

[0026] On the other hand, an embodiment of the present application further provides an anti-backflow ESD protection system, which includes a first module, a second module and the above-mentioned anti-backflow ESD protection circuit, and the anti-backflow ESD protection circuit is connected to the first module and the second module respectively.

[0027] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0028] The embodiment of the present application provides an anti-backflow ESD protection circuit and system, the anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein, the source and drain are shared between multiple MOS tubes. On the one hand, since the source or drain of two adjacent MOS tubes share the same resistor, the total number of resistors in the entire anti-backflow ESD protection circuit is reduced, thereby reducing the layout area occupied by the resistors. On the other hand, since the source and drain are shared between multiple MOS tubes, the layout area occupied by the MOS tube of the entire anti-backflow ESD protection circuit is also reduced. It can be seen that the anti-backflow ESD protection circuit provided by the present application simultaneously reduces the occupied area of ​​the resistor and the MOS tube, thereby making the occupied layout area of ​​the entire anti-backflow ESD protection circuit smaller.

[0029] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 The figure is a circuit diagram of an anti-backflow ESD protection circuit in the prior art.

[0032] Figure 2 Another circuit diagram of an anti-backflow ESD protection circuit in the prior art.

[0033] Figure 3 The figure is a schematic diagram of the layout of the switch tube in the anti-backflow ESD protection circuit in the prior art.

[0034] Figure 4 A first schematic diagram of an anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0035] Figure 5 A schematic diagram of the layout of a MOS tube in an anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0036] Figure 6 A second schematic diagram of the anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0037] Figure 7A third schematic diagram of the anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0038] Figure 8 A fourth circuit diagram of the anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0039] Fig. 9 Another schematic diagram of the layout of the MOS tube in the anti-backflow ESD protection circuit provided in the embodiment of the present application.

[0040] Fig.10 A fifth schematic diagram of the anti-backflow ESD protection circuit provided in an embodiment of the present application.

[0041] Fig.11 A sixth schematic diagram of the anti-backflow ESD protection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0044] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0045] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0046] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0047] As described in the background art, currently, when a bus is shared between two or more electronic systems, an ESD protection circuit needs to be provided. However, the current ESD protection circuit occupies a large layout area.

[0048] For example, see Figure 1 , is a schematic diagram of a shared bus between two electronic systems in the prior art, wherein IO1 and IO2 are interfaces of the two electronic systems, respectively. For example, IO1 represents the input and output interface of chip A, and IO2 represents the input and output interface of chip B, and the two are connected through the switch tube Q1. When the switch tube Q1 is turned on, chip A and chip B are connected through the bus; when the switch tube Q1 is turned off, chip A and chip B are disconnected, thereby achieving the anti-backflow requirement. That is, when chip A loses power, the switch tube Q1 is turned off. At this time, even if chip B is still in a high level state, it will not affect chip A, thereby achieving the anti-backflow function. Similarly, when chip B loses power, the switch tube Q1 is turned off, so that chip B will not be affected by chip A.

[0049] In addition, in order to achieve ESD protection for IO1 and IO2, it is usually necessary to set up ESD protection tubes Q2 and Q3. Among them, ESD protection tubes Q2 and Q3 generally use GGNMOS (Gate-Grounded NMOS, gate-grounded NMOS devices). GGNMOS consists of an NMOS transistor, whose source (Source) is connected to the ground (VSS), the gate (Gate) is grounded, and the drain (Drain) is connected to the input and output interface. When the IO port is hit by ESD, GGNMOS will start the path to discharge the ESD current to achieve the ESD protection function.

[0050] At the same time, when ESD exists between IO1 and IO2, the ESD current will pass through the switch tube Q1. Therefore, the switch tube Q1 also needs to have the ability to pass the ESD current, otherwise it is easy to be damaged. At present, in one implementation, the switch tube Q1 uses a specific ESD tube instead of an ordinary switch tube to achieve the function of passing the ESD current.

[0051] However, compared with ordinary switching tubes, the area of ​​ESD tubes is larger. Therefore, achieving the function of passing ESD current in this way will cause the chip layout to occupy a larger area. Generally, the area of ​​​​the ESD tube will increase by more than 3 times.

[0052] To save area, in another implementation, see Figure 2, the switch tube Q1 can also use an ordinary switch tube, but in order to reduce the ESD current when it is impacted by ESD, resistors are connected in series at both ends of the switch tube Q1 to achieve the effect of preventing ESD impact. However, since the resistance is too large, it will affect the switch impedance from IO1 to IO2, so it is necessary to set up multiple switch tube strings, and multiple switch tube strings are connected in parallel, and each switch tube string includes a switch tube Q1 and two resistors, and the two resistors are connected in series with the source and drain of the switch tube Q1 respectively.

[0053] With this configuration, when subjected to ESD shock, the ESD current flowing through each switch tube string is small. Since the total impedance of multiple switch tube strings connected in parallel is low, the switch impedance from IO1 to IO2 will not be affected, that is, the normal communication between IO1 and IO2 will not be affected.

[0054] Although this method does not require the use of specific ESD tubes, it still occupies a large layout area because resistors need to be added to each switch tube string. For example, if the number of switch tube strings is 6, 12 resistors need to be added. The introduction of more resistors increases the occupied layout area. Figure 3 Since resistors need to be referenced at both ends of each switch tube Q1, each switch tube also needs to be independently laid out on the layout, further increasing the layout area occupied.

[0055] Therefore, there is a problem in the prior art that the layout of the anti-backflow ESD protection circuit occupies a large area. In view of this, in order to solve the above problem, the present application provides an anti-backflow ESD protection circuit. The anti-backflow ESD protection circuit provided by the present application is exemplarily described below:

[0056] As an implementation, see Figure 4 The anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors. The multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein the multiple MOS tubes share the source and drain.

[0057] On the one hand, since the source or drain of two adjacent MOS tubes share the same resistor, the total number of resistors in the entire anti-backflow ESD protection circuit is reduced, thereby reducing the layout area occupied by the resistors. Figure 5 Since multiple MOS tubes share the source and drain, the layout area occupied by the MOS tubes of the entire anti-backflow ESD protection circuit is also reduced. It can be seen that the anti-backflow ESD protection circuit provided by the present application reduces the occupied area of ​​both the resistor and the MOS tube, thereby making the occupied layout area of ​​the entire anti-backflow ESD protection circuit smaller.

[0058] Through the above implementation, the MOS tube in the anti-backflow ESD protection circuit can be used as follows Figure 5 The interdigitated electrode structure shown is formed, thereby achieving source-drain sharing. Figure 4 In the figure, F=1 indicates that the fork index of each MOS tube is 1. The fork index of a MOS tube refers to the number of channels included in the MOS tube. The larger the fork index of a MOS tube, the more channels the MOS tube occupies. For example, if the fork index of a MOS tube is 3, it means that the number of channels occupied by the MOS tube is 3, and accordingly, the number of gates is also 3.

[0059] It should be noted that when the fork index of the MOS tube is larger, it means that the MOS tube occupies more channels, which is equivalent to combining multiple MOS tubes into one MOS tube, so that the number of resistors can be reduced, but at the same time, the effect of ESD protection will be reduced. In view of this, in the anti-backflow ESD protection circuit provided by the present application, the fork index of each MOS tube is less than or equal to 5. In addition, the fork index of each MOS tube is an odd number.

[0060] In one implementation, the cross index of each MOS tube is the same, the multiple resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to twice the resistance of the first resistor, and N is the number of MOS tubes; wherein the source or drain of two adjacent MOS tubes shares a first resistor, and the source or drain of the first MOS tube and the last MOS tube are connected to the second resistor.

[0061] On this basis, when the number of MOS tubes is an odd number, the source of the first MOS tube is connected to the second resistor and connected to the first port through the second resistor; the drain of the last MOS tube is connected to the second resistor and connected to the second port through the second resistor; the sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0062] For example, see Figure 6 , Figure 6 The figure shows that the cross index of each MOS tube is 3 and the total number of MOS tubes is 3. Of course, in practical applications, the number of MOS tubes and the cross index may also vary. For example, the number of MOS tubes is 7 and the cross index of each MOS tube is 5. This is not limited here. Figure 6As shown, the entire circuit includes a first MOS tube Q11, a second MOS tube Q12 and a third MOS tube Q13, the first MOS tube Q11 is adjacent to the second MOS tube Q12, and the second MOS tube Q12 is adjacent to the third MOS tube Q13. Therefore, the number of first resistors is N-1=3-1=2, the number of second resistors is two, and the resistance of the first resistor is R, and the resistance of the second resistor is 2R. The source of the first MOS tube Q11 is connected to the second resistor, and is connected to the first port IO1 through the second resistor; the drain of the third MOS tube Q13 is connected to the second resistor, and is connected to the second port IO2 through the second resistor; the source of the second MOS tube Q12 and the source of the third MOS tube Q13 are both connected to the first port through the first resistor, and the drain of the second MOS tube Q12 and the drain of the first MOS tube Q11 are both connected to the second port through the first resistor. The source of the second MOS tube Q12 and the source of the third MOS tube Q13 can share the same resistor, and the drain of the second MOS tube Q12 and the drain of the first MOS tube Q11 can also share the same resistor, thereby reducing the number of resistors. In addition, the first port and the second port of the present application can be connected to different chips or different electronic systems, which is not limited here.

[0063] At the same time, multiple MOS tubes can be Figure 5 The forked finger structure is used to realize source-drain sharing and reduce the layout area occupied by the entire MOS tube.

[0064] For the sake of convenience, this application is described with the number of MOS tubes in the prior art being 12. Figure 2 In the prior art, 12 MOS tubes and 24 resistors are required. In this application, please combine Figure 4 If F=1, 12 MOS tubes and 13 resistors are required; if F=3, 4 MOS tubes and 5 resistors are required, which greatly reduces the number of MOS tubes and resistors. At the same time, the source and drain of the MOS tube can be shared, reducing the layout area of ​​the entire anti-backflow ESD protection circuit.

[0065] When the number of MOS tubes is even, please refer to Figure 7 , the source of the first MOS tube is connected to the second resistor and connected to the first port through the second resistor; the source of the last MOS tube is connected to the second resistor and connected to the first port through the second resistor; the sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the second resistor.

[0066] As another implementation, see Figure 8 , the cross indexes of multiple MOS tubes can also be different. Similarly, please refer to Fig. 9In this implementation mode, the source and drain of the MOS tube can also be shared, thereby reducing the layout area occupied by the entire circuit.

[0067] On this basis, when the number of MOS tubes is an odd number, the multiple MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the multiple resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to the resistance of the first resistor*(M1+M2) / M3, N is the total number of MOS tubes, M1 and M2 represent the cross index of the first MOS tube and the second MOS tube respectively, and M3 represents the cross index of the first MOS tube; wherein the source or drain of two adjacent MOS tubes shares a first resistor, and the source or drain of the first MOS tube and the last MOS tube is connected to the second resistor.

[0068] Among them, the source of the first MOS tube is connected to the second resistor and connected to the first port through the second resistor; the drain of the last MOS tube is connected to the second resistor and connected to the second port through the second resistor; the sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0069] See also Fig.10 , the cross indexes of the multiple MOS tubes are not the same, and the cross index of the first MOS tube is 1, and the cross index of the second MOS tube is 3. At this time, the resistance value of the second resistor is equal to the resistance value of the first resistor * 4. The source of the first MOS tube is connected to the second resistor and connected to the first port through the second resistor; the drain of the last MOS tube is connected to the second resistor and connected to the second port through the second resistor.

[0070] When the number of MOS tubes is an even number, the multiple MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the multiple resistors include N-1 first resistors, a third resistor and a fourth resistor, the resistance value of the third resistor is equal to the resistance value of the first resistor*(M1+M2) / M3, the resistance value of the fourth resistor is equal to the resistance value of the first resistor*(M1+M2) / M4, N is the total number of MOS tubes, M1 and M2 represent the fork indexes of the first MOS tube and the second MOS tube respectively, M3 represents the fork index of the first MOS tube, and M4 represents the fork index of the last MOS tube.

[0071] The source or drain of two adjacent MOS tubes shares a first resistor, and the source or drain of the first MOS tube is connected to the third resistor, and the source or drain of the last MOS tube is connected to the fourth resistor. The source of the first MOS tube is connected to the third resistor and connected to the first port through the third resistor; the source of the last MOS tube is connected to the fourth resistor and connected to the first port through the fourth resistor; the sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

[0072] For example, see Fig.11 When the cross index of the first MOS tube is 1, the cross index of the second MOS tube is 3, and the total number of MOS is 4, the resistance of the first resistor is R, the resistance of the third resistor is 4R, and the resistance of the fourth resistor is 4R / 3.

[0073] Therefore, the present application reduces the number of MOS tubes and resistors by changing the connection relationship between the MOS tubes and the resistors, and at the same time realizes the source and drain sharing of the MOS tubes, thereby reducing the layout area occupied by the circuit and achieving miniaturization.

[0074] Based on the above implementation, an embodiment of the present application also provides an anti-backflow ESD protection system, which includes a first module, a second module and the above-mentioned anti-backflow ESD protection circuit, and the anti-backflow ESD protection circuit is connected to the first module and the second module respectively. Wherein, the first module and the second module are two electronic systems or circuits sharing a bus, and the first module and the second module are connected through the anti-backflow ESD protection circuit, thereby realizing anti-backflow and ESD protection. For example, the first module is an electronic system X, and the second module is an electronic system Y, and the input and output interfaces of the electronic system X and the electronic system Y are connected to the anti-backflow ESD protection circuit.

[0075] In summary, the embodiment of the present application provides an anti-backflow ESD protection circuit and system, the anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein, the source and drain are shared between multiple MOS tubes. On the one hand, since the source or drain of two adjacent MOS tubes share the same resistor, the total number of resistors in the entire anti-backflow ESD protection circuit is reduced, thereby reducing the layout area occupied by the resistors. On the other hand, since the source and drain are shared between multiple MOS tubes, the layout area occupied by the MOS tube of the entire anti-backflow ESD protection circuit is also reduced. It can be seen that the anti-backflow ESD protection circuit provided by the present application simultaneously reduces the occupied area of ​​the resistor and the MOS tube, thereby making the occupied layout area of ​​the entire anti-backflow ESD protection circuit smaller.

[0076] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0077] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An anti-backflow ESD protection circuit, characterized in that: The anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, the multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein the multiple MOS tubes share the source and drain; When the cross index of each MOS tube is the same, the multiple resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to twice the resistance of the first resistor, and N is the number of MOS tubes; wherein, The sources or drains of two adjacent MOS tubes share a first resistor, and the sources or drains of the first MOS tube and the last MOS tube are connected to the second resistor; When the number of the MOS tubes is an odd number, the source of the first MOS tube is connected to the second resistor, and connected to the first port through the second resistor; The drain of the last MOS tube is connected to the second resistor, and is connected to the second port through the second resistor; The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

2. The ESD protection circuit for backflow prevention according to claim 1, characterized in that: The fork index of each of the MOS tubes is an odd number, and the fork index of each of the MOS tubes is less than or equal to 5.

3. The ESD protection circuit for backflow prevention according to claim 1, characterized in that: The plurality of MOS tubes are formed by adopting an interdigital electrode structure.

4. An anti-backflow ESD protection circuit, characterized in that: The anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, the multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein the multiple MOS tubes share the source and drain; In the case where the fork indexes of the plurality of MOS tubes are different, when the number of the MOS tubes is an odd number, the plurality of MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the plurality of resistors include N-1 first resistors and 2 second resistors, the resistance of the second resistor is equal to the resistance of the first resistor * (M1+M2) / M3, N is the total number of MOS tubes, M1 and M2 represent the fork indexes of the first MOS tube and the second MOS tube respectively, and M3 represents the fork index of the first MOS tube; wherein, The sources or drains of two adjacent MOS tubes share a first resistor, and the sources or drains of the first MOS tube and the last MOS tube are connected to the second resistor; The source of the first MOS tube is connected to the second resistor, and is connected to the first port through the second resistor; The drain of the last MOS tube is connected to the second resistor, and is connected to the second port through the second resistor; The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

5. The ESD protection circuit for backflow prevention according to claim 4, characterized in that: The fork index of each of the MOS tubes is an odd number, and the fork index of each of the MOS tubes is less than or equal to 5.

6. The ESD protection circuit for backflow prevention according to claim 4, characterized in that: The plurality of MOS tubes are formed by adopting an interdigital electrode structure.

7. An anti-backflow ESD protection circuit, characterized in that: The anti-backflow ESD protection circuit includes multiple MOS tubes and multiple resistors, the multiple MOS tubes are connected in parallel, the source and drain of each MOS are connected to a resistor, and the source or drain of two adjacent MOS tubes share the same resistor; wherein the multiple MOS tubes share the source and drain; In the case where the fork indexes of the plurality of MOS tubes are different, when the number of the MOS tubes is an even number, the plurality of MOS tubes include a first MOS tube and a second MOS tube, and the first MOS tube and the second MOS tube are arranged alternately; the plurality of resistors include N-1 first resistors, a third resistor and a fourth resistor, the resistance value of the third resistor is equal to the resistance value of the first resistor * (M1+M2) / M3, the resistance value of the fourth resistor is equal to the resistance value of the first resistor * (M1+M2) / M4, N is the total number of MOS tubes, M1 and M2 represent the fork indexes of the first MOS tube and the second MOS tube respectively, M3 represents the fork index of the first MOS tube, and M4 represents the fork index of the last MOS tube; wherein, The source or drain of two adjacent MOS tubes shares a first resistor, the source or drain of the first MOS tube is connected to the third resistor, and the source or drain of the last MOS tube is connected to the fourth resistor; The source of the first MOS tube is connected to the third resistor, and is connected to the first port through the third resistor; The source of the last MOS tube is connected to the fourth resistor, and is connected to the first port through the fourth resistor; The sources of the remaining MOS tubes are all connected to the first port through the first resistor, and the drains are all connected to the second port through the first resistor.

8. The ESD protection circuit for backflow prevention according to claim 7, characterized in that: The fork index of each of the MOS tubes is an odd number, and the fork index of each of the MOS tubes is less than or equal to 5.

9. The ESD protection circuit for backflow prevention according to claim 7, characterized in that: The plurality of MOS tubes are formed by adopting an interdigital electrode structure.

10. An anti-backflow ESD protection system, characterized in that: The anti-backflow ESD protection system comprises a first module, a second module and an anti-backflow ESD protection circuit according to any one of claims 1 to 9, and the anti-backflow ESD protection circuit is connected to the first module and the second module respectively.

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