Direct-current bias suppression device and method for dual-active bridge and dual-active bridge system

Abstract

The invention relates to a direct current bias suppression device and method for a dual-active bridge and a dual-active bridge system, and the device comprises a high-frequency signal detection module which receives the primary side current and the secondary side current of a high-frequency transformer in the dual-active bridge, converts the primary side current and the secondary side current into voltage signals, and outputs the voltage signals to a control module; obtaining a primary side current detection signal and a secondary side current detection signal; the peak value detection module is used for detecting the maximum value and the minimum value of the primary side current in the primary side current detection signal and the maximum value and the minimum value of the secondary side current in the secondary side current detection signal; the sampling module is used for sampling the maximum value and the minimum value of the primary side current and the maximum value and the minimum value of the secondary side current; the control module is used for calculating the difference value between the sum value of the maximum value and the minimum value of the primary side current and zero and the difference value between the sum value of the maximum value and the minimum value of the secondary side current and zero, and obtaining the duty ratio adjustment amount of the primary side and the duty ratio adjustment amount of the secondary side by using the PI controller; and the direct-current bias current on the two sides of the dual-active bridge is suppressed according to the duty ratio adjustment amount.

Description

Technical Field

[0001] The present application relates to the field of direct current conversion technology, and in particular to a direct current bias suppression device and method for a dual active bridge, and a dual active bridge system. Background Art

[0002] The dual active bridge (DAB) converter plays a vital role in the new energy system, but its performance is also affected by the DC bias problem. DC bias is mainly divided into two types: steady-state DC bias and transient DC bias. Steady-state DC bias is usually caused by the asymmetry of circuit and switch parameters, while transient DC bias is caused by the update of the phase shift ratio. These bias phenomena will lead to increased magnetic circuit losses, increased switching element losses, and even saturation of magnetic components, affecting the stability and reliability of the entire system.

[0003] Conventional DAB devices use a DC blocking capacitor in series in the primary and secondary high-frequency circuits to suppress the DC current bias of the primary and secondary sides, thereby suppressing the transformer bias. However, at higher power, most capacitors on the market are difficult to meet the working conditions of high frequency and high current. Even if they meet the requirements, the size of the DC blocking capacitor is large, which will reduce the power density of the device. Therefore, it is hoped that a control method can be used to suppress the bias.

[0004] Conventional control methods use the controller's analog-to-digital converter ADC (Analog-to-Digital Converter) to sample and calculate the detected high-frequency current signal. However, the frequency of DAB's high-frequency current is too high, and extracting a small DC bias from a large current requires high precision, which poses a great challenge to the sampling frequency and precision of the DSP (Digital Signal Processor), and also places high requirements on the performance of the sensor and conditioning circuit. Summary of the invention

[0005] The present application provides a DC bias suppression device, method and dual active bridge system for a dual active bridge, so as to solve the problems that the primary and secondary sides of a dual active bridge (DAB) device have steady-state and transient DC biases, the conventional DC blocking capacitors are difficult to withstand the high current requirements of a high-power DAB device and occupy a large space, and the high-frequency current is difficult to sample.

[0006] The first aspect of the present application provides a DC bias suppression device for a dual active bridge, comprising: a high-frequency signal detection module, used to receive the primary current and the secondary current of the high-frequency transformer in the dual active bridge, and convert the primary current and the secondary current into voltage signals respectively, to obtain the primary current detection signal and the secondary current detection signal; a peak detection module, used to receive the primary current detection signal and the secondary current detection signal, and based on the primary current detection signal and the secondary current detection signal, respectively detect the maximum value and the minimum value of the primary current and the maximum value of the secondary current and minimum value; a sampling module, used to sample the maximum value and minimum value of the primary current and the maximum value and minimum value of the secondary current output by the peak detection circuit according to a preset sampling strategy; a control module, used to calculate the difference between the sum of the maximum value and the minimum value of the primary current and zero, and calculate the difference between the sum of the maximum value and the minimum value of the secondary current and zero, and use a preset PI controller to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and adjust the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0007] Optionally, the peak detection module includes: an upper peak detection circuit, which is used to detect the maximum value of the primary current of the dual active bridge medium and high frequency transformer and the maximum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle; and a lower peak detection circuit, which is connected to the upper peak detection circuit and is used to detect the minimum value of the primary current of the dual active bridge medium and high frequency transformer and the minimum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle.

[0008] Optionally, the upper peak detection circuit includes: a first resistor, a first-stage amplifier, a second resistor, a first diode, a second diode, a first voltage follower, a third resistor, a fourth resistor, a first capacitor and a first RST reset element, wherein the in-phase input terminal of the first-stage amplifier is connected to one end of the first resistor for receiving the high-frequency current detection signal, the inverting input terminal of the first-stage amplifier is connected to the anode of the second diode and one end of the second resistor, the output terminal of the first-stage amplifier is respectively connected to the cathode of the second diode and the anode of the first diode, the cathode of the first diode is connected to one end of the third resistor, the in-phase input terminal of the first voltage follower is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor, the inverting input terminal of the first voltage follower is connected to the other end of the second resistor, the output terminal of the first voltage follower is connected to the inverting input terminal, the other end of the first capacitor is grounded, the input terminal of the first RST reset element is connected to the other end of the fourth resistor, and the output terminal and the ground terminal of the first RST reset element are both connected to the other end of the first capacitor and grounded.

[0009] Optionally, the lower peak detection circuit includes: a fifth resistor, a second-stage amplifier, a sixth resistor, a third diode, a fourth diode, a second voltage follower, a seventh resistor, an eighth resistor, a second capacitor and a second RST reset element, wherein the in-phase input terminal of the second-stage amplifier is connected to one end of the fifth resistor for receiving the high-frequency current detection signal, the other end of the fifth resistor is connected to the other end of the first resistor, the inverting input terminal of the second-stage amplifier is connected to the cathode of the fourth diode and one end of the sixth resistor, the output terminal of the second-stage amplifier is respectively connected to the anode of the fourth diode and the cathode of the third diode, the anode of the third diode is connected to one end of the seventh resistor, the in-phase input terminal of the second voltage follower is connected to the other end of the seventh resistor, one end of the eighth resistor and one end of the second capacitor, the inverting input terminal of the second voltage follower is connected to the other end of the sixth resistor, the output terminal of the second voltage follower is connected to the inverting input terminal, the other end of the second capacitor is grounded, the input terminal of the second RST reset element is connected to the other end of the eighth resistor, and the output terminal and the ground terminal of the second RST reset element are both connected to the other end of the second capacitor and grounded.

[0010] Optionally, the control module includes: a calculation submodule, used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero.

[0011] Optionally, the control module also includes: a PI control submodule connected to the calculation submodule, the PI control submodule including a first PI controller and a second PI controller, which is used to input the difference between the sum of the primary currents of the dual active bridge medium and high frequency transformer and zero into the first PI controller to obtain the duty cycle adjustment amount on the primary side, and input the difference between the sum of the secondary currents of the dual active bridge medium and high frequency transformer and zero into the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

[0012] Optionally, the high-frequency signal detection module includes: a current sensor and a sampling resistor, wherein the current sensor is used to convert the primary current and the secondary current into a small signal current, and the sampling resistor is used to convert the small signal current into a voltage signal.

[0013] The second aspect of the present application provides a DC bias suppression method for a dual active bridge, comprising the following steps: receiving the primary current and the secondary current of the dual active bridge medium and high frequency transformer, and converting the primary current and the secondary current into voltage signals respectively to obtain the primary current detection signal and the secondary current detection signal; receiving the primary current detection signal and the secondary current detection signal, and detecting the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current based on the primary current detection signal and the secondary current detection signal respectively; sampling the peak detection circuit output according to a preset sampling strategy; The maximum value and minimum value of the primary current of the dual active bridge medium and high frequency transformer and the maximum value and minimum value of the secondary current of the dual active bridge medium and high frequency transformer are sampled; the difference between the sum of the maximum value and the minimum value of the primary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the difference between the sum of the maximum value and the minimum value of the secondary current of the dual active bridge medium and high frequency transformer and zero is calculated, and a preset PI controller is used to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0014] A third aspect of the present application provides a dual active bridge system, which includes the above-mentioned DC bias suppression device for the dual active bridge.

[0015] In the above implementation, the primary current and the secondary current of the high frequency transformer in the dual active bridge are received by the high frequency signal detection module, and the primary current and the secondary current are respectively converted into voltage signals to obtain the primary current detection signal and the secondary current detection signal, the primary current detection signal and the secondary current detection signal are received by the peak detection module, and the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current are respectively detected based on the primary current detection signal and the secondary current detection signal, and the maximum value and the minimum value of the primary current output by the peak detection circuit and the maximum value and the minimum value of the secondary current are sampled by the sampling module according to the preset sampling strategy, the difference between the sum of the maximum value and the minimum value of the primary current and zero and the difference between the sum of the maximum value and the minimum value of the secondary current and zero are calculated by the control module, and the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side are obtained by using the preset PI controller, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit are adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. As a result, the problems of steady-state and transient DC bias on the primary and secondary sides of the dual active bridge DAB device, the difficulty of traditional DC blocking capacitors in meeting the large current requirements of high-power DAB devices and the large space they occupy, and the difficulty in sampling high-frequency currents, are solved. The sampling frequency and accuracy requirements for ADC and the calculation speed requirements for DSP are reduced, and the DC blocking capacitors can be replaced at a low cost and better, thereby improving power density and achieving the purpose of suppressing the DC bias of the primary and secondary sides respectively.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 It is a schematic diagram of a non-resonant DAB topology structure in the related art;

[0019] Figure 2 A schematic diagram of the relationship between the DAB inductor voltage and current waveform and the bridge arm voltage during single phase shift modulation in the related art;

[0020] Figure 3 A schematic diagram of a DC bias caused by a primary side duty cycle deviation in the related art;

[0021] Figure 4 A schematic diagram of a DC bias caused by a positive voltage deviation on the primary side in the related art;

[0022] Figure 5 A schematic diagram of a DC bias caused by an increase in the shift phase in the related art;

[0023] Figure 6 A schematic diagram of a non-resonant DAB topology structure with a DC blocking capacitor in series in the related art;

[0024] Figure 7 is a schematic diagram of a DC bias suppression device for a dual active bridge according to an embodiment of the present application;

[0025] Figure 8 Schematic diagram of an upper and lower peak detection circuit according to an embodiment of the present application;

[0026] Fig. 9 A schematic diagram of the upper and lower peak detection circuit simulation waveform verification according to an embodiment of the present application;

[0027] Fig.10 A schematic diagram of a flow chart of DC bias suppression of a dual active bridge according to an embodiment of the present application;

[0028] Fig.11 Schematic block diagram of DC bias suppression of a dual active bridge according to an embodiment of the present application;

[0029] Fig.12 A schematic diagram of changes in primary DC bias current according to various methods of one embodiment of the present application;

[0030] Fig.13 The present invention is a flowchart of a DC bias suppression method for a dual active bridge according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0032] The following describes a DC bias suppression device, method and dual active bridge system for a dual active bridge according to an embodiment of the present application with reference to the accompanying drawings. In view of the problem that the primary and secondary sides of the dual active bridge DAB device mentioned in the above background technology have steady-state and transient DC biases, the traditional DC blocking capacitors are difficult to meet the high current requirements of high-power DAB devices and occupy a large space, and high-frequency currents are difficult to sample, the present application provides a DC bias suppression device for a dual active bridge, in which the primary current and secondary current of the high-frequency transformer in the dual active bridge are received by a high-frequency signal detection module, and the primary current and secondary current are respectively converted into voltage signals to obtain a primary current detection signal and a secondary current detection signal, the primary current detection signal and the secondary current detection signal are received by a peak detection module, and based on the primary current detection signal, the secondary current detection signal is obtained. The signal and the secondary current detection signal respectively detect the maximum value and minimum value of the primary current and the maximum value and minimum value of the secondary current, and the maximum value and minimum value of the primary current output by the peak detection circuit and the maximum value and minimum value of the secondary current are sampled by the sampling module according to the preset sampling strategy, and the difference between the sum of the maximum value and the minimum value of the primary current and zero and the difference between the sum of the maximum value and the minimum value of the secondary current and zero are calculated by the control module, and the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side are obtained by using the preset PI controller, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit are adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. As a result, the problems of steady-state and transient DC bias on the primary and secondary sides of the dual active bridge DAB device, the difficulty of traditional DC blocking capacitors in meeting the large current requirements of high-power DAB devices and the large space they occupy, and the difficulty in sampling high-frequency currents, are solved. The sampling frequency and accuracy requirements for ADC and the calculation speed requirements for DSP are reduced, and the DC blocking capacitors can be replaced at a low cost and better, thereby improving power density and achieving the purpose of suppressing the DC bias of the primary and secondary sides respectively.

[0033] The dual active bridge DAB circuit model is as follows Figure 1 As shown in the figure, in DAB, the upper and lower switches of the same bridge arm are both complementary and turned on with a duty cycle of 0.5, and the ratio of the bridge arm phase shift angle to π is defined as the phase shift ratio (i.e., the phase shift ratio range is -1 to 1). The phase shift ratio between the primary bridge arm and the secondary bridge arm is called the external phase shift ratio. It is agreed here that when S1 and Q1 are in phase, the external phase shift ratio is 0.

[0034] When there is no high requirement for converter efficiency, single phase shift control (SPS) is usually used to simplify the DAB control strategy, and the DAB switching frequency is recorded as f s , define the phase shift of Q1 lagging behind S1 as D in single phase shift control, and derive the inductor current expression. The waveforms of DAB bridge arm voltage, inductor voltage and inductor current are as follows Figure 2 Show.

[0035] When the DAB voltage is asymmetric and the duty cycle is not 0.5 due to asymmetry of switching elements and circuit parameters, the volt-second characteristic is unbalanced, which will cause steady-state DC bias, such as Figure 3 and Figure 4 As shown in Figure 1, when the DAB suddenly changes due to the adjustment of the working conditions or the shift ratio, it will cause a transient DC bias, such as Figure 5 shown.

[0036] According to the transformer model, the DC bias currents on the primary and secondary sides of the DAB are independent of each other. Therefore, the duty cycle of the primary side cannot be modified alone, and the DC bias currents on both sides must be suppressed simultaneously.

[0037] In order to suppress the influence of DC bias, the current mainstream suppression method is to connect a DC blocking capacitor in series on the primary and secondary sides of the transformer, such as Figure 6 As shown in the figure, the main function of this DC blocking capacitor is to isolate the DC component and ensure that only the AC component can pass. However, this method still has some obvious limitations. First, the required capacitance value is large, which not only takes up a large space, but also reduces the power density of the device. Secondly, the capacitor in series in the circuit needs to bear a large high-frequency AC current, which places high demands on the capacitor. It also means that the life of the capacitor may limit the life of the entire device. For DAB devices with higher power levels, it is difficult to find capacitors that meet the requirements. In addition, the introduction of capacitors may also bring new resonant frequency points in the circuit, which may cause additional electromagnetic interference problems.

[0038] Some researchers have proposed some active DC blocking methods, hoping to suppress the DC bias that may be generated in the circuit by detecting, sampling, and calculating the circuit quantity, and actively adjusting the trigger pulse of the switch tube according to the control strategy, replacing the passive DC blocking capacitor. The research on active DC blocking is also mainly divided into transient DC bias suppression and steady-state DC bias suppression, and the research on transient DC bias suppression is more. For example, the detection of the induced current i (the primary or secondary current of the transformer) proposed in the related technology is compared with the upper and lower thresholds. Once i exceeds the design threshold, the comparator output will trigger the monostable to generate a fixed-width pulse, thereby limiting the displacement. Compared with the above, it can limit the transient DC bias generated when the load changes, but the improvement effect of this type of transient DC bias suppression method is mainly to optimize the transient process, and it is difficult to work for the steady-state DC bias caused by device parameter imbalance. There are also some control methods to suppress steady-state DC bias, which all rely on the detection of high-frequency current or voltage, and there are some difficulties: first, the requirements for the bandwidth and accuracy of the sensor are high, second, the requirements for the sampling frequency and accuracy of the ADC are high, and third, the requirements for the calculation speed and delay of the DSP are high. As proposed in the related art, the primary and secondary currents are detected and integrated to obtain the magnitude of the DC bias current. Through closed-loop control, the duty cycle of the primary and secondary sides is adjusted so that the integral of the current of the primary and secondary sides within one cycle is zero, so that the DC bias is zero. This method not only has high requirements on the bandwidth and accuracy of the sensor, but also has high requirements on the sampling rate and calculation speed of the ADC and DSP. An improved method for the sensor is also proposed in the related art. By using the principle of flux cancellation, a current transformer and a low-range high-precision current sensor are used to achieve high-precision DC bias current detection. However, there are few high-frequency and high-current current transformers of 200kHz, 100A and above on the market, which are difficult to be used in high-frequency and high-power devices. There is also an improved method for the sampling rate in the related art, which attempts to use a Δ-Σ modulator to exchange low resolution for high sampling frequency, but the data obtained by this method has low resolution, requires more digital processing capabilities, and has a high delay.

[0039] In response to the problems existing in the related art, the embodiment of the present application proposes an active DC isolation method, which adopts an analog circuit to realize the peak value maintenance and sampling of the inductor current, and performs a feedback control method based on the peak value of the inductor current, thereby avoiding the extremely high sampling rate required by the ADC and the large amount of calculation required by the DSP. It can replace the DC isolation capacitor at a low cost and better, improve the power density, and compared with the ordinary active DC isolation method, it reduces the requirements for the sampling frequency and accuracy of the ADC and the calculation speed requirement for the DSP.

[0040] Specifically, Figure 7 A schematic diagram of a DC bias suppression device for a dual active bridge provided in an embodiment of the present application.

[0041] like Figure 7As shown, the DC bias suppression device for dual active bridges includes: a high-frequency signal detection module 100, a peak detection module 200, a sampling module 300 and a control module 400.

[0042] Among them, the high-frequency signal detection module 100 is used to receive the primary current and the secondary current of the dual active bridge medium and high frequency transformer, and convert the primary current and the secondary current into voltage signals respectively to obtain the primary current detection signal and the secondary current detection signal; the peak detection module 200 is used to receive the primary current detection signal and the secondary current detection signal, and detect the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current based on the primary current detection signal and the secondary current detection signal; the sampling module 300 is used to sample according to the preset The strategy samples the maximum and minimum values ​​of the primary current and the maximum and minimum values ​​of the secondary current output by the peak detection circuit; the control module 400 is used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and calculate the difference between the sum of the maximum and minimum values ​​of the secondary current and zero, and use a preset PI controller to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and adjust the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0043] In some embodiments, the high-frequency signal detection module 100 includes: a current sensor and a sampling resistor, the current sensor is used to convert the primary current and the secondary current into a small signal current, and the sampling resistor is used to convert the small signal current into a voltage signal.

[0044] Optionally, in some embodiments, the peak detection module 200 includes: an upper peak detection circuit, used to detect the maximum value of the primary current of the dual active bridge medium and high frequency transformer and the maximum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle; a lower peak detection circuit, the lower peak detection circuit is connected to the upper peak detection circuit, and is used to detect the minimum value of the primary current of the dual active bridge medium and high frequency transformer and the minimum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle.

[0045] Optionally, in some embodiments, Figure 8As shown, the upper peak detection circuit includes: a first resistor, a first-stage amplifier A1, a second resistor, a first diode D1, a second diode D2, a first voltage follower A2, a third resistor, a fourth resistor, a first capacitor C1 and a first RST reset element, wherein the in-phase input terminal of the first-stage amplifier A1 is connected to one end of the first resistor for receiving a high-frequency current detection signal, the reverse input terminal of the first-stage amplifier A1 is connected to the anode of the second diode D2 and one end of the second resistor, and the output terminal of the first-stage amplifier A1 is respectively connected to the cathode of the second diode D2, the first diode The anode of the first diode D1 is connected, the cathode of the first diode D1 is connected to one end of the third resistor, the non-inverting input terminal of the first voltage follower A2 is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor C1, the inverting input terminal of the first voltage follower A2 is connected to the other end of the second resistor, the output terminal of the first voltage follower A2 is connected to the inverting input terminal, the other end of the first capacitor C1 is grounded, the input terminal of the first RST reset element is connected to the other end of the fourth resistor, and the output terminal and the ground terminal of the first RST reset element are both connected to the other end of the first capacitor C1 and grounded.

[0046] Optionally, in some embodiments, Figure 8 As shown, the lower peak detection circuit includes: a fifth resistor, a second-stage amplifier A3, a sixth resistor, a third diode D3, a fourth diode D4, a second voltage follower A4, a seventh resistor, an eighth resistor, a second capacitor C2 and a second RST reset element, wherein the in-phase input terminal of the second-stage amplifier A3 is connected to one end of the fifth resistor for receiving a high-frequency current detection signal, the other end of the fifth resistor is connected to the other end of the first resistor, the reverse input terminal of the second-stage amplifier A3 is connected to the cathode of the fourth diode D4 and one end of the sixth resistor, and the output terminal of the second-stage amplifier A3 is connected to the fourth diode D4 respectively. The anode of the third diode D3 is connected to the cathode of the third diode D3, the anode of the third diode D3 is connected to one end of the seventh resistor, the non-inverting input terminal of the second voltage follower A4 is connected to the other end of the seventh resistor, one end of the eighth resistor and one end of the second capacitor C2, the inverting input terminal of the second voltage follower A4 is connected to the other end of the sixth resistor, the output terminal of the second voltage follower A4 is connected to the inverting input terminal, the other end of the second capacitor C2 is grounded, the input terminal of the second RST reset element is connected to the other end of the eighth resistor, and the output terminal and the ground terminal of the second RST reset element are both connected to the other end of the second capacitor C2 and grounded.

[0047] In the peak detection circuit, such as Figure 8 As shown in the figure, the upper part is the upper peak detection circuit, and the lower part is the lower peak detection circuit. Take the above peak detection circuit as an example to illustrate. When the high-frequency current detection signal u ihfWhen the current rises, the current passes through the first amplifier A1 and the first diode D1 (Schottky diode) to charge the first capacitor C1. The voltage of the first capacitor C1 is output through the first voltage follower A2 on the right, ensuring that the capacitor voltage is consistent with the input voltage. When the high-frequency current detection signal u ihf When the voltage drops, the first diode D1 ensures that the capacitive current cannot flow back, and the first capacitor C1 cannot discharge, so the peak voltage is maintained. The upper peak signal is recorded as u ippeak .

[0048] The function of the second diode D2 (Schottky diode) connected in parallel with the reverse input and output of the first-stage amplifier A1 is to prevent the first-stage operational amplifier A1 from being in a negative saturation state for a long time when the input voltage drops, but to continue to follow the input signal. When the peak detection is performed again to charge the first capacitor C1, the output voltage of the first-stage amplifier A1 may not start to rise from the negative saturation state, thereby reducing the voltage rise time and speeding up the response speed. The lower peak detection circuit reverses the direction of the diode, and the principle is the same as that of the upper peak detection circuit. Fig. 9 As shown, Fig. 9 This is the effect of the peak detection circuit under the input 20kHz waveform. It can be seen that the peak detection circuit can complete the peak hold, reset and multiple detections.

[0049] Optionally, in some embodiments, the control module 400 includes: a calculation submodule, used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero.

[0050] Optionally, in some embodiments, the control module 400 also includes: a PI control submodule connected to the calculation submodule, the PI control submodule including a first PI controller and a second PI controller, which is used to input the difference between the sum of the primary currents of the dual active bridge medium and high frequency transformer and zero into the first PI controller to obtain the duty cycle adjustment amount on the primary side, and input the difference between the sum of the secondary currents of the dual active bridge medium and high frequency transformer and zero into the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

[0051] In order to solve the problems existing in the dual active bridge DAB, such as steady-state and transient DC bias, the difficulty in meeting the current carrying capacity requirements of the DC blocking capacitor and the large space occupied, and the difficulty in sampling high-frequency current, the embodiments of the present application propose a novel DC bias suppression device, which uses an analog circuit to realize the peak detection of the primary and secondary high-frequency circuits, and adopts PI control to adjust the duty cycle, so as to achieve the purpose of suppressing the DC bias of the primary and secondary sides respectively.

[0052] Since the DC bias currents of the primary and secondary sides of the DAB medium and high frequency transformer are independent of each other, it is necessary to detect and suppress the DC current bias on both sides at the same time. The specific suppression method is as follows: Fig.10 shown.

[0053] The embodiment of the present application uses the current sensor in the high-frequency signal detection module 100 to convert the primary high-frequency large current and the secondary high-frequency large current of the dual active bridge medium and high-frequency transformer into small signal current, and then converts the small signal current into a voltage signal through a sampling resistor to obtain a primary current detection signal and a secondary current detection signal.

[0054] The DAB high frequency current in normal operation is as follows Figure 2 As shown, the average value of the current in each cycle is the DC bias current. However, integrating the current waveform within one cycle to obtain the DC bias places high demands on the accuracy and calculation speed of the sensor and ADC, which may lead to large errors. Note that when there is no DC bias, the positive and negative half-cycle current waveforms of each cycle of the original secondary current waveform are symmetrical. Therefore, it is only necessary to use a peak detection circuit to sample the peak values ​​of the positive and negative half cycles to make their sum zero, thereby ensuring that the DC bias is zero.

[0055] The primary current detection signal and the secondary current detection signal are sent to the peak detection circuit. The peak detection circuit needs to re-detect once at a certain interval, so it is necessary to configure a switch to periodically reset the capacitor voltage to zero. Considering that the peak detection must be complete for at least one entire cycle, and the discharge of the detection capacitor takes time, in every two switching cycles, the first switching cycle completes a detection, and the capacitor is reset to zero in the second cycle. This is repeated, so that the maximum and minimum values ​​of the high-frequency current of the primary and secondary sides can be detected once every two switching cycles.

[0056] After the peak detection circuit maintains the maximum and minimum values ​​of the detected primary current and the maximum and minimum values ​​of the secondary current, the analog-to-digital converter ADC (i.e., sampling circuit) of the DAB controller samples the maximum and minimum values ​​of the primary current output by the peak detection circuit and the maximum and minimum values ​​of the secondary current according to a preset sampling strategy. Specifically, an analog-to-digital converter ADC needs to perform sampling at least once every two cycles, which greatly reduces the requirements for the ADC sampling frequency.

[0057] The maximum value i of the primary current is obtained by sampling ppeak and the minimum value i npeak The maximum value of the secondary current i ppeak and the minimum value i npeak , respectively sum the maximum and minimum values ​​of the primary current, compare the sum with zero, and send it to the first PI controller, and the output is the duty cycle adjustment amount dDuty1 of the primary side, as shown in the following figure: Fig.11As shown, adjusting the output voltage duty cycle of the primary side bridge circuit can suppress the DC current bias on the primary side. Similarly, the maximum and minimum values ​​of the secondary current are summed, compared with zero, and sent to the second PI controller to output the duty cycle adjustment amount dDuty2 on the secondary side to adjust the output voltage duty cycle of the secondary side bridge circuit. By adjusting the duty cycles of the primary side bridge circuit and the secondary side circuit, the DC bias current on the primary side and the secondary side can be suppressed respectively, thereby achieving the purpose of suppressing the bias magnetization.

[0058] In addition, a simulation model is built in the embodiment of the present application to verify the effectiveness of the proposed control method. A 1V DC voltage bias is applied to the primary side for 0.1s and a 1V DC voltage bias is applied to the secondary side for 0.2s. The schematic diagram of the primary side DC bias current obtained by the three methods is shown. Fig.12 (a) is a schematic diagram of the primary DC bias current without taking any suppression measures. Fig.12 (b) is a schematic diagram of the primary DC bias current with a DC blocking capacitor in series with the primary and secondary sides. Fig.12 (c) is a schematic diagram of the primary DC bias current using the active DC blocking method proposed in an embodiment of the present application. The simulation results show that the proposed active DC blocking method can achieve a better suppression effect and replace the DC blocking capacitor.

[0059] According to the DC bias suppression device for a dual active bridge proposed in an embodiment of the present application, the primary current and the secondary current of the high frequency transformer in the dual active bridge are received by a high frequency signal detection module, and the primary current and the secondary current are respectively converted into voltage signals to obtain a primary current detection signal and a secondary current detection signal. The primary current detection signal and the secondary current detection signal are received by a peak detection module, and the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current are respectively detected based on the primary current detection signal and the secondary current detection signal. The maximum value and the minimum value of the primary current output by the peak detection circuit and the maximum value and the minimum value of the secondary current are sampled by a sampling module according to a preset sampling strategy, the difference between the sum of the maximum value and the minimum value of the primary current and zero and the difference between the sum of the maximum value and the minimum value of the secondary current and zero are calculated by a control module, and a preset PI controller is used to obtain a duty cycle adjustment amount of the primary side and a duty cycle adjustment amount of the secondary side, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. As a result, the problems of steady-state and transient DC bias on the primary and secondary sides of the dual active bridge DAB device, the difficulty of traditional DC blocking capacitors in meeting the large current requirements of high-power DAB devices and the large space they occupy, and the difficulty in sampling high-frequency currents, are solved. The sampling frequency and accuracy requirements for ADC and the calculation speed requirements for DSP are reduced, and the DC blocking capacitors can be replaced at a low cost and better, thereby improving power density and achieving the purpose of suppressing the DC bias of the primary and secondary sides respectively.

[0060] Next, a DC bias suppression method for a dual active bridge proposed in accordance with an embodiment of the present application will be described with reference to the accompanying drawings.

[0061] Fig.13 It is a flow chart of a DC bias suppression method for a dual active bridge according to an embodiment of the present application.

[0062] like Fig.13 As shown, the DC bias suppression method for dual active bridges includes the following steps:

[0063] In step S1301, the primary current and the secondary current of the dual active bridge medium and high frequency transformer are received, and the primary current and the secondary current are respectively converted into voltage signals to obtain a primary current detection signal and a secondary current detection signal.

[0064] In step S1302, a primary current detection signal and a secondary current detection signal are received, and the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current are detected based on the primary current detection signal and the secondary current detection signal, respectively.

[0065] In step S1303, the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer output by the peak detection circuit are sampled according to a preset sampling strategy.

[0066] In step S1304, the difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side are obtained by using a preset PI controller, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit are adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0067] It should be noted that the aforementioned explanation of the embodiment of the DC bias suppression device for dual active bridges is also applicable to the DC bias suppression method for dual active bridges of this embodiment, which will not be described in detail here.

[0068] According to the DC bias suppression method for a dual active bridge proposed in an embodiment of the present application, the primary current and the secondary current of the dual active bridge medium and high frequency transformer are received, and the primary current and the secondary current are respectively converted into voltage signals to obtain a primary current detection signal and a secondary current detection signal, the primary current detection signal and the secondary current detection signal are received, and the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current are respectively detected based on the primary current detection signal and the secondary current detection signal, and the peak detection circuit outputs the dual active bridge medium and high frequency transformer according to a preset sampling strategy. The maximum and minimum values ​​of the primary current and the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer are sampled, the difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side are obtained by using a preset PI controller, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit are adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. Thus, the problems of the existence of steady-state and transient DC bias in the primary and secondary sides of the dual active bridge DAB device, the difficulty of the traditional DC blocking capacitor to withstand the high current requirements of the high-power DAB device and the large space occupied, and the difficulty of sampling high-frequency current are solved, the sampling frequency and accuracy requirements of the ADC and the calculation speed requirements of the DSP are reduced, and the DC blocking capacitor can be replaced at a low cost and better, the power density is improved, and the purpose of suppressing the DC bias of the primary and secondary sides is achieved.

[0069] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0070] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0071] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

Claims

1. A DC bias suppression device for a dual active bridge, characterized in that: include: A high-frequency signal detection module, used for receiving the primary current and the secondary current of the dual active bridge medium and high frequency transformer, and converting the primary current and the secondary current into voltage signals respectively, to obtain the primary current detection signal and the secondary current detection signal; a peak detection module, configured to receive the primary current detection signal and the secondary current detection signal, and detect the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current respectively based on the primary current detection signal and the secondary current detection signal; A sampling module, used for sampling the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current output by the peak detection circuit according to a preset sampling strategy; The control module is used to calculate the difference between the sum of the maximum value and the minimum value of the primary current and zero, and calculate the difference between the sum of the maximum value and the minimum value of the secondary current and zero, and use a preset PI controller to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and adjust the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit to suppress the DC bias current of the primary side and the secondary side of the dual active bridge.

2. The device according to claim 1, characterized in that The peak detection module comprises: An upper peak detection circuit, used to detect the maximum value of the primary current of the dual active bridge medium and high frequency transformer and the maximum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle; The lower peak detection circuit is connected to the upper peak detection circuit and is used to detect the minimum value of the primary current of the dual active bridge medium and high frequency transformer and the minimum value of the secondary current of the dual active bridge medium and high frequency transformer in each cycle.

3. The device according to claim 2, characterized in that The upper peak detection circuit comprises: a first resistor, a first-stage amplifier, a second resistor, a first diode, a second diode, a first voltage follower, a third resistor, a fourth resistor, a first capacitor, and a first RST reset element, wherein: The in-phase input terminal of the first-stage amplifier is connected to one end of the first resistor for receiving the high-frequency current detection signal, the inverting input terminal of the first-stage amplifier is connected to the anode of the second diode and one end of the second resistor, the output terminal of the first-stage amplifier is respectively connected to the cathode of the second diode and the anode of the first diode, the cathode of the first diode is connected to one end of the third resistor, the in-phase input terminal of the first voltage follower is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor, the inverting input terminal of the first voltage follower is connected to the other end of the second resistor, the output terminal of the first voltage follower is connected to the inverting input terminal, the other end of the first capacitor is grounded, the input terminal of the first RST reset element is connected to the other end of the fourth resistor, and the output terminal and the ground terminal of the first RST reset element are both connected to the other end of the first capacitor and grounded.

4. The device according to claim 2, characterized in that The lower peak detection circuit comprises: a fifth resistor, a second stage amplifier, a sixth resistor, a third diode, a fourth diode, a second voltage follower, a seventh resistor, an eighth resistor, a second capacitor, and a second RST reset element, Among them, the non-inverting input terminal of the second-stage amplifier is connected to one end of the fifth resistor for receiving the high-frequency current detection signal, the other end of the fifth resistor is connected to the other end of the first resistor, the inverting input terminal of the second-stage amplifier is connected to the cathode of the fourth diode and one end of the sixth resistor, the output terminal of the second-stage amplifier is respectively connected to the anode of the fourth diode and the cathode of the third diode, the anode of the third diode is connected to one end of the seventh resistor, the non-inverting input terminal of the second voltage follower is connected to the other end of the seventh resistor, one end of the eighth resistor and one end of the second capacitor, the inverting input terminal of the second voltage follower is connected to the other end of the sixth resistor, the output terminal of the second voltage follower is connected to the inverting input terminal, the other end of the second capacitor is grounded, the input terminal of the second RST reset element is connected to the other end of the eighth resistor, and the output terminal and the ground terminal of the second RST reset element are both connected to the other end of the second capacitor and grounded.

5. The device according to claim 1, characterized in that The control module comprises: The calculation submodule is used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero.

6. The device according to claim 1, characterized in that The control module further includes: A PI control submodule connected to the calculation submodule, the PI control submodule includes a first PI controller and a second PI controller, which is used to input the difference between the sum of the primary currents of the dual active bridge medium and high frequency transformer and zero into the first PI controller to obtain the duty cycle adjustment amount on the primary side, and input the difference between the sum of the secondary currents of the dual active bridge medium and high frequency transformer and zero into the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

7. The device according to claim 1, characterized in that The high-frequency signal detection module comprises: A current sensor and a sampling resistor, wherein the current sensor is used to convert the primary current and the secondary current into a small signal current, and the sampling resistor is used to convert the small signal current into a voltage signal.

8. A dual active bridge system, characterized in that: The invention comprises a DC bias suppression device for a dual active bridge as claimed in any one of claims 1 to 7.

9. A DC bias suppression method for a dual active bridge, characterized in that: A DC bias suppression device for a dual active bridge according to any one of claims 1 to 7 comprises the following steps: Receiving the primary current and the secondary current of the dual active bridge medium and high frequency transformer, and converting the primary current and the secondary current into voltage signals respectively, to obtain the primary current detection signal and the secondary current detection signal; receiving the primary current detection signal and the secondary current detection signal, and detecting the maximum value and the minimum value of the primary current and the maximum value and the minimum value of the secondary current respectively based on the primary current detection signal and the secondary current detection signal; Sampling the maximum value and the minimum value of the primary current of the dual active bridge medium and high frequency transformer and the maximum value and the minimum value of the secondary current of the dual active bridge medium and high frequency transformer output by the peak detection circuit according to a preset sampling strategy; The difference between the sum of the maximum and minimum values ​​of the primary current of the dual active bridge medium and high frequency transformer and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current of the dual active bridge medium and high frequency transformer and zero is calculated, and a preset PI controller is used to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

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