An X-capacitor discharge circuit based on dual envelope tracking

Abstract

The present application discloses an X-capacitor discharge circuit based on dual envelope tracking, which relates to the field of AC-DC conversion technology, including: a voltage divider / sampling circuit for collecting a sampled voltage on an X-capacitor; an envelope tracking circuit, including a bidirectional counter, a digital-to-analog conversion circuit, and an analog-to-digital conversion circuit connected in sequence, wherein the bidirectional counter counts forward or reversely under the control of a counting direction control bit signal to generate a multi-bit count value; the digital-to-analog conversion circuit converts the multi-bit count value into a high reference voltage and a low reference voltage, wherein the high reference voltage and the low reference voltage respectively perform envelope tracking on the sampled voltage, and the analog-to-digital conversion circuit compares the high reference voltage and the low reference voltage respectively with the sampled voltage to generate a counting direction control bit signal; and a discharge circuit discharges the X-capacitor under the control of the counting direction control bit signal. The detection frequency of the present application is independent of the frequency of the AC input voltage itself, and the detection frequency is greatly increased by a high-frequency clock, so as to have a faster response speed.

Description

Technical Field

[0001] The present application relates to the technical field of AC / DC conversion, and in particular to an X-capacitor discharge circuit based on double envelope tracking. Background Art

[0002] In an AC-DC (Alternating Current-Direct Current) or DC-DC (Direct Current-Direct Current) power supply, the AC input needs to pass through an EMI (Electromagnetic Interference) filter to filter out its high-frequency components before entering the rectifier bridge, and then enter the rectifier bridge for use by the subsequent DC-DC conversion circuit. EMI filters usually include common-mode inductors, X capacitors, and Y capacitors, among which X capacitors are mainly used to filter out high-frequency differential-mode interference in AC. For 50 / 60Hz mains frequency, X capacitors have very high impedance and have almost no effect on power frequency AC signals, such as Figure 1 shown.

[0003] When the AC plug is disconnected, the residual voltage is still on the X capacitor. If a person touches the neutral or live wire of the plug at this time, the charge on the X capacitor will be discharged through the human body, posing a safety hazard. There are currently two ways to control the discharge of the X capacitor: passive discharge and active discharge. Passive discharge is achieved by connecting a discharge resistor in parallel at both ends of the X capacitor, such as Figure 2 As shown. The discharge resistor has a continuous current flowing through it, and its discharge speed and static power consumption are in a contradictory relationship. If the resistance value is increased to reduce the static current, the discharge speed will be reduced accordingly, and the discharge of the X capacitor cannot be completed in a sufficiently short time, and the safety risk will increase. If the resistance value is reduced to shorten the discharge time, the static power consumption of the circuit will increase.

[0004] In order to solve the static power consumption problem of the discharge resistor, the active discharge solution determines whether it needs to be discharged by detecting the waveform characteristics at both ends of the X capacitor. The passive discharge resistor is removed in the active discharge solution, and a rectifier circuit composed of two diodes is used instead. Therefore, the diode on the side with higher voltage at both ends of the X capacitor will be turned on to provide a discharge path. It is worth emphasizing that the output signal of the rectifier diode is not transmitted to the power stage, but is only used for the discharge and control of the X capacitor. There is also a full-wave rectifier bridge in the AC-DC module, and its output is connected to the DC-DC converter after capacitor filtering, which is a power signal. Figure 3 , 4As shown in the figure, a threshold voltage VREF is set. If the AC input changes in a quasi-sinusoidal waveform, the output voltage value of the rectifier diode will periodically cross the threshold voltage, and the pulse caused by the comparator flipping will periodically reset the de-bounce timer. At this time, there is no need to discharge the X capacitor. If the AC input is disconnected, the AC voltage amplitude before the disconnection will be stored on the X capacitor as a DC voltage. This voltage no longer crosses the threshold voltage, so the comparator result does not change. After a period of de-bounce, the X capacitor is discharged through the discharge tube.

[0005] In the above X-capacitor discharge scheme, in order to be compatible with the full range of VAC (Volts Alternating Current, AC voltage) (85-265V), the threshold voltage needs to be set at a lower level, that is, detection is performed when the waveform is close to or far away from the horizontal axis. The defect of this scheme is that for an ideal sinusoidal AC signal, the rectified output signal will always cross the set threshold, but in fact, during the load adjustment process, the rectified output waveform will deviate from the ideal shape, and its peak and valley values ​​may change, such as Figure 5 If the valley value is higher than the preset reference voltage VREF, even if the AC input is not disconnected, the discharge process will be triggered, causing the system to be accidentally powered off, affecting system functions, such as Figure 5 shown.

[0006] In order to reduce the occurrence of such misjudgment, the prior art also proposes to adaptively adjust the reference voltage VREF according to the specific conditions of the peak and valley values ​​of the rectified output voltage, so that the reference voltage is always between the valley and the peak value, such as CN102457180A. Although this method can effectively reduce the occurrence of misjudgment, the adjustment of the reference voltage can only take effect after one cycle of the rectified output waveform. For example, for a 100Hz rectified output waveform, this time is about 10ms, resulting in an unsatisfactory response speed of power failure detection. Summary of the invention

[0007] The embodiment of the present application provides an X-capacitor discharge circuit based on dual envelope tracking, which is used to solve the problems existing in the passive discharge and active discharge technologies in the prior art.

[0008] The embodiment of the present application provides an X-capacitor discharge circuit based on dual envelope tracking, including:

[0009] A voltage divider / sampling circuit, used for connecting to a switching power supply circuit, and the voltage divider / sampling circuit is used for collecting a sampling voltage on an X capacitor in the switching power supply circuit;

[0010] An envelope tracking circuit is connected to the voltage divider / sampling circuit. The envelope tracking circuit includes a bidirectional counter, a digital-to-analog conversion circuit, and an analog-to-digital conversion circuit connected in sequence. The bidirectional counter counts forward or reversely under the control of a counting direction control bit signal to generate a multi-bit count value. When the sampling voltage increases, the bidirectional counter counts forward, and when the sampling voltage decreases, the bidirectional counter counts reversely. The digital-to-analog conversion circuit converts the multi-bit count value into a corresponding high reference voltage and a low reference voltage. The high reference voltage and the low reference voltage respectively perform envelope tracking on the sampling voltage above and below the sampling voltage. The analog-to-digital conversion circuit compares the high reference voltage and the low reference voltage with the sampling voltage to generate a counting direction control bit signal.

[0011] The discharge circuit includes a debounce timer, a discharge timer, a drive circuit and a discharge tube connected in sequence. The discharge tube is a power metal-oxide-semiconductor field-effect transistor (MOSFET), the gate of the discharge tube is connected to the drive circuit, the drain of the discharge tube is connected to the external resistor Rext, and the source is grounded. When the AC signal is disconnected, the discharge tube is turned on by the drive circuit, and discharges the X capacitor through the rectifier diode.

[0012] In a possible implementation, the voltage of the X capacitor is input to the control tube M1 through the external resistor Rext. The control tube M1 samples the control signal The voltage output by the control tube M1 is grounded through the internal resistor Rint on the one hand, and is output as a sampling voltage through the sampling tube M2 on the other hand. The sampling tube M2 is turned on or off under the control of the second sampling control signal. The output end of the sampling tube M2 is also grounded through the sampling capacitor C1.

[0013] In a possible implementation, the first sampling control signal The second sampling control signal is obtained by the clock signal after capacitor delay, inversion and NAND processing. The first sampling control signal It is obtained through capacitor delay, inversion and NAND processing.

[0014] In a possible implementation, the bidirectional counter includes a plurality of basic counting units and a logic circuit connected to each basic counting unit, and each basic counting unit is used to record 1-bit binary data. The basic counting unit includes an XOR gate and a D flip-flop connected to each other, and a counting direction control bit signal is input to a logic circuit connected to the basic counting unit of the lowest bit. The counting direction control bit signal is processed by the logic circuit to generate a control bit signal Ci, wherein the subscript i represents the sequence number of the basic counting unit controlled by the control bit. The basic counting unit determines the counting direction as forward counting, reverse counting or pause counting according to the control bit signal Ci, and the count value generated by this stage is input to a logic circuit connected to the basic counting unit of the next higher level until all the basic counting units output corresponding count values, and all the count values ​​form a multi-bit count value.

[0015] In a possible implementation, the logic circuit includes two NOT gates and three NAND gates, the counting direction control bit signal includes a high counting direction control bit signal A0 and a low counting direction control bit signal B0, the high counting direction control bit signal A0 and the low counting direction control bit signal B0 are respectively inverted by a NOT gate and input into a NAND gate respectively, the two NAND gates respectively perform NAND processing on the inverted high counting direction control bit signal A0 and the low counting direction control bit signal B0, the two NAND processing results are input into the remaining NAND gate to obtain the control bit signal Ci, and the NAND processing results output by the two NAND gates are input into the logic circuit connected to the basic counting unit of the higher level as the counting direction control bit signal of the higher level.

[0016] In one possible implementation, the multi-bit count value output by the bidirectional counter when counting forward is a multi-bit forward count value, and the multi-bit count value output by the bidirectional counter when counting reversely is a multi-bit reverse count value. The multi-bit forward count value is processed by a NAND gate and input into a NAND gate connected to a NAND gate that inverts the low counting direction control bit signal B0, and the multi-bit reverse count value is processed by a NAND gate and input into a NAND gate connected to a NAND gate that inverts the high counting direction control bit signal A0.

[0017] In a possible implementation, the discharge circuit includes a de-jitter timer and a discharge timer. After the sampled voltage does not change for a de-jitter time, the discharge tube is turned on to discharge the X capacitor. After the discharge tube discharges for a discharge time, the discharge tube is turned off.

[0018] An X-capacitor discharge circuit based on dual envelope tracking in this application has the following advantages:

[0019] 1. Compared with the traditional detection scheme in which the waveform of each rectifier bridge output waveform only crosses the reference voltage twice within a cycle, the discharge detection interval of the present application has nothing to do with the cycle of the rectifier bridge output waveform itself (that is, half of the AC power frequency cycle), but depends on the higher-frequency clock generated by the internal or external oscillator, which greatly improves the effective detection frequency and has a faster response speed.

[0020] 2. The dual envelope tracking method is adopted to dynamically adjust the high and low reference voltages, which can adapt to the peak and valley values ​​of the rectifier bridge output waveform. This solves the problem in the traditional solution that the fixed threshold voltage cannot solve the problem of excessively high local valley values ​​of the rectifier bridge output waveform caused by load adjustment, leading to misjudgment of discharge.

[0021] 3. The on-chip sampling circuit only turns on the resistor divider string for a very short time, greatly reducing the static power consumption of the sampling short circuit.

[0022] 4. A bidirectional timer is developed based on the traditional unidirectional timer to achieve bidirectional counting with fewer digital circuits, and the digital-to-analog conversion circuit is used to enable the envelope to track the input waveform upward or downward. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 Figure 2 shows a typical EMI filter and its input and output voltage waveforms.

[0025] Figure 2 It is a circuit diagram of passive discharge in the prior art.

[0026] Figure 3 This is a circuit diagram of active discharge in the prior art.

[0027] Figure 4 This is the discharge timing diagram under the ideal rectified output waveform.

[0028] Figure 5 This is the timing diagram of misjudgment after the rectifier output waveform changes.

[0029] Figure 6 A module diagram of an X-capacitor discharge circuit and a switching power supply circuit based on dual envelope tracking provided in an embodiment of the present application.

[0030] Figure 7 A circuit diagram of a voltage divider / sampling circuit and a switching power supply circuit provided in an embodiment of the present application.

[0031] Figure 8 The waveform diagram of the sampling voltage and the timing diagram of the sampling control signal provided in the embodiment of the present application.

[0032] Fig. 9 A module diagram of an envelope tracking circuit provided in an embodiment of the present application.

[0033] Fig.10 Circuit diagram of a bidirectional counter, a digital-to-analog conversion circuit, and an analog-to-digital conversion circuit provided in an embodiment of the present application.

[0034] Fig.11 A waveform diagram of dual envelope tracking provided in an embodiment of the present application.

[0035] Fig.12 A module diagram of a bidirectional counter provided in an embodiment of the present application.

[0036] Fig.13 A circuit diagram of a bidirectional counter provided in an embodiment of the present application.

[0037] Fig.14 A module diagram of a basic counting unit provided in an embodiment of the present application.

[0038] Fig.15 This is a timing diagram when the control bit signal Ci=1 provided in an embodiment of the present application.

[0039] Fig.16 This is an equivalent circuit of a D flip-flop when the control bit signal Ci=1 provided in an embodiment of the present application.

[0040] Fig.17 This is a timing diagram when the control bit signal Ci=0 provided in an embodiment of the present application.

[0041] Fig.18 This is an equivalent circuit of a D flip-flop when the control bit signal Ci=0 provided in an embodiment of the present application.

[0042] Fig.19 The equivalent circuit of the bidirectional counter when counting in the forward direction provided in the embodiment of the present application.

[0043] Fig. 20 The equivalent circuit of the bidirectional counter when counting in reverse provided in the embodiment of the present application.

[0044] Fig.21 The digital change characteristics during forward counting provided in the embodiment of the present application.

[0045] Fig. 22 The digital change characteristics during reverse counting provided in the embodiment of the present application.

[0046] Fig.23The equivalent circuit of each basic counting unit during forward counting provided in the embodiment of the present application.

[0047] Fig.24 The self-adjustment process of the bidirectional counter provided in the embodiment of the present application.

[0048] Fig.25 The equivalent circuit of each basic counting unit during reverse counting provided in the embodiment of the present application.

[0049] Fig.26 The waveform of the dual envelope tracking and the timing diagram of the counting direction control bit provided in the embodiment of the present application.

[0050] Fig. 27 A circuit diagram of a discharge circuit and a switching power supply circuit provided in an embodiment of the present application.

[0051] Fig.28 The waveform of dual envelope tracking, the timing diagram of the counting direction control bit signal, and the timing diagram of de-jittering and discharge provided in the embodiments of the present application.

[0052] Fig.29 A circuit diagram of an X-capacitor discharge circuit and a switching power supply circuit based on dual envelope tracking provided in an embodiment of the present application.

[0053] Explanation of the accompanying symbols: 1. Switching power supply circuit; 11. Rectifier diode; 12. External resistor; 2. Voltage divider / sampling circuit; 21. Sampling circuit; 22. Voltage divider circuit; 3. Envelope tracking circuit; 31. Analog-to-digital conversion circuit; 311. High-order comparator; 312. Low-order comparator; 32. Bidirectional counter; 321. Basic counting unit; 322. Logic circuit; 323. Full judgment NAND gate; 324. Clear judgment NAND gate; 33. Digital-to-analog conversion circuit; 4. Discharge circuit; 41. Debounce timer; 42. Discharge timer; 43. Drive circuit; 44. Discharge tube. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] Figure 6 A block diagram of an X-capacitor discharge circuit based on dual envelope tracking provided in an embodiment of the present application. An embodiment of the present application provides an X-capacitor discharge circuit based on dual envelope tracking, including:

[0056] The voltage divider / sampling circuit 2 is used to be connected to the switching power supply circuit 1, and the voltage divider / sampling circuit 2 is used to collect the sampled voltage on the X capacitor in the switching power supply circuit 1. In the switching power supply circuit 1, the rectifier diode 11 rectifies the alternating current and then inputs it into the voltage divider / sampling circuit 2 through the external resistor 12. The voltage divider / sampling circuit 2 includes a sampling circuit 21 and a voltage divider circuit 22.

[0057] The envelope tracking circuit 3 is connected to the voltage divider / sampling circuit 2, such as Fig. 9 and 10 As shown, the envelope tracking circuit 3 includes a bidirectional counter 32, a digital-to-analog conversion circuit 33 and an analog-to-digital conversion circuit 31 connected in sequence. The bidirectional counter 32 counts forward or reversely under the control of a counting direction control bit signal to generate a multi-bit count value. When the sampling voltage increases, the bidirectional counter 32 counts forward, and when the sampling voltage decreases, the bidirectional counter 32 counts reversely; the digital-to-analog conversion circuit 33 converts the multi-bit count value into a corresponding high reference voltage and a low reference voltage, and the high reference voltage and the low reference voltage respectively perform envelope tracking on the sampling voltage above and below the sampling voltage, and the analog-to-digital conversion circuit 31 compares the high reference voltage with the sampling voltage through a high-bit comparator 311, and compares the low reference voltage with the sampling voltage through a low-bit comparator 312 to generate a counting direction control bit signal.

[0058] The discharge circuit 4 includes a discharge tube 44, which is a power MOS field effect tube. The gate of the discharge tube 44 is connected to the drive circuit 43, the drain of the discharge tube is connected to the external resistor Rext and the source is grounded. When the sampling voltage does not change, the discharge tube is turned on under the control of the counting direction control bit signal to discharge the X capacitor.

[0059] For example, Figure 7 As shown in the figure, the AC input passes through the EMI filter and enters the full bridge composed of two diodes, which is equivalent to taking the absolute value of the AC sine wave. The voltage divider resistor is composed of an external resistor Rext and an internal resistor Rint. k for:

[0060]

[0061] In a possible embodiment, the voltage of the X capacitor is input to the control tube M1 after being divided by the external resistor Rext. The control tube M1 is in the first sampling control signal The voltage output by the control tube M1 is grounded through the internal resistor Rint on the one hand, and is output as a sampling voltage through the sampling tube M2 on the other hand. The sampling tube M2 is turned on or off under the control of the second sampling control signal. The output end of the sampling tube M2 is also grounded through the sampling capacitor C1.

[0062] For example, under the control of a 6.25kHz sampling clock, the sampling tube M2 and the sampling capacitor C1 sample the output voltage of the rectifier diode in a short period of time at a fixed interval. When the voltage is high, M1 is turned on. Sampling is performed at high level. When sampling, the voltage of HV is the voltage VHV divided by two resistors, that is, VHV= k VAC, the sampling tube M2 samples the divided voltage on the sampling capacitor C1. Although the sampled voltage is discrete, the sampling frequency (6.25kHz) is much higher than the changing frequency of the rectified output voltage (100Hz), so it can be considered that the sampled voltage can almost reflect the AC waveform in real time. = =0, M1 is off, so the voltage of HV is equal to VAC, which can be used for high-voltage startup. It should be understood that Figure 8 The timing in the figure is for reference only. and The frequency is much higher than the power frequency, and its pulse width is much smaller than its period.

[0063] In a possible embodiment, the first sampling control signal The second sampling control signal is obtained by inverting and negating the clock signal. The first sampling control signal Obtained through inversion and NAND processing.

[0064] For example, Fig.29 As shown, the clock signal clk is inverted by three sequentially connected NOT gates, and then input into the two input ends of the NAND gate together with the clock signal clk. The signal output by the NAND gate is processed by a NOT gate to obtain the first sampling control signal. . The first sampling control signal After being processed by the edge-to-pulse circuit, the first sampling control signal The falling edge of the positive pulse signal is converted into a positive pulse signal, and the positive pulse signal is inverted to obtain the second sampling control signal .

[0065] In a possible embodiment, the bidirectional counter 32 includes a plurality of basic counting units 321 and a logic circuit 322 connected to each basic counting unit 321. The basic counting unit 321 includes an XOR gate and a D flip-flop connected to each other. The counting direction control bit signal is input to the logic circuit 322 connected to the basic counting unit 321 of the lowest bit. The counting direction control bit signal is processed by the logic circuit to generate a control bit signal Ci. The basic counting unit 321 determines the counting direction as forward counting, reverse counting or pause counting according to the control bit signal Ci. The generated lowest bit count value is input to the logic circuit connected to the basic counting unit 321 of the next higher level until all the basic counting units 321 output corresponding count values, and all the count values ​​constitute a multi-bit count value.

[0066] For example, Fig.13 As shown, the logic circuit 322 includes two NOT gates and three NAND gates, the counting direction control bit signal includes a high counting direction control bit signal A0 and a low counting direction control bit signal B0, the high counting direction control bit signal A0 and the low counting direction control bit signal B0 are respectively input to a NAND gate after being inverted by a NOT gate, the two NAND gates respectively perform NAND processing on the inverted high counting direction control bit signal A0 and the low counting direction control bit signal B0, the two NAND processing results are input to the remaining NAND gate to obtain the control bit signal Ci, the NAND processing results output by the two NAND gates are input as the counting direction control bit signal of the higher level to the logic circuit connected to the basic counting unit 321 of the higher level. The logic circuit 322 is connected to the basic counting unit 321 of the first level, and the full judgment NAND gate 323 and the clear judgment NAND gate 324 are both connected to the logic circuit 322.

[0067] Furthermore, when the bidirectional counter 32 counts forward, the multi-bit count value is a multi-bit forward count value, and when the bidirectional counter 32 counts reversely, the multi-bit count value is a multi-bit reverse count value. The multi-bit forward count value is processed by a NAND gate and input into a NAND gate connected to a NAND gate that inverts the low counting direction control bit signal B0, and the multi-bit reverse count value is processed by a NAND gate and input into a NAND gate connected to a NAND gate that inverts the high counting direction control bit signal A0.

[0068] The purpose of the bidirectional counter 32 is to generate a positive count value or a reverse count value so that the digital-to-analog conversion circuit generates two voltages: a high reference voltage (VREFH) and a low reference voltage (VREFL) to track the envelope of the input signal, i.e., the sampling voltage. If these two reference voltages are continuously changing, it means that Vin is continuously changing; if neither VREFH nor VREFL changes, it proves that Vin is a DC voltage at this time. Using this method, it is possible to determine whether the voltage on the X capacitor is AC or DC, thereby determining the state of the AC input. For generalization, Fig.11 Where Vin is an arbitrary waveform.

[0069] Compared with the traditional method of setting a fixed threshold voltage to determine the position of the AC waveform, the present application can adapt to different VAC sizes and different rectifier diode conduction voltage drops VD, that is, there is no need to worry about the maximum and minimum values ​​of the rectifier output waveform, and it is more versatile.

[0070] The digital-to-analog conversion circuit 33 is composed of an operational amplifier and a voltage-dividing resistor.

[0071] The analog-to-digital conversion circuit 31 uses two comparators with floating reference voltages, which are generated by a logic circuit and a DAC (Digital Analog Converter) circuit 33. This approach dynamically changes the threshold voltage of the comparator to adapt to the size of the input signal Vin. The signals A0 and B0 generated by the comparator enter the digital circuit. The digital circuit is mainly composed of a bidirectional counter 32, which can count both forward and reverse. A0 and B0 are counting direction selection control bits, and their logical functions are as follows: Fig.12 And as shown in Table 1.

[0072] Table 1 Logical functions of the counting direction control bit signal

[0073]

[0074] The circuit of the bidirectional counter 32 is as follows: Fig.13 As shown, the bidirectional counter 32 only uses the same number of D flip-flops as the unidirectional counter and a small amount of additional logic circuits to achieve both forward and bidirectional counting functions, thus saving chip area.

[0075] Fig.14 The figure shows a basic counting unit 321, which is composed of an XOR gate and a D flip-flop. Ci (i=1,2,3,4,5) is called a control bit signal of a basic counting unit 321. When Ci=1, the input terminal (D) of the flip-flop is the reverse output (Qib) of the flip-flop. Under the action of the clock signal clk, the results of the positive output (Q) and the reverse output (Qib) of the flip-flop will flip respectively, as shown in FIG. Fig.15 and 16 When Ci=0, D inputs Qi, and the result will not flip with the clock signal clk, which is equivalent to keeping the current result, such as Fig.17 and 18 shown.

[0076] The role of the logic circuit connected to each basic counting unit 321 is to calculate the results of all units at a lower level than the current unit to generate the control signal of the current level. Its function is that when the bidirectional counter is configured as a forward counter, the logic circuit outputs the control bit Ci=1 when and only when the count values ​​of all lower-level units are 1, otherwise it is 0; when the bidirectional counter is configured as a reverse counter, the logic circuit outputs the control bit Ci=1 when and only when the count values ​​of all lower-level units are 0, otherwise it is 0.

[0077] Further, Fig.13 The bidirectional counter shown has different effective signal paths for the input of different counting direction control bit signals A0 and B0. The principles of forward counting, reverse counting and pause are explained below in different situations.

[0078] (1) When A0=1, B0=0, the counter is configured to count forward. Fig.19 The equivalent circuit under this configuration is shown in the figure. The logic function of the control bit signal Ci is shown in the figure. The necessary and sufficient condition for a certain bit Ci=1 is that the Q values ​​of all lower bits are 1, then it flips at the clock edge Qi, which can be written as the following formula:

[0079]

[0080] in, Indicates that the result is updated at the clock edge, It represents the inverted signal of Qi, and Qn represents a signal lower than Qi.

[0081] It should be noted that when the forward count is full, all Qs are 1, so the output signal of the full count judgment NAND gate 323 is =0, that is, the lowest control bit C1=0, the lowest bit no longer flips, so the higher bits no longer change, triggering the full lock counter to stop at 11111.

[0082] (2) When A0=0, B0=1, count backwards. Fig. 20 The equivalent circuit in this case is shown below. The necessary and sufficient condition for Ci=1 of a certain bit is that the Q values ​​of all lower bits are 0, and then it flips at the clock edge Qi, which can be written as the following formula:

[0083]

[0084] The end time of reverse counting is when all Q are 0, so the output signal of NAND gate 324 is cleared. =0, that is, the lowest control bit C1 = 0. Similarly, the clear lock is triggered and the counter stops at 00000.

[0085] (3) When A0=1, B0=1, the lowest control bit C1=0, that is, the lowest bit does not flip, so the higher bits do not change. In this case, the counter stops at the previous count value.

[0086] Further, in order to illustrate the mathematical principle of the above counting, observe the changes in the data when counting forward. Fig.21 It is obvious that before a certain bit is carried out, all lower bits must be 1 at this moment. Therefore, a positive counter can be constructed by using the above basic counting unit 321 and logic circuit, such as Fig.23 It can be understood that whether the clock is connected to the counter is controlled by all low-bit results.

[0087] Observe the changes in data when counting backwards. Fig. 22 Obviously, before a carry flips, all lower bits must be 0 at this moment. Similarly, construct the logic circuit of the reverse counter, such as Fig.25 shown.

[0088] Therefore, the bidirectional counter 32 proposed in the present application substantially unifies the two counting circuits by constructing a logic function, thereby saving the number of D flip-flops.

[0089] The envelope tracking circuit 3 can be constructed by using the above analog-to-digital conversion circuit 31, the bidirectional counter 32, and the digital-to-analog conversion circuit 33. Vin is compared with the high and low reference voltages in the comparator, and the result is sent to the bidirectional counter 32 to control its multi-bit count value Q<5:1> to increase, decrease or remain unchanged. The digital-to-analog conversion circuit 33 generates an analog voltage according to this code to adjust the reference voltage of the comparator. The self-adjustment process of the bidirectional counter 32 is shown in Table 2, and the process is as follows Fig.24 shown.

[0090] Table 2 Reference voltage dynamic adjustment process

[0091]

[0092] Assuming that the change of Vin is much slower than that of clk, the combination of the bidirectional counter 32 and the digital-to-analog conversion circuit 33 can respond quickly to the change of Vin, and it can be considered that it has continuity in time. However, the output result of the digital-to-analog conversion circuit 33 is encoded by binary numbers, and its voltage amplitude is discrete, such as Fig.26 As shown in the middle step waveform.

[0093] Based on the dynamic adjustment process of the closed loop, the two reference voltages will always track Vin like an envelope, and the change interval is determined by the clock cycle, and the accuracy is determined by the number of bits of the digital-to-analog conversion circuit 33. Using this feature, it is possible to monitor whether the input signal is changing slowly, that is, if the input signal is changing and the amplitude exceeds the step size of the reference voltage, then the bidirectional counter 32 will always send out changing A0 and B0 signals to force the counter result to change; if the input signal is almost unchanged, then A0 and B0 will always be 1, indicating that the reference voltage does not need to be adjusted.

[0094] In a possible embodiment, the discharge circuit 4 includes a de-jitter timer 41 for de-jittering. After the sampling voltage does not change for a de-jitter time, the de-jitter timer 41 turns on the discharge tube 44 .

[0095] For example, Fig. 27 As shown, the discharge circuit 4 is composed of a de-jitter timer 41, a discharge timer 42, a driving circuit 43 and a discharge tube 44. The de-jitter timer 41 is composed of an XOR gate, a cascaded D flip-flop and an RS flip-flop, which is used to set the time from the disappearance of the AC signal to the start of the discharge to achieve de-jitter and prevent false triggering. The discharge timer 42 is composed of an inverter, a cascaded D flip-flop and an RS flip-flop, which is used to set the duration of the discharge tube opening during the discharge process. The input end of the de-jitter timer 41 is connected to the output signals A0 and B0 of the analog-to-digital conversion circuit 31, and is connected to the reset end R of the cascaded D flip-flop after passing through the XOR gate. When the AC signal exists, A0 or B0 will always generate a logically opposite signal to adjust the reference voltage generated by the digital-to-analog conversion circuit 33. Therefore, the positive pulse generated by the XOR of A0 and B0 will repeatedly reset the cascaded D flip-flop of the de-jitter timer 41, so that the timer cannot reach the set timing value, and the output result QT1 of the de-jitter timer 41 remains low. When the AC signal disappears, A0 and B0 remain high, the XOR output of the debounce timer 41 is 0, and the debounce timer 41 can count normally. After the set timing time is reached, its output result QT1 becomes high, and QT2 is set high through the RS trigger of the discharge timer 42. At the same time, the reset of the timer is released, so that the cascaded D trigger of the discharge timer 42 starts timing until the set time is reached, and QT2 becomes low through the RS trigger. During the period when QT2 is high, the discharge tube is turned on under the action of the driving circuit, and the residual charge on the X capacitor is discharged to the ground through the rectifier diode 11, the external resistor 12 and the discharge tube 44. Fig.28 shown.

[0096] In the embodiment of the present application, the full time of the debounce timer 41 is set to 60 milliseconds. For a 50 Hz AC signal, if there is no AC change within the 6 cycles of the rectified output waveform, the X capacitor discharge is triggered. Specifically, the full time of the discharge timer 42 can be set to 300 milliseconds, and the discharge process lasts for 300 milliseconds.

[0097] Compared with the traditional approach, the present application only needs to detect whether the voltage across the X capacitor has a local up and down change to determine whether the X capacitor needs to be discharged, regardless of the specific rectifier output peak and valley values, thus avoiding the problems caused by fixed threshold judgment.

[0098] X capacitors are widely used in AC-DC conversion circuits and need to be discharged after the AC input is disconnected. In order to balance its safety and power consumption, the present application proposes an X capacitor discharge circuit 4, which consists of a voltage divider / sampling circuit 2, an envelope tracking circuit 3 and a discharge circuit 4. The overall circuit is as follows Fig.29 shown.

[0099] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An X-capacitor discharge circuit based on dual envelope tracking, characterized in that: include: A voltage divider / sampling circuit, used to be connected to the switching power supply circuit, and the voltage divider / sampling circuit is used to collect a sample voltage on the X capacitor in the switching power supply circuit; An envelope tracking circuit is connected to the voltage divider / sampling circuit, wherein the envelope tracking circuit includes a bidirectional counter, a digital-to-analog conversion circuit, and an analog-to-digital conversion circuit connected in sequence, wherein the bidirectional counter counts forward or reversely under the control of a counting direction control bit signal to generate a multi-bit count value, and when the sampling voltage increases, the bidirectional counter counts forward, and when the sampling voltage decreases, the bidirectional counter counts reversely; The digital-to-analog conversion circuit converts the multi-bit count value into a corresponding high reference voltage and a low reference voltage, wherein the high reference voltage and the low reference voltage respectively perform envelope tracking on the sampling voltage above and below the sampling voltage, and the analog-to-digital conversion circuit compares the high reference voltage and the low reference voltage with the sampling voltage respectively to generate the counting direction control bit signal; The discharge circuit comprises a discharge tube, wherein the discharge tube is a power MOS field effect tube, a gate of the discharge tube is connected to the envelope tracking circuit, a drain and a source of the discharge tube are respectively connected to an X capacitor and grounded, and when the sampling voltage does not change, the discharge tube is turned on under the control of the counting direction control bit signal to discharge the X capacitor.

2. The X-capacitor discharge circuit based on dual envelope tracking according to claim 1, characterized in that: The voltage of the X capacitor is input to the control tube M1 after passing through the rectifier diode and the external resistor Rext. The control tube M1 is The voltage output by the control tube M1 is grounded through the internal resistor Rint on the one hand, and is output as a sampling voltage through the sampling tube M2 on the other hand. The sampling tube M2 is turned on or off under the control of the second sampling control signal. The output end of the sampling tube M2 is also grounded through the sampling capacitor C1.

3. The X-capacitor discharge circuit based on dual envelope tracking according to claim 2, characterized in that: The first sampling control signal The second sampling control signal is obtained by the clock signal after capacitor delay, inversion and NAND processing. The first sampling control signal It is obtained through capacitor delay, inversion and NAND processing.

4. The X-capacitor discharge circuit based on dual envelope tracking according to claim 1, characterized in that: The bidirectional counter includes a plurality of basic counting units and a logic circuit connected to each of the basic counting units. The basic counting units include mutually connected XOR gates and D flip-flops. The counting direction control bit signal is input into the logic circuit connected to the basic counting unit of the lowest bit. The counting direction control bit signal is processed by the logic circuit to generate a control bit signal Ci. The basic counting unit determines the counting direction as forward counting, reverse counting or pause counting according to the control bit signal Ci. The generated lowest bit count value is input into the logic circuit connected to the basic counting unit of the next higher level until all the basic counting units output corresponding count values. All the count values ​​constitute the multi-bit count value.

5. The X-capacitor discharge circuit based on dual envelope tracking according to claim 4, characterized in that: The logic circuit includes two NOT gates and three NAND gates, the counting direction control bit signal includes a high counting direction control bit signal A0 and a low counting direction control bit signal B0, the high counting direction control bit signal A0 and the low counting direction control bit signal B0 are respectively input into one of the NAND gates after being inverted by one of the NOT gates, the two NAND gates respectively perform NAND processing on the inverted high counting direction control bit signal A0 and the low counting direction control bit signal B0, the two NAND processing results are input into the remaining NAND gate to obtain the control bit signal Ci, the NAND processing results output by the two NAND gates are input into the logic circuit connected to the basic counting unit of the higher level as the counting direction control bit signal of the higher level.

6. The X-capacitor discharge circuit based on dual envelope tracking according to claim 5, characterized in that: The multi-bit count value output by the bidirectional counter when counting forward is a multi-bit forward count value, and the multi-bit count value output by the bidirectional counter when counting reversely is a multi-bit reverse count value, the multi-bit forward count value is processed by a NAND gate and input into the NAND gate connected to the NAND gate that inverts the low counting direction control bit signal B0, and the multi-bit reverse count value is processed by a NAND gate and input into the NAND gate connected to the NAND gate that inverts the high counting direction control bit signal A0.

7. The X-capacitor discharge circuit based on dual envelope tracking according to claim 1, characterized in that: The discharge circuit includes a de-jitter timer, and after the sampling voltage does not change for a de-jitter time, the de-jitter timer turns on the discharge tube.

8. The X-capacitor discharge circuit based on dual envelope tracking according to claim 7, characterized in that: The discharge circuit also includes a discharge timer, which is connected to the output end of the de-jitter timer. After the sampling voltage does not change for the de-jitter time, the discharge timer turns on the discharge tube under the control of the de-jitter timer. After the discharge tube discharges for the discharge time, the discharge timer turns off the discharge tube.

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