Common ground type five-level photovoltaic inverter with self-balancing function of capacitor voltage

Abstract

The application discloses a common ground type five-level photovoltaic inverter with a self-balancing function of capacitor voltage. The inverter topology comprises a photovoltaic cell, a five-level inverter circuit with a self-balancing function of capacitor voltage, a single-phase output LC filter circuit and a single-phase load. The five-level inverter circuit is composed of a direct current input filter capacitor Cdc, switching capacitors C1 and C2 and ten switching tubes S1-S10, wherein S1 is an IGBT without a freewheeling diode, and S2-S10 are IGBTs with freewheeling diodes. The control method of the inverter compares a sine wave reference signal with two same-phase and two phase-shifted triangular carriers to generate four preprocessed signals, and then performs logical operation according to the switching tube conduction relationship under six working modes to obtain control signals. The inverter can realize self-balancing of the switching capacitor voltage through mode switching, and significantly improves the output voltage quality.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronic DC-AC conversion, and is suitable for application scenarios where the load is an AC load and the power supply is a DC power supply, and has good application value in photovoltaic off-grid or grid-connected inverters in particular, and specifically relates to a common-ground five-level photovoltaic inverter with a capacitor voltage self-balancing function. BACKGROUND

[0002] With the intensification of fossil energy consumption and the continuous deterioration of the ecological environment, the development and utilization of new energy has become an urgent need. Solar energy, as a clean, harmless and abundant renewable energy, has received widespread attention. Among them, photovoltaic power generation, as a major form of utilizing solar energy, is being intensively studied. In the 2023 edition of the "China Renewable Energy Development Report", it shows that the renewable energy development in China in 2023 reached 2.95 trillion kilowatt-hours, of which solar power generation was 583.3 billion kilowatt-hours, an increase of 36.4% year-on-year. According to the forecast of the International Energy Agency (IEA), by 2028, renewable energy will account for more than 42% of global power generation, of which solar and wind power generation will account for 25%. However, with the rapid development of photovoltaic power generation, traditional photovoltaic inverters face problems such as large system size, high cost and low efficiency due to the inclusion of an isolation transformer. Therefore, non-isolated photovoltaic inverters, with the advantages of small size, low cost and high conversion efficiency, have gradually become an effective solution and are widely used in solar power generation systems.

[0003] Non-isolated photovoltaic inverters directly connect the photovoltaic input side to the grid or load by removing the isolation transformer, thereby significantly improving system efficiency. However, due to the lack of electrical isolation provided by traditional isolation devices, this structure also brings new technical challenges. In particular, the power switch tube in the photovoltaic inverter will generate a common-mode voltage when working at high frequency. This voltage will act on the loop formed by the parasitic capacitor between the photovoltaic panel and the ground, the output side filter and the grid impedance, and then cause common-mode leakage current (commonly known as leakage current). The generation of leakage current may cause electromagnetic interference and radiation, and lead to grid current harmonic distortion, reduced conversion efficiency, and even pose a threat to equipment and personnel safety. In order to suppress the leakage current in the non-isolated photovoltaic inverter, the topology of the inverter and the control strategy of the switch tube are often optimized to reduce the pulsating range of the common-mode voltage or keep it constant. However, due to the influence of parasitic parameters and dead time, it is still challenging to completely eliminate the common-mode voltage fluctuation and leakage current.

[0004] To solve the problem, the prior art proposes a common ground photovoltaic inverter, which effectively eliminates the leakage current by connecting the negative terminal of the photovoltaic panel to the neutral line of the power grid. However, the existing capacitor-type common ground photovoltaic inverter has some disadvantages, such as lack of voltage doubling function, continuous discharge of switching capacitor leading to increased voltage ripple and output voltage distortion, affecting system efficiency and performance.

[0005] Therefore, it is necessary to design a new common ground five-level photovoltaic inverter with capacitor voltage self-balancing function to solve the above problems. SUMMARY

[0006] The main purpose of the present application is to provide a common ground five-level photovoltaic inverter with capacitor voltage self-balancing function, which effectively solves the problem of continuous discharge of switching capacitor in common ground inverter, reduces the capacitance value of required capacitor, and significantly improves the quality of output voltage waveform.

[0007] The present application provides a common ground five-level photovoltaic inverter with capacitor voltage self-balancing function, which comprises a photovoltaic cell PV, a five-level inverter circuit with capacitor voltage self-balancing function, a single-phase output LC filter circuit and a single-phase load. The five-level inverter circuit comprises a DC input filter capacitor Cdc, two switching capacitors C1 and C2, and ten switching tubes S1-S10, wherein the switching tube S1 is an IGBT without freewheeling diode, and the switching tubes S2-S9 are IGBTs with freewheeling diode. The single-phase output LC filter circuit and the single-phase load comprise a filter inductor Lf, a filter capacitor Cf and a single-phase load Ro.

[0008] The further improvement of the present application is that the positive electrode of the photovoltaic cell PV is connected to the positive electrode of the DC input filter capacitor Cdc and the collector of the switching tube S1; the emitter of the switching tube S1 is connected to the collector of the switching tube S2, the collector of the switching tube S3, the collector of the switching tube S4 and the positive electrode of the switching capacitor C1; the emitter of the switching S2 is connected to the collector of the switching tube S9 and one end of the filter inductor Lf; the emitter of the switching tube S4 is connected to the collector of the switching tube S5 and the positive electrode of the switching capacitor C2; the negative electrode of the switching capacitor C1 is connected to the emitter of the switching tube S5, the collector of the switching tube S6 and the collector of the switching tube S8; the emitter of the switching tube S6 is connected to the emitter of the switching tube S7; the negative electrode of the switching capacitor C2 is connected to the emitter of the switching tube S8, the emitter of the switching tube S9 and the emitter of the switching tube S10; the other end of the filter inductor Lf is connected to the positive electrode of the filter capacitor Cf and one end of the load Ro; the negative electrode of the photovoltaic cell PV is connected to the negative electrode of the DC input filter capacitor Cdc, the emitter of the switching tube S3, the emitter of the switching tube S7, the collector of the switching tube S10, the negative electrode of the filter capacitor Cf and the other end of the load Ro.

[0009] The further improvement of the present application is that the switch tube S6 and the switch tube S7 adopt the connection mode of reverse series in the common ground type five-level photovoltaic inverter circuit with the function of self-balancing of capacitor voltage, so that the current bidirectional flow of the branch is realized.

[0010] The further improvement of the present application is that the six working modes [M1, M2, M3, M4, M5, M6] of the inverter are defined; wherein the working mode M1 represents that the SPWM voltage output by the inverter is 2U PV ; the working mode M2 represents that the SPWM voltage output by the inverter is U PV ; the working mode M3 represents that the SPWM voltage output by the inverter is 0; the working mode M4 represents that the SPWM voltage output by the inverter is -U PV ; the working mode M5 represents that the SPWM voltage output by the inverter is -2U PV ; the working mode M6 represents that the SPWM voltage output by the inverter is -2U PV .

[0011] The present application also provides a control method of the common ground type five-level photovoltaic inverter with the function of self-balancing of capacitor voltage, which is used for controlling the common ground type five-level photovoltaic inverter circuit, and specifically includes the following steps:

[0012] The first step is that the sine wave reference signal uref is respectively intersected with the two same-phase superimposed triangular carriers uc1 and uc2 on the positive half axis and the two phase-shifted triangular carriers uc3 and uc4 on the negative half axis, when uref>uc1, a high level is output, when uref<uc1, a low level is output, the pre-processing signal A is generated, and the inverse of the pre-processing signal A is obtained; similarly, when uref>uc2, a high level is output, when uref<uc2, a low level is output, the pre-processing signal B is generated, and the inverse of the pre-processing signal B is obtained; when uref>uc3, a high level is output, when uref<uc3, a low level is output, the pre-processing signal C is generated, and the inverse of the pre-processing signal C is obtained; when uref>uc4, a high level is output, when uref<uc4, a low level is output, the pre-processing signal D is generated, and the inverse of the pre-processing signal D is obtained;

[0013] Second step: according to the preprocessed signal generated in the first step, the logic control signal of each switch tube is determined combined with the signal state under different working modes. Specifically, the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signal ug1 of the switch tube S1; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, and the AND operation result and the preprocessed signal A are operated with OR to obtain the driving signal ug2 of the switch tube S2; the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the two are operated with OR to obtain the driving signal ug3 of the switch tube S3; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signals ug4 and ug6 of the switch tubes S4 and S6; the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the two and the preprocessed signal A are operated with OR to obtain the driving signal ug5 of the switch S5; the inverse signals of the preprocessed signal C and the preprocessed signal D are operated with AND to obtain the driving signals ug6 and ug7 of the switch tubes S6 and S7; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signal ug8 of the switch tube S8; the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the four are operated with OR to obtain the driving signal ug9 of the switch tube S9; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the two and the preprocessed signal A are operated with OR to obtain the driving signal ug10 of the switch tube S10.

[0014] Further improvement of the present application is to define the switch state configuration of each working mode of the inverter, specifically: the switch state of working mode M1 is [0, 1, 0, 0, 1, 0, 0, 0, 0, 1], the switch state of working mode M2 is [1, 1, 0, 1, 0, 0, 0, 1, 0, 1], the switch state of working mode M3 is [1, 0, 0, 1, 0, 0, 0, 1, 1, 1], the switch state of working mode M4 is [1, 0, 0, 0, 1, 1, 1, 0, 1, 0], the switch state of working mode M5 is [0, 0, 1, 1, 0, 0, 0, 1, 1, 0], the switch state of working mode M6 is [0, 0, 1, 0, 1, 0, 0, 0, 1, 0], wherein 0 represents IGBT switch tube off, and 1 represents IGBT switch tube on.

[0015] The present application has the beneficial effects that: the present application provides a common ground type five-level photovoltaic inverter with a capacitor voltage self-balancing function, wherein the photovoltaic panel on the DC side is connected with the load on the AC side in a common ground mode, and the parasitic capacitor of the photovoltaic panel to the ground is short-circuited, thereby effectively eliminating the influence of the leakage current. The inverter cooperates with the control signals of the switch capacitor and the switch tube to output a five-level voltage with a voltage doubler in the whole working cycle, and the output voltage range is 0, ±U PV , ±2U PV . The five-level design improves the output voltage amplitude, improves the utilization rate of the DC voltage, suppresses the generation of harmonics, and reduces the size of the filter. The inverter constructs two working modes with an output voltage of -U PV , thereby realizing the self-balancing of the charging and discharging of the switch capacitor voltage. This design effectively avoids the continuous discharge of the capacitor C2 in the negative half cycle of the inverter output, significantly reduces the capacitor voltage ripple, and further improves the quality of the inverter output voltage waveform. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is the main circuit structure diagram of the present application.

[0017] Figure 2 It is the logic control principle diagram of the present application.

[0018] Figure 3 It is the drive signal timing diagram of the present application.

[0019] Figure 4 It is the schematic diagram of mode one in the present application.

[0020] Figure 5 It is the schematic diagram of mode two in the present application.

[0021] Figure 6 It is the schematic diagram of mode three in the present application.

[0022] Figure 7 is a schematic diagram of mode four in the present application.

[0023] Figure 8 is a schematic diagram of mode five in the present application.

[0024] Figure 9 is a schematic diagram of mode six in the present application.

[0025] Figure 10 is an output SPWM voltage waveform diagram of the present application.

[0026] Figure 11 is a leakage current waveform diagram of the present application.

[0027] Figure 12 is a switched capacitor waveform diagram of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is described in detail below in combination with the drawings and specific embodiments.

[0029] It is emphasized that in the description of the present application, various formulas and constraints are respectively distinguished by consistent symbols before and after, but different symbols are not excluded to mark the same formula and / or constraint, and the purpose of such setting is to make the features of the present application more clear.

[0030] In order to improve the DC voltage utilization rate of the inverter, improve the output voltage quality and realize zero leakage current, the present application provides a common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, as shown in Figure 1 the formula, including a photovoltaic cell PV, a five-level inverter circuit with capacitor voltage self-balancing function, a single-phase output LC filter circuit and a single-phase load. The five-level inverter circuit includes a DC input filter capacitor Cdc, two switched capacitors C1 and C2, and ten switching tubes S1-S10, wherein the switching tube S1 is an IGBT without freewheeling diode, and the switching tubes S2-S9 are IGBTs with freewheeling diode. The single-phase output LC filter circuit and the single-phase load include a filter inductor Lf, a filter capacitor Cf and a single-phase load Ro.

[0031] The positive electrode of the photovoltaic cell PV is connected with the positive electrode of the direct current input filter capacitor Cdc and the collector of the switch tube S1; the emitter of the switch tube S1 is connected with the collector of the switch tube S2, the collector of the switch tube S3, the collector of the switch tube S4 and the positive electrode of the switch capacitor C1; the emitter of the switch S2 is connected with the collector of the switch tube S9 and one end of the filter inductor Lf; the emitter of the switch tube S4 is connected with the collector of the switch tube S5 and the positive electrode of the switch capacitor C2; the negative electrode of the switch capacitor C1 is connected with the emitter of the switch tube S5, the collector of the switch tube S6 and the collector of the switch tube S8; the emitter of the switch tube S6 is connected with the emitter of the switch tube S7; the negative electrode of the switch capacitor C2 is connected with the emitter of the switch tube S8, the emitter of the switch tube S9 and the emitter of the switch tube S10; the other end of the filter inductor Lf is connected with the positive electrode of the filter capacitor Cf and one end of the load Ro; the negative electrode of the photovoltaic cell PV is connected with the negative electrode of the direct current input filter capacitor Cdc, the emitter of the switch tube S3, the emitter of the switch tube S7, the collector of the switch tube S10, the negative electrode of the filter capacitor Cf and the other end of the load Ro.

[0032] The common ground type five-level photovoltaic inverter circuit with the capacitor voltage self-balancing function is provided with the switch tube S7, wherein the switch tube S6 and the switch tube S7 form a pair of reverse series switch combination, so that the current bidirectional flow of the branch is realized. Meanwhile, the switch combination also provides a charging path for the switch capacitor C1, a discharging path for the switch capacitor C2 and an energy feedback path.

[0033] The embodiment also provides a control method of the common ground type five-level photovoltaic inverter with the capacitor voltage self-balancing function, which specifically comprises the following steps: Figure 2 and Figure 3 as shown in the drawings, specifically comprising the following steps:

[0034] Firstly, the sine wave reference signal uref is respectively intersected with two road in-phase superimposed triangular carrier uc1 and uc2 on the positive half axis and two road phase-shifted triangular carrier uc3 and uc4 on the negative half axis, when uref>uc1, a high level is outputted, when uref<uc1, a low level is outputted, a pre-processing signal A is generated, and the inverse of the pre-processing signal A is taken to obtain a pre-processing signal a; similarly, when uref>uc2, a high level is outputted, when uref<uc2, a low level is outputted, a pre-processing signal B is generated, and the inverse of the pre-processing signal B is taken to obtain a pre-processing signal b; when uref>uc3, a high level is outputted, when uref<uc3, a low level is outputted, a pre-processing signal C is generated, and the inverse of the pre-processing signal C is taken to obtain a pre-processing signal c. Similarly, when uref>uc4, a high level is outputted, when uref<uc4, a low level is outputted, a pre-processing signal D is generated, and the inverse of the pre-processing signal D is taken to obtain a pre-processing signal d;

[0035] Second step: according to the preprocessed signal generated in the first step, the logic control signal of each switch tube is determined combined with the signal state under different working modes. Specifically, the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signal ug1 of the switch tube S1; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, and the AND operation result and the preprocessed signal A are operated with OR to obtain the driving signal ug2 of the switch tube S2; the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the two are operated with OR to obtain the driving signal ug3 of the switch tube S3; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signals ug4 and ug6 of the switch tubes S4 and S6; the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the two and the preprocessed signal A are operated with OR to obtain the driving signal ug5 of the switch S5; the inverse signals of the preprocessed signal C and the preprocessed signal D are operated with AND to obtain the driving signals ug6 and ug7 of the switch tubes S6 and S7; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the three are operated with OR to obtain the driving signal ug8 of the switch tube S8; the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal d of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the preprocessed signal D are operated with AND, the inverse signal c of the preprocessed signal C and the inverse signal d of the preprocessed signal D are operated with AND, and the AND operation results of the four are operated with OR to obtain the driving signal ug9 of the switch tube S9; the inverse signal a of the preprocessed signal A and the preprocessed signal B are operated with AND, the inverse signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D are operated with AND, and the AND operation results of the two and the preprocessed signal A are operated with OR to obtain the driving signal ug10 of the switch tube S10.

[0036] Therefore, by the above control method, the inverter can switch among six working modes [M1, M2, M3, M4, M5, M6], each corresponding to different output SPWM voltage and corresponding switching state; wherein working mode M1 means that the inverter outputs SPWM voltage 2U PV , and the corresponding switching state is [0, 1, 0, 0, 1, 0, 0, 0, 0, 1]; working mode M2 means that the inverter outputs SPWM voltage U PV , and the corresponding switching state is [1, 1, 0, 1, 0, 0, 0, 1, 0, 1]; working mode M3 means that the inverter outputs SPWM voltage 0, and the corresponding switching state is [1, 0, 0, 1, 0, 0, 0, 1, 1, 1]; working mode M4 means that the inverter outputs SPWM voltage -U PV , and the corresponding switching state is [1, 0, 0, 0, 1, 1, 1, 0, 1, 0]; working mode M5 means that the inverter outputs SPWM voltage -U PV , and the corresponding switching state is [0, 0, 1, 1, 0, 0, 0, 1, 1, 0]; working mode M6 means that the inverter outputs SPWM voltage -2U PV , and the corresponding switching state is [0, 0, 1, 0, 1, 0, 0, 0, 1, 0].

[0037] The above working modes are shown in Figures 4 to 9 , and the working principle of the inverter in each working mode is analyzed as follows:

[0038] Mode 1: as shown in Figure 4 , in this mode, the switching state of the inverter is [0, 1, 0, 0, 1, 0, 0, 0, 0, 1], and the switching tubes S2, S5 and S10 are in the on state, and the switching tubes S1, S3, S4, S6, S7, S8 and S9 are in the off state. The current flows out from the positive electrode of the switching capacitor C1, flows through S4-S2-Lf-Ro-S10, and then returns to the negative electrode of the switching capacitor C2, and the switching tube S5 makes the two switching capacitors C1 and C2 in series. At this time, both switching capacitors are in the forward discharge state, and the inverter outputs SPWM voltage 2U PV .

[0039] Mode 2: as shown in Figure 5As shown, in this mode, the inverter's switching state is [1,1,0,1,0,0,0,1,0,1], with switches S1, S2, S4, S8, and S10 in the ON state, and switches S3, S5, S6, S7, and S9 in the OFF state. Current flows from the positive terminal of the photovoltaic cell (PV), passing through S1-C1-S8-S10, S1-S4-C2-S10, and S1-S2-Lf-Ro, and finally returning to the negative terminal of the PV cell. At this time, both switching capacitors C1 and C2 are charging, and the DC-side photovoltaic cell (PV) directly supplies power to the load. The inverter outputs an SPWM voltage of U. PV .

[0040] Modal 3: such as Figure 6 As shown, in this mode, the inverter's switching state is [1,0,0,1,0,0,0,1,1,1], with switches S1, S4, S8, S9, and S10 in the ON state, and switches S2, S3, S5, S6, and S7 in the OFF state. Current flows from the positive terminal of the photovoltaic cell (PV), through S1-C1-S8-S10 and S1-S4-C2-S10 respectively, and then back to the negative terminal of the photovoltaic cell (PV). Simultaneously, the current in the filter and load freewheels in the loop formed by S9 and S10. At this time, both switched capacitors C1 and C2 remain charged, and the inverter output SPWM voltage is 0.

[0041] Modal 4: such as Figure 7 As shown, in this mode, the inverter's switching state is [1,0,0,0,1,1,1,0,1,0], with switches S1, S5, S6, S7, and S9 in the ON state, and switches S2, S3, S4, S8, and S10 in the OFF state. Current flows from the positive terminal of the photovoltaic cell (PV), through S1-C1-S6-S7, and then back to the negative terminal of the PV cell. Simultaneously, current flows from the positive terminal of the switching capacitor C2, through S5-S6-S7-Ro-Lf-S9, and back to the negative terminal of the switching capacitor C2. At this time, the DC-side photovoltaic cell (PV) charges the switching capacitor C1 through the loop, and the switching capacitor C2 discharges to the load. The inverter outputs an SPWM voltage of -U. PV .

[0042] Modal 5: such as Figure 8 As shown, in this mode, the inverter's switching state is [0,0,1,1,0,0,0,1,1,0], with switches S3, S4, S8, and S9 in the ON state, and switches S1, S2, S5, S6, S7, and S10 in the OFF state. Because the voltage of switched capacitor C1 is high, current flows from its positive terminal, sequentially through S4-C2-S8, and back to the negative terminal of switched capacitor C1. When the voltages of both switched capacitors C1 and C2 reach U... PVThen, the current flows through S3-Ro-Lf-S9. At this time, switched capacitor C1 charges switched capacitor C2, and then the two discharge in parallel. The inverter outputs an SPWM voltage of -U. PV .

[0043] Modal 6: such as Figure 9 As shown, in this mode, the inverter's switching state is [0,0,1,0,1,0,0,0,1,0], with switches S3, S5, and S9 in the ON state, and switches S1, S2, S4, S6, S7, S8, and S10 in the OFF state. Current flows from the positive terminal of switched capacitor C2, through C2-S5-C1-S3-Ro-Lf-S9, and finally back to the negative terminal of switched capacitor C2. At this time, both switched capacitors C1 and C2 are in reverse discharge mode, and the inverter output SPWM voltage is -2U. PV .

[0044] Table 1 shows the switching state, switched capacitor state, and output SPWM voltage of a common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function under different operating modes.

[0045] Table 1. Switching transistor status, switched capacitor status, and output SPWM voltage under each operating mode of the inverter.

[0046]

[0047]

[0048] Based on the above specific implementation scheme, the ground-type five-level photovoltaic inverter with capacitor voltage self-balancing function of the present invention was simulated using MATLAB / Simulink, and its output SPWM voltage waveform and leakage current waveform were obtained, as shown below. Figure 10 and Figure 11 As shown. The peak SPWM voltage output by this inverter reaches 2U. PV This results in five voltage levels: 0, ±U PV and ±2U PV Compared to traditional three-level inverters, this design significantly reduces output harmonic content, decreases filter size, and simultaneously improves output voltage amplitude and DC voltage utilization. Furthermore, this topology effectively eliminates leakage current through a common ground configuration, and simulation results show that zero leakage current is achieved.

[0049] As shown in the table above, this inverter constructs two output voltages of -U PV The operating mode of the switched capacitors was optimized to achieve self-balancing of charging and discharging, effectively preventing continuous discharge of capacitor C2 during the negative half-cycle, significantly reducing capacitor voltage ripple, and improving the quality of the output voltage waveform. The simulated waveforms of switched capacitors C1 and C2 are shown below. Figure 12As shown.

[0050] In summary, the application provides a common ground type five-level photovoltaic inverter with a self-balancing function of capacitor voltage, which has the following advantages: the topology eliminates the system leakage current through the common ground connection of the DC side and the AC side, and improves the safety; the voltage utilization rate is improved and the voltage harmonic is effectively reduced by using the voltage doubler five-level output technology; the self-balancing of the switching capacitor voltage is realized by increasing the inverter working mode, the capacitor voltage ripple is reduced, and the quality of the output voltage waveform is improved.

[0051] The above examples are only used to illustrate the technical solutions of the application and not to limit it. Although the application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the application.

Claims

1. A common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function, characterized in that: It includes a photovoltaic cell PV, a five-level inverter circuit with a capacitor voltage self-balancing function, a single-phase output LC filter circuit, and a single-phase load; the five-level inverter circuit includes a DC input filter capacitor Cdc, two switching capacitors C1, C2, and ten switching tubes S1~S10, where the switching tube S1 is an IGBT without a freewheeling diode, and the switching tubes S2~S10 are all IGBTs with freewheeling diodes; the single-phase output LC filter circuit and the single-phase load include a filter inductor Lf, a filter capacitor Cf, and a single-phase load Ro; the positive pole of the photovoltaic cell PV is connected to the positive pole of the DC input filter capacitor Cdc and the collector of the switching tube S1; the emitter of the switching tube S1 is connected to the collectors of the switching tube S2, the switching tube S3, the switching tube S4, and the positive pole of the switching capacitor C1; the emitter of the switch S2 is connected to the collector of the switching tube S9 and one end of the filter inductor Lf; the emitter of the switching tube S4 is connected to the collector of the switching tube S5 and the positive pole of the switching capacitor C2; the negative pole of the switching capacitor C1 is connected to the emitters of the switching tube S5, the collector of the switching tube S6, and the collector of the switching tube S8; the emitter of the switching tube S6 is connected to the emitter of the switching tube S7; the negative pole of the switching capacitor C2 is connected to the emitters of the switching tube S8, the emitter of the switching tube S9, and the emitter of the switching tube S10; the other end of the filter inductor Lf is connected to the positive pole of the filter capacitor Cf and one end of the load Ro; the negative pole of the photovoltaic cell PV is connected to the negative pole of the DC input filter capacitor Cdc, the emitter of the switching tube S3, the emitter of the switching tube S7, the collector of the switching tube S10, the negative pole of the filter capacitor Cf, and the other end of the load Ro.

2. The common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: The switching tubes S6 and S7 are connected in reverse series to enable bidirectional current flow in this branch.

3. The common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: Define six operating modes for the inverter [M1, M2, M3, M4, M5, M6]; where operating mode M1 indicates that the inverter output SPWM voltage is 2U. PV Operating mode M2 ​​indicates that the inverter output SPWM voltage is U. PV Operating mode M3 indicates that the inverter output SPWM voltage is 0; operating mode M4 indicates that the inverter output SPWM voltage is -U. PV At this time, switched capacitor C1 is charging, and switched capacitor C2 provides energy to the load; operating mode M5 indicates that the inverter output SPWM voltage is -U PV At this time, switched capacitor C1 charges capacitor C2, and then the two are connected in parallel to supply power to the load; operating mode M6 indicates that the inverter output SPWM voltage is -2U. PV .

4. The common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: The control method of the common-ground photovoltaic inverter specifically includes the following steps: The first step: The sine wave reference signal uref is respectively compared with two positive half-axis in-phase stacked triangular carriers uc1, uc2 and two negative half-axis phase-shifted triangular carriers uc3, uc4. When uref>uc1, a high level is output; when uref<uc1, a low level is output to generate a preprocessing signal A, and its inverse is taken to obtain a preprocessing signal a; similarly, when uref>uc2, a high level is output; when uref<uc2, a low level is output to generate a preprocessing signal B, and its inverse is taken to obtain a preprocessing signal b; when uref>uc3, a high level is output; when uref<uc3, a low level is output to generate a preprocessing signal C, and its inverse is taken to obtain a preprocessing signal c; when uref>uc4, a high level is output; when uref<uc4, a low level is output to generate a preprocessing signal D, and its inverse is taken to obtain a preprocessing signal d; Step 2: Based on the preprocessed signals generated in Step 1, and combined with the signal states under different operating modes, determine the logic control signals for each switch. Specifically, perform an AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B; perform an AND operation on the inverted signal b of preprocessed signal B and preprocessed signals C and D; perform an AND operation on preprocessed signals C and the inverted signal d of preprocessed signal D; then perform an OR operation on the result of the three AND operations to obtain the drive signal ug1 for switch S1; perform an AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B; then perform an OR operation on the result of the AND operation and preprocessed signal A to obtain the drive signal ug2 for switch S2; perform an AND operation on the inverted signal a of preprocessed signal A and preprocessed signal B; then perform an OR operation on the result of the AND operation and preprocessed signal A to obtain the drive signal ug2 for switch S2; perform an AND operation on the preprocessed signal... The inverted signal c of signal C and the preprocessed signal D are ANDed together. The inverted signal c of preprocessed signal C and the inverted signal d of preprocessed signal D are then ANDed together. Finally, the result of the AND operation is ORed to obtain the drive signal ug3 for switch S3. The inverted signal a of preprocessed signal A and preprocessed signal B are ANDed together. The inverted signal b of preprocessed signal B is ANDed together with preprocessed signals C and D. The inverted signal c of preprocessed signal C and preprocessed signal D are then ANDed together. Finally, the result of the AND operation is ORed to obtain the drive signals ug4 and ug6 for switches S4 and S6. The inverted signal d of preprocessed signal C and preprocessed signal D are then ANDed together. The inverted signal c of C and the inverted signal d of preprocessed signal D are ANDed together, and then the result of the AND operation is ORed with the preprocessed signal A to obtain the drive signal ug5 for switch S5; the inverted signals c of preprocessed signal C and D are ANDed together to obtain the drive signals ug6 and ug7 for switches S6 and S7; the inverted signal a of preprocessed signal A and preprocessed signal B are ANDed together, the inverted signal b of preprocessed signal B is ANDed together with preprocessed signals C and D, the inverted signal c of preprocessed signal C and preprocessed signal D are ANDed together, and then the result of the AND operation is ORed to obtain the drive signal ug8 for switch S8; the inverted signal c of preprocessed signal B is ANDed together with the preprocessed signal D, and then the result of the AND operation is ORed with the preprocessed signal A to obtain the drive signal ug8 for switch S8; the inverted signal d of preprocessed signal B is ANDed together with the preprocessed signal D, and then the result of the AND operation is ORed ... The inverted signal b is ANDed with the preprocessed signals C and D. The inverted signal d of preprocessed signal C and D is ANDed with the inverted signal c of preprocessed signal C and D. The inverted signal c of preprocessed signal C and the inverted signal d of preprocessed signal D are ANDed with the inverted signal c of preprocessed signal C and the inverted signal d of preprocessed signal D. The result of the AND operation of the four signals is then ORed with the result of the AND operation of the two signals to obtain the drive signal ug9 of the switch S9. The inverted signal a of preprocessed signal A and preprocessed signal B are ANDed with the inverted signal b of preprocessed signal B, preprocessed signal C and preprocessed signal D. The result of the AND operation of the two signals is then ORed with the result of the AND operation of preprocessed signal A to obtain the drive signal ug10 of the switch S10.

5. The common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 4, characterized in that: Define the switching state configuration for each operating mode of the inverter as follows: the switching state for operating mode M1 is [0,1,0,0,1,0,0,0,0,1], the switching state for operating mode M2 ​​is [1,1,0,1,0,0,0,1,0,1], the switching state for operating mode M3 is [1,0,0,1,0,0,0,1,1,1], the switching state for operating mode M4 is [1,0,0,0,1,1,1,0,1,0], the switching state for operating mode M5 is [0,0,1,1,0,0,0,1,1,0], and the switching state for operating mode M6 is [0,0,1,0,1,0,0,0,1,0], where 0 indicates that the IGBT switch is off and 1 indicates that the IGBT switch is on.

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