A switched capacitor amplifier

Abstract

The present application discloses a switched capacitor amplifier, which relates to the field of analog or mixed analog-digital integrated circuit technology. The amplifier includes a bias circuit, a first-stage transconductance amplifier, and a second-stage transconductance amplifier. When the amplifier is operating in the amplification state, a large current is required to enable the amplifier to quickly establish. The technology proposed in the present invention can provide a large current. When the amplifier is operating in the reset state, it only needs to provide the correct operating point and does not require a large current. The technology proposed in the present invention can reduce the current to a set value, which can minimize the power consumption of the amplifier. This changes the disadvantage of the traditional structure that the current of the amplifier in the reset state and the amplification state is not adjusted, resulting in a large power consumption of the amplifier. The technology proposed in the present invention can switch the amplifier gain according to the different operating modes of the amplifier, changing the disadvantage of the traditional structure that the gain cannot be changed.

Description

Technical Field

[0001] The present application relates to the technical field of analog or mixed analog and digital integrated circuits, and in particular to a switched capacitor amplifier. Background Art

[0002] As an important module of analog circuits, amplifiers are widely used in various analog integrated circuits and mixed analog and digital integrated circuits. Among them, switched capacitor amplifiers are an important application of amplifiers.

[0003] The two-stage switched capacitor amplifier traditionally used in switched capacitor circuits includes a bias circuit, a first-stage transconductance amplifier, and a second-stage transconductance amplifier. Figure 1 This is the bias circuit for a traditional two-stage switched capacitor amplifier. A constant current source IB is injected into the drain of NMOS transistor M0. NMOS transistor M0 is diode-connected. The gate of NMOS transistor M0 is connected to the gate of NMOS transistor M1. The sources of NMOS transistors M0 and M1 are both grounded. The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3. The source of PMOS transistor M3 is connected to the drain of PMOS transistor M4. Both PMOS transistors M3 and PMOS transistors M4 are diode-connected. The source of PMOS transistor M4 is connected to power supply Vdd. The gate of PMOS transistor M5 is connected to the gate of PMOS transistor M4. The source of PMOS transistor M5 is connected to power supply Vdd. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M6. The gate of PMOS transistor M6 is connected to the gate of PMOS transistor M3. The drain of PMOS transistor M6 is connected to the drain of NMOS transistor M2. NMOS transistor M2 is diode-connected, its source is grounded, and its gate and drain bias voltage is vn1. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M6. The source of PMOS transistor M7 is connected to the drain of PMOS transistor M8. The source of PMOS transistor M8 is connected to the power supply vdd. The gate of PMOS transistor M8 is connected to the drain of PMOS transistor M7. The gate bias voltage of PMOS transistor M8 is vb1. The drain of PMOS transistor M7 is connected to the drain of NMOS transistor M9. The source of NMOS transistor M9 is grounded, and the gate of NMOS transistor M9 is connected to the gate of NMOS transistor M1. Vn1, vb, and vb1 provide fixed bias voltages for the gain stage of the switched capacitor amplifier. Figure 2This is the first-stage transconductance amplifier of a traditional two-stage switched capacitor amplifier. PMOS transistors M10, M11, M12, M13, M14, and M15 form the input stage of the first-stage transconductance amplifier. PMOS transistors M10 and M11 form the input differential pair of transistors, with the gates of PMOS transistors M10 and M11 connected to input signals VP and VM, respectively. PMOS transistors M12, M13, M14, and M15 form a cascode structure. The gates of PMOS transistors M12 and M13 are connected to a fixed bias voltage vb, while their drains are also connected. The gates of PMOS transistors M14 and M15 are connected to a fixed bias voltage vb1, with bias voltages vb and vb1 being fixed bias voltages. The NMOS transistors M16, M17, M18, M19, M20, M21, M22, M23, M24, M25 and M39 and the PMOS transistors M26, M27, M28, M29, M30 and M31 constitute a first gain stage of a first transconductance amplifier. Among them, the PMOS transistors M26, M27, M28, M29, M30 and M31 constitute a gain bootstrap structure, and the NMOS transistors M16, M17, M18, M19, M20, M21, M22, M23, M24, M25 and M39 constitute a negative resistance structure. The function of the above structures is to increase the output impedance of the first gain stage. Figure 3 This is the second-stage transconductance amplifier of a traditional two-stage switched capacitor amplifier. NMOS transistors M32 and M33 form the input differential pair of the second-stage transconductance amplifier. The gates of NMOS transistors M32 and M33 are connected to the output signals vo1 and vo2 of the first-stage transconductance amplifier, respectively. PMOS transistors M34, M35, M36, and M37 are load transistors, providing the first-stage gain of the first-stage transconductance amplifier. vb1 and vb are fixed bias voltages.

[0004] The disadvantages of the above-mentioned traditional amplifier structure are: 1. The various bias voltages of the amplifier are fixed bias voltages, so that the bias current of the amplifier remains unchanged regardless of whether the amplifier is operating in the reset state or the amplification state, and thus the power consumption does not change. In practical applications, when the amplifier is operating in the amplification state, it often needs to establish a large signal, which requires a large current; when the amplifier is operating in the reset state, it only needs to provide the correct operating point, and does not need to provide a large current. However, in the traditional structure, there is no distinction between the current when the amplifier is operating in the reset state and the amplification state. Therefore, in order to meet the amplifier's establishment time in the amplification state, a large power consumption is also consumed in the reset state, resulting in high power consumption of the amplifier. 2. In the traditional amplifier structure, the amplifier has the same gain in the reset phase and the amplification phase. Since the amplifier has an offset voltage, the offset voltage needs to be eliminated. However, high gain can cause the amplifier to exit the saturation region during the offset storage phase, affecting the amplifier's accuracy.

[0005] In view of this, a switched capacitor amplifier is urgently needed. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the present application proposes a switched capacitor amplifier, which solves the problem in the prior art that the current of the amplifier is not adjusted when it is working in the reset state and the amplification state, resulting in high power consumption of the amplifier and the inability to change the gain of the amplifier in the reset and amplification states.

[0007] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions:

[0008] A switched capacitor amplifier comprises a bias circuit, a first-stage transconductance amplifier, and a second-stage transconductance amplifier, wherein:

[0009] The bias circuit includes a constant current source IB, which is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in a diode connection form. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, the source of the PMOS tube M4 is connected to the power supply VDD; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply VDD, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The source of the PMOS transistor M6 is connected, and the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M3; the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M2, and the NMOS transistor M2 is in a diode connection form. The source of the NMOS transistor M2 is grounded, and the gate and drain bias voltage of the NMOS transistor M2 is vn1; the gate of the NMOS transistor M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of the capacitor C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of both the switch k4 and the switch k4n, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn;

[0010] The device further includes a PMOS transistor M7, wherein the gate of the PMOS transistor M7 is connected to the gate of the PMOS transistor M6, the source of the PMOS transistor M7 is connected to the drain of the PMOS transistor M8, the source of the PMOS transistor M8 is connected to the power supply vdd, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M7, the gate bias voltage of the PMOS transistor M8 is vb1, the drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M47, the source of the NMOS transistor M47 is grounded, and the gate of the NMOS transistor M47 is connected to the gate of the NMOS transistor M1; the gate of the PMOS transistor M8 is connected to one end of the capacitor C2 via a switch k1, one end of the capacitor C1, and a switch k1n in sequence, the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is connected to one end of both the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to a fixed bias voltage vb.

[0011] As an optional technical solution, when the switched capacitor amplifier is in the reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off;

[0012] One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through the turned-on switch k4, and one end is reset phase adjustable bias voltage vn2. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time.

[0013] One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

[0014] As an optional technical solution, when the switched capacitor amplifier is in the amplification phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off;

[0015] The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the law of conservation of charge, at this time vn2 = vn1 + C4 (vdd - vn) / (C3 + C4). Therefore, vn2 in the amplification phase is higher than vn2 in the reset phase by C4 (vdd - vn) / (C3 + C4).

[0016] The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2 = vb1 - C2 (vb2 - vb) / (C1 + C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2 (vb2 - vb) / (C1 + C2).

[0017] As an optional technical solution, the first-stage transconductance amplifier includes an input stage of a first-stage transconductance amplifier composed of PMOS transistors M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of the first-stage transconductance amplifier composed of NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS transistors M23, M24, M25, M26, M27, M28, M29, M30; wherein:

[0018] The PMOS transistors M9 and M10 are input differential pair transistors, and the gates of the PMOS transistors M9 and M10 are connected to the input signals VP and VM respectively; the PMOS transistors M11, M12, M13, M14, M15 and M16 are cascode structures; the gates of the PMOS transistors M11 and M12 are connected and connected to a fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS transistors M9 and M10; the gates of the PMOS transistors M13 and M15 are connected and connected to a fixed bias voltage vb1, the drains of the PMOS transistors M13 and M14 are connected and connected to the source of the PMOS transistor M12; the gates of the PMOS transistors M14 and M16 are connected and connected to a variable bias voltage vb2, the drains of the PMOS transistors M15 and M16 are connected and connected to the source of the PMOS transistor M11; the sources of the PMOS transistors M13, M14, M15 and M16 are all connected to the power supply voltage vdd;

[0019] The PMOS transistors M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

[0020] It should be noted that the PMOS tubes M21 and M22 are part of the gain bootstrap structure and are also included in the negative resistance structure, which is uniformly described here as a negative resistance structure.

[0021] As an optional technical solution, the gain bootstrap structure is as follows: the PMOS transistors M29 and M23 form a common source and common gate structure, with the gate connected to a fixed bias voltage vb1; the gate of the PMOS transistor M24 is connected to a variable bias voltage vb2;

[0022] The drain of the PMOS transistor M29 is simultaneously connected to the gate of the NMOS transistor M21, the source of the NMOS transistor M48, the common drain of the NMOS transistors M17 and M18, and the gate of the NMOS transistor M35. The gate is simultaneously connected to the drain of the NMOS transistor M21 and the drain of the PMOS transistor M27. The source is simultaneously connected to the drain of the PMOS transistor M23, the drain of the PMOS transistor M24, and the gate of the PMOS transistor M27. The sources of the PMOS transistors M23, M24, and M27 are all connected to the power supply voltage vdd. The source of the NMOS transistor M21 is grounded.

[0023] The PMOS transistors M30 and M25 form a common source and common gate structure, and the gates are connected to a fixed bias voltage vb1; the gate of the PMOS transistor M26 is connected to a variable bias voltage vb2;

[0024] The drain of the PMOS transistor M30 is simultaneously connected to the gate of the NMOS transistor M22, the drain of the NMOS transistor M48, the common drain of the NMOS transistors M19 and M20, and the gate of the NMOS transistor M34. The gate is simultaneously connected to the drain of the NMOS transistor M22 and the drain of the PMOS transistor M28. The source is simultaneously connected to the drain of the PMOS transistor M25, the drain of the PMOS transistor M26, and the gate of the PMOS transistor M28. The sources of the PMOS transistors M25, M26, and M28 are all connected to the power supply voltage vdd. The source of the NMOS transistor M22 is grounded.

[0025] As an optional technical solution, the negative resistance structure is as follows: the NMOS transistors M17, M31, M32 and M33 form a common source and common gate structure, the gate of which is connected to a fixed bias voltage vn, the gate of the NMOS transistor M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS transistor M33 is connected to a variable bias voltage vn2;

[0026] The source of the NMOS transistor M17 is simultaneously connected to the source of the NMOS transistor M18 and the drains of the NMOS transistors M31, M32, M33, and M34. The gate of the NMOS transistor M18 is simultaneously connected to the gates of the NMOS transistors M48 and M19. The gate of the NMOS transistor M31 is connected to the drain of the NMOS transistor M49. The source of the NMOS transistor M49 is connected to the gate of the NMOS transistor M35, and the gate is connected to the switch K5n. The sources of the NMOS transistors M31, M32, M33, and M34 are all grounded.

[0027] The NMOS transistors M20, M36, M37 and M38 form a common source and common gate structure, with the gate connected to a fixed bias voltage vn, the gate of the NMOS transistor M37 connected to a fixed bias voltage vn1, and the gate of the NMOS M36 connected to a variable bias voltage vn2;

[0028] The source of the NMOS transistor M20 is simultaneously connected to the source of the NMOS transistor M19 and the drains of the NMOS transistors M35, M36, M37, and M38. The gate of the NMOS transistor M38 is connected to the source of the NMOS transistor M50. The drain of the NMOS transistor M50 is connected to the gate of the NMOS transistor M34, and the gate is connected to the switch K6n. The sources of the NMOS transistors M35, M36, M37, and M38 are all grounded.

[0029] The common end of the NMOS transistor M35 and the PMOS transistor M29 serves as the first differential signal output end of the first-stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS transistor M34 and the PMOS transistor M30 serves as the second differential signal output end of the first-stage transconductance amplifier, outputting the signal vo2.

[0030] As an optional technical solution, the second-stage transconductance amplifier includes a differential input pair of NMOS transistors M39 and M40, wherein the sources of the NMOS transistors M39 and M40 are connected and connected to one end of the resistor R, the other end of the resistor R is grounded, and the gates of the NMOS transistors M39 and M40 are connected to the signal vo1 and the signal vo2, respectively.

[0031] The drains of the NMOS transistors M39 and M40 are connected to the drains of the PMOS transistors M42 and M43 respectively, the sources of the PMOS transistors M42 and M43 are connected to the drains of the PMOS transistors M44 and M45 respectively, and the sources of the PMOS transistors M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS transistors M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS transistors M42 and M43 are connected to the adjustable bias voltage vb2;

[0032] The circuit further includes an NMOS transistor M41, the drain of which is connected to the drain of the NMOS transistor M39 and the drain of the PMOS transistor M42, and the common end serves as the first differential signal output end of the second-stage transconductance amplifier, outputting the signal vop; the source of the NMOS transistor M41 is connected to the drain of the NMOS transistor M40 and the drain of the PMOS transistor M43, and the common end serves as the second differential signal output end of the second-stage transconductance amplifier, outputting the signal vom.

[0033] The beneficial effects of this application include:

[0034] When the amplifier is operating in the amplification state, a large current is required to enable the amplifier to quickly establish itself. The technology proposed in this invention can provide a large current. When the amplifier is operating in the reset state, it only needs to provide the correct operating point, not a large current. The technology proposed in this invention can reduce the current to a set value, thereby minimizing the power consumption of the amplifier. This changes the disadvantage of the traditional structure that does not adjust the current when the amplifier is operating in the reset state and the amplification state, resulting in high power consumption of the amplifier.

[0035] When the amplifier is operating in the reset state, the amplifier stores the offset voltage, and the first-stage amplifier switches to a low output impedance mode, operating in a low gain state. This allows the offset voltage to be stored while the amplifier's transistors remain in the saturation region. When the amplifier is operating in the amplification state, the first-stage amplifier output impedance switches to a high impedance mode, operating in a high gain state, achieving signal amplification. The technology proposed in this invention can switch the amplifier gain according to the different operating modes of the amplifier, overcoming the disadvantage of conventional structures where the amplifier gain cannot be changed in the reset and amplification states.

[0036] Other beneficial effects or advantages of the present application will be described in detail in conjunction with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive labor. In addition, it should be understood that the proportional relationship of the various components in the drawings of this specification does not represent the proportional relationship in the actual material selection and design. It is only a schematic diagram of the structure or position, among which:

[0038] Figure 1 The bias circuit schematic diagram of a traditional two-stage switched capacitor amplifier;

[0039] Figure 2 This is the schematic diagram of the first-stage transconductance amplifier of a traditional two-stage switched capacitor amplifier;

[0040] Figure 3 This is the schematic diagram of the second-stage transconductance amplifier of a traditional two-stage switched capacitor amplifier;

[0041] Figure 4 This is a schematic diagram of the bias circuit of the switched capacitor amplifier proposed in the present invention;

[0042] Figure 5This is a schematic diagram of the first-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention;

[0043] Figure 6 This is a schematic diagram of the second-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention;

[0044] Figure 7 This is an equivalent schematic diagram of the bias circuit in the reset state of the switched capacitor amplifier proposed by the present invention;

[0045] Figure 8 This is an equivalent schematic diagram of the first-stage transconductance amplifier in the reset state of the switched capacitor amplifier proposed by the present invention;

[0046] Figure 9 This is an equivalent schematic diagram of the second-stage transconductance amplifier in the reset state of the switched capacitor amplifier proposed by the present invention;

[0047] Figure 10 This is an equivalent schematic diagram of the bias circuit in the amplifying state of the switched capacitor amplifier proposed by the present invention;

[0048] Figure 11 This is an equivalent schematic diagram of the first-stage transconductance amplifier in the amplifying state of the switched capacitor amplifier proposed by the present invention;

[0049] Figure 12 This is an equivalent schematic diagram of the second-stage transconductance amplifier in the amplifying state of the switched capacitor amplifier proposed by the present invention;

[0050] Figure 13 This is a comparison diagram of the current changes of the reset and amplification phase amplifiers of the switched capacitor amplifier proposed by the present invention. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0053] In the description of this application, it should be noted that the terms used, such as "top" and "bottom," refer to the portion of the application near the top when in use as the top, and the portion near the bottom as the bottom; the terms used, such as "first" and "second," are used solely for distinction and do not indicate or imply a distinction in importance or order; and the terms used, such as "inner" and "outer," refer to the inside and outside of a specific outline. The use of the above terms is solely for the purpose of clearly and simply describing the technical solution of this application and should not be construed as limiting this application.

[0054] Example 1:

[0055] The present invention discloses a switched capacitor amplifier, comprising a bias circuit, a first-stage transconductance amplifier, and a second-stage transconductance amplifier, wherein:

[0056] like Figure 4 As shown, the bias circuit includes a constant current source IB, which is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in a diode connection form. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, the source of the PMOS tube M4 is connected to the power supply vdd; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply vdd, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The electrode of the PMOS transistor M6 is connected to the source of the PMOS transistor M6, and the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M3; the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M2, and the NMOS transistor M2 is in a diode connection form. The source of the NMOS transistor M2 is grounded, and the gate and drain bias voltage of the NMOS transistor M2 is vn1; the gate of the NMOS transistor M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of both the switch k4 and the switch k4n, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn;

[0057] The device further includes a PMOS transistor M7, wherein the gate of the PMOS transistor M7 is connected to the gate of the PMOS transistor M6, the source of the PMOS transistor M7 is connected to the drain of the PMOS transistor M8, the source of the PMOS transistor M8 is connected to the power supply vdd, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M7, the gate bias voltage of the PMOS transistor M8 is vb1, the drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M47, the source of the NMOS transistor M47 is grounded, and the gate of the NMOS transistor M47 is connected to the gate of the NMOS transistor M1; the gate of the PMOS transistor M8 is connected to one end of the capacitor C2 via a switch k1, one end of the capacitor C1, and a switch k1n in sequence, the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is connected to one end of both the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to a fixed bias voltage vb.

[0058] As an implementable solution:

[0059] like Figure 7 As shown, when the switched capacitor amplifier is in the reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off;

[0060] One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through the turned-on switch k4, and one end is reset phase adjustable bias voltage vn2. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time.

[0061] One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

[0062] On the contrary, if Figure 10 As shown, when the switched capacitor amplifier is in the amplifying phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off;

[0063] The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the law of conservation of charge, at this time vn2 = vn1 + C4 (vdd - vn) / (C3 + C4). Therefore, vn2 in the amplification phase is higher than vn2 in the reset phase by C4 (vdd - vn) / (C3 + C4).

[0064] The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2 = vb1 - C2 (vb2 - vb) / (C1 + C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2 (vb2 - vb) / (C1 + C2).

[0065] Furthermore, if Figure 5 The first-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention includes an input stage of a first-stage transconductance amplifier composed of PMOS transistors M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of the first-stage transconductance amplifier composed of NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS transistors M23, M24, M25, M26, M27, M28, M29 and M30; wherein:

[0066] The PMOS transistors M9 and M10 are input differential pair transistors, and the gates of the PMOS transistors M9 and M10 are connected to the input signals VP and VM respectively; the PMOS transistors M11, M12, M13, M14, M15 and M16 are cascode structures; the gates of the PMOS transistors M11 and M12 are connected and connected to a fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS transistors M9 and M10; the gates of the PMOS transistors M13 and M15 are connected and connected to a fixed bias voltage vb1, the drains of the PMOS transistors M13 and M14 are connected and connected to the source of the PMOS transistor M12; the gates of the PMOS transistors M14 and M16 are connected and connected to a variable bias voltage vb2, the drains of the PMOS transistors M15 and M16 are connected and connected to the source of the PMOS transistor M11; the sources of the PMOS transistors M13, M14, M15 and M16 are all connected to the power supply voltage vdd;

[0067] The PMOS transistors M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

[0068] As an implementable solution:

[0069] The gain bootstrap structure is as follows: the PMOS transistors M29 and M23 form a common source and common gate structure, with the gate connected to a fixed bias voltage vb1; the gate of the PMOS transistor M24 is connected to a variable bias voltage vb2;

[0070] The drain of the PMOS transistor M29 is simultaneously connected to the gate of the NMOS transistor M21, the source of the NMOS transistor M48, the common drain of the NMOS transistors M17 and M18, and the gate of the NMOS transistor M35. The gate is simultaneously connected to the drain of the NMOS transistor M21 and the drain of the PMOS transistor M27. The source is simultaneously connected to the drain of the PMOS transistor M23, the drain of the PMOS transistor M24, and the gate of the PMOS transistor M27. The sources of the PMOS transistors M23, M24, and M27 are all connected to the power supply voltage vdd. The source of the NMOS transistor M21 is grounded.

[0071] The PMOS transistors M30 and M25 form a common source and common gate structure, and the gates are connected to a fixed bias voltage vb1; the gate of the PMOS transistor M26 is connected to a variable bias voltage vb2;

[0072] The drain of the PMOS transistor M30 is simultaneously connected to the gate of the NMOS transistor M22, the drain of the NMOS transistor M48, the common drain of the NMOS transistors M19 and M20, and the gate of the NMOS transistor M34. The gate is simultaneously connected to the drain of the NMOS transistor M22 and the drain of the PMOS transistor M28. The source is simultaneously connected to the drain of the PMOS transistor M25, the drain of the PMOS transistor M26, and the gate of the PMOS transistor M28. The sources of the PMOS transistors M25, M26, and M28 are all connected to the power supply voltage vdd. The source of the NMOS transistor M22 is grounded.

[0073] The negative resistance structure is as follows: the NMOS transistors M17, M31, M32 and M33 form a common source and common gate structure, the gates of which are connected to a fixed bias voltage vn, the gate of the NMOS transistor M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS transistor M33 is connected to a variable bias voltage vn2;

[0074] The source of the NMOS transistor M17 is simultaneously connected to the source of the NMOS transistor M18 and the drains of the NMOS transistors M31, M32, M33, and M34. The gate of the NMOS transistor M18 is simultaneously connected to the gates of the NMOS transistors M48 and M19. The gate of the NMOS transistor M31 is connected to the drain of the NMOS transistor M49. The source of the NMOS transistor M49 is connected to the gate of the NMOS transistor M35, and the gate is connected to the switch K5n. The sources of the NMOS transistors M31, M32, M33, and M34 are all grounded.

[0075] The NMOS transistors M20, M36, M37 and M38 form a common source and common gate structure, with the gate connected to a fixed bias voltage vn, the gate of the NMOS transistor M37 connected to a fixed bias voltage vn1, and the gate of the NMOS M36 connected to a variable bias voltage vn2;

[0076] The source of the NMOS transistor M20 is simultaneously connected to the source of the NMOS transistor M19 and the drains of the NMOS transistors M35, M36, M37, and M38. The gate of the NMOS transistor M38 is connected to the source of the NMOS transistor M50. The drain of the NMOS transistor M50 is connected to the gate of the NMOS transistor M34, and the gate is connected to the switch K6n. The sources of the NMOS transistors M35, M36, M37, and M38 are all grounded.

[0077] The common end of the NMOS transistor M35 and the PMOS transistor M29 serves as the first differential signal output end of the first-stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS transistor M34 and the PMOS transistor M30 serves as the second differential signal output end of the first-stage transconductance amplifier, outputting the signal vo2.

[0078] Further popular explanation:

[0079] The first-stage gain stage of the first-stage switched capacitor amplifier is a fully differential structure. Bias voltages vn and vn1 are fixed bias voltages for the NMOS transistor, while bias voltage vn2 is a variable bias voltage for the NMOS transistor. Bias voltage vb1 is a fixed bias voltage for the PMOS transistor, while bias voltage vb2 is an adjustable bias voltage for the PMOS transistor.

[0080] Taking a single side as an example, the PMOS transistors M29 and M23 form a cascode structure. The NMOS transistors M17, M31, M32, and M33 also form a cascode structure to provide high gain for the first gain stage. M34 and M35 form a negative resistance structure to further improve the gain of the first gain stage.

[0081] The NMOS transistors M18, M19, M48, M49 and M50 are switching transistors. When the amplifier is in the reset state, the signals controlling switches k1, k2, k3 and k4 are high, and the switches are in the on state; the signals controlling switches k1n, k2n, k3n, k4n, k5n and k6n are low, and the switches are in the off state; when the amplifier is in the amplification state, the signals controlling switches k1n, k2n, k3n, k4n, k5n and k6n are high, and the switches are in the on state; the signals controlling switches k1, k2, k3 and k4 are low, and the switches are in the off state;

[0082] It is further explained that switches k1n, k2n, k3n, k4n, k5n and k6n may be one or more switches in an actual circuit and need to be controlled by the same set of signals and turned on or off at the same time. The same applies to switches k1, k2, k3 and k4.

[0083] The working principle of the first-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention is further explained in different states:

[0084] like Figure 8 As shown, in the first-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention, in the reset state, since vb2 = vb1 and vn2 = vn1, if the four PMOS transistors M13, M14, M15, and M16 are of the same size, the current flowing through them is also the same and can be set to I1. Since the reset state has a lower requirement for the amplifier's settling time and requires a smaller bias current, the amplifier's operating state only needs to provide a bias voltage that meets the requirement. Therefore, by controlling the bias circuit, vb2 and vn2 can be set to vb1 and vn1, respectively, so that the amplifier operates in a smaller bias current state in the reset state, saving the amplifier's power consumption. At the same time, since the NMOS transistors M31 and M38 are in a diode connection state, the amplifier's output impedance is small, enabling offset storage of the first-stage gain stage, so that the first-stage gain stage of the amplifier will not exit the saturation region while storing the offset voltage. When the amplifier is in the amplification state, since the amplifier needs to quickly settle, the control signal k1 is low and k1n is high.

[0085] like Figure 11 As shown, in the first stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention, at this time, since vb2 = vb1-C2(vb2-vb) / (C1+C2), vn2 = vn1+C4(vdd-vn) / (C3+C4), vb2 decreases and vn2 increases. Figure 10 As can be seen, the current flowing through PMOS transistors M14 and M15 increases by ΔI1, while the current flowing through PMOS transistors M24 and M26 increases by ΔI2. This increase in current allows the amplifier's first-stage gain stage to quickly establish during the amplification phase. Furthermore, since the first-stage gain stage is connected to NMOS transistors M17 and M20 in this state, the output impedance of the gain stage is increased, thereby boosting the amplification factor of the first-stage gain stage and suppressing the impact of offset voltage on the amplifier's gain stage.

[0086] like Figure 6 As shown, the second-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention includes a differential input pair of NMOS transistors M39 and M40. The sources of the NMOS transistors M39 and M40 are connected and connected to one end of the resistor R. The other end of the resistor R is grounded. The gates of the NMOS transistors M39 and M40 are connected to the signal vo1 and the signal vo2, respectively.

[0087] The drains of the NMOS transistors M39 and M40 are connected to the drains of the PMOS transistors M42 and M43 respectively, the sources of the PMOS transistors M42 and M43 are connected to the drains of the PMOS transistors M44 and M45 respectively, and the sources of the PMOS transistors M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS transistors M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS transistors M42 and M43 are connected to the adjustable bias voltage vb2;

[0088] The circuit further includes an NMOS transistor M41. The drain of the NMOS transistor M41 is connected to the drain of the NMOS transistor M39 and the drain of the PMOS transistor M42, and the common terminal serves as the first differential signal output terminal of the second-stage transconductance amplifier, outputting a signal vop. The source of the NMOS transistor M41 is connected to the drain of the NMOS transistor M40 and the drain of the PMOS transistor M43, and the common terminal serves as the second differential signal output terminal of the second-stage transconductance amplifier, outputting a signal vom. The gate of the NMOS transistor M41 is connected to a switch K5. The switch K5 and switches k1, k2, k3, and k4 are all controlled by the same signal.

[0089] The working principle of the second-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention is further explained in different states:

[0090] like Figure 9 As shown, the second-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention in the reset state:

[0091] When the amplifier is in the reset state, the amplifier needs to quickly establish. At this time, since vb2=vb1, the current flowing through the PMOS tubes M44 and M45 is set to I3. Since the reset state has a lower requirement for the amplifier establishment time, the required bias current is small. The working state of the amplifier only needs to provide a bias voltage that meets the requirement, so that the second-stage gain stage of the amplifier operates in a smaller bias current state in the reset state, saving the power consumption of the amplifier.

[0092] like Figure 12 As shown, the second-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention is in the amplifying state:

[0093] When the amplifier is in the amplification state, since the amplifier needs to quickly settle, in the amplification state, vb2 = vb1-C2(vb2-vb) / (C1+C2), thereby reducing vb2 and increasing the current flowing through the PMOS tubes M44 and M45 by ΔI3. By increasing the current, the second stage of the amplifier can quickly settle in the amplification phase.

[0094] As an implementable solution, the amplifier proposed in the present invention is designed using 180nm CMOS technology. When the amplifier operates at 125MHz, ΔI1 / I1=5, ΔI2 / I2=8, ΔI3 / I3=4. The comparison of the current changes of the reset and amplification phases of the switched capacitor amplifier proposed in the present invention is shown in the figure below. Figure 13 As shown in the figure. The above current change ratio shows that the current drawn by the amplifier in the reset phase is only 1 / 6 of the current drawn by the amplifier in the amplification phase. Compared to conventional structures, where the current drawn by the amplifier in the reset phase differs from the current drawn by the amplification phase, the present invention reduces the amplifier's power consumption by approximately 40%. Furthermore, because the amplifier proposed in the present invention can provide a smaller gain in the reset phase, enabling offset storage, and a larger gain in the amplification phase, enabling signal amplification, compared to conventional structures, the amplifier proposed in the present invention can effectively suppress offset voltage and improve amplifier precision.

[0095] Finally, it should be understood that the embodiments described in this specification are intended only to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, by way of example and not limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly described and illustrated in this specification.

Claims

1. A switched capacitor amplifier, characterized in that: The invention comprises a bias circuit, a first-stage transconductance amplifier and a second-stage transconductance amplifier, wherein: The bias circuit includes a constant current source IB, which is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in a diode connection form. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, the source of the PMOS tube M4 is connected to the power supply VDD; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply VDD, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The source of the PMOS transistor M6 is connected, and the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M3; the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M2, and the NMOS transistor M2 is in a diode connection form. The source of the NMOS transistor M2 is grounded, and the gate and drain bias voltage of the NMOS transistor M2 is vn1; the gate of the NMOS transistor M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of the capacitor C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of both the switch k4 and the switch k4n, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn; The device further includes a PMOS transistor M7, wherein the gate of the PMOS transistor M7 is connected to the gate of the PMOS transistor M6, the source of the PMOS transistor M7 is connected to the drain of the PMOS transistor M8, the source of the PMOS transistor M8 is connected to the power supply vdd, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M7, the gate bias voltage of the PMOS transistor M8 is vb1, the drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M47, the source of the NMOS transistor M47 is grounded, and the gate of the NMOS transistor M47 is connected to the gate of the NMOS transistor M1; the gate of the PMOS transistor M8 is connected to one end of the capacitor C2 via a switch k1, one end of the capacitor C1, and a switch k1n in sequence, the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is connected to one end of both the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to a fixed bias voltage vb.

2. The switched capacitor amplifier according to claim 1, wherein: When the switched capacitor amplifier is in the reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off; One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through the turned-on switch k4, and one end is reset phase adjustable bias voltage vn2. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time. One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

3. The switched capacitor amplifier according to claim 1, wherein: When the switched capacitor amplifier is in the amplification phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off; The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the law of conservation of charge, at this time vn2 = vn1 + C4 (vdd - vn) / (C3 + C4). Therefore, vn2 in the amplification phase is higher than vn2 in the reset phase by C4 (vdd - vn) / (C3 + C4). The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2 = vb1 - C2 (vb2 - vb) / (C1 + C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2 (vb2 - vb) / (C1 + C2).

4. The switched capacitor amplifier according to claim 1, wherein: The first-stage transconductance amplifier includes an input stage of the first-stage transconductance amplifier composed of PMOS transistors M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of the first-stage transconductance amplifier composed of NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS transistors M23, M24, M25, M26, M27, M28, M29 and M30; wherein: The PMOS transistors M9 and M10 are input differential pair transistors, and the gates of the PMOS transistors M9 and M10 are connected to the input signals VP and VM respectively; the PMOS transistors M11, M12, M13, M14, M15 and M16 are cascode structures; the gates of the PMOS transistors M11 and M12 are connected and connected to a fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS transistors M9 and M10; the gates of the PMOS transistors M13 and M15 are connected and connected to a fixed bias voltage vb1, the drains of the PMOS transistors M13 and M14 are connected and connected to the source of the PMOS transistor M12; the gates of the PMOS transistors M14 and M16 are connected and connected to a variable bias voltage vb2, the drains of the PMOS transistors M15 and M16 are connected and connected to the source of the PMOS transistor M11; the sources of the PMOS transistors M13, M14, M15 and M16 are all connected to the power supply voltage vdd; The PMOS transistors M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS transistors M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

5. The switched capacitor amplifier according to claim 4, wherein: The gain bootstrap structure is as follows: the PMOS transistors M29 and M23 form a common source and common gate structure, with the gate connected to a fixed bias voltage vb1; the gate of the PMOS transistor M24 is connected to a variable bias voltage vb2; The drain of the PMOS transistor M29 is simultaneously connected to the gate of the NMOS transistor M21, the source of the NMOS transistor M48, the common drain of the NMOS transistors M17 and M18, and the gate of the NMOS transistor M35. The gate is simultaneously connected to the drain of the NMOS transistor M21 and the drain of the PMOS transistor M27. The source is simultaneously connected to the drain of the PMOS transistor M23, the drain of the PMOS transistor M24, and the gate of the PMOS transistor M27. The sources of the PMOS transistors M23, M24, and M27 are all connected to the power supply voltage vdd. The source of the NMOS transistor M21 is grounded. The PMOS transistors M30 and M25 form a common source and common gate structure, and the gates are connected to a fixed bias voltage vb1; the gate of the PMOS transistor M26 is connected to a variable bias voltage vb2; The drain of the PMOS transistor M30 is simultaneously connected to the gate of the NMOS transistor M22, the drain of the NMOS transistor M48, the common drain of the NMOS transistors M19 and M20, and the gate of the NMOS transistor M34. The gate is simultaneously connected to the drain of the NMOS transistor M22 and the drain of the PMOS transistor M28. The source is simultaneously connected to the drain of the PMOS transistor M25, the drain of the PMOS transistor M26, and the gate of the PMOS transistor M28. The sources of the PMOS transistors M25, M26, and M28 are all connected to the power supply voltage vdd. The source of the NMOS transistor M22 is grounded.

6. The switched capacitor amplifier according to claim 4, wherein: The negative resistance structure is as follows: the NMOS transistors M17, M31, M32 and M33 form a common source and common gate structure, the gates of which are connected to a fixed bias voltage vn, the gate of the NMOS transistor M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS transistor M33 is connected to a variable bias voltage vn2; The source of the NMOS transistor M17 is simultaneously connected to the source of the NMOS transistor M18 and the drains of the NMOS transistors M31, M32, M33, and M34. The gate of the NMOS transistor M18 is simultaneously connected to the gates of the NMOS transistors M48 and M19. The gate of the NMOS transistor M31 is connected to the drain of the NMOS transistor M49. The source of the NMOS transistor M49 is connected to the gate of the NMOS transistor M35, and the gate is connected to the switch K5n. The sources of the NMOS transistors M31, M32, M33, and M34 are all grounded. The NMOS transistors M20, M36, M37 and M38 form a common source and common gate structure, with the gate connected to a fixed bias voltage vn, the gate of the NMOS transistor M37 connected to a fixed bias voltage vn1, and the gate of the NMOS M36 connected to a variable bias voltage vn2; The source of the NMOS transistor M20 is simultaneously connected to the source of the NMOS transistor M19 and the drains of the NMOS transistors M35, M36, M37, and M38. The gate of the NMOS transistor M38 is connected to the source of the NMOS transistor M50. The drain of the NMOS transistor M50 is connected to the gate of the NMOS transistor M34, and the gate is connected to the switch K6n. The sources of the NMOS transistors M35, M36, M37, and M38 are all grounded. The common end of the NMOS transistor M35 and the PMOS transistor M29 serves as the first differential signal output end of the first-stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS transistor M34 and the PMOS transistor M30 serves as the second differential signal output end of the first-stage transconductance amplifier, outputting the signal vo2.

7. The switched capacitor amplifier according to claim 1, wherein: The second-stage transconductance amplifier includes a differential input pair of NMOS transistors M39 and M40. The sources of the NMOS transistors M39 and M40 are connected and connected to one end of a resistor R. The other end of the resistor R is grounded. The gates of the NMOS transistors M39 and M40 are connected to signals vo1 and vo2, respectively. The drains of the NMOS transistors M39 and M40 are connected to the drains of the PMOS transistors M42 and M43 respectively, the sources of the PMOS transistors M42 and M43 are connected to the drains of the PMOS transistors M44 and M45 respectively, and the sources of the PMOS transistors M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS transistors M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS transistors M42 and M43 are connected to the adjustable bias voltage vb2; The circuit further includes an NMOS transistor M41, the drain of which is connected to the drain of the NMOS transistor M39 and the drain of the PMOS transistor M42, and the common end serves as the first differential signal output end of the second-stage transconductance amplifier, outputting the signal vop; the source of the NMOS transistor M41 is connected to the drain of the NMOS transistor M40 and the drain of the PMOS transistor M43, and the common end serves as the second differential signal output end of the second-stage transconductance amplifier, outputting the signal vom.

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