Phase discriminator-based frequency synthesizer and frequency synthesis method

Abstract

The invention provides a frequency synthesizer based on a phase discriminator and a frequency synthesis method thereof. The frequency synthesizer based on the phase discriminator comprises a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit and a frequency multiplication amplification circuit, wherein the first-stage phase-locked loop circuit is used for generating a first-stage frequency signal based on a reference clock signal; the frequency multiplication amplification circuit is used for generating a frequency multiplication amplification signal based on the reference clock signal; the second-stage phase-locked loop circuit is used for generating a second-stage frequency signal based on the first-stage frequency signal and the frequency multiplication amplification signal; and the third-stage phase-locked loop circuit is used for generating a frequency output signal based on the second-stage frequency signal. According to the frequency synthesizer based on the phase discriminator and the frequency synthesis method of the frequency synthesizer, the problems that integer boundary stray is difficult to avoid by using a single-loop phase-locked source and frequency stepping cannot meet the requirement sometimes in an existing frequency synthesizer can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency synthesis, and more specifically, to a frequency synthesizer based on a phase detector and a frequency synthesis method thereof. Background Art

[0002] Frequency synthesizer is the source of carrier signal of electronic system. In modern electronic technology, frequency synthesizer has become an important part of electronic system and is widely used in wireless communication system. Frequency synthesizer is an important part of frequency converter. The step, phase noise and spurious of frequency synthesizer will directly affect the index of frequency converter output signal. Therefore, frequency synthesizer with small step and low spurious is the key to achieve the index of frequency converter. Frequency converter is also an important part of wireless communication system. The index of frequency synthesizer will directly affect the overall index of wireless communication system and the quality of wireless communication system signal.

[0003] It is difficult to avoid integer boundary spurs when using a single-loop phase-locked source in a commonly used frequency synthesizer, and the frequency step sometimes fails to meet the requirements. Based on the above technical problems, there is an urgent need for a solution that can effectively avoid integer boundary spurs and ensure that the frequency step meets the requirements. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a frequency synthesizer based on a phase detector and a frequency synthesis method to solve the problem that the existing frequency synthesizer using a single-loop phase-locked source is difficult to avoid integer boundary spurious and the frequency step sometimes cannot meet the requirements.

[0005] The frequency synthesizer based on the phase detector provided by the present invention comprises a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit and a frequency multiplication amplifier circuit; wherein, The first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on a reference clock signal; The frequency multiplication and amplification circuit is used to generate a frequency multiplication and amplification signal based on the reference clock signal; The second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal; The third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal.

[0006] In addition, a preferred solution is to further include a power divider, which is used to divide the reference clock signal into two reference clock signals, one of which is sent to the first-stage phase-locked loop circuit, and the other is sent to the frequency multiplication amplifier circuit.

[0007] In addition, a preferred solution is that the first-stage phase-locked loop circuit includes a first phase detector, a first loop filter and a first voltage-controlled oscillator; wherein, The first phase detector is used to perform phase detection on a reference clock signal sent by the power divider and a first-level frequency signal generated by the first voltage-controlled oscillator, and generate a first-level current source signal; The first loop filter is used to filter the first-level current source signal to generate a first-level voltage signal; The first voltage-controlled oscillator is used to generate the first-level frequency signal based on the first-level voltage signal, and send the first-level frequency signal to the first phase detector and the second-level phase-locked loop circuit respectively.

[0008] In addition, a preferred solution is that the frequency multiplication and amplification circuit includes a frequency multiplier and an amplifier, wherein: The frequency multiplier is used to perform frequency multiplication processing on another reference clock signal sent by the power divider to generate a frequency multiplied primary signal; The amplifier is used to generate the frequency-doubled amplified signal based on the frequency-doubled primary signal.

[0009] In addition, a preferred solution is that the frequency multiplication amplifier circuit further includes a first filter; wherein, The first filter is used to filter the frequency-doubled primary signal to generate a frequency-doubled secondary signal, and send the frequency-doubled secondary signal to the amplifier; The amplifier is used to amplify the frequency-doubled secondary signal to generate the frequency-doubled amplified signal.

[0010] In addition, a preferred solution is that the second-stage phase-locked loop circuit includes a mixer, a second phase detector, a second loop filter and a second voltage-controlled oscillator; wherein, The mixer is used to mix the frequency multiplication amplification signal sent by the frequency multiplication amplification circuit and the second-level frequency signal generated by the second voltage-controlled oscillator to generate an intermediate frequency primary signal; The second phase detector is used to perform phase detection based on the intermediate frequency primary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate a second-level current source signal; The second loop filter is used for filtering the second-level current source signal to generate a second-level voltage signal; The second voltage-controlled oscillator is used to generate the second-level frequency signal based on the second-level voltage signal, and send the second-level frequency signal to the mixer and the third-level phase-locked loop circuit respectively.

[0011] In addition, a preferred solution is that the second-stage phase-locked loop circuit further includes a second filter; wherein, The second filter is used for filtering the intermediate frequency primary signal to generate an intermediate frequency secondary signal, and sending the intermediate frequency secondary signal to the second phase detector; The second phase detector is used to perform phase detection on the intermediate frequency secondary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate the second-level current source signal.

[0012] In addition, a preferred solution is that the third-stage phase-locked loop circuit includes a third phase detector, a third loop filter and a third voltage-controlled oscillator; wherein, The third phase detector is used to perform phase detection on the second-level frequency signal sent by the second-level phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-level current source signal; The third loop filter is used to process the third level current source signal to generate a third level voltage signal; The third voltage-controlled oscillator is used to generate the frequency output signal based on the third-level voltage signal, and output the frequency output signal.

[0013] In addition, a preferred solution is that the frequency of the reference clock signal is fo, the frequency of the first-level frequency signal is f1, the frequency of the second-level frequency signal is f2, and the frequency of the frequency output signal is f3; wherein, The frequency calculation formula of the first-stage phase-locked loop circuit is:

[0014] The frequency calculation formula of the second-stage phase-locked loop circuit is:

[0015] The frequency calculation formula of the third-stage phase-locked loop circuit is: , that is:

[0016] Among them, N1, N2, N3, frac1, frac2, MOD1, and MOD2 are all integer parameters, and the specific value of each integer parameter is determined by the preset indicators of the first phase detector, the second phase detector, and the third phase detector.

[0017] On the other hand, the present invention further provides a frequency synthesis method, wherein the frequency synthesis method performs frequency synthesis by the aforementioned frequency synthesizer based on the phase detector, comprising: Generate a first-stage frequency signal based on a reference clock signal by the first-stage phase-locked loop circuit; Generate a frequency-multiplied amplified signal based on the reference clock signal by the frequency-multiplied amplification circuit; Generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal by the second-stage phase-locked loop circuit; A frequency output signal is generated based on the second-stage frequency signal by the third-stage phase-locked loop circuit.

[0018] Compared with the prior art, the frequency synthesizer based on the phase detector and the frequency synthesis method according to the present invention have the following beneficial effects: The present invention has the characteristics of small frequency step and low spurious of the generated frequency output signal by setting a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit and a frequency multiplication amplifier circuit. A reference signal is generated by signal processing of the first-stage phase-locked loop circuit and the second-stage phase-locked loop circuit, so that the third-stage phase-locked loop circuit can always work in integer mode, avoiding the problem of integer boundary spurious generated in the phase-locked loop decimal mode.

[0019] In order to achieve the above and related purposes, one or more aspects of the present invention include features that will be described in detail later and are particularly pointed out in the claims. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings: Figure 1 The structural principle diagram of the frequency synthesizer based on the phase detector provided by the present invention.

[0021] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0022] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0023] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention; the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Figure 1 The schematic diagram of the frequency synthesizer based on the phase detector provided by the present invention is shown. Figure 1 It can be seen that the frequency synthesizer based on the phase detector provided by the present invention includes a main reference clock module (corresponding to the attached Figure 1 The reference clock in the circuit), a frequency multiplication amplifier circuit and a three-pole phase-locked loop circuit, wherein the reference clock module is used to output a reference clock signal, and the three-pole phase-locked loop circuit includes a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit and a third-stage phase-locked loop circuit; the first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on the reference clock signal (original input signal); the frequency multiplication amplifier circuit is used to generate a frequency multiplication amplified signal based on the reference clock signal; the second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency multiplication amplified signal; the third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal.

[0025] Furthermore, in order to facilitate the first-stage phase-locked loop circuit and the frequency multiplier amplifier circuit to receive mutually synchronized reference clock signals in a timely manner, the phase detector-based frequency synthesizer provided by the present invention also includes a power divider, which is used to split the reference clock signal into two reference clock signals (by power), one of which is sent to the first-stage phase-locked loop circuit, and the other is sent to the frequency multiplier amplifier circuit.

[0026] In a specific embodiment of the present invention, the first-stage phase-locked loop circuit may include a first phase detector (corresponding to Figure 1 Phase detector 1 in), first loop filter (corresponding to Figure 1 The loop filter 1 in the circuit) and the first voltage-controlled oscillator (corresponding to Figure 1VCO1 in the circuit); wherein the first phase detector is used to detect the phase of a reference clock signal sent by the power divider and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate a first-level current source signal; the first loop filter is used to process (filter) the first-level current source signal to generate a first-level voltage signal; the first voltage-controlled oscillator is used to generate the first-level frequency signal based on the first-level voltage signal, and send the first-level frequency signal to the first phase detector and the second-level phase-locked loop circuit respectively; wherein the first-level voltage signal is used to control the frequency of the first-level frequency signal.

[0027] In another specific embodiment of the present invention, in order to achieve the frequency doubling amplification effect of the frequency doubling amplification circuit, the frequency doubling amplification circuit may include a frequency multiplier and an amplifier, wherein the frequency multiplier is used to perform frequency multiplication processing on another reference clock signal sent by the power divider to generate a frequency multiplied primary signal; and the amplifier is used to generate the frequency multiplied amplified signal based on the frequency multiplied primary signal.

[0028] In addition, in order to further improve the accuracy of the frequency-multiplied amplified signal, the frequency-multiplied amplification circuit may further include a first filter (corresponding to Figure 1 ); wherein the first filter is used to filter the frequency-doubled primary signal to generate a frequency-doubled secondary signal, and send the frequency-doubled secondary signal to the amplifier; the amplifier is used to amplify the frequency-doubled secondary signal to generate the frequency-doubled amplified signal.

[0029] In a preferred embodiment of the present invention, the second-stage phase-locked loop circuit may include a mixer, a second phase detector (corresponding to Figure 1 Phase detector 2 in the second loop filter (corresponding to Figure 1 The loop filter 2 in the circuit) and the second voltage-controlled oscillator (corresponding to Figure 1 VCO2 in the circuit); wherein the mixer is used to mix the frequency multiplication amplification signal sent by the frequency multiplication amplification circuit and the second-level frequency signal generated by the second voltage-controlled oscillator to generate an intermediate frequency primary signal; the second phase detector is used to perform phase detection based on the intermediate frequency primary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate a second-level current source signal; the second loop filter is used to filter the second-level current source signal to generate a second-level voltage signal; the second voltage-controlled oscillator is used to generate the second-level frequency signal based on the second-level voltage signal, and send the second-level frequency signal to the mixer and the third-level phase-locked loop circuit respectively; wherein the second-level voltage signal is used to control the frequency of the second-level frequency signal.

[0030] In addition, in order to further improve the accuracy of the second-stage current source signal, the second-stage phase-locked loop circuit may further include a second filter (corresponding to Figure 1wherein the second filter is used to filter the intermediate frequency primary signal, filter out the stray signal in the intermediate frequency primary signal, so as to generate an intermediate frequency secondary signal, and send the intermediate frequency secondary signal to the second phase detector; the second phase detector is used to perform phase detection on the intermediate frequency secondary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate the second-level current source signal.

[0031] In another preferred embodiment of the present invention, the third-stage phase-locked loop circuit may further include a third phase detector (corresponding to Figure 1 Phase detector 3 in the third loop filter (corresponding to Figure 1 The loop filter 3 in the circuit) and the third voltage-controlled oscillator (corresponding to Figure 1 VCO3 in the circuit); wherein the third phase detector is used to perform phase detection on the second-level frequency signal sent by the second-level phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-level current source signal; the third loop filter is used to process the third-level current source signal to generate a third-level voltage signal; the third voltage-controlled oscillator is used to generate the frequency output signal based on the third-level voltage signal, and output the frequency output signal; wherein the third-level voltage signal is used to control the frequency of the frequency output signal.

[0032] It should be noted that the working mode of the third-stage phase-locked loop circuit of the frequency synthesizer based on the phase detector provided by the present invention is the integer mode, which directly avoids the problem of integer boundary spurious caused by the decimal mode. Figure 1 The frequency synthesizer structure based on the phase detector provided by the present invention is shown, assuming that the frequency of the reference clock signal is fo, the frequency of the first-level frequency signal is f1, the frequency of the second-level frequency signal is f2, and the frequency of the frequency output signal is f3; wherein, The frequency calculation formula of the first-stage phase-locked loop circuit is:

[0033] The frequency calculation formula of the second-stage phase-locked loop circuit is:

[0034] The frequency calculation formula of the third-stage phase-locked loop circuit is: , where N1, N2, N3, frac1, frac2, MOD1, and MOD2 are all integer parameters, and the specific values ​​of each integer parameter are determined by the preset indicators of the first phase detector, the second phase detector, and the third phase detector. The output frequency of the frequency output signal of the third-stage phase-locked loop circuit is obtained by calculation: .

[0035] On the other hand, to further illustrate the working principle of the frequency synthesizer based on the phase detector provided by the present invention, the present invention also provides a frequency synthesis method, which performs frequency synthesis by the aforementioned frequency synthesizer based on the phase detector, comprising: Generate a first-stage frequency signal based on a reference clock signal by the first-stage phase-locked loop circuit; Generate a frequency-multiplied amplified signal based on the reference clock signal by the frequency-multiplied amplification circuit; Generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal by the second-stage phase-locked loop circuit; A frequency output signal is generated based on the second-stage frequency signal by the third-stage phase-locked loop circuit.

[0036] It can be seen from the above specific embodiments that the frequency synthesizer based on the phase detector and the frequency synthesis method provided by the present invention have the characteristics of small frequency step and low spurious of the generated frequency output signal by setting a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit and a frequency multiplication amplifier circuit; in addition, a reference signal is generated by signal processing of the first-stage phase-locked loop circuit and the second-stage phase-locked loop circuit, so that the third-stage phase-locked loop circuit can always work in the integer mode, avoiding the problem of integer boundary spurious generated in the phase-locked loop decimal mode.

[0037] As above Figure 1 The frequency synthesizer based on the phase detector and the frequency synthesis method provided according to the present invention are described by way of example. However, it should be understood by those skilled in the art that various improvements can be made to the frequency synthesizer based on the phase detector and the frequency synthesis method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A frequency synthesizer based on a phase detector, characterized in that: It includes a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit and a frequency multiplication amplifier circuit; wherein, The first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on a reference clock signal; The frequency multiplication and amplification circuit is used to generate a frequency multiplication and amplification signal based on the reference clock signal; The second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal; The third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal.

2. The frequency synthesizer based on phase detector as claimed in claim 1, characterized in that: It also includes a power divider, which is used to divide the reference clock signal into two reference clock signals, one of which is sent to the first-stage phase-locked loop circuit, and the other is sent to the frequency multiplication amplifier circuit.

3. The frequency synthesizer based on phase detector as claimed in claim 2, characterized in that: The first-stage phase-locked loop circuit includes a first phase detector, a first loop filter and a first voltage-controlled oscillator; wherein, The first phase detector is used to perform phase detection on a reference clock signal sent by the power divider and a first-level frequency signal generated by the first voltage-controlled oscillator, and generate a first-level current source signal; The first loop filter is used to process the first-level current source signal to generate a first-level voltage signal; The first voltage-controlled oscillator is used to generate the first-level frequency signal based on the first-level voltage signal, and send the first-level frequency signal to the first phase detector and the second-level phase-locked loop circuit respectively.

4. The frequency synthesizer based on phase detector as claimed in claim 3, characterized in that: The frequency multiplication and amplification circuit comprises a frequency multiplier and an amplifier, wherein: The frequency multiplier is used to perform frequency multiplication processing on another reference clock signal sent by the power divider to generate a frequency multiplied primary signal; The amplifier is used to generate the frequency-doubled amplified signal based on the frequency-doubled primary signal.

5. The frequency synthesizer based on phase detector as claimed in claim 4, characterized in that: The frequency multiplication amplifier circuit further includes a first filter; wherein, The first filter is used to filter the frequency-doubled primary signal to generate a frequency-doubled secondary signal, and send the frequency-doubled secondary signal to the amplifier; The amplifier is used to amplify the frequency-doubled secondary signal to generate the frequency-doubled amplified signal.

6. The frequency synthesizer based on phase detector as claimed in claim 5, characterized in that: The second-stage phase-locked loop circuit includes a mixer, a second phase detector, a second loop filter and a second voltage-controlled oscillator; wherein, The mixer is used to mix the frequency multiplication amplification signal sent by the frequency multiplication amplification circuit and the second-level frequency signal generated by the second voltage-controlled oscillator to generate an intermediate frequency primary signal; The second phase detector is used to perform phase detection based on the intermediate frequency primary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate a second-level current source signal; The second loop filter is used for filtering the second-level current source signal to generate a second-level voltage signal; The second voltage-controlled oscillator is used to generate the second-level frequency signal based on the second-level voltage signal, and send the second-level frequency signal to the mixer and the third-level phase-locked loop circuit respectively.

7. The frequency synthesizer based on phase detector as claimed in claim 6, characterized in that: The second-stage phase-locked loop circuit also includes a second filter; wherein, The second filter is used for filtering the intermediate frequency primary signal to generate an intermediate frequency secondary signal, and sending the intermediate frequency secondary signal to the second phase detector; The second phase detector is used to perform phase detection on the intermediate frequency secondary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate the second-level current source signal.

8. The frequency synthesizer based on phase detector as claimed in claim 7, characterized in that: The third-stage phase-locked loop circuit includes a third phase detector, a third loop filter and a third voltage-controlled oscillator; wherein, The third phase detector is used to perform phase detection on the second-level frequency signal sent by the second-level phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-level current source signal; The third loop filter is used to process the third level current source signal to generate a third level voltage signal; The third voltage-controlled oscillator is used to generate the frequency output signal based on the third-level voltage signal, and output the frequency output signal.

9. The frequency synthesizer based on phase detector as claimed in claim 8, characterized in that: Assume that the frequency of the reference clock signal is fo, the frequency of the first-level frequency signal is f1, the frequency of the second-level frequency signal is f2, and the frequency of the frequency output signal is f3; wherein, The frequency calculation formula of the first-stage phase-locked loop circuit is: ， The frequency calculation formula of the second-stage phase-locked loop circuit is: ， The frequency calculation formula of the third-stage phase-locked loop circuit is: , i.e.: , Among them, N1, N2, N3, frac1, frac2, MOD1, and MOD2 are all integer parameters, and the specific value of each integer parameter is determined by the preset indicators of the first phase detector, the second phase detector, and the third phase detector.

10. A frequency synthesis method, characterized in that: The frequency synthesis method performs frequency synthesis by using the phase detector-based frequency synthesizer according to any one of claims 1 to 9, comprising: Generate a first-stage frequency signal based on a reference clock signal by the first-stage phase-locked loop circuit; Generate a frequency-multiplied amplified signal based on the reference clock signal by the frequency-multiplied amplification circuit; Generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal by the second-stage phase-locked loop circuit; A frequency output signal is generated based on the second-stage frequency signal by the third-stage phase-locked loop circuit.

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