A high performance phase-locked digital frequency synthesis device

Abstract

The present invention proposes a high-performance phase-locked digital frequency synthesis device, comprising: the output end of a crystal oscillator circuit is connected to the input end of a DDS device, the output end of a DSP device is connected to the input end of the DDS device, the output end of the crystal oscillator circuit is connected to the input end of a mixer, the output end of the mixer is connected to the input end of a bandpass filter, the output end of the bandpass filter is connected to the input end of a phase detector, the output end of the phase detector is connected to the input end of a low-pass filter device, the output end of the low-pass filter device is connected to the input end of an amplifier, the output end of the amplifier is connected to the input end of a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of a dual-mode pre-frequency divider, the output end of the dual-mode pre-frequency divider is connected to the input end of an N-frequency divider, and the output end of the N-frequency divider is connected to the input end of the phase detector.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a high-performance phase-locked digital frequency synthesis device. Background Art

[0002] With the development of modern electronic science and technology, the application of frequency synthesis technology is becoming more and more extensive, and the requirements for frequency synthesis are becoming higher and higher. Frequency synthesis technology has been widely used in radar, electronic countermeasures, communications, digital television, medical equipment, remote control and telemetry, and electronic measuring instruments.

[0003] Frequency synthesizer is the heart of many modern electronic devices, and can greatly affect the overall performance of the equipment. For example, in radar and communication systems, the frequency synthesizer is both the excitation signal source of the transmitter and the local oscillation source of the receiver, which is directly related to the modulation and demodulation of the transmitted and received signals; in electronic countermeasure systems, frequency synthesizers can be used in jammers and frequency detection equipment, which is directly related to the overall performance of electronic countermeasure equipment; in electronic measuring instruments and other equipment, frequency synthesizers can also be used as standard signal sources. The performance of the frequency synthesizer is directly related to the overall performance indicators of the equipment.

[0004] DDS technology can achieve frequency resolution in the μHz range, but due to its low output frequency, generally below 1GHz, it is necessary to cooperate with other methods to generate signals with a wider bandwidth. Usually, DDS can be used to directly drive the phase-locked loop, which is simple to implement and low in cost. However, since the spurious signal of DDS is poor, it will further deteriorate after the phase-locked loop frequency multiplication, and there is no effective way to suppress the degree of deterioration, so the DDS direct drive phase-locked loop method cannot meet the index requirements. For example, the use of fractional frequency division can achieve frequency steps in the Hz range, but fractional frequency division will also generate more spurious signals. At present, the spurious signal generated by the fractional frequency division is modulated, and the power of the spurious signal is modulated to the far end to achieve the effect of reducing the spurious signal, but ultimately it cannot meet the low spurious index requirements. Summary of the invention

[0005] The object of the present invention is to solve at least one of the technical drawbacks.

[0006] Therefore, the object of the present invention is to provide a high-performance phase-locked digital frequency synthesis device.

[0007] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a high-performance phase-locked digital frequency synthesis device, comprising: a crystal oscillator circuit, a DSP device, a DDS device, a mixer, a bandpass filter, a phase detector, a low-pass filter device, an amplifier, a voltage-controlled oscillator, a dual-mode pre-divider, and an N-divider, wherein the output end of the crystal oscillator circuit is connected to the input end of the DDS device, the output end of the DSP device is connected to the input end of the DDS device, the output end of the crystal oscillator circuit is connected to the input end of the mixer, the output end of the mixer is connected to the input end of the bandpass filter, the output end of the bandpass filter is connected to the input end of the phase detector, the output end of the phase detector is connected to the input end of the low-pass filter device, the output end of the low-pass filter device is connected to the input end of the amplifier, the output end of the amplifier is connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the dual-mode pre-divider, the output end of the dual-mode pre-divider is connected to the input end of the N-divider, and the output end of the N-divider is connected to the input end of the phase detector, wherein:

[0008] The DDS device comprises: a reference clock source, a first phase accumulator, a phase register, a second phase accumulator, a phase-to-amplitude converter, a D / A converter and a low-pass filtering device, wherein the output end of the reference clock source is respectively connected to the D / A converter and the first phase accumulator, the output end of the first phase accumulator is connected to the phase register, the phase register is connected to the second phase accumulator, the output end of the second phase accumulator is connected to the input end of the D / A converter, and the output end of the D / A converter is further connected to the input end of the low-pass filtering device.

[0009] The data input terminal of the D / A converter is connected to the limiter converter, the first output terminal of the D / A converter is connected to the negative input terminal of the comparator, the second output terminal of the D / A converter is connected to the positive input terminal of the comparator, and the output terminal of the comparator is connected to the low-pass filter device;

[0010] The phase detector, low-pass filter, amplifier, voltage-controlled oscillator, dual-mode pre-frequency divider and program counter form a phase-locked loop.

[0011] Further, the low-pass filtering device includes: a first resistor, a second resistor, a first capacitor, a second capacitor and an operational amplifier, wherein one end of the first resistor is connected to the output end of the comparator, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor is connected to the positive terminal of the operational amplifier and one end of the second capacitor, the other end of the second capacitor is grounded, the negative terminal of the operational amplifier is connected to the output end of the operational amplifier, the other end of the first resistor is further connected to one end of the first capacitor, and the other end of the first capacitor is connected to the output end of the operational amplifier.

[0012] Furthermore, the DSP device adopts a DSP chip of model TMS320C5402.

[0013] Furthermore, the dual-mode pre-prescaler includes: a high-speed divider, a first subtraction counter, and a second subtraction counter. The output end of the high-speed divider is connected to the input end of the first subtraction counter, the input end of the second subtraction counter and two input ends of the AND gate. The first subtraction counter is further connected to an internal digital phase detector.

[0014] Further, the voltage-controlled oscillator includes: a resonant circuit and a voltage-controlled oscillation circuit, wherein the resonant circuit includes a first varactor diode, a second varactor diode, a third varactor diode and a fourth varactor diode, and a first inductor, the reverse end of the first varactor diode is connected to the reverse end of the second varactor diode, the reverse end of the third varactor diode is connected to the reverse end of the fourth varactor diode, the first inductor is connected in parallel between the first varactor diode and the second varactor diode, and between the third varactor diode and the fourth varactor diode, and the voltage-controlled oscillation circuit is further connected at both ends of the first inductor.

[0015] Further, the voltage-controlled oscillation circuit includes: a resistor is connected between the base and emitter of the first triode, the emitter of the first triode is further connected to the collector of the second triode, the base of the second triode is connected to the collector of the third triode, the base of the third triode is connected to the bias voltage, and is further connected to the base of the fourth triode, the emitters of the fourth triode and the fifth triode are commonly connected to the collector of the sixth triode through a resistor, the collector of the fifth triode is connected to the base of the seventh triode, the collector of the seventh triode is connected to the base of the eighth triode, the emitter of the eighth triode is connected to the emitter of the ninth triode, the collector of the ninth triode is connected to the base of the tenth triode, and the emitter of the tenth triode is connected to the dual-mode pre-divider as an output end.

[0016] According to the high-performance phase-locked digital frequency synthesis device of the embodiment of the present invention, the design scheme of DDS+PLL frequency synthesizer is adopted, and it has the characteristics of excellent phase noise, small frequency step, low spurious, wide frequency range, strong frequency scalability, etc. It is realized by using PLL synthesis technology, and has the characteristics of high frequency, express, and good spectrum quality. In addition, the circuit design of the present invention is simple, and it is easy to realize miniaturization, and it is suitable for application in communication and measurement equipment with relatively high cost performance requirements. The present invention adopts DDS technology, which can have an extremely wide coverage frequency, and has high stability and accuracy, fast frequency switching, continuous waveform, small error and low price when switching frequency, and is widely used in radar, communication, remote control and telemetry, navigation and instrumentation and other fields.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 is a structural diagram of a high-performance phase-locked digital frequency synthesis device according to an embodiment of the present invention;

[0020] Figure 2 is a structural diagram of a DDS device according to an embodiment of the present invention;

[0021] Figure 3 is a circuit diagram of a DSP device according to an embodiment of the present invention;

[0022] Figure 4 A circuit diagram of a D / A converter according to an embodiment of the present invention;

[0023] Figure 5 is a circuit diagram of a low-pass filtering device according to an embodiment of the present invention;

[0024] Figure 6 is a circuit diagram of a bandpass filter according to an embodiment of the present invention;

[0025] Figure 7 is a circuit diagram of a voltage-controlled oscillation tuning circuit according to an embodiment of the present invention;

[0026] Figure 8 is a circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention;

[0027] Fig. 9 4 is a circuit diagram of a dual-mode pre-divider according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0029] like Figure 1 As shown, the high-performance phase-locked digital frequency synthesis device of the embodiment of the present invention includes: a crystal oscillator circuit 1, a DSP device 2, a DDS device 3, a mixer 4, a bandpass filter 5, a phase detector 6, a low-pass filter device, an amplifier 8, a voltage-controlled oscillator 9, a dual-mode pre-divider 10, and an N divider.

[0030] The output end of the crystal oscillator circuit 1 is connected to the input end of the DDS device 3, the output end of the DSP device 2 is connected to the input end of the DDS device 3, the output end of the crystal oscillator circuit 1 is connected to the input end of the mixer 4, the output end of the mixer 4 is connected to the input end of the bandpass filter 5, the output end of the bandpass filter 5 is connected to the input end of the phase detector 6, the output end of the phase detector 6 is connected to the input end of the low-pass filter device, the output end of the low-pass filter device is connected to the input end of the amplifier 8, the output end of the amplifier 8 is connected to the input end of the voltage-controlled oscillator 9, the output end of the voltage-controlled oscillator 9 is connected to the input end of the dual-mode pre-divider 10, the output end of the dual-mode pre-divider 10 is connected to the input end of the N divider, and the output end of the N divider is connected to the input end of the phase detector 6.

[0031] Specifically, Figure 5 As shown, the low-pass filtering device includes: a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2 and an operational amplifier, wherein one end of the first resistor R1 is connected to the output end of the comparator, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the positive terminal of the operational amplifier and one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the negative terminal of the operational amplifier is connected to the output end of the operational amplifier, the other end of the first resistor R1 is further connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the output end of the operational amplifier.

[0032] Figure 6 FIG. 4 is a circuit diagram of a bandpass filter according to an embodiment of the present invention. Figure 6 As shown, the bandpass filter adopts a comparator, wherein the negative input terminal of the comparator is connected to the output terminal of the mixer through the capacitor C1 and the resistor R1, the positive input terminal is grounded, the output terminal of the comparator is connected to the input terminal of the phase detector, and the negative input terminal and the output terminal of the comparator are short-circuited.

[0033] In the embodiments of the present invention, reference Figure 3 As shown, the DSP device 2 uses a DSP chip of model TMS320C5402.

[0034] like Figure 2 As shown, the DDS device 3 includes: a reference clock source, a first phase accumulator, a phase register, a second phase accumulator, a phase-to-amplitude converter, a D / A converter and a low-pass filtering device, wherein the output end of the reference clock source is respectively connected to the D / A converter and the first phase accumulator, the output end of the first phase accumulator is connected to the phase register, the phase register is connected to the second phase accumulator, the output end of the second phase accumulator is connected to the input end of the D / A converter, and the output end of the D / A converter is further connected to the input end of the low-pass filtering device.

[0035] It should be noted that the present invention selects the DDS excitation PLL method, which can combine the two frequency synthesis technologies of DDS and PLL, and the digital and analog synthesis methods work simultaneously, taking advantage of each other's strengths and making up for each other's weaknesses, so as to achieve high-speed broadband frequency synthesis with high resolution and less spurious.

[0036] The principle of DDS is to utilize the corresponding characteristics of the phase and amplitude of the sinusoidal signal, use digital circuits to construct a relationship table between phase and amplitude, obtain discrete amplitude data through discrete phase values, and finally reconstruct the frequency of the analog sinusoidal signal through digital-to-analog conversion. It includes multiple parts such as phase accumulator, waveform memory, digital-to-analog converter and filter.

[0037] The present invention adopts a DDS mixing and frequency division driving phase-locked loop method, which satisfies the small stepping and achieves low spurious index at the same time. The small step signal generated by the DDS is moved to the required frequency through mixing and then divided as a reference signal for frequency synthesis. In this way, the small step signal generated by the DDS can improve the spurious suppression degree after processing, reduce the phase noise and ensure the frequency step of the final output.

[0038] In addition, since DDS generates a large amount of spurious signals, in order to obtain better spurious suppression performance, a bandpass filter 5 is added after mixing to suppress the spurious components. Preferably, a double-tuned bandpass filter 5 is used, which can take into account factors such as the complexity of the filter, the reference frequency of the DDS, and the output frequency of the DDS. The double-tuned filter has extremely steep sidebands and a smaller bandwidth.

[0039] like Figure 4 As shown, the data input end of the D / A converter is connected to the limiter converter, the first output end of the D / A converter is connected to the negative input end of the comparator, the second output end of the D / A converter is connected to the positive input end of the comparator, and the output end of the comparator is connected to the low-pass filter device. The D / A converter uses a digital-to-analog conversion chip model DAC0830LCM.

[0040] The phase detector 6, the low-pass filter device, the amplifier 8, the voltage-controlled oscillator, the dual-mode pre-divider 10 and the program counter 11 constitute a phase-locked loop.

[0041] Specifically, Fig. 9 As shown, the dual-mode pre-prescaler includes: a high-speed divider 91, a first subtraction counter 92, and a second subtraction counter 93. The output end of the high-speed divider 91 is connected to the input end of the first subtraction counter 92, the input end of the second subtraction counter 93 and the two input ends of the AND gate. The first subtraction counter 92 is further connected to the internal digital phase detector PD.

[0042] The dual-mode pre-prescaler uses the high-speed frequency divider of the previous stage to pre-divide f0, thereby reducing the frequency, and then the first subtraction counter and the second subtraction counter continue to divide the frequency to obtain a frequency equal to the reference frequency, which is then sent to the internal digital phase detector PD for phase detection. In addition, the present invention adopts the swallow pulse counting method for counting, so that the frequency division coefficient is continuously adjustable.

[0043] At the beginning, the dual-mode pre-divider 10 works with a P+1 frequency division ratio, and the value of the pulse swallow counter A is reduced to 0. At this time, a total of (P+1)×A voltage-controlled oscillator 9 pulses are input. At this time, the pulse swallow counter A stops working, and the program counter 11N continues to count from (NA). The dual-mode pre-divider 10 works with a P frequency division ratio. When the value of the program counter 11A is reduced to 0, a total of P×(NA) voltage-controlled oscillator 9 pulses are input. In this way, the frequency division ratio in one operation is M=(P+1)×A+P×(NA)=NP+A. During the operation, only the dual-mode pre-divider 10 works at a high speed. The pulse swallow counter and the program counter are both P times lower than the dual-mode divider rate, and the frequency division ratio also reaches NP+A, which can achieve higher frequency output requirements.

[0044] The voltage-controlled oscillator 9 includes a resonant circuit and a voltage-controlled oscillation circuit.

[0045] Specifically, Figure 7 As shown, the resonant circuit includes a first varactor diode, a second varactor diode, a third varactor diode, a fourth varactor diode, and a first inductor. The reverse end of the first varactor diode is connected to the reverse end of the second varactor diode, the reverse end of the third varactor diode is connected to the reverse end of the fourth varactor diode, the first inductor is connected in parallel between the first varactor diode and the second varactor diode, and between the third varactor diode and the fourth varactor diode, and a voltage-controlled oscillation circuit is further connected at both ends of the first inductor.

[0046] The resonant circuit has an operating voltage of 5V, an output frequency of up to 225MHz, and a high purity of the output spectrum. The bias voltage of the varactor diode can be controlled by using an LC resonant tank composed of a varactor diode and an inductor. By connecting two varactor diodes back to back, that is, for DC and modulated signals, it is equivalent to a parallel connection, and the bias point is the same as the modulated state; for high-frequency signals, it is equivalent to a series connection, which reduces the voltage amplitude at both ends of each varactor diode, weakens the effect of the high-frequency voltage, and prevents the influence of the varactor diode conduction on the resonant circuit when the high-frequency voltage amplitude is too large.

[0047] like Figure 8 As shown, the voltage-controlled oscillation circuit includes: a resistor is connected between the base and emitter of the first triode, the emitter of the first triode is further connected to the collector of the second triode, the base of the second triode is connected to the collector of the third triode, the base of the third triode is connected to the bias voltage, and is further connected to the base of the fourth triode, the emitters of the fourth triode and the fifth triode are commonly connected to the collector of the sixth triode through a resistor, the collector of the fifth triode is connected to the base of the seventh triode, the collector of the seventh triode is connected to the base of the eighth triode, the emitter of the eighth triode is connected to the emitter of the ninth triode, the collector of the ninth triode is connected to the base of the tenth triode, and the emitter of the tenth triode is connected to the dual-mode pre-divider 10 as an output end.

[0048] The resonant circuit is connected from pin 10BIAS and pin 12TANK, and forms a positive feedback sinusoidal oscillation circuit with a phase shift of 720° with internal Q7, Q4, Q5, D1, and Q8. The base of Q6 is connected to the collector of Q7 to form positive feedback. The output frequency amplitude is stabilized by using the amplifier circuit and automatic gain control circuit (D1, Q6, Q7, Q8) in the voltage-controlled oscillation circuit. When the oscillation amplitude increases, the base voltage of Q8 increases, the collector current increases, and the output amplitude decreases. If the oscillation amplitude decreases, the current of the constant current source Q8 decreases, the amplification factor of Q6 and Q7 increases, and the output amplitude increases.

[0049] By adopting the present invention, in the direct in-loop mixing of DDS and PLL, the phase noise near the output 6 GHz signal is taken for testing, and the phase noise output at a frequency shift of 10 kHz is obtained to be -114.92d Bc / Hz; after dual phase-locked loop optimization, the phase noise output by the system at a frequency shift of 10 kHz is better than -126.38d Bc / Hz.

[0050] The working principle of the high-performance phase-locked digital frequency synthesis device of the present invention is as follows: the crystal oscillator circuit provides a high-stability clock signal, the DSP device sends a control instruction, and the DDS device generates a low-frequency sinusoidal signal according to the control instruction, and then mixes it with the reference source of the crystal oscillator circuit and inputs it to the mixer 4. The mixer 4 mixes the clock signal of the reference source and the low-frequency sinusoidal signal to obtain a higher reference frequency, and then passes through the bandpass filter 5 to filter the filtered signal. Enter the phase-locked link. That is, the filtered signal is sent to the phase detector, and the reference frequency after mixing is divided by R times and the frequency signal finally output by the system is divided by N times (pre-divided by the dual-mode pre-divider 10 first), and then the phase is compared, and the error voltage is obtained and then passed through the active low-pass filter 7 to tune the voltage-controlled oscillator and output a signal that meets the system requirements.

[0051] According to the high-performance phase-locked digital frequency synthesis device of the embodiment of the present invention, the design scheme of DDS+PLL frequency synthesizer is adopted, and it has the characteristics of excellent phase noise, small frequency step, low spurious, wide frequency range, strong frequency scalability, etc. It is realized by using PLL synthesis technology, and has the characteristics of high frequency, express, and good spectrum quality. In addition, the circuit design of the present invention is simple, and it is easy to realize miniaturization, and it is suitable for application in communication and measurement equipment with relatively high cost performance requirements. The present invention adopts DDS technology, which can have an extremely wide coverage frequency, and has high stability and accuracy, fast frequency switching, continuous waveform, small error and low price when switching frequency, and is widely used in radar, communication, remote control and telemetry, navigation and instrumentation and other fields.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0053] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. Those skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-performance phase-locked digital frequency synthesis device, characterized in that: include: A crystal oscillator circuit, a DSP device, a DDS device, a mixer, a bandpass filter, a phase detector, a low-pass filter device, an amplifier, a voltage-controlled oscillator, a dual-mode pre-divider, and an N-divider, wherein the output end of the crystal oscillator circuit is connected to the input end of the DDS device, the output end of the DSP device is connected to the input end of the DDS device, the output end of the crystal oscillator circuit is connected to the input end of the mixer, the output end of the mixer is connected to the input end of the bandpass filter, the output end of the bandpass filter is connected to the input end of the phase detector, the output end of the phase detector is connected to the input end of the low-pass filter device, the output end of the low-pass filter device is connected to the input end of the amplifier, the output end of the amplifier is connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the dual-mode pre-divider, the output end of the dual-mode pre-divider is connected to the input end of the N-divider, and the output end of the N-divider is connected to the input end of the phase detector, wherein, The DDS device comprises: a reference clock source, a first phase accumulator, a phase register, a second phase accumulator, a phase-to-amplitude converter, a D / A converter and a low-pass filtering device, wherein the output end of the reference clock source is respectively connected to the D / A converter and the first phase accumulator, the output end of the first phase accumulator is connected to the phase register, the phase register is connected to the second phase accumulator, the output end of the second phase accumulator is connected to the input end of the D / A converter, and the output end of the D / A converter is connected to the input end of the low-pass filtering device. Wherein, the data input terminal of the D / A converter is connected to the limiter converter, the first output terminal of the D / A converter is connected to the negative input terminal of the comparator, the second output terminal of the D / A converter is connected to the positive input terminal of the comparator, and the output terminal of the comparator is connected to the low-pass filtering device; Wherein, the phase detector, low-pass filter device, amplifier, voltage-controlled vibrator, dual-mode pre-divider and program counter constitute a phase-locked loop; The low-pass filter device comprises: a first resistor, a second resistor, a first capacitor, a second capacitor and an operational amplifier, wherein one end of the first resistor is connected to the output end of the comparator, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor is connected to the positive terminal of the operational amplifier and one end of the second capacitor, the other end of the second capacitor is grounded, the negative terminal of the operational amplifier is connected to the output end of the operational amplifier, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the output end of the operational amplifier; The DSP device adopts a DSP chip of model TMS320C5402.

2. The high performance phase-locked digital frequency synthesizer according to claim 1, characterized in that: The dual-mode pre-prescaler includes: a high-speed frequency divider, a first subtraction counter, and a second subtraction counter. The output end of the high-speed frequency divider is connected to the input end of the first subtraction counter, the input end of the second subtraction counter and two input ends of the AND gate. The first subtraction counter is connected to an internal digital phase detector.

3. The high performance phase-locked digital frequency synthesizer according to claim 1, characterized in that: The voltage-controlled oscillator comprises: a resonant circuit and a voltage-controlled oscillation circuit, wherein the resonant circuit comprises a first varactor diode, a second varactor diode, a third varactor diode, a fourth varactor diode, and a first inductor, the reverse end of the first varactor diode is connected to the reverse end of the second varactor diode, the reverse end of the third varactor diode is connected to the reverse end of the fourth varactor diode, the first inductor is connected in parallel between the first varactor diode and the second varactor diode, and between the third varactor diode and the fourth varactor diode, and the voltage-controlled oscillation circuit is connected at both ends of the first inductor.

4. The high performance phase-locked digital frequency synthesizer as claimed in claim 3, characterized in that: The voltage-controlled oscillation circuit includes: a resistor is connected between the base and emitter of the first triode, the emitter of the first triode is connected to the collector of the second triode, the base of the second triode is connected to the collector of the third triode, the base of the third triode is connected to a bias voltage, connected to the base of the fourth triode, the emitters of the fourth triode and the fifth triode are commonly connected to the collector of the sixth triode through a resistor, the collector of the fifth triode is connected to the base of the seventh triode, the collector of the seventh triode is connected to the base of the eighth triode, the emitter of the eighth triode is connected to the emitter of the ninth triode, the collector of the ninth triode is connected to the base of the tenth triode, and the emitter of the tenth triode is connected to the dual-mode pre-divider as an output end.

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