Phase Detector-Based Frequency Synthesizer and Frequency Synthesis Method

Abstract

The present invention provides a phase detector-based frequency synthesizer and its frequency synthesis method. The phase detector-based frequency synthesizer includes a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit, and a frequency doubling and amplifying circuit. Among them, the first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on a reference clock signal; the frequency doubling and amplifying circuit is used to generate a frequency doubling and amplifying signal based on the reference clock signal; the second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency doubling and amplifying signal; the third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal. The phase detector-based frequency synthesizer and its frequency synthesis method provided by the present invention can solve the problems that it is difficult to avoid integer boundary spurs in existing frequency synthesizers using a single-loop phase-locked source, and sometimes the frequency step cannot meet the requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency synthesis, and more specifically, to a phase detector-based frequency synthesizer and a frequency synthesis method thereof. Background Art

[0002] A frequency synthesizer is the source of the carrier signal in an electronic system. In modern electronic technology, the frequency synthesizer has become an important part of the electronic system and is widely used in wireless communication systems. The frequency synthesizer is an important part of the frequency converter. The step size, phase noise, and spurs of the frequency synthesizer will directly affect the indicators of the output signal of the frequency converter. Therefore, a frequency synthesizer with a small step size and low spurs is the key to achieving the indicators of the frequency converter. The frequency converter is also an important part of the wireless communication system. The indicators of the frequency synthesizer will directly affect the overall indicators of the wireless communication system and the quality of the signals in the wireless communication system.

[0003] Commonly used frequency synthesizers using a single-loop phase-locked source are difficult to avoid integer boundary spurs, and sometimes the frequency step size cannot meet the requirements either. Based on the above technical problems, there is an urgent need for a solution that can effectively avoid integer boundary spurs and ensure that the frequency step size meets the requirements. Summary of the Invention

[0004] In view of the above problems, the purpose of the present invention is to provide a phase detector-based frequency synthesizer and a frequency synthesis method to solve the problems that the existing frequency synthesizers using a single-loop phase-locked source are difficult to avoid integer boundary spurs and sometimes the frequency step size cannot meet the requirements.

[0005] The phase detector-based frequency synthesizer provided by the present invention includes a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit, and a frequency doubling and amplifying circuit; wherein,

[0006] The first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on a reference clock signal;

[0007] The frequency doubling and amplifying circuit is used to generate a frequency doubling and amplifying signal based on the reference clock signal;

[0008] The second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency doubling and amplifying signal;

[0009] The third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal.

[0010] In addition, a preferred solution is that it further includes a power divider, and the power divider is used to divide the reference clock signal into two paths of reference clock signals, one path of the reference clock signal is sent to the first-stage phase-locked loop circuit, and the other path of the reference clock signal is sent to the frequency doubling and amplifying circuit.

[0011] In addition, preferably, the first-stage phase-locked loop circuit includes a first phase detector, a first loop filter, and a first voltage-controlled oscillator; wherein,

[0012] The first phase detector is configured to perform phase detection on a path of reference clock signal sent by the power splitter and a first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a first-stage current source signal;

[0013] The first loop filter is configured to filter the first-stage current source signal to generate a first-stage voltage signal;

[0014] The first voltage-controlled oscillator is configured to generate the first-stage frequency signal based on the first-stage voltage signal, and send the first-stage frequency signal to the first phase detector and the second-stage phase-locked loop circuit respectively.

[0015] In addition, preferably, the frequency multiplication and amplification circuit includes a frequency multiplier and an amplifier, wherein,

[0016] The frequency multiplier is configured to perform frequency multiplication processing on another path of reference clock signal sent by the power splitter to generate a primary frequency multiplication signal;

[0017] The amplifier is configured to generate the frequency multiplication and amplification signal based on the primary frequency multiplication signal.

[0018] In addition, preferably, the frequency multiplication and amplification circuit further includes a first filter; wherein,

[0019] The first filter is configured to filter the primary frequency multiplication signal to generate a secondary frequency multiplication signal, and send the secondary frequency multiplication signal to the amplifier;

[0020] The amplifier is configured to amplify the secondary frequency multiplication signal to generate the frequency multiplication and amplification signal.

[0021] In addition, preferably, the second-stage phase-locked loop circuit includes a mixer, a second phase detector, a second loop filter, and a second voltage-controlled oscillator; wherein,

[0022] The mixer is configured to mix the frequency multiplication and amplification signal sent by the frequency multiplication and amplification circuit and a second-stage frequency signal generated by the second voltage-controlled oscillator to generate an intermediate-frequency primary signal;

[0023] The second phase detector is configured to perform phase detection based on the intermediate-frequency primary signal and the first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a second-stage current source signal;

[0024] The second loop filter is used to filter the second-stage current source signal to generate a second-stage voltage signal;

[0025] The second voltage-controlled oscillator is used to generate the second-stage frequency signal based on the second-stage voltage signal and send the second-stage frequency signal to the mixer and the third-stage phase-locked loop circuit respectively.

[0026] In addition, preferably, the second-stage phase-locked loop circuit further includes a second filter; wherein,

[0027] The second filter is used to filter the intermediate-frequency primary signal to generate an intermediate-frequency secondary signal and send the intermediate-frequency secondary signal to the second phase detector;

[0028] The second phase detector is used to perform phase detection on the intermediate-frequency secondary signal and the first-stage frequency signal generated by the first voltage-controlled oscillator and generate the second-stage current source signal.

[0029] In addition, preferably, the third-stage phase-locked loop circuit includes a third phase detector, a third loop filter, and a third voltage-controlled oscillator; wherein,

[0030] The third phase detector is used to perform phase detection on the second-stage frequency signal sent by the second-stage phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator and generate a third-stage current source signal;

[0031] The third loop filter is used to process the third-stage current source signal to generate a third-stage voltage signal;

[0032] The third voltage-controlled oscillator is used to generate the frequency output signal based on the third-stage voltage signal and output the frequency output signal.

[0033] In addition, preferably, let the frequency of the reference clock signal be fo, the frequency of the first-stage frequency signal be f1, the frequency of the second-stage frequency signal be f2, and the frequency of the frequency output signal be f3; wherein,

[0034] The frequency calculation formula of the first-stage phase-locked loop circuit is: The frequency calculation formula of the second-stage phase-locked loop circuit is: The frequency calculation formula of the third-stage phase-locked loop circuit is: Among them, N1 is the integer part of the N - divider of the first phase - detector, frac1 is the numerator of the fractional part of the N - divider of the first phase - detector, and MOD1 is the denominator of the fractional part of the N - divider of the first phase - detector; N2 is the integer part of the N - divider of the second phase - detector, frac2 is the numerator of the fractional part of the N - divider of the second phase - detector, and MOD2 is the denominator of the fractional part of the N - divider of the second phase - detector; N3 is the integer part of the N - divider of the third phase - detector; for the third phase - detector, it only has an integer part and no fractional part; and N1, N2, N3, frac1, frac2, MOD1, and MOD2 are all integer parameters, and the specific values of each integer parameter are determined by the preset indexes of the first phase - detector, the second phase - detector, and the third phase - detector.

[0035] On the other hand, the present invention also provides a frequency synthesis method. The frequency synthesis method performs frequency synthesis through the aforementioned phase - detector - based frequency synthesizer, and includes:

[0036] Generating a first - stage frequency signal by the first - stage phase - locked loop circuit based on a reference clock signal;

[0037] Generating a frequency - multiplied and amplified signal by the frequency - multiplying and amplifying circuit based on the reference clock signal;

[0038] Generating a second - stage frequency signal by the second - stage phase - locked loop circuit based on the first - stage frequency signal and the frequency - multiplied and amplified signal;

[0039] Generating a frequency output signal by the third - stage phase - locked loop circuit based on the second - stage frequency signal.

[0040] Compared with the prior art, the above - mentioned phase - detector - based frequency synthesizer and frequency synthesis method according to the present invention have the following beneficial effects:

[0041] By setting the first - stage phase - locked loop circuit, the second - stage phase - locked loop circuit, the third - stage phase - locked loop circuit, and the frequency - multiplying and amplifying circuit, the present invention has the characteristics of small frequency step and low spurious of the generated frequency output signal. Through the signal processing of the first - stage phase - locked loop circuit and the second - stage phase - locked loop circuit, a reference signal is generated, which can enable the third - stage phase - locked loop circuit to always work in the integer mode, avoiding the problem of integer - boundary spurs generated in the fractional mode of the phase - locked loop.

[0042] To achieve the above and related purposes, one or more aspects of the present invention include features that will be described in detail later and particularly pointed out in the claims. The following description and the drawings illustrate certain exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to cover all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] By referring to the content of the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the drawings:

[0044] Figure 1 It is a schematic structural diagram of a phase detector-based frequency synthesizer provided by the present invention.

[0045] In all the drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed implementation manners

[0046] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is obvious that these embodiments can also be implemented without these specific details. In other examples, in order to facilitate the description of one or more embodiments, well-known structures and devices are shown in the form of block diagrams.

[0047] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention; the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; in addition, unless otherwise clearly specified and defined, the terms "installed", "connected", "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] Figure 1 The schematic diagram of the phase detector-based frequency synthesizer provided by the present invention is shown. It can be seen that Figure 1 the phase detector-based frequency synthesizer provided by the present invention includes a main reference clock module (corresponding to the attachment Figure 1a reference clock (in the reference clock), a frequency multiplication and amplification circuit, and a triple-phase locked loop circuit. Among them, the reference clock module is used to output a reference clock signal. The triple-phase locked loop circuit includes a first-stage phase locked loop circuit, a second-stage phase locked loop circuit, and a third-stage phase locked loop circuit. The first-stage phase locked loop circuit is used to generate a first-stage frequency signal based on the reference clock signal (the original input signal). The frequency multiplication and amplification circuit is used to generate a frequency multiplication and amplification signal based on the reference clock signal. The second-stage phase locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency multiplication and amplification signal. The third-stage phase locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal.

[0049] Furthermore, to facilitate the first-stage phase locked loop circuit and the frequency multiplication and amplification circuit to both receive mutually synchronized reference clock signals in a timely manner, the frequency synthesizer based on a phase detector provided by the present invention further includes a power divider. The power divider is used to divide the reference clock signal into (divide by power) two reference clock signals. One of the reference clock signals is sent to the first-stage phase locked loop circuit, and the other reference clock signal is sent to the frequency multiplication and amplification circuit.

[0050] In a specific embodiment of the present invention, the first-stage phase locked loop circuit may include a first phase detector (corresponding to Figure 1 phase detector 1 in Figure 1 ), a first loop filter (corresponding to Figure 1 loop filter 1 in

[0051] ), and a first voltage-controlled oscillator (corresponding to

[0052] VCO1 in Figure 1 Figure 1 ). Among them, the first phase detector is used to perform phase detection on one of the reference clock signals sent by the power divider and the first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a first-stage current source signal. The first loop filter is used to process (filter) the first-stage current source signal to generate a first-stage voltage signal. The first voltage-controlled oscillator is used to generate the first-stage frequency signal based on the first-stage voltage signal, and send the first-stage frequency signal to the first phase detector and the second-stage phase locked loop circuit respectively. Among them, the first-stage voltage signal is used to control the frequency of the first-stage frequency signal.

[0051] In another specific embodiment of the present invention, to achieve the frequency multiplication and amplification effect of the frequency multiplication and amplification circuit, the frequency multiplication and amplification circuit may include a frequency multiplier and an amplifier. Among them, the frequency multiplier is used to perform frequency multiplication on the other reference clock signal sent by the power divider to generate a primary frequency multiplication signal. The amplifier is used to generate the frequency multiplication and amplification signal based on the primary frequency multiplication signal.

[0052] In addition, to further improve the accuracy of the frequency multiplication and amplification signal, the frequency multiplication and amplification circuit may further include a first filter (corresponding to Figure 1The filter in 1); wherein, the first filter is used to filter the frequency - doubled primary signal to generate a frequency - doubled secondary signal and send the frequency - doubled secondary signal to the amplifier; the amplifier is used to amplify the frequency - doubled secondary signal to generate the frequency - doubled amplified signal.

[0053] In a preferred embodiment of the present invention, the second - stage phase - locked loop circuit may include a mixer, a second phase - detector (corresponding to Figure 1 the phase - detector 2 in Figure 1 the loop filter 2 in Figure 1 and a second voltage - controlled oscillator (corresponding to

[0054] VCO2 in Figure 1 ); wherein, the mixer is used to mix the frequency - doubled amplified signal sent by the frequency - doubled amplification circuit and the second - stage frequency signal generated by the second voltage - controlled oscillator to generate an intermediate - frequency primary signal; the second phase - detector is used to perform phase - detection based on the intermediate - frequency primary signal and the first - stage frequency signal generated by the first voltage - controlled oscillator and generate a second - stage current - source signal; the second loop filter is used to filter the second - stage current - source signal to generate a second - stage voltage signal; the second voltage - controlled oscillator is used to generate the second - stage frequency signal based on the second - stage voltage signal and send the second - stage frequency signal to the mixer and the third - stage phase - locked loop circuit respectively; wherein, the second - stage voltage signal is used to control the frequency of the second - stage frequency signal.

[0055] In another preferred solution of the present invention, the third - stage phase - locked loop circuit may further include a third phase - detector (corresponding to Figure 1 the phase - detector 3 in Figure 1 the loop filter 3 in Figure 1VCO3 in it); wherein, the third phase detector is used to perform phase detection on the second-stage frequency signal sent by the second-stage phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-stage current source signal; the third loop filter is used to process the third-stage current source signal to generate a third-stage voltage signal; the third voltage-controlled oscillator is used to generate the frequency output signal based on the third-stage voltage signal and output the frequency output signal; wherein, the third-stage voltage signal is used to control the frequency of the frequency output signal.

[0056] It should be noted that the working mode of the third-stage phase-locked loop circuit of the frequency synthesizer based on the phase detector provided by the present invention is an integer mode, which directly avoids the problem of integer boundary spurs caused by the decimal mode. And, combined with Figure 1 As shown in the structure of the frequency synthesizer based on the phase detector provided by the present invention, assuming that the frequency of the reference clock signal is fo, the frequency of the first-stage frequency signal is f1, the frequency of the second-stage frequency signal is f2, and the frequency of the frequency output signal is f3; wherein, the frequency calculation formula of the first-stage phase-locked loop circuit is: The frequency calculation formula of the second-stage phase-locked loop circuit is: The frequency calculation formula of the third-stage phase-locked loop circuit is: , where N1, N2, N3, frac1, frac2, MOD1, MOD2 are all integer parameters, and the specific values of each integer parameter are determined by the preset indexes of the first phase detector, the second phase detector, and the third phase detector. Through calculation, the output frequency of the frequency output signal of the third-stage phase-locked loop circuit is: On the other hand, to further illustrate the working principle of the frequency synthesizer based on the phase detector provided by the present invention, the present invention also provides a frequency synthesis method. The frequency synthesis method performs frequency synthesis through the aforementioned frequency synthesizer based on the phase detector, including:

[0057] Generating a first-stage frequency signal based on a reference clock signal through the first-stage phase-locked loop circuit;

[0058] Generating a frequency-doubled amplified signal based on the reference clock signal through the frequency-doubling and amplifying circuit;

[0059] Generating a second-stage frequency signal based on the first-stage frequency signal and the frequency-doubled amplified signal through the second-stage phase-locked loop circuit;

[0060] Generating a frequency output signal based on the second-stage frequency signal through the third-stage phase-locked loop circuit.

[0061] As can be seen from the above specific embodiments, the phase detector-based frequency synthesizer and frequency synthesis method provided by the present invention have the characteristics of small frequency step and low spurious of the generated frequency output signal by setting the first-stage phase-locked loop circuit, the second-stage phase-locked loop circuit, the third-stage phase-locked loop circuit and the frequency doubling and amplification circuit; in addition, through the signal processing of the first-stage phase-locked loop circuit and the second-stage phase-locked loop circuit, a reference signal is generated, which can make the third-stage phase-locked loop circuit always work in the integer mode, avoiding the problem of integer boundary spurs generated in the fractional mode of the phase-locked loop.

[0062] As described above with reference to Figure 1 The phase detector-based frequency synthesizer and frequency synthesis method provided by the present invention are described by way of example. However, those skilled in the art should understand that various improvements can be made to the above-mentioned phase detector-based frequency synthesizer and frequency synthesis method of the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the appended claims.

Claims

1. A frequency synthesizer based on a phase detector, characterized in that: It includes a first-stage phase-locked loop circuit, a second-stage phase-locked loop circuit, a third-stage phase-locked loop circuit, a frequency multiplier amplifier circuit and a power divider; wherein, The first-stage phase-locked loop circuit is used to generate a first-stage frequency signal based on a reference clock signal; The frequency multiplication and amplification circuit is used to generate a frequency multiplication and amplification signal based on the reference clock signal; The second-stage phase-locked loop circuit is used to generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal; The third-stage phase-locked loop circuit is used to generate a frequency output signal based on the second-stage frequency signal; The power divider is used to divide the reference clock signal into two reference clock signals, one of which is sent to the first-stage phase-locked loop circuit, and the other is sent to the frequency multiplication amplifier circuit; wherein, The first-stage phase-locked loop circuit includes a first phase detector, a first loop filter and a first voltage-controlled oscillator; wherein the first phase detector is used to perform phase detection on a reference clock signal sent by the power divider and a first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a first-stage current source signal; the first loop filter is used to process the first-stage current source signal to generate a first-stage voltage signal; the first voltage-controlled oscillator is used to generate the first-stage frequency signal based on the first-stage voltage signal, and send the first-stage frequency signal to the first phase detector and the second-stage phase-locked loop circuit respectively; The second-stage phase-locked loop circuit includes a mixer, a second phase detector, a second loop filter and a second voltage-controlled oscillator; wherein the mixer is used to mix the frequency-multiplied amplified signal sent by the frequency-multiplied amplification circuit and the second-stage frequency signal generated by the second voltage-controlled oscillator to generate an intermediate frequency primary signal; the second phase detector is used to perform phase detection based on the intermediate frequency primary signal and the first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a second-stage current source signal; the second loop filter is used to filter the second-stage current source signal to generate a second-stage voltage signal; the second voltage-controlled oscillator is used to generate the second-stage frequency signal based on the second-stage voltage signal, and send the second-stage frequency signal to the mixer and the third-stage phase-locked loop circuit respectively; The third-level phase-locked loop circuit includes a third phase detector, a third loop filter and a third voltage-controlled oscillator; wherein the third phase detector is used to perform phase detection on the second-level frequency signal sent by the second-level phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-level current source signal; the third loop filter is used to process the third-level current source signal to generate a third-level voltage signal; the third voltage-controlled oscillator is used to generate the frequency output signal based on the third-level voltage signal, and output the frequency output signal.

2. In the phase detector based frequency synthesizer as claimed in claim 1, it is characterized in that The frequency multiplication and amplification circuit comprises a frequency multiplier and an amplifier, wherein: The frequency multiplier is used to perform frequency multiplication processing on another reference clock signal sent by the power divider to generate a frequency multiplied primary signal; The amplifier is used to generate the frequency-doubled amplified signal based on the frequency-doubled primary signal.

3. The frequency synthesizer based on phase detector as claimed in claim 2, characterized in that: The frequency multiplication amplifier circuit further includes a first filter; wherein, The first filter is used to filter the frequency-doubled primary signal to generate a frequency-doubled secondary signal, and send the frequency-doubled secondary signal to the amplifier; The amplifier is used to amplify the frequency-doubled secondary signal to generate the frequency-doubled amplified signal.

4. The frequency synthesizer based on phase detector as claimed in claim 3, characterized in that: The second-stage phase-locked loop circuit also includes a second filter; wherein, The second filter is used for filtering the intermediate frequency primary signal to generate an intermediate frequency secondary signal, and sending the intermediate frequency secondary signal to the second phase detector; The second phase detector is used to perform phase detection on the intermediate frequency secondary signal and the first-level frequency signal generated by the first voltage-controlled oscillator, and generate the second-level current source signal.

5. The frequency synthesizer based on phase detector as claimed in claim 4, characterized in that: Assume that the frequency of the reference clock signal is fo, the frequency of the first-level frequency signal is f1, the frequency of the second-level frequency signal is f2, and the frequency of the frequency output signal is f3; wherein, The frequency calculation formula of the first-stage phase-locked loop circuit is: The frequency calculation formula of the second-stage phase-locked loop circuit is: The frequency calculation formula of the third-stage phase-locked loop circuit is: Among them, N1 is the integer part of the N frequency divider of the first phase detector, frac1 is the numerator of the fractional part of the N frequency divider of the first phase detector, and MOD1 is the denominator of the fractional part of the N frequency divider of the first phase detector; N2 is the integer part of the N frequency divider of the second phase detector, frac2 is the numerator of the fractional part of the N frequency divider of the second phase detector, and MOD2 is the denominator of the fractional part of the N frequency divider of the second phase detector; N3 is the integer part of the N frequency divider of the third phase detector; for the third phase detector, it has only an integer part and no fractional part; and N1, N2, N3, frac1, frac2, MOD1, and MOD2 are all integer parameters, and the specific value of each integer parameter is determined by the preset indicators of the first phase detector, the second phase detector, and the third phase detector.

6. A frequency synthesis method, characterized in that: The frequency synthesis method performs frequency synthesis by using the phase detector-based frequency synthesizer according to any one of claims 1 to 5, comprising: Generate a first-stage frequency signal based on a reference clock signal by the first-stage phase-locked loop circuit; Generate a frequency-multiplied amplified signal based on the reference clock signal by the frequency-multiplied amplification circuit; Generate a second-stage frequency signal based on the first-stage frequency signal and the frequency-multiplied amplified signal by the second-stage phase-locked loop circuit; The frequency output signal is generated based on the second-stage frequency signal by the third-stage phase-locked loop circuit; wherein, The first-stage phase-locked loop circuit includes a first phase detector, a first loop filter and a first voltage-controlled oscillator; wherein the first phase detector is used to perform phase detection on a reference clock signal sent by the power divider and a first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a first-stage current source signal; the first loop filter is used to process the first-stage current source signal to generate a first-stage voltage signal; the first voltage-controlled oscillator is used to generate the first-stage frequency signal based on the first-stage voltage signal, and send the first-stage frequency signal to the first phase detector and the second-stage phase-locked loop circuit respectively; The second-stage phase-locked loop circuit includes a mixer, a second phase detector, a second loop filter and a second voltage-controlled oscillator; wherein the mixer is used to mix the frequency-multiplied amplified signal sent by the frequency-multiplied amplification circuit and the second-stage frequency signal generated by the second voltage-controlled oscillator to generate an intermediate frequency primary signal; the second phase detector is used to perform phase detection based on the intermediate frequency primary signal and the first-stage frequency signal generated by the first voltage-controlled oscillator, and generate a second-stage current source signal; the second loop filter is used to filter the second-stage current source signal to generate a second-stage voltage signal; the second voltage-controlled oscillator is used to generate the second-stage frequency signal based on the second-stage voltage signal, and send the second-stage frequency signal to the mixer and the third-stage phase-locked loop circuit respectively; The third-level phase-locked loop circuit includes a third phase detector, a third loop filter and a third voltage-controlled oscillator; wherein the third phase detector is used to perform phase detection on the second-level frequency signal sent by the second-level phase-locked loop circuit and the frequency output signal generated by the third voltage-controlled oscillator, and generate a third-level current source signal; the third loop filter is used to process the third-level current source signal to generate a third-level voltage signal; the third voltage-controlled oscillator is used to generate the frequency output signal based on the third-level voltage signal, and output the frequency output signal.

Images