A broadband signal receiving preprocessing component and method

Abstract

The present invention discloses a broadband signal receiving preprocessing component and method, which belongs to the field of communication, and includes a programmable logic device, an analog-to-digital converter, a clock distribution chip and a photoelectric conversion module; the analog-to-digital converter receives an input broadband radio frequency signal or a linear frequency modulation signal for correction, and outputs the sampled data after analog-to-digital conversion; the programmable logic device receives an external control signal and the sampled data input by the analog-to-digital converter, preprocesses the sampled data according to the control signal, and outputs the sampled data of the preprocessed broadband radio frequency signal to the photoelectric conversion module; the photoelectric conversion module receives an electrical signal output by the programmable logic device containing the preprocessed data, and outputs an optical signal after photoelectric conversion; the clock distribution chip receives an external synchronization signal and a clock signal, and outputs a clock synchronization signal required for the programmable logic device and the analog-to-digital converter to work. The present invention can realize large instantaneous bandwidth processing, and at the same time realize adaptive amplitude and phase correction to improve the accuracy and efficiency of amplitude and phase correction.

Description

Technical Field

[0001] The invention belongs to the field of communications, and in particular relates to a broadband signal receiving preprocessing component and method. Background Art

[0002] The existing signal receiving preprocessing components are not able to process sufficient instantaneous bandwidth (less than 200MHz). At the same time, during amplitude and phase correction, unlike the narrowband correction model where the amplitude error A and the phase error φ are fixed coefficients, the amplitude error A and the phase error φ in the broadband correction model are not fixed values, but frequency-related error functions A(f) and φ(f). Broadband amplitude and phase correction is usually implemented by the host computer transmitting the calibration signal, collecting and preprocessing the signal, and then performing amplitude and phase analysis on the preprocessing result on the host computer to obtain the amplitude and phase error with the calibration signal, and then calculating the correction coefficient and feeding it back to the preprocessing component for amplitude and phase adjustment to complete the correction. This method cannot achieve a self-closed loop within the amplitude and phase adjustment component, and requires a lot of time and effort. Summary of the invention

[0003] The purpose of the present invention is to provide a broadband signal receiving preprocessing component and method, which can realize large instantaneous bandwidth processing, and can also realize adaptive amplitude and phase correction, thereby improving the accuracy and efficiency of amplitude and phase correction.

[0004] In order to achieve the above-mentioned object, one aspect of the present invention provides a broadband signal receiving preprocessing component, including a programmable logic device, an analog-to-digital converter, a clock distribution chip and an optoelectronic conversion module;

[0005] The analog-to-digital converter is used to receive an input broadband radio frequency signal or a linear frequency modulation signal for correction, and output the sampled data after analog-to-digital conversion; the programmable logic device is used to receive an external control signal and the sampled data input by the analog-to-digital converter, pre-process the sampled data according to the control signal, and output the sampled data of the pre-processed broadband radio frequency signal to the photoelectric conversion module; the photoelectric conversion module is used to receive the electrical signal output by the programmable logic device containing the pre-processed data, and output an optical signal after photoelectric conversion; the clock distribution chip is used to receive an external synchronization signal and a clock signal, and output a clock synchronization signal required for the programmable logic device and the analog-to-digital converter to work;

[0006] The programmable logic device includes an equalization correction module, a filter extraction module and an equalization coefficient calculation module. The equalization correction module uses an FIR filter as an equalizer to perform amplitude and phase correction on the sampled data, and receives the equalization filter coefficients calculated by the equalization coefficient calculation module, and updates the tap coefficients of the FIR filter to achieve adaptive equalization; the filter extraction module is used to receive the corrected data output by the equalization correction module, pre-process the data and output it;

[0007] The equalization coefficient calculation module is used to receive the sampling data of the pre-processed correction linear frequency modulation signal output by the filtering and extraction module, obtain the frequency response function before correction by fast Fourier transform, obtain the ideal equalization filter response function by comparing it with the frequency response function of the standard linear frequency modulation signal, obtain the correction response function according to the ideal equalization filter response function and the actual effective bandwidth to be equalized, and then obtain the equalization filter coefficient by fast inverse Fourier transform.

[0008] Preferably, the programmable logic device further includes an analog-to-digital converter driving module, a data packaging module, and a high-speed serial interface module;

[0009] The analog-to-digital converter driving module is used to configure parameters of the analog-to-digital converter, receive sampled data from the analog-to-digital converter and rearrange the received sampled data in parallel;

[0010] The data packaging module receives the pre-processed data output by the filtering and extraction module, performs multi-channel interleaving and splits the data into multiple information frames for output;

[0011] The high-speed serial interface module performs parallel-to-serial conversion on the multiple information frames output by the data packaging module, converts the converted information frames into serial data, and then outputs the converted data.

[0012] Preferably, the analog-to-digital converter driving module is also used to configure the analog-to-digital converter to output a PRBS test code and monitor and count bit errors. The high-speed serial interface module is also used to use the PRBS test code to perform self-transmission and self-reception verification to verify the stability of the interface operation.

[0013] Preferably, the filtering and extraction module adopts a parallel filtering structure, completes the down-conversion and phase rotation of the input signal through a digitally controlled oscillator, and realizes fixed-point sampling of the data through a three-stage filter, wherein the first and second stage filters are FIR half-band filters with fixed tap coefficients, and the third stage filter is a FIR filter with reconfigurable coefficients.

[0014] Preferably, the equalization coefficient calculation module obtains a pre-correction frequency response function by performing a 256-point fast Fourier transform, and obtains an ideal equalization filter response function by dividing the pre-correction frequency response function with the frequency response function of a 256-point standard linear frequency modulation signal; according to the actual effective bandwidth to be equalized, the frequency response values ​​of points outside the effective bandwidth in the ideal equalization filter response function are replaced with the average value of all frequency response values ​​within the effective bandwidth; 8-point equal-interval sampling is performed on the replaced response function to obtain a sampled 32-point frequency response, and a 32-order filter coefficient is obtained as the equalization filter coefficient by performing a fast inverse Fourier transform on the 32-point frequency response.

[0015] Another aspect of the present invention provides a broadband signal reception preprocessing method, which uses the broadband signal reception preprocessing component to perform broadband signal reception preprocessing, including:

[0016] At the beginning of each working cycle, the component parses the working state control field in the control signal sent externally, and controls the programmable logic device to switch the working state according to the working state control field, and the working state includes a normal working state and a coefficient correction state;

[0017] In the normal working state, the component receives the sampled data of the broadband radio frequency signal output by the analog-to-digital converter, completes the preprocessing of the sampled data through the programmable logic device, and outputs an optical signal after performing photoelectric conversion through the photoelectric conversion module;

[0018] In the coefficient correction state, the component receives sampling data of the linear frequency modulation signal for correction output by the analog-to-digital converter, completes data preprocessing through the filtering extraction module, completes the calculation of the equalization filter coefficient through the equalization coefficient calculation module, transmits it to the equalization correction module and updates the tap coefficient of the FIR filter.

[0019] Preferably, the programmable logic device also includes an analog-to-digital converter driving module and a high-speed serial interface module. The working state also includes a self-test state. In the self-test state, the analog-to-digital converter driving module configures the analog-to-digital converter to output a PRBS test code, and monitors and counts bit errors. The high-speed serial interface module uses the PRBS test code to perform self-transmission and self-reception verification to verify the stability of the interface operation.

[0020] The broadband signal reception preprocessing component and method according to the above aspects of the present invention can realize large instantaneous bandwidth processing, and can also realize adaptive amplitude and phase correction, thereby improving the accuracy and efficiency of amplitude and phase correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0022] Figure 1 is a structural block diagram of a broadband signal receiving preprocessing component according to an embodiment of the present invention;

[0023] Figure 2 is a block diagram of an FPGA according to an embodiment of the present invention;

[0024] Figure 3It is a structural block diagram of a filtering and extraction module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] An embodiment of the present invention provides a broadband signal receiving preprocessing component, such as Figure 1 As shown, the broadband signal receiving preprocessing component of the embodiment of the present invention includes a field programmable logic device (FPGA), an analog-to-digital converter (ADC), a clock distribution chip and an optoelectronic conversion module.

[0027] The ADC is used to receive the input broadband RF signal and the linear frequency modulation signal for correction, and output the sampled data after analog-to-digital conversion. The FPGA is used to receive the external control signal and the sampled data input by the ADC, and complete the amplitude and phase correction (amplitude and phase correction), equalization, filtering and other pre-processing of the sampled data according to the input control signal, and then output it to the photoelectric conversion module. The photoelectric conversion module is used to receive the electrical signal containing the pre-processed data output by the FPGA, perform photoelectric conversion, and output the optical signal to the post-processing equipment. The clock distribution chip receives the external synchronization signal and clock signal (reference frequency source), and outputs the clock synchronization signal required for the operation of the FPGA and ADC.

[0028] FPGA Figure 2 The shown module includes an analog-to-digital converter ADC driving module, an equalization correction module, a filtering extraction module, an equalization coefficient calculation module, a data packaging module, and a high-speed serial interface module.

[0029] The ADC driver module is used to complete the parameter configuration of the ADC, complete the reception of ADC sampling data and parallel rearrange the received sampling data in accordance with the JESD204B high-speed protocol to meet the input requirements of the subsequent equalization correction module, and support the verification of the test code input to the ADC to verify the correctness of the high-speed interface used to communicate with the ADC and the use of the JESD204B protocol.

[0030] The equalization correction module uses the FIR (Finite Impulse Response) filter as an equalizer to perform amplitude and phase error correction on the received sampled data, so that the frequency response of each channel after equalization can be close to the reference signal under the same amplitude and phase correction coefficient. At the same time, the equalization correction module receives the real-time equalization filter coefficient obtained by the equalization coefficient calculation module every cycle, and updates the tap coefficient of the FIR filter in the module to realize the function of adaptive equalization.

[0031] The filter extraction module receives the corrected waveform data output by the equalization correction module and performs signal preprocessing processes such as down-conversion, filtering, and extraction on the data. Figure 3 The parallel filtering structure shown in the figure increases the instantaneous bandwidth that can be processed and reduces the operating frequency. The sampled data enters the filter extraction module in the form of 8 parallel channels, and the NCO (Numerically Controlled Oscillator) module completes the down-conversion and phase rotation of the input signal, and then passes through a three-stage bypassable filter-extraction structure to achieve fixed-point sampling of the data. The first-stage filter FIR0 and the second-stage filter FIR1 are FIR half-band filters with fixed tap coefficients, and the third-stage filter FIR2 is a FIR filter with reconfigurable coefficients. Figure 3 The "↓" symbol in the figure indicates that the data is decimated (downsampled), and the number after "↓" indicates the decimation multiple. The first filter FIR0 performs a fixed 2x decimation (↓2), the second filter FIR1 performs a fixed 2x decimation (↓2), and the third filter FIR2 can perform 2x decimation (↓2), 3x decimation (↓3), and 5x decimation (↓5). After filtering and decimation, the data is also output in 8-way parallel form. By using parallel processing, the maximum receiving instantaneous bandwidth is increased from 100MHz of serial to 800MHz.

[0032] The equalization coefficient calculation module is used to receive the sampling data of the pre-processed correction linear frequency modulation signal output by the filtering and extraction module, obtain the frequency response function before correction by fast Fourier transform, obtain the ideal equalization filter response function by comparing it with the frequency response function of the standard linear frequency modulation signal, obtain the correction response function according to the ideal equalization filter response function and the actual effective bandwidth to be equalized, and then obtain the equalization filter coefficient by fast inverse Fourier transform.

[0033] In one embodiment, the equalization coefficient calculation module uses an FPGA instantiated embedded microprocessor module (Microblaze), receives a linear frequency modulation signal for correction in the coefficient correction state, and performs a 256-point fast Fourier transform (FFT) to obtain a frequency response function before correction. .

[0034] Will The frequency response function of the 256-point standard linear FM signal has been stored in ROM Divide and obtain the ideal equalization filter response function .

[0035] According to the effective bandwidth to be equalized, the frequency response function of the equalization filter is The points outside the effective bandwidth are processed to improve the equalization effect. Assume that the left and right boundary points corresponding to the effective bandwidth in the equalization filter response function are , .when or The corresponding frequency response value is If the frequency response values ​​of these out-of-band points are outside the effective bandwidth, they are replaced by the average value of all frequency response values ​​within the band.

[0036] Right now , ( or )

[0037] Equalized response to processing Perform 8-point equal-interval sampling to obtain a 32-point frequency response after sampling .

[0038] Last pair Perform a fast inverse Fourier transform (IFFT) to obtain the corresponding 32-order filter coefficients, send the calculated coefficients to the equalization correction module through the AXI bus, and update the tap coefficients of the FIR equalization filter to complete the component adaptive amplitude and phase equalization correction. After equalization, the channel amplitude consistency and in-band flatness are reduced from 4dB to within 1dB, and the phase consistency is reduced to within 3°.

[0039] The data packing module receives the pre-processed data output by the filter extraction module, performs multi-channel interleaving, and splits it into multiple information frames for output according to a specific protocol. The high-speed serial interface module performs parallel-to-serial conversion on the frame data output by the data packing module, converts it into serial data, and outputs it through the high-speed serial interface of the FPGA.

[0040] The working mode of the broadband signal receiving preprocessing component of the embodiment of the present invention is as follows: the component switches the working state by identifying the external control signal. At the beginning of each working cycle of the component, the component parses the working state control field in the control signal sent externally, and controls the internal state machine of the FPGA to switch different working states according to the working state control field. The working state is divided into three types: normal working state, coefficient correction state and self-test state. It should be noted that in the coefficient correction state, the time to complete the calculation and update of the equalization coefficient is usually greater than one working cycle, so before the new working cycle arrives, the FPGA will check whether the previous working state has been completed. Only when the FPGA completes the previous work and is in an idle state will it respond to the new working state control field.

[0041] Under normal working conditions, all modules are in working state. The components receive the RF signal sampled by the ADC and complete the preprocessing of the sampled data inside the FPGA. Finally, the preprocessed results are packaged and sent to the subsequent equipment through the high-speed serial interface module.

[0042] In the coefficient correction state, the component completes the calculation and update of the equalization filter coefficients. The main working modules are the filter extraction module, the equalization correction module and the equalization coefficient calculation module. The component receives the correction linear frequency modulation signal sampled by the ADC, completes the data preprocessing through the filter extraction module, and sends it to the equalization coefficient calculation module to complete the calculation of the equalization filter coefficients. The calculated filter coefficients are transmitted to the equalization correction module through the AXI bus interface and the FIR filter tap coefficients therein are updated.

[0043] In the self-test state, the component performs bit error checks on its external high-speed interface. The main working modules are the ADC driver module and the high-speed serial interface module. The ADC driver module configures the ADC to output a specific PRBS (Pseudo-Random Binary Sequence) test code, and monitors and counts the bit errors. The high-speed serial interface module implements the self-loop working mode, uses the PRBS test code for self-transmission and self-reception verification, and verifies the stability of the interface operation.

[0044] The broadband signal receiving preprocessing component and method of the embodiment of the present invention can realize large instantaneous bandwidth processing, and realize adaptive amplitude and phase correction at the same time, improve the accuracy and efficiency of amplitude and phase correction, and the maximum instantaneous bandwidth of the received signal that can be processed can reach 800MHz, the amplitude consistency between different channels is within 1dB, and the phase consistency is within 3°; it can realize adaptive updating of filter coefficients, and the amplitude and phase correction method is more flexible compared with other receiving components.

[0045] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A broadband signal receiving preprocessing component, characterized in that: It includes a programmable logic device, an analog-to-digital converter, a clock distribution chip and an optoelectronic conversion module; The analog-to-digital converter is used to receive an input broadband radio frequency signal or a linear frequency modulation signal for correction, and output the sampled data after analog-to-digital conversion; the programmable logic device is used to receive an external control signal and the sampled data input by the analog-to-digital converter, pre-process the sampled data according to the control signal, and output the sampled data of the pre-processed broadband radio frequency signal to the photoelectric conversion module; the photoelectric conversion module is used to receive the electrical signal output by the programmable logic device containing the pre-processed data, and output an optical signal after photoelectric conversion; the clock distribution chip is used to receive an external synchronization signal and a clock signal, and output a clock synchronization signal required for the programmable logic device and the analog-to-digital converter to work; The programmable logic device includes an equalization correction module, a filter extraction module and an equalization coefficient calculation module. The equalization correction module uses an FIR filter as an equalizer to perform amplitude and phase correction on the sampled data, and receives the equalization filter coefficient calculated by the equalization coefficient calculation module, and updates the tap coefficient of the FIR filter to achieve adaptive equalization; The filtering and extraction module is used to receive the corrected data output by the equalization correction module, pre-process the data and output it; The equalization coefficient calculation module is used to receive the sampling data of the pre-processed correction linear frequency modulation signal output by the filtering and extraction module, obtain the frequency response function before correction by fast Fourier transform, obtain the ideal equalization filter response function by comparing it with the frequency response function of the standard linear frequency modulation signal, obtain the correction response function according to the ideal equalization filter response function and the actual effective bandwidth to be equalized, and then obtain the equalization filter coefficient by fast inverse Fourier transform.

2. The broadband signal receiving preprocessing component according to claim 1, characterized in that: The programmable logic device also includes an analog-to-digital converter driving module, a data packaging module, and a high-speed serial interface module; The analog-to-digital converter driving module is used to configure parameters of the analog-to-digital converter, receive sampled data from the analog-to-digital converter and rearrange the received sampled data in parallel; The data packaging module receives the pre-processed data output by the filtering and extraction module, performs multi-channel interleaving and splits the data into multiple information frames for output; The high-speed serial interface module performs parallel-to-serial conversion on the multiple information frames output by the data packaging module, converts the converted information frames into serial data, and then outputs the converted data.

3. The broadband signal receiving preprocessing component according to claim 2, characterized in that: The analog-to-digital converter driving module is also used to configure the analog-to-digital converter to output a PRBS test code and monitor and count bit errors. The high-speed serial interface module is also used to use the PRBS test code to perform self-transmission and self-reception verification to verify the stability of the interface operation.

4. The broadband signal receiving preprocessing component according to any one of claims 1 to 3, characterized in that: The filter extraction module adopts a parallel filtering structure, completes the down-conversion and phase rotation of the input signal through a digitally controlled oscillator, and realizes fixed-point sampling of data through a three-stage filter, wherein the first and second stage filters are FIR half-band filters with fixed tap coefficients, and the third stage filter is a FIR filter with reconfigurable coefficients.

5. The broadband signal receiving preprocessing component according to any one of claims 1 to 3, characterized in that: The equalization coefficient calculation module obtains a pre-correction frequency response function by performing a 256-point fast Fourier transform, and obtains an ideal equalization filter response function by dividing the pre-correction frequency response function with the frequency response function of a 256-point standard linear frequency modulation signal; according to the actual effective bandwidth to be equalized, the frequency response values ​​of the points outside the effective bandwidth in the ideal equalization filter response function are replaced with the average value of all frequency response values ​​within the effective bandwidth; 8-point equal-interval sampling is performed on the replaced response function to obtain a sampled 32-point frequency response, and a 32-order filter coefficient is obtained as the equalization filter coefficient by performing a fast inverse Fourier transform on the 32-point frequency response.

6. A broadband signal receiving preprocessing method, characterized in that: Using the broadband signal reception preprocessing component according to any one of claims 1 to 5 to perform broadband signal reception preprocessing, comprising: At the beginning of each working cycle, the component parses the working state control field in the control signal sent externally, and controls the programmable logic device to switch the working state according to the working state control field, and the working state includes a normal working state and a coefficient correction state; In the normal working state, the component receives the sampled data of the broadband radio frequency signal output by the analog-to-digital converter, completes the preprocessing of the sampled data through the programmable logic device, and outputs an optical signal after performing photoelectric conversion through the photoelectric conversion module; In the coefficient correction state, the component receives sampling data of the linear frequency modulation signal for correction output by the analog-to-digital converter, completes data preprocessing through the filtering extraction module, completes the calculation of the equalization filter coefficient through the equalization coefficient calculation module, transmits it to the equalization correction module and updates the tap coefficient of the FIR filter.

7. The broadband signal receiving preprocessing method according to claim 6, characterized in that: The programmable logic device also includes an analog-to-digital converter drive module and a high-speed serial interface module. The working state also includes a self-test state. In the self-test state, the analog-to-digital converter drive module configures the analog-to-digital converter to output a PRBS test code, and monitors and counts bit errors. The high-speed serial interface module uses the PRBS test code to perform self-transmission and self-reception verification to verify the stability of the interface operation.

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