Coding method, device, system and chip

Abstract

The invention discloses a coding method, device and system and a chip, and relates to the technical field of communication. In the method, a block pair is sent through a serial channel, the block pair comprises a first block and a second block, the lengths of the first block and the second block are the same, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include contents indicating the type of the second block, so that the second block can carry other contents except the contents indicating the type of the second block, and the expandability of the second block is high. Further, the lengths of the first block and the second block are the same, the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and include the same number of bits of the signal. Through one serial channel transmission block pair, the number of pins of the serial channel can be reduced. The serial channel in the method can be realized based on the MII, so that the method can be applied to the scene of the MII.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a coding method, device, system and chip. Background Art

[0002] In the field of communication technology, a signal transmitting end may encode a signal to obtain an encoding result, and transmit the encoding result to a signal receiving end, and the signal receiving end decodes the received encoding result to restore the signal. Summary of the invention

[0003] The present application proposes an encoding method, a decoding method, a device, a system and a chip for transmitting signals in the form of block pairs.

[0004] In a first aspect, a coding method is provided, the method comprising: sending a block pair through a serial channel, the block pair comprising a first block and a second block, the first block and the second block having the same length, and the first block indicating the type of the second block. In the method, since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In addition, the first block and the second block have the same length, so the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By sending the block pair through a serial channel, the number of pins of the serial channel can be small. Furthermore, the serial channel in the method can be implemented based on a media independent interface (MII), so the method can be applied to the MII scenario.

[0005] In a second aspect, a decoding method is provided, the method comprising: receiving a block pair through a serial channel, the block pair comprising a first block and a second block, the first block and the second block having the same length, and the first block indicating the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In addition, the first block and the second block have the same length, so the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By receiving the block pair through a serial channel, the number of pins of the serial channel can be small. Furthermore, the serial channel in the method can be implemented based on MII, so the method can be applied to the MII scenario.

[0006] In a possible implementation manner of the first aspect or the second aspect, the first block indicates a type of the second block, including but not limited to at least one of the following:

[0007] The first block is a data block, indicating that the second block is a data block;

[0008] In the case where the first block is a control block with a value of X, indicating that the second block is a control block;

[0009] In the case where the first block is a control block with a value of Y, it indicates that the second block is a management block;

[0010] In the case where the first block is a control block with a value of Z, indicating that the second block is a data block;

[0011] In the case where the first block is a control block with a value of W, it indicates that the second block indicates collision detection (collision detected, COL) and carrier sense (carrier sense, CRS) in a bitmap manner.

[0012] By indicating the type of the second block through one or more of the above-mentioned first blocks, the encoding method is more flexible and diverse.

[0013] In some possible implementations of the first aspect or the second aspect, the first block is a J code block and the second block is a K code block; or the first block is a T code block and the second block is an R code block. When the first block is a J code block and the second block is a K code block, the block pair can be used to indicate a stream start delimiter. When the first block is a T code block and the second block is an R code block, the code block can be used to indicate a stream end delimiter.

[0014] In some possible implementations of the first aspect or the second aspect described above, the second block includes a management signal, and thus the management signal can be transmitted through the transmission block pair.

[0015] Exemplarily, the management signal occupies 1 bit.

[0016] Exemplarily, the lengths of the first block and the second block are both 5 bits, and thus the first block and the second block can be obtained based on bits of a transmit data signal (transmit data, TXD) of one cycle, respectively.

[0017] In some possible implementations of the first aspect or the second aspect, the first block is encoded in 4B / 5B mode. In another possible implementation, the first block is encoded in 8B / 10B mode. Therefore, the encoding mode of the first block is relatively flexible.

[0018] Exemplarily, the second block includes a management signal, and the management signal occupies 1 bit or 2 bits. Therefore, in the second block, the carrying mode of the management signal is relatively flexible.

[0019] Exemplarily, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal. Since the second block includes only a 1-bit management signal, the bit positions used to transmit the management signal in the second block are relatively small, and when the management signal transmission is implemented, the efficiency of transmitting the data signal or data signal is relatively high.

[0020] According to a third aspect, a data structure is provided, which includes the block pair described in the first aspect or any one of the first aspects.

[0021] In a fourth aspect, a coding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method; and a processing module for performing other operations besides the operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method.

[0022] In a fifth aspect, a decoding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method; a processing module for performing other operations besides the operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method.

[0023] In a sixth aspect, a communication system is provided, comprising a media access control (MAC) layer circuit and a physical layer (PHY) circuit, the MAC layer circuit being used to execute any encoding method in the first aspect, and the PHY circuit being used to execute any decoding method in the second aspect; or, the PHY circuit being used to execute any encoding method in the first aspect, and the MAC layer circuit being used to execute any decoding method in the second aspect.

[0024] In a seventh aspect, a chip is provided, comprising: a MAC layer circuit, the MAC layer circuit being used to execute any encoding method in the first aspect, or any decoding method in the second aspect.

[0025] In an eighth aspect, another chip is provided, which includes: a PHY circuit, and the PHY circuit is used to execute any encoding method in the first aspect, or any decoding method in the second aspect.

[0026] It should be understood that the beneficial effects achieved by the technical solutions of the third to eighth aspects of the present application and the corresponding possible implementation methods can be referred to the technical effects of the technical solutions of the first to second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0028] Figure 2 is a flowchart of an encoding method provided in an embodiment of the present application;

[0029] Figure 3 is a schematic diagram of a block pair provided in an embodiment of the present application;

[0030] Figure 4 It is a transmission schematic diagram of an Ethernet frame provided in an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of misidentification provided by an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of a process of transmitting a block pair provided by an embodiment of the present application;

[0033] Figure 7 It is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application;

[0034] Figure 8 This is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application;

[0035] Fig. 9 This is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application;

[0036] Fig.10 is a schematic diagram of another block pair provided in an embodiment of the present application;

[0037] Fig.11 It is a schematic diagram of a process of transmitting an H.sig code block provided in an embodiment of the present application;

[0038] Fig.12 It is a schematic diagram of another process of transmitting H.sig code blocks provided in an embodiment of the present application;

[0039] Fig.13 This is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application;

[0040] Fig.14 is a flowchart of a decoding method provided in an embodiment of the present application;

[0041] Fig.15 It is a schematic diagram of a process of inputting a block pair into RS provided by an embodiment of the present application;

[0042] Fig.16 It is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application;

[0043] Fig.17 It is a schematic diagram of a synchronization process of a data channel provided in an embodiment of the present application;

[0044] Fig.18 is a schematic diagram of the structure of an encoding device provided in an embodiment of the present application;

[0045] Fig.19 is a structural schematic diagram of a decoding device provided in an embodiment of the present application;

[0046] Fig. 20 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0047] Fig.21 It is a structural diagram of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In the field of communication technology, the signal transmitting end can encode the signal to be sent to obtain the encoding result, and send the encoding result to the signal receiving end. After receiving the encoding result, the signal receiving end restores the signal based on the encoding result. In addition, in the field of communication technology, the media access control (MAC) chip and the physical layer (PHY) chip can transmit signals through the media independent interface (MII). For example, in scenarios such as industrial IoT, the IoT terminal includes a PHY chip and a microcontroller (MCU), and the MCU includes a MAC chip. The PHY chip and the MAC chip transmit signals through the MII. For another example, in a scenario where a switch is used, the switch includes a PHY chip and a MAC chip, and the PHY chip and the MAC chip transmit signals through the MII.

[0049] In the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, MII is a parallel interface, which includes 18 pins, and these 18 pins are used to transmit data signals, control signals, and management signals. The specific method of transmitting signals by these 18 pins can be found in the relevant content of the IEEE 802.3 standard, which will not be described in detail here. However, since the packaging cost of the chip increases with the increase in the number of pins of the chip, when the number of pins that the chip can provide is relatively limited, it is necessary to reduce the number of MII pins in the chip, so that the number of pins used to provide other functions in the chip is relatively large.

[0050] The embodiment of the present application provides an encoding method and a decoding method for obtaining a block pair based on a signal and realizing the transmission of a signal in the form of a transmission block pair. The method can be applied to a scenario where a signal is transmitted via MII, that is, the above-mentioned signal is a signal transmitted by MII. The method can also be applied to other scenarios besides MII.

[0051] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application taking the MII scenario as an example. The method can be applied to Figure 1 The implementation environment shown. The method can also be applied to other implementation environments. For example, the implementation environment in which the method is applied includes chip 1 and chip 2, and chip 1 and chip 2 are connected, and the method can be applied to chip 1 or chip 2.

[0052] See also Figure 1 , the implementation environment includes a first device 101 and a second device 102. The first device 101 includes a MAC function module 1011 and one or more PHY function modules 1012 ( Figure 1 In the example, the first device 101 includes multiple PHY function modules 1012, and the MAC function module 1011 transmits signals to each PHY function module 1012 via MII. The second device 102 includes a MAC function module 10211 and a PHY function module 1022, and the MAC function module 10211 and the PHY function module 1022 transmit signals via MII. Signals can be transmitted between the PHY function module 1012 and the PHY function module 1022.

[0053] In some embodiments, the second device 102 includes an MCU 1021 and a PHY functional module 1022, and the MCU 1021 includes a MAC functional module 10211. In some embodiments, the MAC functional module 1011, the PHY functional module 1012, one or more of the MAC functional module 10211 and the PHY functional module 1022 may be located in a separate chip, in a separate die, or in one or more cores of a multi-core chip.

[0054] The encoding method and decoding method provided in the embodiments of the present application can be applied to signal transmission between the MAC function module 1011 and the PHY function module 1012 , and can also be applied to signal transmission between the MAC function module 10211 and the PHY function module 1022 . Figure 1 The number of first devices 101, the number of MAC function modules 1011, the number of PHY function modules 1012, the number of second devices 102, the number of MCUs 1021, the number of MAC function modules 10211, and the number of PHY function modules 1022 shown are only examples, and the embodiments of the present application are not limited to this. The above-mentioned first device 101 can be a switch or a device applied to an IoT terminal, and the second device 102 can be an IoT terminal or a device applied to an IoT terminal. Exemplarily, the above-mentioned first device 101 and the second device 102 can be single pair Ethernet (SPE) devices or advanced physical layer (APL) devices.

[0055] The encoding method provided in the embodiment of the present application can be as follows Figure 2 As shown, next, combined with Figure 1 The method is described in the implementation environment shown. The method can be applied to Figure 1 The MAC functional module or PHY functional module shown. Figure 2 As shown, the method includes but is not limited to S201.

[0056] S201, sending a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

[0057] In the embodiment of the present application, a block pair refers to a pair of blocks, and a transmission block pair refers to a pair of transmission blocks. Exemplarily, the first block is a code block encoded according to the IEEE 802.3 standard, and the second block is a block with the same length as the first block. That is, the second block may include a plurality of consecutive bits, which are regarded as a block, and the number of bits included in the second block is the same as the number of bits included in the first block.

[0058] The block pair sent by the serial channel is obtained by encoding the signal to be transmitted. In a possible implementation, the signal to be transmitted includes at least one of a data signal and / or a first control signal, and the signal to be transmitted also includes a management signal. In an embodiment of the present application, the data signal may be a signal for transmitting data, the first control signal may be a signal for controlling the transmission of data, and the management signal may be a signal other than the data signal and the first control signal.

[0059] In one possible implementation, the signal to be transmitted is related to the Ethernet frame. For example, the signal to be transmitted includes a data signal and / or a first control signal generated based on the Ethernet frame to be transmitted. Exemplarily, when the method is applied to the execution of the MAC function module, the MAC function module converts the Ethernet frame to be transmitted into a parallel signal transmitted through the MII, and obtains the signal to be transmitted based on the parallel signal transmitted by the MII. Among them, the parallel signal transmitted through the MII refers to a signal transmitted through multiple pins of the MII in the IEEE802.3 standard. Exemplarily, the data signal includes part or all of the data signal transmitted by the MII, and the first control signal includes part or all of the control signal transmitted by the MII.

[0060] Alternatively, both the data signal and the first control signal can be generated based on an Ethernet frame. For example, when the method is applied to a MAC functional module, the MAC functional module obtains an Ethernet frame and generates a data signal based on the Ethernet frame. For another example, when the method is applied to a MAC functional module, the MAC functional module obtains an Ethernet frame and generates a first part of the first control signal based on the Ethernet frame. In some embodiments, the first control signal also includes a second part. The second part can be generated by the execution subject of the method, that is, if the method is applied to a MAC functional module, the MAC functional module can generate the second part; if the method is applied to a PHY functional module, the PHY functional module can generate the second part.

[0061] In an embodiment of the present application, the first part may be a signal obtained based on the content of the Ethernet frame, for example, the first part is a control signal of MII transmission obtained based on the Ethernet frame; the second part may be an error signal for transmitting error information. For example, in the case where the transmission of the Ethernet frame needs to be interrupted, an error signal is generated. For another example, after the transmission of the Ethernet frame is completed, if it is necessary to continue to occupy the channel, an error signal is generated. The embodiment of the present application does not limit the format of the error signal. That is, if the signal to be transmitted includes a data signal, the data signal is obtained based on the Ethernet frame; if the signal to be transmitted includes a first control signal, the first control signal includes at least one of the first part obtained based on the Ethernet frame or the generated second part.

[0062] In a possible implementation, when the Ethernet frame carries data, the signal to be transmitted includes a data signal generated based on the carried data; when the Ethernet frame does not carry data, the signal to be transmitted does not include the data signal. Exemplarily, the first part of the first control signal is obtained based on other parts of the Ethernet frame except the start of the Ethernet frame, or is obtained based on other parts of the Ethernet frame except the start of the Ethernet frame and the end of the Ethernet frame. Exemplarily, the Ethernet frame is also used to obtain a second control signal, and the signal to be transmitted may include the second control signal. Alternatively, the Ethernet frame is also used to obtain a second control signal and a third control signal, and the signal to be transmitted may include the second control signal and the third control signal. The second control signal may be generated based on the Ethernet frame start of the Ethernet frame, and the third control signal may be generated based on the Ethernet frame end of the Ethernet frame.

[0063] In the case where the method is applied to the MII scenario, the signal to be transmitted may include a signal transmitted through the MII, for example, the management signal includes a management data input output (MDIO) signal. Exemplarily, the method is applied to a MAC functional module, and the MAC functional module includes a management entity (STA). In this case, the management signal includes an MDIO signal driven by the STA. For another example, the method is applied to a PHY functional module. In this case, the management signal includes an MDIO signal driven by the PHY functional module. The way in which STA drives the MDIO signal can refer to the way in which STA drives the MDIO signal in the IEEE 802.3 standard, and the way in which the PHY functional module drives the MDIO signal can refer to the way in which the PHY functional module drives the MDIO signal in the IEEE 802.3 standard, which will not be described in detail here.

[0064] Still taking the signal to be transmitted including the signal transmitted through MII as an example for explanation, when the method is applied to the MAC functional module, the data signal and the first control signal can be represented as a whole by the transmit enable signal (transmit enable, TX_EN), transmit data error prompt signal (transmit error, TX_ER) and transmit data signal (transmit data, TXD) transmitted by MII in the IEEE 802.3 standard. For example, by the validity and invalidity of TX_EN and the validity and invalidity of TX_ER, it is indicated whether the signal transmitted by TXD is a data signal or a control signal. Among them, the data signal includes but is not limited to the data (data) included in the Ethernet frame, and the control signal includes but is not limited to the preamble (preamble), low power idle (low power idle, LPI) and end-of-frame delimiter (end-of-frame delimiter, EFD) during Ethernet frame transmission. When the method is applied to the PHY function module, the data signal and the first control signal can be represented by the receive data valid signal (receive data valid, RX_DV), the receive data error prompt signal (receive error, RX_ER) and the receive data signal (receive data, RXD) transmitted by the MII in the IEEE 802.3 standard. That is, the validity and invalidity of RX_DV and the validity and invalidity of RX_ER indicate whether the signal transmitted by RXD is a data signal or a control signal.

[0065] After the signal to be transmitted is obtained, the signal to be transmitted can be encoded to obtain a block pair, and then the block pair is sent through a serial channel. In some embodiments, the first block indicates the type of the second block, including but not limited to at least one of the following situations:

[0066] Case 1: The first block is a data block, indicating that the second block is a data block. The value of the first block used to indicate that the second block is a data block can be set according to experience or actual needs.

[0067] Case 2, when the first block is a control block with a value of X, indicates that the second block is a control block.

[0068] Case 3, when the first block is a control block with a value of Y, indicates that the second block is a management block.

[0069] Case 4, when the first block is a control block with a value of Z, indicates that the second block is a data block.

[0070] Case 5, when the first block is a control block with a value of W, the second block is indicated to indicate COL and CRS in a bitmap manner. Indicating COL and CRS means indicating the position of COL and CRS in the second block, and the values ​​of COL and CRS that do not indicate COL and CRS can be set according to experience or actual needs. For example, a COL value of 0 indicates valid, a value of 1 indicates invalid, or a value of 0 indicates invalid, and a value of 1 indicates valid. For another example, a CRS value of 0 indicates valid, a value of 1 indicates invalid, or a value of 0 indicates invalid, and a value of 1 indicates valid.

[0071] In the above cases 2 to 5, the values ​​of X, Y, Z, and W can be set according to experience or actual needs, and the values ​​of X, Y, Z, and W are different. In addition, the above cases can be for multiple block pairs, that is, the method provided by the embodiment of the present application can be to send multiple block pairs through a serial channel, each block pair includes a first block and a second block, and the way in which the first block in different block pairs indicates the type of the second block can be any one of the above cases 1 to 5.

[0072] Exemplarily, the data block includes a data signal, the control block includes a control signal, and the management block includes a management signal. The data block and the control block may also include other signals, for example, the data block may also include a management signal, and the control block may also include a data signal and a management signal. That is, in some embodiments, no matter which type of block the second block is, the second block includes a management signal. Exemplarily, the first control signal, the second control signal, and the third control signal are collectively referred to as control signals, and the type of the control block corresponds to the type of the control signal.

[0073] In some embodiments, the management signal occupies 1 bit. The position of the 1 bit occupied by the management signal can be set based on experience or actual needs. In other embodiments, the management signal occupies 1 bit or 2 bits. The position of the 1 bit or 2 bits occupied by the management signal can be set based on experience or actual needs. In the case where the management signal occupies 2 bits, the positions occupied by these 2 bits can be adjacent or non-adjacent, and the number and position of the bit positions occupied by the management signal are relatively flexible.

[0074] In a possible implementation, the length of the first block and the second block are both 5 bits. Therefore, the first block and the second block can be obtained based on the bits of 1 cycle of TXD respectively. Among them, the cycle in which the bits of the first block are obtained and the cycle in which the bits of the second block are obtained can be 2 consecutive cycles. In some embodiments, when the lengths of the first block and the second block are both 5 bits, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal. In some embodiments, the first block can be encoded in a 4-bit (bit, B) / 5B manner. The content of 4B / 5B encoding can refer to the content of 4B / 5B encoding in the IEEE 802.3 standard, which will not be repeated here.

[0075] In another possible implementation, the length of the first block and the second block are both 10 bits. Therefore, the first block and the second block can be obtained based on the bits of TXD of 2 cycles respectively. Among them, the 2 cycles for obtaining the bits of the first block are continuous with the 2 cycles for obtaining the bits of the second block. In some embodiments, if the length of the first block and the second block are both 10 bits, the situation of the first block and the second block is similar to the situation where the length of the first block and the second block are both 5 bits. For example, the first block is a data block, and the second block includes a bit of data signal and b bit of management signal; or, the first block is a control block, and the second block includes a bit of data signal and b bit of management signal; or, the first block is a control block, and the second block includes a bit of control signal and b bit of management signal, b is equal to 1 or 2, and a is equal to 10-b. For example, the first block can be encoded in 8B / 10B mode. The content of 8B / 10B encoding can refer to the content of 8B / 10B encoding in the IEEE 802.3 standard, which will not be repeated here.

[0076] In some embodiments, the second block may be encoded, or may directly include the corresponding signal without encoding. In the case where the second block is obtained by encoding, the encoding method of the second block may be the same as or different from the encoding method of the first block.

[0077] Exemplarily, in a block pair, the first block is a J code block and the second block is a K code block; or the first block is a T code block and the second block is an R code block. The above-mentioned J code block, K code block, T code block and R code block can be the J code block, K code block, T code block and R code block defined in IEEE 802.3, respectively. For example, the J code block is 11000, the K code block is 10001, the T code block is 01101, and the R code block is 00111. In a possible implementation, the block pair including the J code block and the K code block is used to indicate the start of stream delimiter (SSD), and the block pair including the T code block and the R code block is used to indicate the end of stream delimiter (ESD).

[0078] In a possible implementation, if the second block includes multiple bits of the same signal, the multiple bits may be transformed bits or untransformed bits. The embodiment of the present application does not limit the transformation method, for example, the transformation method includes sequential transformation.

[0079] Next, taking the first block encoded in 4B / 5B mode as an example, the obtained block pair is described.

[0080] The 4B / 5B encoding method specified in the IEEE 802.3 standard is to encode bits based on half-byte width, and the encoded symbols obtained are used to represent data codes and control codes. The encoding efficiency of 4B / 5B encoding is 4 / 5*100%=80%. Figure 3 is a schematic diagram of a block pair provided in an embodiment of the present application. Figure 3 , the block pair includes a first block and a second block, the first block is encoded in 4B / 5B mode, the second block includes a 1-bit management signal and 4-bit other signals, and the type of other signals included in the second block is indicated by the first block. Figure 3 As shown, the first block can be a data code or a control code.

[0081] In some embodiments, the situation of getting the bits of the first block can be indicated by TX_EN and TX_ER of MII transmission. Figure 3 TX_EN and TX_ER can indicate that the bits of the first half byte are bits of a data signal or bits of a control signal, and can also indicate that the bits of the second half byte are bits of a data signal or bits of a control signal. The bits of the first half byte are used to obtain the first block, and the bits of the second half byte are used to obtain the second block.

[0082] Management signals are used to get the second block, such as Figure 3 As shown, the second block includes a 1-bit management signal, which is marked as "0". Figure 3As shown, the 1-bit management signal can be located at the highest bit of the second block. The 1-bit management signal can also be located at other positions of the second block, which is not limited in the embodiment of the present application. The second block also includes four bits of the second half byte, which can be a 4-bit data signal or a 4-bit control signal. Figure 3 For the block pair shown, if the block pair is obtained based on an 8-bit data signal, or based on an 8-bit control signal, or based on a 4-bit data signal and a 4-bit control signal, the coding efficiency of the block pair is 8 / 10*100%=80%.

[0083] In the embodiment of the present application, the continuous J code block and the K code block are used for stream synchronization and to indicate SSD. When the continuous J code block and the K code block are identified, it is determined that the Ethernet frame starts to be transmitted. The continuous T code block and the R code block are used to indicate ESD. Thus, when the continuous T code block and the R code block are identified, it is determined that the Ethernet frame transmission ends. Figure 4 Schematic diagram of the transmission of an Ethernet frame provided in an embodiment of the present application. Figure 4 As shown, the Ethernet frame is represented by TX_EN, TX_ER and TXD transmitted by the MII. The Ethernet frame includes the Ethernet frame start, the Ethernet frame end and the parts of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end. The signal encoding the Ethernet frame start representing the Ethernet frame is obtained to obtain a block pair, the first block of the block pair is a J code block, and the second block is a K code block. Figure 4 The block pair is represented by / J / K / code. The signal representing the end of the Ethernet frame is encoded to obtain a block pair, the first block of which is a T code block and the second block is an R code block. Figure 4 The block pair is represented as / T / R / code. The signal representing the part of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end is encoded to obtain multiple block pairs. Exemplarily, if the number of bits included in the Ethernet frame is not an integer multiple of bytes, the first block of the last block pair in the multiple block pairs is a control block, and if Figure 4 As shown, the second block of the block pair is a data block.

[0084] In a possible implementation, by using consecutive J code blocks and K code blocks to represent the SSD, it is possible to avoid a block pair that is not composed of a J code block and a K code block being identified as a block pair composed of a J code block and a K code block. Figure 5 is a schematic diagram of misidentification provided by an embodiment of the present application. Figure 5As shown in FIG. 1 , the first block is identified as a J code block, and the second block of the block pair is mistakenly identified as a K code block, or the first block is identified as a K code block, and the second block of the previous block pair of the block pair is mistakenly identified as a J code block. By using consecutive T code blocks and R code blocks to represent ESD, it is possible to avoid a block pair that is not composed of a T code block and an R code block being identified as a block pair composed of a T code block and an R code block. For example, Figure 5 As shown, the first block is identified as a T code block, and the second block of the block pair is misidentified as an R code block. Consecutive J code blocks and K code blocks can be represented as / J / K / codes, and consecutive T code blocks and R code blocks can be represented as / T / R / codes. Figure 5 The three situations shown will all lead to misidentification of block pairs, that is, the bits of the management signal are mistakenly regarded as bits of the J code block, the K code block, or the R code block. Therefore, in the embodiment of the present application, the J code block and the K code block need to be used continuously, and the T code block and the R code block need to be used continuously to avoid misidentification of block pairs.

[0085] Exemplarily, when the first block is encoded in 4B / 5B mode, the content included in the block pair may be as shown in the following Table 1. In which, 1 O represents a 1-bit management signal, the value of the position represented by O may be 1, and the value of the position represented by x may be 0 or 1.

[0086] Table 1

[0087]

[0088]

[0089] Exemplarily, in combination with the above-mentioned Table 1, the R code block can be used alone, that is, the first block of the block pair can be an R code block, and the second block of the block pair can be Oxxxx. In an embodiment of the present application, a 5-bit block with a value of 00111 is called an R code block. If the value of the block is 00111 for the first block of the block pair, the block pair can also be called an R code block. In some embodiments, if the second block of the R code block is other than Ox1xx in Oxxxx, the block pair represents a reset extension. If the second block of the H code block is O ERR 1CRS COL, the second block indicates COL and CRS, the block pair represents a physical layer channel state indication, wherein ERR represents an error indication (error), and the block pair can also be called an H.sig code block. If the second block of the S code block is O1110, the block pair represents PHY-level collision avoidance (PLCA) BEACON (a signal type). If the second block of the S code block is O1101, the block pair represents PLCA COMMIT (a signal type). If the second block of the S code block is other than O1110 and O1101 in Oxxxx, the block pair indicates set extension. In other cases where the block pair is other than the case shown in Table 1, the first block and the second block of the block pair are both control blocks and the block pair indicates reserved. Exemplarily, the reserved block pair is used to expand new Ethernet functions, which is not limited in the embodiments of the present application.

[0090] After obtaining the block pair, the block pair is sent through a serial channel. In a possible implementation, the serial channel is used to connect the MAC layer and the PHY, and the serial channel may also be referred to as a serial channel implemented based on the MII. Exemplarily, the serial channel is implemented by a pin or a group of pins. Thus, if the serial channel is implemented by a pin, the pin is used to send the block pair. If the serial channel is implemented by multiple pins, the differential signal transmitted through multiple pins can be first obtained based on the block pair, and then the differential signal is transmitted through multiple pins to implement the sending of the block pair through a serial channel. Thus, by using a serial channel to send the block pair, only fewer pins need to be set to implement the serial channel.

[0091] Figure 6 1 is a schematic diagram of a process of transmitting a block pair provided in an embodiment of the present application. The method can be applied to a MAC function module or a PHY function module. If the method is applied to a MAC function module, the method can transmit a block pair to a PHY function module via a serial channel. The transmission process can correspond to Figure 6 If the method is applied to the PHY functional module, the method can transmit the block pair to the MAC functional module through the serial channel. The transmission process can correspond to Figure 6shows the RX serial transfer.

[0092] In the embodiment of the present application, when a block pair is transmitted through a serial channel, the obtained block pair can be directly transmitted, or the block pair can be processed first and then the processed block pair can be transmitted. The processing of the block pair includes at least one of encoding or scrambling, and the encoding includes non-return-to-zero-invert (NRZI) encoding or non-return-to-zero (NRZ) encoding.

[0093] Figure 7 is a schematic diagram of another process of transmitting block pairs provided by an embodiment of the present application. Figure 7 As shown, the signal to be transmitted includes a management signal, a data signal and a first control signal transmitted in parallel by MII. The signal to be transmitted is encoded to obtain a block pair. The length of the first block and the second block of the block pair are both 5 bits. After obtaining the block pair, the bits of the block pair are transmitted serially through MII. And, as Figure 7 As shown, when transmitting a block pair, the bits of the block pair may be transmitted in a descending order of bit position. In some embodiments, the bits of the block pair may also be transmitted in a descending order of bit position.

[0094] Figure 8 is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application. Figure 8 As shown, the bit positions corresponding to the block pairs are used as management channels and data and control channels, wherein the bit positions used as management channels carry management signals, and the bit positions used as data and control channels carry data signals or first control signals. Figure 8 As shown, the 1-bit management signal included in each block pair is used to constitute the MDIO signal. Fig. 9 is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application. Fig. 9 As shown, when there is no need to transmit data signals, that is, the data channel is idle, the first block of the block pair is a control block, and the second block of the block pair is a management block, which includes a management signal of multiple bits. Fig. 9 , each second block includes a 4-bit management signal, and the 4 bits are represented by “0”. In this case, compared with the case where the second block includes only a 1-bit management signal, the transmission efficiency of the management signal is higher.

[0095] Fig.10 is a schematic diagram of another block pair provided in an embodiment of the present application. Fig.10 As shown, the first block of the block pair is a control block, and the second block of the block pair indicates COL and CRS. The block pair can be called an H.sig code block, wherein, Fig.10 The x shown can be 0 or 1. Fig.11 Schematic diagram of a process of transmitting H.sig code blocks provided by an embodiment of the present application. Fig.11 As shown, in the case where the method is applied to the PHY function module and the block pair is transmitted to the MAC function module, if the MAC function module is in the sending mode, that is, the MAC function module sends the block pair to the PHY function module, the PHY function module can transmit the H.sig code block to the MAC function module through the receiving channel of the MAC function module. Among them, the sending channel of the MAC function module can be a channel established by the MAC function module based on MII for transmitting the block pair to the PHY function module, and the receiving channel of the MAC function module can be a channel established by the MAC function module based on MII for receiving the block pair transmitted by the PHY function module.

[0096] If the method is applied to a PHY functional module and a block pair is transmitted to a MAC functional module, if the MAC functional module is in a receiving mode, that is, the MAC functional module receives the block pair sent by the PHY functional module, the PHY functional module can transmit the H.sig code block to the MAC functional module through the receiving channel of the MAC functional module.

[0097] Fig.12 FIG. 1 is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application. Fig.12 As shown, the MAC function module receives data through the receiving channel, and the data is obtained based on the Ethernet frame. For example, the data obtained based on the Ethernet frame includes Fig.12 The / data / shown. Fig.12 As shown, the PHY functional module also transmits a block pair for representing SSD to the MAC functional module, and the block pair includes a / J / K / code. The PHY functional module also transmits a block pair for representing ESD to the MAC functional module, and the block pair includes a / T / R / code. In the case where there is no abnormality in the data, the MAC functional module can obtain COL and / or CRS based on the received Ethernet frame. The MAC functional module can also receive the H.sig code block sent by the PHY functional module through the receiving channel, and the CRS indicated by the second block in the H.sig code block can be valid, so that the second block of the H.sig code block can indicate virtual CRS occupancy.

[0098] When the method is applied to the PHY functional module and a block pair is transmitted to the MAC functional module, if the MAC functional module is in a receiving mode and the data sent by the PHY functional module to the MAC functional module is abnormal, the H.sig code block can be used to replace the abnormal data for transmission. Fig.13 FIG. 1 is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application. Fig.13As shown, the MAC function module receives data through the receiving channel, and the data is obtained based on the Ethernet frame. For example, the data obtained based on the Ethernet frame includes Fig.13 The / data / shown. Fig.13 As shown, the PHY function module also transmits a block pair for representing SSD to the MAC function module, and the block pair includes / J / K / code. The MAC function module also receives the H.sig code block through the receiving channel. The validity of the COL and CRS indicated by the second block in the H.sig code block can be set according to the requirements. The H.sig code block is obtained by replacing the abnormal data. Fig.13 As shown, the PHY functional module can also transmit a block pair indicating idleness to the MAC functional module. Exemplarily, Figures 11 to 13 The process of transmitting the H.sig code block by the PHY functional module is implemented in a half-duplex scenario.

[0099] The above description uses the example of the first block being encoded in 4B / 5B mode. If the first block is encoded in 8B / 10B mode, the setting method of the values ​​of the first block and the second block may be the same as the principle of the setting method of the values ​​of the first block and the second block in the 4B / 5B mode, and the embodiment of the present application will not be described in detail.

[0100] The above text describes the encoding method provided in the embodiment of the present application. The embodiment of the present application also provides a decoding method. Fig.14 This method can be applied to Figure 1 The MAC functional module or the PHY functional module shown in the figure can be located in the same chip or in different chips. Fig.14 As shown, the method includes but is not limited to S1401.

[0101] S1401, receiving a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates a type of the second block.

[0102] In the embodiment of the present application, the serial channel for receiving the block pair is the same as the serial channel for sending the block pair in the encoding method. The content of the serial channel can refer to the relevant description in the encoding method, which will not be repeated here. The situation of the block pair can also refer to the relevant description in the encoding method, which will not be repeated here. Exemplarily, the block pair is decoded according to the encoding method of obtaining the block pair to obtain the signal included in the block pair. Figure 7 Taking the schematic diagram of the process of transmitting a block pair as an example, the bits of the block pair are transmitted serially through the MII. After the bits of the block pair are received serially through the MII, the block pair is decoded to obtain the signal to be transmitted, that is, the management signal, the data signal and the first control signal. The length of the first block and the second block of the block pair are both 5 bits.

[0103] In some embodiments, if the method is applied to a PHY functional module, the serially received block pairs are input into a reconciliation sublayer (RS), and an operation of decoding the block pairs is performed in the RS. By performing the operation of decoding the block pairs in the RS, the method can directly convert the signals included in the block pairs into signals that can be processed in the physical layer signaling sublayer (PLS) in the RS, without first converting the signals included in the block pairs into parallel signals transmitted by MII in the IEEE 802.3 standard, and then converting the parallel signals into signals processed by PLS, and the efficiency of obtaining the signals processed by PLS is higher.

[0104] Fig.15 Schematic diagram of a process of inputting a block pair into RS provided by an embodiment of the present application. Fig.15 As shown, the block pairs received through the serial channel enter the RS, and the RS performs the operation of decoding the block pairs. The RS also converts the signal to be transmitted into a signal processed by PLS, for example, the signal processed by PLS includes Fig.15 PLS service primitives are shown. Exemplarily, a block pair whose first block is a data block is called a data code block, and a block pair whose first block is a control block is called a control code block. Fig.15 The code block represented by C shown may be a control code block, Fig.15 The code block represented by D shown may be a data code block.

[0105] like Fig.15 As shown, the RS can separate the control code block and the data code block, and perform operations on the separated data code block and the control code block. The operations performed are as follows: Fig.15 As shown in C1 and C2 in FIG. 1 , the present embodiment does not limit the type of operation. The PLS service primitives include but are not limited to Fig.15 PLS control request, PLS data request, PLS signal indication, PLS carrier indication, PLS data indication and PLS control indication are shown.

[0106] In a possible implementation, after receiving multiple block pairs, it is necessary to identify the boundaries of the multiple block pairs to achieve synchronization of the multiple block pairs. The synchronization of the multiple block pairs includes but is not limited to synchronization of management channels and synchronization of data channels. The interaction of management signals can be ensured by synchronizing the management channels, and the interaction of data signals and control signals can be ensured by synchronizing the data channels.

[0107] Fig.16 This is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application, see Fig.16 , the block pair is an I code block, and the I code block can be uniquely identified, where x can be 0 or 1. In the case where the management signal does not include the MDIO signal, the value of the bit of the management signal is 1. In the case where the management signal includes the MDIO signal and the MDIO signal starts to be transmitted, a plurality of bits of the management signal will have a "101" jump, which can indicate the start field. Therefore, by identifying the start field, the synchronization of the management channel can be achieved. Fig.16 For other contents of the management signal shown, please refer to the relevant description of the management frame corresponding to the management signal in the IEEE 802.3 standard, which will not be repeated here. Fig.16 A0 to A4 shown are only used to illustrate the value of the physical layer address field of the management frame, and R0 to R4 are only used to illustrate the value of the register address field of the management frame, and are not used to limit the values ​​of these two fields.

[0108] In a possible implementation, data channel synchronization is achieved by identifying the SSD of the Ethernet frame. That is, by identifying consecutive J code blocks and K code blocks, it is determined that the Ethernet frame starts to be transmitted, thereby achieving data channel synchronization. Fig.17 is a schematic diagram of a synchronization process of a data channel provided by an embodiment of the present application, wherein: Fig.17 The x in can be 1 or 0. Fig.17 As shown, the previous block pair is first identified as an I code block, and then the first block of the next block pair is identified as a J code block, and the second block is identified as a K code block. Therefore, after identifying the next block pair, it can be determined that the Ethernet frame starts to be transmitted, and the synchronization of the data channel is achieved. In a possible implementation, when the synchronization of the data channel has been achieved, since the bit position corresponding to the management channel is fixed in the block pair, in this case, the bit position corresponding to the management channel can be directly located, so that the synchronization of the management channel can be achieved by identifying the start field of the management signal.

[0109] In the method provided in the embodiment of the present application, a block pair is transmitted through a serial channel, and the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the method provided in the embodiment of the present application, the first block and the second block have the same length, so that the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting a block pair through a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the method can be implemented based on MII, so the method can be applied to the scenario of MII.

[0110] An embodiment of the present application also provides a data structure, which includes any block pair in the above method embodiments.

[0111] The embodiment of the present application also provides a coding device. Fig.18 Schematic diagram of a coding device provided in an embodiment of the present application. The device is applied to a MAC function module or a PHY function module, based on Fig.18 The multiple modules shown in the figure can perform Figure 2 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiments of the present application are not limited to this. Fig.18 As shown, the device includes a coding module 1801.

[0112] The encoding module 1801 is used to send a block pair through a serial channel, where the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

[0113] In some embodiments, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0114] In some embodiments, the first block indicates the type of the second block, including: if the first block is a control block with a value of X, indicating that the second block is a control block.

[0115] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Y, indicating that the second block is a management block.

[0116] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Z, indicating that the second block is a data block.

[0117] In some embodiments, the first block indicates the type of the second block, including: when the first block is a control block with a value of W, indicating that the second block indicates COL and CRS in a bitmap manner.

[0118] In some embodiments, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0119] In some embodiments, the second block includes a management signal.

[0120] In some embodiments, the management signal occupies 1 bit.

[0121] In some embodiments, the length of the first block and the second block are both 5 bits.

[0122] In some embodiments, the first block is encoded in 4B / 5B mode.

[0123] In some embodiments, the first block is encoded in 8B / 10B mode.

[0124] In some embodiments, the second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

[0125] In some embodiments, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0126] In the device provided in the embodiment of the present application, a block pair is sent through a serial channel, and the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the device, the length of the first block and the second block is the same, so that the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting a block pair through a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the device can be implemented based on MII, so the device can be applied to the scenario of MII.

[0127] The embodiment of the present application also provides a decoding device. Fig.19 Schematic diagram of a decoding device provided in an embodiment of the present application. The device is applied to a MAC function module or a PHY function module. Fig.19The multiple modules shown in the figure can perform Fig.14 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiments of the present application are not limited to this. Fig.19 As shown, the device includes a decoding module 1901.

[0128] The decoding module 1901 is used to receive a block pair through a serial channel, where the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

[0129] In some embodiments, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0130] In some embodiments, the first block indicates the type of the second block, including: if the first block is a control block with a value of X, indicating that the second block is a control block.

[0131] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Y, indicating that the second block is a management block.

[0132] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Z, indicating that the second block is a data block.

[0133] In some embodiments, the first block indicates the type of the second block, including: when the first block is a control block with a value of W, indicating that the second block indicates COL and CRS in a bitmap manner.

[0134] In some embodiments, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0135] In some embodiments, the second block includes a management signal.

[0136] In some embodiments, the management signal occupies 1 bit.

[0137] In some embodiments, the length of the first block and the second block are both 5 bits.

[0138] In some embodiments, the first block is encoded in 4B / 5B mode.

[0139] In some embodiments, the first block is encoded in 8B / 10B mode.

[0140] In some embodiments, the second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

[0141] In some embodiments, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0142] In the device provided in the embodiment of the present application, a block pair is received through a serial channel, and the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the device, the length of the first block and the second block is the same, so that the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting the block pair through a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the device can be implemented based on MII, so the device can be applied to the scenario of MII.

[0143] It should be understood that the above Fig.18 and Fig.19 When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0144] See also Fig. 20 , Fig. 20 The following is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. Fig. 20 As shown, the computer system is a computer system 2000. The computer system 2000 may be a network device, a routing device or a switching device. Fig. 20 The computer system 2000 shown is used to execute the above Figure 2 The encoding method or Fig.14 The decoding method shown. The computer system 2000 is, for example, a server, etc. The computer system 2000 can be implemented by a general bus architecture.

[0145] like Fig. 20 As shown, the computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0146] Processor 2001 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the method provided in the embodiment of the present application. For example, processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. Processor 2001 can be a combination of various logic boxes, modules and circuits described in conjunction with the disclosure of the embodiment of the present application, or a combination of computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessors, and the like.

[0147] Optionally, the computer system 2000 further includes a bus. The bus is used to transmit information between the components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 20 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0148] The memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0149] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, radio access network (RAN) or wireless local area network (WLAN), etc. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0150] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Fig. 20 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0151] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as Fig. 20 2001 and processor 2005 are shown in FIG. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0152] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0153] In some embodiments, the memory 2003 is used to store program code 2010, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself may also store program code or instructions.

[0154] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the MAC functional module and / or PHY functional module in the above-mentioned method embodiments, and the MAC functional module and / or PHY functional module may be implemented by the processor 2001 in the computer system 2000.

[0155] The computer system 2000 may also correspond to the above Fig.18 and Fig.19 The device shown, Fig.18 or Fig.19 Each functional module in the illustrated apparatus may be implemented by a circuit in the processor 2000 .

[0156] in, Figure 2 The encoding method shown and Fig.14 Each step of the decoding method shown is completed by a hardware integrated logic circuit in a processor of the computer system 2000. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware processor.

[0157] Fig.21 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application, the computer system is used to execute the above Figure 2 The encoding method shown and Fig.14 The decoding method shown. Exemplarily, the computer system is a server, and the server may have relatively large differences due to different configurations or performances. The computer system may include one or more processors 2101, and the one or more processors 2101 are used to implement the MAC function module and / or PHY function module in the method embodiment. Fig.21 As shown, the computer system may further include one or more memories 2102, wherein at least one computer program is stored in the one or more memories 2102, and the at least one computer program is loaded and executed by one or more processors 2101. Exemplarily, the processor 2101 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the computer system may also include other components for realizing device functions, which will not be described in detail here.

[0158] The present application also provides a communication device, which includes: a transceiver module for executing Figure 2 The receiving and / or sending related operations in the encoding method shown; a processing module for performing Figure 2 The encoding method shown in the figure has other operations other than the operations related to receiving and / or sending. The embodiment of the present application also provides another communication device, which includes: a transceiver module, which is used to perform Fig.14 The receiving and / or sending related operations in the decoding method shown; a processing module for performing Fig.14 The decoding method shown includes other operations except the operations related to receiving and / or sending.

[0159] The present application provides a chip, which includes: a MAC layer circuit, the MAC layer circuit is used to execute Figure 2 The encoding method shown and / or Fig.14 The present application also provides another chip, which includes: a PHY circuit, the PHY circuit is used to execute Figure 2 The encoding method shown and / or Fig.14 The decoding method shown.

[0160] The embodiment of the present application also provides a communication system, the communication system includes a MAC layer circuit and a PHY circuit; the MAC layer circuit is used to perform Figure 2 The encoding method shown in the figure is used by the PHY circuit to perform Fig.14 The decoding method shown; or, the PHY circuit is used to perform Figure 2 The encoding method shown in the figure is used by the MAC layer circuit to perform Fig.14 The decoding method shown.

[0161] It should be understood that the processor may be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting an advanced RISC machines (ARM) architecture.

[0162] Further, in an optional embodiment, if one or more of the above-mentioned computer system, communication device, chip or communication system also includes a memory, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0163] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a ROM, a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM) or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic random access memory, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

[0164] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program or a computer program product. A computer program or a computer program product includes one or more computer instructions. When loading and executing a computer program instruction on a computer, a process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, a computer instruction can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0165] In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0166] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on the remote computer or completely on the remote computer or server.

[0167] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, etc. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0168] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0169] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0170] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0171] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0172] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first block can be referred to as the second block, and similarly, the second block can be referred to as the first block.

[0173] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0174] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple range locks means two or more range locks. The terms "system" and "network" are often used interchangeably herein.

[0175] It should be understood that the terms used in the description of various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0176] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0177] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining that…” or “in response to determining that…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0178] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0179] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0180] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A coding method, characterized in that: The method comprises: A block pair is sent through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates a type of the second block.

2. The method according to claim 1, characterized in that The first block indicates a type of the second block, including: The first block is a data block, indicating that the second block is a data block.

3. The method according to claim 1 or 2, characterized in that: The first block indicates a type of the second block, including: In the case where the first block is a control block having a value of X, it is indicated that the second block is a control block.

4. The method according to any one of claims 1 to 3, characterized in that: The first block indicates a type of the second block, including: In case the first block is a control block with a value of Y, it is indicated that the second block is a management block.

5. The method according to any one of claims 1 to 4, characterized in that: The first block indicates a type of the second block, including: In case the first block is a control block having a value of Z, it indicates that the second block is a data block.

6. The method according to any one of claims 1 to 5, characterized in that: The first block indicates a type of the second block, including: In the case where the first block is a control block with a value of W, it indicates that the second block indicates conflict detection COL and carrier detection CRS in a bitmap manner.

7. The method according to claim 1, characterized in that The first block is a J code block, and the second block is a K code block; Alternatively, the first block is a T code block, and the second block is an R code block.

8. The method according to any one of claims 1 to 7, characterized in that: The second block includes management signals.

9. The method according to claim 8, characterized in that The management signal occupies 1 bit.

10. The method according to any one of claims 1 to 9, characterized in that: The length of the first block and the length of the second block are both 5 bits.

11. The method according to any one of claims 1 to 10, characterized in that: The first block is encoded in 4-bit B / 5B mode.

12. The method according to any one of claims 1 to 6, characterized in that: The first block is encoded in 8-bit B / 10B mode.

13. The method according to claim 12, characterized in that The second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

14. The method according to claim 8, characterized in that The first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

15. A coding device, characterized in that: The device comprises: A transceiver module, used to perform operations related to receiving and / or sending in any of the methods described in claims 1-14; A processing module, used to perform other operations in the method described in any one of claims 1-14 except for operations related to receiving and / or sending.

16. A chip, characterized in that: The chip comprises: a media access control MAC layer circuit, and the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-14.

17. A chip, characterized in that: The chip comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the encoding method as described in any one of claims 1-14.

18. A communication system, characterized in that: The communication system includes a media access control MAC layer circuit and a physical layer PHY circuit; the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-14, or the PHY circuit is used to execute the encoding method as described in any one of claims 1-14.

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