An adaptive inter-chip current balancing circuit for linear LED driving and control method thereof

Abstract

The present invention relates to an adaptive inter-chip current balancing circuit for linear LED driving and a control method thereof. The current balancing circuit comprises a reference circuit module, an operational amplifier, a power tube, a plurality of current mirrors and a sampling port, and adjusts the current flowing through each chip by a reference voltage and a reference current source to achieve current balancing of multiple chips. The operational amplifier controls the power tube to maintain a constant current output according to a sampling resistor feedback signal. The current mirror group forms a proportional current feedback mechanism to ensure that the ratio of the sampling current to the reference current is constant, thereby stabilizing the driving current. When multiple chips are connected in parallel, the current sampling tube is combined with the current mirror to adjust the overload current to ensure that the driving current of each chip is within the rated range. Thus, adaptive current balancing control is achieved, which is suitable for a multi-chip current balancing control device and a computer device, and realizes accurate distribution and adjustment of the LED driving current, ensuring a stable lighting effect and efficient energy utilization.

Description

Technical Field

[0001] The present invention relates to the technical field of LED circuits, and in particular to an adaptive inter-chip current balancing circuit for linear LED driving and a control method thereof. Background Art

[0002] Existing linear LED drive circuits usually use linear LED drive control chips for current regulation, and use external sampling resistors to control the current flowing through the LED lamp. The resistance of the sampling resistor (R1) can be adjusted to achieve precise control of the LED current, and the reference voltage (VREF) is provided by the internal circuit of the control chip.

[0003] However, in a high current system, a single control chip cannot provide enough current, so two or more control chips are often used in parallel to increase the current flowing through the LED lamp. However, when multiple control chips are used in parallel, the system will have some significant deficiencies.

[0004] First, each control chip needs to be independently configured with a sampling resistor (such as Figure 2 Otherwise, if a single sampling resistor is used (such as Figure 3 This imbalance is caused by the fact that the reference voltage (VREF) of different control chips and the offset voltage of the operational amplifier (AMP) may be slightly different, causing some chips to withstand higher currents and even exceed their maximum rated currents and be damaged.

[0005] For example, when VREF1 of chip 1 is slightly greater than VREF2 of chip 2, the current of the LED may flow mainly to chip 1, while chip 2 hardly bears the current.

[0006] In addition, the independent sampling resistor configuration increases the volume and cost of the system and reduces the integration and economy of the system.

[0007] Therefore, how to realize an LED driving solution that can achieve current balance when multiple chips are connected in parallel, simplify the circuit structure, and reduce costs has become a problem that needs to be solved urgently in the prior art. Summary of the invention

[0008] The main purpose of the present invention is to provide an adaptive inter-chip current balancing circuit for linear LED driving and a control method thereof, so as to solve the technical problems of current imbalance, large volume and high cost in the existing multi-chip parallel driving LED process.

[0009] To achieve the above-mentioned object, the present invention provides an adaptive inter-chip current balancing circuit for linear LED driving, the adaptive inter-chip current balancing circuit comprising: a reference circuit module, an operational amplifier (AMP), a first power tube MN1, a first current mirror MP1, a second current mirror MP2, and an N port for connecting the cathode of the LED and a sampling port CS for connecting the signal ground, wherein the reference circuit module is used to provide a reference voltage VREF and a reference current source, the reference voltage VREF is provided to the operational amplifier as a reference voltage, and the reference current source is provided to the first current mirror MP1 to form a current reference for circuit adjustment; the operational amplifier, the positive electrode is connected to the reference voltage VREF, the negative electrode is connected to the sampling port CS, the first power tube MN1 and the second current mirror MP2 form a control loop, and the output of the operational amplifier is connected to the Gate terminal of the first power tube MN1 to provide a driving signal, and the current size in the path is controlled by adjusting the Gate terminal voltage of the first power tube MN1 to achieve constant current output; the first power tube MN1, the Drain terminal is connected to the N port to connect to the cathode of the LED, and the Source terminal is connected to the sampling resistor R at the sampling port CS. cs , the Gate terminal is connected to the output terminal of the operational amplifier, the first power tube MN1 is used to provide a constant driving current for the LED, and the magnitude of the driving current is controlled by the operational amplifier according to the reference voltage and the feedback signal of the sampling resistor; the first current mirror MP1, and the second current mirror MP2 form a proportional current feedback mechanism, and the Gate and Drain terminals of the first current mirror MP1 are short-circuited and connected to the reference current source, and the Source terminal is connected to the internal power supply VDD, and the first current mirror MP1 is used to generate and stabilize part of the current as the adjustment reference of the circuit; the second current mirror MP2, the Gate terminal is connected to the Gate terminal of the first current mirror MP1, and the Drain terminal is connected to the sampling port CS, and by forming a proportional current feedback mechanism with the first current mirror MP1, the ratio of the sampling current flowing through the CS port to the reference current is constant, thereby participating in the adjustment of the LED driving current; the sampling port CS is connected to the sampling resistor R cs , the sampling resistor R cs One end is connected to the CS port and the other end is grounded, which is used to detect the current flowing through the first power tube MN1 and feed back the sampled voltage to the negative input terminal of the operational amplifier so as to pass through the sampling resistor R cs The operational amplifier can adjust the voltage output to the Gate terminal of the first power tube MN1 by receiving the voltage feedback signal, thereby controlling the current flowing through the first power tube MN1 to be maintained within a preset range.

[0010] In one example, the adaptive inter-chip current balancing circuit also includes: a third current mirror MP3 and a fourth current mirror MP4, wherein the Gate and Drain terminals of the third current mirror MP3 are short-circuited and connected to the Drain terminal of the second current mirror MP2, and the Source terminal of the third current mirror MP3 is connected to the internal power supply VDD, so as to form a second set of proportional current feedback mechanisms with the second current mirror MP2; the output current of the third current mirror MP3 is adjusted according to the output current of the second current mirror MP2, so as to balance the current distribution of multiple chips in a multi-chip parallel working mode in the circuit; the Gate terminal of the fourth current mirror MP4 is connected to the Gate terminal of the third current mirror MP3, the Drain terminal of the fourth current mirror MP4 is connected to the negative input of the operational amplifier, and the Source terminal of the fourth current mirror MP4 is connected to the internal power supply VDD; the fourth current mirror MP4 guides the current fed back by the second current mirror MP2 to the negative electrode of the operational amplifier through the proportional current relationship formed with the third current mirror MP3, so as to form an overall negative feedback regulation, thereby regulating the current flowing through the first power tube MN1, so as to balance the current of each chip in the multi-chip working mode.

[0011] In one example, the adaptive inter-chip current balancing circuit also includes: a second power tube MN2, the Gate end of the second power tube MN2 is connected to the Gate end of the first power tube MN1, and the Source end of the second power tube MN2 and the Source end of the first power tube MN1 are both connected to the sampling port CS, the Drain end of the current sampling tube is connected to the Drain end of the second current mirror MP2, which is used to form a current distribution circuit together with the first power tube MN1, so that current diversion can be achieved in the multi-chip parallel working mode, and the current balance flowing through each chip is adjusted by combining with the second current mirror MP2.

[0012] In one example, the adaptive inter-chip current balancing circuit further includes: a feedback resistor R fb , the feedback resistor R fb connected between the negative input of the operational amplifier and the sampling port CS, and generates a negative feedback regulation voltage together with the current of the fourth current mirror MP4, wherein when the current flowing through the fourth current mirror MP4 is I1, the feedback resistor R fb The feedback voltage generated is I1*R fb and transmits the voltage to the negative input of the operational amplifier to dynamically adjust the control voltage output by the operational amplifier to the Gate terminal of the first power tube MN1.

[0013] The present invention also provides an adaptive inter-chip current balancing circuit group for linear LED driving, wherein the adaptive inter-chip current balancing circuit group comprises: a plurality of adaptive inter-chip current balancing circuits, wherein the adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group described in any one of the embodiments of the present application, and the adaptive inter-chip current balancing circuits are arranged in parallel.

[0014] The present invention also provides a circuit control method based on an adaptive inter-chip current balancing circuit group, the circuit control method comprising: controlling the reference circuit module to start up to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify the subsequent current regulation standard; controlling the operational amplifier to start up, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and the sampling resistor R cs The current state of the current is fed back, and the output voltage of the operational amplifier is transmitted to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; under the control of the operational amplifier, the Drain terminal of the first power tube MN1 is connected to the N port, and the Source terminal of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R cs The voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; the second current mirror MP2 is controlled to cooperate with the first current mirror MP1 to form a reference current by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

[0015] The present invention also provides a circuit control method based on an adaptive inter-chip current balancing circuit group, the circuit control method comprising: controlling the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each operational amplifier, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; in each parallel adaptive inter-chip current balancing circuit, controlling the positive electrode of the operational amplifier to receive the reference voltage, and the negative electrode to be connected to a sampling port and a sampling resistor, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time, and the sampling resistor Rcs feedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs , to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; when multiple adaptive inter-chip current balancing circuits are connected in parallel, there is a proportional current feedback relationship between the first current mirror MP1 and the second current mirror MP2, wherein the first current mirror MP1 generates a reference current, the Gate end of the second current mirror MP2 is connected to the first current mirror MP1, and the Drain end of the second power tube MN2 is connected to the sampling port CS; when it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, the second power tube MN2 is started, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, and the Source end of the second power tube MN2 is connected to the sampling port CS, the Drain end of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting to relieve the overload of the first power tube MN1; when the feedback current of the second current mirror MP2 exceeds the set value, the third current mirror MP3 and the fourth current mirror MP4 are started, and the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein, when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

[0016] The present invention also provides a circuit control device based on an adaptive inter-chip current balancing circuit group, the circuit control device comprising: a first control unit, used to control the start-up of the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify the subsequent current regulation standard; a second control unit, used to control the start-up of the operational amplifier, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and through the sampling resistor R cs The current state of the current is fed back, and the output voltage of the operational amplifier is transmitted to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; the first feedback unit is used for connecting the Drain terminal of the first power tube MN1 to the N port and the Source terminal of the first power tube MN1 to the sampling port CS and the sampling resistor R under the control of the operational amplifier. cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R cs The voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; a third control unit is used to control the second current mirror MP2 to cooperate with the first current mirror MP1, and a reference current is formed by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

[0017] The present invention also provides a circuit control device based on an adaptive inter-chip current balancing circuit group, the circuit control device comprising: a fourth control unit, used to control the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each operational amplifier, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; a fifth control unit, used to control the positive electrode of the operational amplifier to receive the reference voltage and the negative electrode to be connected to a sampling port and a sampling resistor in each parallel adaptive inter-chip current balancing circuit, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time through the sampling resistor R csfeedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; a sixth control unit, used to control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs , to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; a second feedback unit, used for, when a plurality of the adaptive inter-chip current balancing circuits are connected in parallel, a proportional current feedback relationship between the first current mirror MP1 and the second current mirror MP2, wherein the first current mirror MP1 generates a reference current, the Gate terminal of the second current mirror MP2 is connected to the first current mirror MP1, and the Drain terminal of the second power tube MN2 is connected to the sampling port CS; a first starting unit, used for starting the second power tube MN2 when it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, and the Source terminal of the second power tube MN2 is connected to The sampling port CS, the Drain end of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting to alleviate the overload of the first power tube MN1; the second starting unit is used to start the third current mirror MP3 and the fourth current mirror MP4 when the feedback current of the second current mirror MP2 exceeds the set value, the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein, when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

[0018] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0019] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0020] The adaptive inter-chip current balancing circuit and control method thereof for linear LED driving provided by the present invention realizes adaptive inter-chip current balancing control by designing components such as reference circuit modules, operational amplifiers, current mirrors and power tubes, thereby solving the problem of uneven current distribution when multiple chips are used in parallel. At the same time, through the proportional feedback mechanism of the unified reference current and current mirror, each power tube can provide accurate constant current output, avoiding the risk of damage to a single chip due to excessive current. In addition, by introducing feedback resistors and current sampling tubes, when the chip is overloaded, the excess current can be shunted and negative feedback can be generated, thereby further ensuring that each chip operates within the rated current range, ensuring the stability and efficiency of the system. This innovative current balancing control scheme not only simplifies the circuit structure and reduces the number of external sampling resistors, but also reduces the manufacturing cost of the system, improves the system integration and economy, and is particularly suitable for high-current LED driving scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the existing linear LED drive circuit architecture. Figure 1 ;

[0022] Figure 2 This is a schematic diagram of the existing linear LED drive circuit architecture. Figure 2 ;

[0023] Figure 3 This is a schematic diagram of the existing linear LED drive circuit architecture. Figure 3 ;

[0024] Figure 4 1 is a schematic diagram of a circuit structure for adaptive current sharing between chips in one embodiment of the present invention;

[0025] Figure 5 1 is a schematic diagram of a block diagram of an adaptive inter-chip current balancing circuit in an embodiment of the present invention;

[0026] Figure 6 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0027] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] Reference Figure 4 The present invention provides an adaptive inter-chip current balancing circuit for linear LED driving. The adaptive inter-chip current balancing circuit includes: a reference circuit module, an operational amplifier (AMP), a first power tube MN1, a first current mirror MP1, a second current mirror MP2, and an N port for connecting the negative electrode of the LED and a sampling port CS for connecting the signal ground, as follows:

[0030] The reference circuit module is used to provide a reference voltage VREF and a reference current source. The reference voltage VREF is provided to the operational amplifier as a reference voltage, and the reference current source is provided to the first current mirror MP1 to form a current reference for circuit regulation.

[0031] The operational amplifier has a positive electrode connected to the reference voltage VREF, a negative electrode connected to the sampling port CS, the first power tube MN1 and the second current mirror MP2 to form a control loop, and the output of the operational amplifier is connected to the Gate terminal of the first power tube MN1 to provide a driving signal, and a constant current output is achieved by adjusting the Gate terminal voltage of the first power tube MN1 to control the current in the path.

[0032] The first power tube MN1 has a Drain terminal connected to the N port to connect to the LED cathode, and a Source terminal connected to the sampling resistor R at the sampling port CS. cs , the Gate terminal is connected to the output terminal of the operational amplifier, the first power tube MN1 is used to provide a constant driving current for the LED, and the magnitude of the driving current is controlled by the operational amplifier according to the reference voltage and the feedback signal of the sampling resistor.

[0033] The first current mirror MP1 and the second current mirror MP2 form a proportional current feedback mechanism, and the Gate and Drain terminals of the first current mirror MP1 are short-circuited and connected to a reference current source, and the Source terminal is connected to an internal power supply VDD. The first current mirror MP1 is used to generate and stabilize a portion of the current as a regulation reference for the circuit;

[0034] The second current mirror MP2 has a Gate terminal connected to the Gate terminal of the first current mirror MP1, and a Drain terminal connected to the sampling port CS. By forming a proportional current feedback mechanism with the first current mirror MP1, a constant ratio of the sampling current flowing through the CS port to the reference current is achieved, thereby participating in the regulation of the LED drive current.

[0035] The sampling port CS is connected to the sampling resistor R cs , the sampling resistor R cs One end is connected to the CS port and the other end is grounded, which is used to detect the current flowing through the first power tube MN1 and feed back the sampled voltage to the negative input terminal of the operational amplifier so as to pass through the sampling resistor R cs The operational amplifier can adjust the voltage output to the Gate terminal of the first power tube MN1 by receiving the voltage feedback signal, thereby controlling the current flowing through the first power tube MN1 to be maintained within a preset range.

[0036] That is, the core goal of the design of this adaptive inter-chip current balancing circuit for linear LED driving is to solve the current imbalance problem that occurs when multiple chips are driven in parallel, while simplifying the circuit design, reducing costs, and maintaining the stability and efficiency of the circuit. In the prior art, the driving capability of a single chip in a high-current scenario is limited, and multiple chips are usually required to be connected in parallel to provide sufficient driving current. However, due to slight differences in the reference voltage of each chip and the offset voltage of the operational amplifier, the current tends to flow to certain chips when multiple chips are connected in parallel, causing some chips to carry too much current, which may even exceed their maximum rated current and cause damage. To solve this problem, an adaptive current balancing mechanism based on a current mirror and the operational amplifier is designed.

[0037] By setting a reference circuit module, it is used to provide a unified reference voltage and reference current source to ensure that the entire system has the same reference voltage standard. The reference voltage VREF is transmitted to the operational amplifier as a reference voltage for comparison, and the reference current source generates and stabilizes the reference current through the first current mirror MP1, and provides it to the second current mirror MP2 to maintain the overall balance of the circuit. The advantage of this is that it can ensure the uniformity of the reference voltage and reference current when multiple circuits are connected in parallel, avoiding the imbalance caused by the difference in the references of different chips.

[0038] The design of the operational amplifier makes full use of the feedback control principle. Its positive electrode receives the reference voltage, and its negative electrode is connected to the sampling port CS, forming a precise control loop. By connecting the output of the operational amplifier to the Gate terminal of the first power tube MN1, the magnitude of the drive current can be adjusted in real time according to the feedback signal, thereby achieving a constant output current. The advantage of this design is that by adjusting the voltage at the Gate terminal of the power tube, the magnitude of the current can be flexibly controlled to ensure a constant output current that is not affected by input voltage fluctuations. This constant current control is particularly important in LED applications because the brightness of the LED is directly proportional to the current flowing through it.

[0039] The first power tube MN1 is used to directly drive the LED, and its Source terminal is connected to the sampling resistor R cs , the current flowing through the LED is accurately controlled by the voltage feedback signal of the sampling resistor. cs The function is to detect the current flowing through the power tube and feed back the corresponding voltage signal to the negative input terminal of the operational amplifier, so that the entire control system can automatically adjust according to the actual current situation. This can avoid chip damage caused by excessive current and also ensure the stable working state of the LED.

[0040] The first current mirror MP1 and the second current mirror MP2 form a proportional current feedback mechanism. The Gate and Drain of the first current mirror MP1 are short-circuited and connected to a reference current source to generate a stable reference current, which is used to control the current regulation of various parts in the circuit. The second current mirror MP2 maintains a proportional feedback relationship with the first current mirror MP1, and its Gate terminal is connected to the Gate terminal of the first current mirror MP1, and the Drain terminal is connected to the sampling port CS. In this way, the ratio of the sampling current flowing through the sampling resistor to the reference current is constant. The advantage of this design is that the feedback characteristics of the current mirror ensure that the proportional regulation of the current is accurate and correct, thereby achieving balanced current distribution.

[0041] This design takes into account multiple factors. The first is the current balancing problem. Through the reference voltage and current mirror mechanism, the current of all parallel chips can be evenly distributed. Secondly, the stability of the circuit is considered. Through the feedback control of the operational amplifier and power tube, a constant current output is maintained. Thirdly, the complexity and cost of the system are reduced, and the number of independent sampling resistors is reduced, making the overall volume of the circuit smaller and more integrated.

[0042] The challenges that need to be overcome are mainly the accuracy of the current mirror and the matching problems between different circuit components. In actual implementation, it is necessary to ensure the accurate matching of the first current mirror MP1 and the second current mirror MP2 to ensure the accuracy of the proportional feedback relationship. In addition, the design of the operational amplifier needs to have a low offset voltage and high gain to achieve accurate current control.

[0043] For example, if two parallel chips are driving a group of LEDs, without current balancing control, one chip may carry 90% of the current due to its slightly higher reference voltage, which will cause the chip to heat up severely or even fail. However, through the above circuit design, the reference voltage and current of each chip are uniformly controlled, and the current mirror ensures that all chips share the same current ratio, so that the current carried by each chip is basically equal, which improves the reliability and life of the overall system.

[0044] In one example, the adaptive inter-chip current balancing circuit also includes: a third current mirror MP3 and a fourth current mirror MP4, wherein the Gate and Drain terminals of the third current mirror MP3 are short-circuited and connected to the Drain terminal of the second current mirror MP2, and the Source terminal of the third current mirror MP3 is connected to the internal power supply VDD, so as to form a second set of proportional current feedback mechanisms with the second current mirror MP2; the output current of the third current mirror MP3 is adjusted according to the output current of the second current mirror MP2, so as to balance the current distribution of multiple chips in a multi-chip parallel working mode in the circuit; the Gate terminal of the fourth current mirror MP4 is connected to the Gate terminal of the third current mirror MP3, the Drain terminal of the fourth current mirror MP4 is connected to the negative input of the operational amplifier, and the Source terminal of the fourth current mirror MP4 is connected to the internal power supply VDD; the fourth current mirror MP4 guides the current fed back by the second current mirror MP2 to the negative electrode of the operational amplifier through the proportional current relationship formed with the third current mirror MP3, so as to form an overall negative feedback regulation, thereby regulating the current flowing through the first power tube MN1, so as to balance the current of each chip in the multi-chip working mode.

[0045] In the design of the adaptive chip-to-chip current balancing circuit, the introduction of the third current mirror MP3 and the fourth current mirror MP4 is mainly to further optimize the current balance and overall stability, especially in applications where multiple chips are in parallel operation. Specifically, the design purpose of these components is to ensure that each chip shares an equal current load through a refined current feedback mechanism, thereby improving the reliability and consistency of the system.

[0046] The Gate and Drain of the third current mirror MP3 are short-circuited and connected to the Drain end of the second current mirror MP2. The purpose of this connection form is to expand the current adjustment range through the proportional relationship formed between the third current mirror MP3 and the second current mirror MP2. The Source end of the third current mirror MP3 is connected to the internal power supply VDD, which allows the third current mirror MP3 to draw enough current from the power supply end to form a stable proportional feedback. Specifically, the output current of the third current mirror MP3 is controlled by the output current of the second current mirror MP2, which means that the output current of the third current mirror MP3 can dynamically follow the change of the output current of the second current mirror MP2 to adapt to the current demand of the overall system. The advantage of this proportional current feedback mechanism is that even when multiple chips work in parallel, the current of each chip can be automatically adjusted according to the feedback mechanism to maintain the current balance.

[0047] In the case of multiple chips in parallel, the current carried by each chip may be inconsistent due to slightly different characteristics and environmental conditions of each chip (such as differences in reference voltage or temperature effects). If these differences cannot be effectively balanced, some chips may carry too much current while others carry insufficient load, thereby increasing the risk of system damage. The second set of proportional feedback mechanisms formed by the second current mirror MP2 and the third current mirror MP3 can accurately adjust the current flowing through each chip to achieve uniform current distribution between different chips, thereby solving the above problem.

[0048] The fourth current mirror MP4 further enhances the current balance control capability. Its Gate terminal is connected to the Gate terminal of the third current mirror MP3, the Drain terminal is connected to the negative input of the operational amplifier, and the Source terminal is connected to the internal power supply VDD. The effect of this connection method is that the fourth current mirror MP4 can guide the current fed back by the second current mirror MP2 to the negative pole of the operational amplifier, thereby realizing negative feedback regulation of the entire circuit. The fourth current mirror MP4 ensures that the feedback current is effectively transmitted to the operational amplifier through the proportional relationship formed with the third current mirror MP3, so that it can be dynamically adjusted according to the actual current situation. A significant advantage of this negative feedback regulation mechanism is that it can control the output current of the first power tube MN1 on a real-time basis to avoid damage to a single chip due to overload.

[0049] Through this multi-level feedback mechanism, the system can effectively achieve adaptive current sharing when facing high current parallel operation. This design takes into account the current imbalance problem that may occur in the circuit in multi-chip mode, and ensures that each chip maintains balance when sharing the load through multi-level feedback current mirrors. This structure makes the entire system more stable when working, and the burden of each chip is even, thereby extending the service life of the system and reducing the risk of failure.

[0050] In order to realize this feedback mechanism, it is necessary to ensure that the matching accuracy of the third current mirror MP3 and the fourth current mirror MP4 is high enough to ensure the accuracy of the proportional relationship. At the same time, the design of the operational amplifier needs to have high gain and small offset voltage to ensure the accuracy of current regulation. In practical applications, for example, in the scenario of parallel multi-chip driving LEDs, through the cooperation between the third current mirror MP3, the fourth current mirror MP4 and the second current mirror MP2, the current can be automatically adjusted between the chips. Even when the current deviation of a chip is caused by temperature or reference voltage changes, it can be quickly adjusted through the feedback mechanism to ensure the balanced distribution of the overall current. This method greatly improves the reliability and consistency of the system, and is particularly suitable for large-scale parallel LED drive applications.

[0051] In one example, the adaptive inter-chip current balancing circuit also includes: a second power tube MN2, the Gate end of the second power tube MN2 is connected to the Gate end of the first power tube MN1, and the Source end of the second power tube MN2 and the Source end of the first power tube MN1 are both connected to the sampling port CS, the Drain end of the current sampling tube is connected to the Drain end of the second current mirror MP2, which is used to form a current distribution circuit together with the first power tube MN1, so that current diversion can be achieved in the multi-chip parallel working mode, and the current balance flowing through each chip is adjusted by combining with the second current mirror MP2.

[0052] In the design of the adaptive inter-chip current balancing circuit, the main purpose of introducing the second power tube MN2 is to further realize the effective distribution of current, especially in the multi-chip parallel working mode, so that the current can flow through each chip more evenly, thereby improving the stability and reliability of the overall system.

[0053] Specifically, the Gate terminal of the second power tube MN2 is connected to the Gate terminal of the first power tube MN1. The reason for this is to ensure that the second power tube MN2 and the first power tube MN1 are consistent in terms of control signals, and the working states of the two are determined by the same control signal. The Source terminal of the second power tube MN2 and the Source terminal of the first power tube MN1 are both connected to the sampling port CS, which means that the two tubes share the same reference point on the current path. This structural design enables the second power tube MN2 and the first power tube MN1 to work under the same voltage conditions, thereby helping to accurately adjust the current flowing through the two tubes.

[0054] The Drain end of the second power tube MN2 is connected to the Drain end of the second current mirror MP2, so that the second power tube MN2 can form a current distribution circuit together with the first power tube MN1, and can participate in current shunting when needed. This parallel relationship between the second power tube MN2 and the first power tube MN1 allows the second power tube MN2 to share part of the current when the first power tube MN1 is overloaded in the multi-chip parallel working mode, ensuring that the current in the entire circuit will not flow through a certain tube. The advantage of this current shunting mechanism is that when the first power tube MN1 is overloaded, the second power tube MN2 can automatically connect to share part of the current, thereby avoiding damage to the first power tube MN1 due to overload.

[0055] By combining with the second current mirror MP2, the second power tube MN2 can also participate in the current regulation of the entire system. As part of the proportional feedback mechanism, the connection between the second current mirror MP2 and the second power tube MN2 ensures that the current flowing through the sampling port CS can be effectively controlled and regulated. In other words, the second power tube MN2 is not just a shunt tube, it also participates in the entire current balancing process through the second current mirror MP2. The second current mirror MP2 provides a precise reference, so that the second power tube MN2 can distribute the current proportionally, thereby achieving current balancing of the entire circuit.

[0056] This design is very important when multiple chips are connected in parallel. For example, when multiple power tubes are connected in parallel to drive LEDs, if there is no good current distribution mechanism, some power tubes may be subjected to excessive current due to slight differences in their intrinsic parameters. This will cause these power tubes to overheat or even fail due to exceeding the rated current. By introducing the second power tube MN2, an active current shunt can be achieved to ensure that when the load of any power tube increases, another tube can be connected to share part of the current. This significantly reduces the burden on a single power tube and makes the entire circuit more reliable.

[0057] The difficulty that needs to be overcome is the matching problem between the second power tube MN2 and the first power tube MN1. In practical applications, it is necessary to ensure that the second power tube MN2 and the first power tube MN1 have sufficient similarity in characteristic parameters, so as to ensure that they can evenly distribute current under the same control voltage. In addition, the design of the second current mirror MP2 also needs to be precise enough to ensure the accuracy and stability of the feedback ratio, so as to ensure that the entire circuit can maintain current balance under various working conditions.

[0058] That is, the type of the second power tube MN2 is the same as that of the first power tube MN1 and their sizes are in a certain ratio. When the circuit is working, the current ratio of the second power tube MN2 to the first power tube MN1 is proportional to their size ratio.

[0059] For example, assuming that at a certain moment, the current carrying capacity of the first power tube MN1 decreases due to temperature changes, the second power tube MN2 will be connected to work in this case. Through its connection with the second current mirror MP2, the second power tube MN2 can dynamically share the current of the first power tube MN1 to avoid the risk of overload of the first power tube MN1. At the same time, since the second current mirror MP2 provides a proportional feedback mechanism, the current in the entire circuit can still be evenly distributed, and the current will not be seriously unbalanced due to the characteristic fluctuations of a certain chip. This structure ensures that in the application scenario of multi-chip parallel drive, each chip can share the appropriate current, improving the reliability and life of the system.

[0060] In one example, the adaptive inter-chip current balancing circuit further includes: a feedback resistor R fb , the feedback resistor R fb connected between the negative input of the operational amplifier and the sampling port CS, and generates a negative feedback regulation voltage together with the current of the fourth current mirror MP4, wherein when the current flowing through the fourth current mirror MP4 is I1, the feedback resistor R fb The feedback voltage generated is I1*R fb and transmits the voltage to the negative input of the operational amplifier to dynamically adjust the control voltage output by the operational amplifier to the Gate terminal of the first power tube MN1.

[0061] At this time, the feedback resistor R fb Its function is that when the current flowing through a chip in the multi-chip parallel working mode exceeds the preset value, negative feedback is generated to limit the current of the chip to within the maximum rated value, thereby extending the chip life and maintaining current balance between chips to achieve the goal of current sharing.

[0062] In the design of the adaptive current balancing circuit, the feedback resistor R is introduced. fb The main purpose is to further accurately control the current of the first power tube MN1, so as to achieve a more stable constant current output, especially when multiple chips are connected in parallel, to ensure the current balance between the chips.

[0063] Feedback resistor R fb is connected between the negative input terminal of the operational amplifier and the sampling port CS. The purpose of this connection is to use the voltage generated on the feedback resistor by the current flowing through the fourth current mirror MP4 to form a negative feedback signal to dynamically adjust the output of the operational amplifier. Specifically, when the output current of the fourth current mirror MP4 is I1, the feedback resistor R fb A voltage value will be generated at both ends, which is determined by the current I1 and the resistance R fb Multiply them together to get the feedback voltage I1 * Rfb This feedback voltage is passed to the negative input terminal of the operational amplifier as a negative feedback signal.

[0064] The role of negative feedback is to automatically adjust the size of the output signal of the operational amplifier by controlling the operational amplifier. Here, the output of the operational amplifier is the control voltage connected to the Gate terminal of the first power tube MN1. The feedback resistor R fb By generating a negative feedback voltage, the output of the operational amplifier is dynamically affected, thereby adjusting the voltage at the Gate terminal of the first power tube MN1. The advantage of this is that negative feedback can suppress any possible output changes, so that the current of the first power tube MN1 is kept within a stable range. This negative feedback control mechanism is very effective in improving the stability of the system in practical applications.

[0065] Introducing feedback resistor R fb The combination with the fourth current mirror MP4 plays an important role in regulating the current. The current change of the fourth current mirror MP4 will affect R fb The feedback voltage on R increases, thereby affecting the control output of the operational amplifier through negative feedback. For example, when the current of the fourth current mirror MP4 increases, R fb The feedback voltage on the gate will also increase, which will cause the output of the operational amplifier to decrease, thereby reducing the control voltage of the gate terminal of the first power tube MN1, so that the current flowing through the first power tube MN1 is reduced. This mechanism ensures that the entire system can make rapid adjustments when facing current changes, thereby achieving current balance flowing through each chip and avoiding overload of a single chip.

[0066] This negative feedback regulation mechanism also has the characteristics of adaptive regulation, and can be quickly adjusted dynamically according to the transient response of the system. When multiple chips are connected in parallel, different chips may have slight changes in characteristics due to factors such as temperature and aging. These changes may increase the current carried by some chips. fb The negative feedback regulation with the fourth current mirror MP4 can adjust the output of the operational amplifier in real time, so that the currents of all chips tend to be consistent, thereby avoiding the impact of uneven current distribution on system stability.

[0067] For example, suppose that at a certain moment, due to external factors, the current I1 flowing through the fourth current mirror MP4 suddenly increases. This change will be reflected in the feedback resistor R fbA higher negative feedback voltage is generated on the output side, and after being transmitted to the negative input terminal of the operational amplifier, the operational amplifier will automatically reduce its output, thereby reducing the control voltage transmitted to the Gate terminal of the first power tube MN1. This process will reduce the conduction degree of the first power tube MN1, thereby reducing its output current, so that the total current of the system returns to a balanced state. Through this design, the system can adapt to current changes under various working conditions, ensure that the current carried by each power tube remains within a preset range, and ultimately achieve a stable constant current output.

[0068] This design effectively solves the problem of unbalanced current distribution when multiple chips work in parallel, and can improve the stability and reliability of the entire circuit in practical applications. The challenges that need to be overcome include the feedback resistor R fb The precise selection of the fourth current mirror MP4 and the precise control of its characteristic parameters ensure that the system can achieve an ideal negative feedback effect and keep the current flowing through each chip balanced.

[0069] like Figure 5 As shown, the present invention also provides an adaptive inter-chip current balancing circuit group for linear LED driving, the adaptive inter-chip current balancing circuit group includes: multiple adaptive inter-chip current balancing circuits, wherein the adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group described in the above embodiment, and the adaptive inter-chip current balancing circuits are arranged in parallel.

[0070] The adaptive inter-chip current balancing circuit group in the present invention is composed of multiple adaptive inter-chip current balancing circuits connected in parallel, aiming to provide higher current capability and balanced current distribution for linear LED driving. This design is particularly suitable for LED application scenarios that require high current driving. By connecting multiple adaptive current balancing circuits in parallel, the overall current is shared, ensuring the stability and reliability of the system.

[0071] Specifically, this current balancing circuit group is composed of a plurality of previously described adaptive inter-chip current balancing circuits, each of which has an independent reference circuit module, the operational amplifier, the current mirror, the power tube and other components, and can achieve independent constant current control. However, by using these current balancing circuits in parallel, the output current capability of the system can be effectively improved. The advantage of this is that each current balancing circuit bears part of the total load current, so even if a larger current is required to drive the LED, each circuit will not carry a current beyond its capability, thereby improving the reliability of the entire system.

[0072] The parallel-connected adaptive chip-to-chip current-sharing circuit group utilizes the previously described current-sharing control mechanism, through the reference current source, current mirror, and feedback control, so that the power tubes in each parallel circuit can accurately output equal current. This design ensures that each parallel current-sharing circuit can adjust its drive current according to the feedback signal, ensuring that the current distribution between each current-sharing circuit is balanced, and the current will not be concentrated on a certain circuit due to differences in individual circuit parameters or changes in external conditions. This is a very important feature, especially in high-current applications, where balanced current distribution can effectively avoid overload and heating problems of individual chips, thereby extending the service life of the system.

[0073] For example, in practical applications, when it is necessary to drive multiple high-power LED light strings and a single current balancing circuit cannot provide sufficient driving current, multiple current balancing circuits can be connected in parallel to meet the demand. Through the adaptive current balancing circuit group set in parallel, each current balancing circuit shares the load current while maintaining a constant output of each current, and through the current mirror and feedback regulation mechanism, ensure that the output current of the first power tube MN1 in each current balancing circuit remains consistent. In this way, all LEDs in the entire system can be driven by uniform current, achieving consistent brightness and reliable performance.

[0074] The present invention also provides a circuit control method based on an adaptive inter-chip current balancing circuit, wherein the adaptive inter-chip current balancing circuit is the adaptive inter-chip current balancing circuit described in the above embodiment, and the circuit control method comprises: controlling the reference circuit module to start up to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify the subsequent current regulation standard; controlling the operational amplifier to start up, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and through the sampling resistor R cs The current state of the current is fed back, and the output voltage of the operational amplifier is transmitted to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; under the control of the operational amplifier, the Drain terminal of the first power tube MN1 is connected to the N port, and the Source terminal of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R csThe voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; the second current mirror MP2 is controlled to cooperate with the first current mirror MP1 to form a reference current by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

[0075] At this time, in the single-chip working mode, no current equalization adjustment is required. The system continues to maintain the current flowing through the first power tube MN1 at a constant value under the control of the reference voltage and the operational amplifier to ensure stable operation of the LED. The current is only adjusted by the reference voltage VREF and the feedback signal of the sampling resistor, and does not involve other current balancing controls.

[0076] In the present invention, the circuit control method based on the adaptive inter-chip current balancing circuit is mainly intended to achieve effective management of the driving current by precisely controlling the working state of each component, especially for linear LED driving scenarios, to maintain constant current output and achieve current balance between chips.

[0077] This circuit control method first involves controlling the startup of the reference circuit module. The function of the reference circuit module is to provide a reference voltage and a reference current source. The reference voltage (VREF) is transmitted to the positive pole of the operational amplifier as a voltage reference for the operational amplifier to compare the input signal and adjust the output. The reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a stable reference current. This step is very important because the uniformity of the reference voltage and reference current provides a standard for subsequent current regulation, ensuring the consistency of the entire system when multiple chips are used in parallel.

[0078] Next, the operational amplifier is started. During the startup process, the positive electrode of the operational amplifier receives the reference voltage as a reference, and the negative electrode is connected to the sampling port CS through the sampling resistor R cs To obtain the actual current state. Sampling resistor R cs The function of the operational amplifier is to convert the current flowing through the first power tube MN1 into a voltage signal, which is fed back to the negative electrode of the operational amplifier to form a closed-loop control system. The operational amplifier adjusts its output voltage by comparing the voltage difference between the positive and negative input terminals, and this output voltage is connected to the Gate terminal of the first power tube MN1. By changing the voltage at the Gate terminal of the first power tube MN1, its conduction degree can be controlled, thereby adjusting the current flowing through it to achieve constant current output.

[0079] The first power tube MN1 plays a key role in the entire control process. Its Drain end is connected to the N port to provide driving current; the Source end is connected to the sampling port CS and the sampling resistor R cs This structure is designed to cs The current flowing through the first power tube MN1 is detected, and the sampled voltage signal is fed back to the negative input terminal of the operational amplifier. Through this feedback mechanism, the operational amplifier can adjust its output in real time so that the first power tube MN1 can maintain a constant current output. The advantage of this closed-loop feedback is that even if the input conditions (such as the power supply voltage) change, the system can still adjust through the feedback signal to keep the output current constant.

[0080] Controlling the collaboration between the second current mirror MP2 and the first current mirror MP1 is also an important part of the circuit control method. The Gate and Drain terminals of the first current mirror MP1 are short-circuited and connected to a reference current source to form a stable reference current, which is used to provide a reference standard for current regulation for the entire circuit. The Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to ensure a stable supply of current. The second current mirror MP2 collaborates with the first current mirror MP1 to form a proportional current feedback mechanism by sharing the same Gate terminal voltage and connecting to the sampling port CS through the Drain terminal of the second current mirror MP2. This means that the output current of the second current mirror MP2 will maintain a certain ratio with the reference current of the first current mirror MP1. Through this proportional relationship, precise control of the current flowing through the sampling port can be achieved to ensure the stability of the entire current distribution.

[0081] This circuit control method utilizes the characteristics of feedback and current mirror, combined with the precise control of the operational amplifier, to achieve constant current output management of the first power tube MN1. Through the cooperation between the reference voltage, the reference current source, the first current mirror MP1, and the second current mirror MP2, the stability of the drive current can be maintained under different working conditions. For example, if the input power supply voltage fluctuates, the sampling resistor R cs After detecting the change of the current flowing through the first power tube MN1, the output of the operational amplifier is quickly adjusted through a negative feedback signal, thereby adjusting the conduction degree of the first power tube MN1 so that the current quickly returns to a preset constant value.

[0082] The advantage of this method is that it realizes automatic and accurate current regulation, which is especially suitable for LED applications that require constant current drive. In the case of multiple chips in parallel, it ensures that each first power tube MN1 can be accurately adjusted according to the feedback signal, avoiding the imbalance of current distribution and effectively preventing the problem of individual chips failing due to current overload. At the same time, through the unified reference current and voltage, the stability of the entire system is significantly improved.

[0083] The present invention also provides a circuit control method based on an adaptive inter-chip current balancing circuit group, wherein the adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group described in the above embodiment, and the circuit control method comprises: controlling the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each operational amplifier, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; in each parallel adaptive inter-chip current balancing circuit, controlling the positive electrode of the operational amplifier to receive the reference voltage, and the negative electrode to be connected to a sampling port and a sampling resistor, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time through the sampling resistor R cs feedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs, to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; when multiple adaptive inter-chip current balancing circuits are connected in parallel, there is a proportional current feedback relationship between the first current mirror MP1 and the second current mirror MP2, wherein the first current mirror MP1 generates a reference current, the Gate end of the second current mirror MP2 is connected to the first current mirror MP1, and the Drain end of the second power tube MN2 is connected to the sampling port CS; when it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, the second power tube MN2 is started, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, and the Source end of the second power tube MN2 is connected to the sampling port CS, the Drain end of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting to relieve the overload of the first power tube MN1; when the feedback current of the second current mirror MP2 exceeds the set value, the third current mirror MP3 and the fourth current mirror MP4 are started, and the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein, when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

[0084] In the present invention, the circuit control method based on the adaptive inter-chip current balancing circuit group aims to ensure the current balance between the current balancing circuits through a multi-level control and feedback mechanism, which is particularly suitable for the application scenario where multiple adaptive inter-chip current balancing circuits are connected in parallel to drive LEDs. Such a method can achieve better reliability and stability in high-current applications.

[0085] First, the reference circuit module is controlled to provide a reference voltage and a reference current source. The reference voltage is transmitted to the positive pole of each operational amplifier to ensure that the operational amplifier of each parallel adaptive current sharing circuit receives the same voltage reference. The reference current source is input to the first current mirror MP1 to generate a stable reference current, which is used for the standardization and consistency of subsequent current regulation.

[0086] In each parallel adaptive current sharing circuit, the positive electrode of the operational amplifier receives the reference voltage, and the negative electrode is connected to the sampling port CS and the sampling resistor R cs On. Sampling resistor R cs It is used to detect the current flowing through the first power tube MN1, convert the current information into a voltage signal and feed it back to the negative electrode of the operational amplifier. The output of the operational amplifier is connected to the Gate terminal of the first power tube MN1. By adjusting the Gate terminal voltage in real time, the conduction state of the first power tube MN1 can be controlled, thereby ensuring that the current flowing through each current-sharing circuit reaches a preset constant value.

[0087] The Drain end of each first power tube MN1 is connected to the N port, and the Source end is connected to the sampling port CS and the sampling resistor R cs , to monitor the current state of each current sharing circuit in real time. The operational amplifier is based on the sampling resistor R cs The feedback signal dynamically adjusts the voltage output to the Gate terminal of the first power tube MN1 to ensure that the current in each current balancing circuit reaches a balanced preset value. This design achieves constant current control through a feedback mechanism, which helps to avoid uneven distribution of current among multiple current balancing circuits.

[0088] When multiple adaptive current balancing circuits are connected in parallel, a proportional current feedback relationship is formed between the first current mirror MP1 and the second current mirror MP2. The first current mirror MP1 generates a reference current and shares the Gate terminal voltage with the second current mirror MP2 to ensure that the currents between them maintain a certain ratio. The Drain terminal of the second current mirror MP2 is connected to the sampling port CS, so that the second current mirror MP2 can participate in the current regulation and keep the current flowing through the sampling resistor R cs The proportional relationship between the current and the reference current.

[0089] When it is detected that the current of the first power tube MN1 in a single adaptive current balancing circuit exceeds its rated value, the second power tube MN2 will start. The Gate end of the second power tube MN2 is connected to the Gate end of the first power tube MN1 to ensure that the two work under the same control signal. The Source end of the second power tube MN2 is connected to the sampling port CS, and the Drain end is connected to the second current mirror MP2. The main function of the second power tube MN2 is to help share the overload current of the first power tube MN1 through a current shunt mechanism. There is a predetermined current ratio between the second power tube MN2 and the first power tube MN1. When the current of the first power tube MN1 exceeds its rated value, the second power tube MN2 is connected and shares the excess current. These shunted currents will be fed back to the second current mirror MP2, thereby alleviating the overload pressure of the first power tube MN1.

[0090] If the feedback current of the second current mirror MP2 continues to exceed the set value, the system will further start the third current mirror MP3 and the fourth current mirror MP4 to increase the feedback strength and control effect. The Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2. The third current mirror MP3 forms a proportional current relationship with the second current mirror MP2 through this connection, and the output current maintains a certain ratio with the second current mirror MP2. The Gate end of the fourth current mirror MP4 is connected to the Gate end of the third current mirror MP3, and its Drain end is connected to the negative pole of the operational amplifier to form a negative feedback path.

[0091] When the fourth current mirror MP4 is turned on, its feedback current I1 passes through the feedback resistor R fb , generates a negative feedback voltage (I1 * R fb ), this negative feedback voltage is transmitted to the negative input terminal of the operational amplifier. The role of negative feedback is to further reduce the current flowing through the first power tube MN1 by reducing the output of the operational amplifier to limit its current to not exceed the maximum rated value, thereby achieving balanced control of the current in the multi-chip current sharing circuit. This negative feedback regulation mechanism is very effective in maintaining the safety and stability of the system in high-current applications. It can adjust the current distribution of each circuit in multiple parallel circuits in real time to prevent a chip from being damaged due to overload.

[0092] This multi-level feedback and current balancing control method is particularly effective in scenarios where multiple chips are connected in parallel to drive LEDs. For example, in an LED array driving application, this method can ensure that each chip shares the load equally, so that the brightness of the LED is uniform and the system operates stably. Difficulties that need to be overcome include the precise matching of the current mirror and feedback components, as well as the control of the response speed of the operational amplifier to ensure that the entire system can quickly and accurately achieve current balancing regulation under various operating conditions.

[0093] The present invention also provides a circuit control device based on an adaptive inter-chip current balancing circuit, wherein the adaptive inter-chip current balancing circuit is the adaptive inter-chip current balancing circuit described in the above embodiment, and the circuit control device comprises: a first control unit, used to control the start-up of the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify the subsequent current regulation standard; a second control unit, used to control the start-up of the operational amplifier, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and is connected to the sampling resistor R cs The current state of the current is fed back, and the output voltage of the operational amplifier is transmitted to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; the first feedback unit is used for connecting the Drain terminal of the first power tube MN1 to the N port and the Source terminal of the first power tube MN1 to the sampling port CS and the sampling resistor R under the control of the operational amplifier. cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R cs The voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; a third control unit is used to control the second current mirror MP2 to cooperate with the first current mirror MP1, and a reference current is formed by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

[0094] The present invention also provides a circuit control device based on an adaptive inter-chip current balancing circuit group, wherein the adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group described in the above embodiment, and the circuit control device comprises: a fourth control unit, used to control the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each operational amplifier, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; a fifth control unit, used to control the positive electrode of the operational amplifier to receive the reference voltage and the negative electrode to be connected to the sampling port and the sampling resistor in each parallel adaptive inter-chip current balancing circuit, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time through the sampling resistor R csfeedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; a sixth control unit, used to control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs , to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; a second feedback unit, used for, when a plurality of the adaptive inter-chip current balancing circuits are connected in parallel, a proportional current feedback relationship between the first current mirror MP1 and the second current mirror MP2, wherein the first current mirror MP1 generates a reference current, the Gate terminal of the second current mirror MP2 is connected to the first current mirror MP1, and the Drain terminal of the second power tube MN2 is connected to the sampling port CS; a first starting unit, used for starting the second power tube MN2 when it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, and the Source terminal of the second power tube MN2 is connected to The sampling port CS, the Drain end of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting to alleviate the overload of the first power tube MN1; the second starting unit is used to start the third current mirror MP3 and the fourth current mirror MP4 when the feedback current of the second current mirror MP2 exceeds the set value, the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein, when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

[0095] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0096] Reference Figure 6 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0097] Those skilled in the art will understand that Figure 6 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0098] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0099] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0100] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0101] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An adaptive inter-chip current balancing circuit for linear LED driving, characterized in that: The adaptive inter-chip current balancing circuit includes: a reference circuit module, an operational amplifier, a first power tube MN1, a first current mirror MP1, a second current mirror MP2, an N port for connecting to the negative electrode of the LED and a sampling port CS for connecting to the signal ground, wherein: The reference circuit module is used to provide a reference voltage VREF and a reference current source, wherein the reference voltage VREF is provided to the operational amplifier as a reference voltage, and the reference current source is provided to the first current mirror MP1 to form a current reference for circuit regulation; The operational amplifier has a positive electrode connected to the reference voltage VREF, a negative electrode connected to the sampling port CS, the first power tube MN1 and the second current mirror MP2 to form a control loop, and the output of the operational amplifier is connected to the Gate terminal of the first power tube MN1 to provide a driving signal, and a constant current output is achieved by adjusting the Gate terminal voltage of the first power tube MN1 to control the current in the path; The first power tube MN1 has a Drain terminal connected to the N port to connect to the LED cathode, and a Source terminal connected to the sampling resistor R at the sampling port CS. cs The Gate terminal is connected to the output terminal of the operational amplifier. The first power tube MN1 is used to provide a constant driving current for the LED. The magnitude of the driving current is determined by the operational amplifier according to the reference voltage and the sampling resistor R cs The feedback signal is used for control; The first current mirror MP1 and the second current mirror MP2 form a proportional current feedback mechanism, and the Gate and Drain terminals of the first current mirror MP1 are short-circuited and connected to a reference current source, and the Source terminal is connected to an internal power supply VDD. The first current mirror MP1 is used to generate and stabilize a portion of the current as a regulation reference for the circuit; The second current mirror MP2 has a Gate terminal connected to the Gate terminal of the first current mirror MP1, and a Drain terminal connected to the sampling port CS. By forming a proportional current feedback mechanism with the first current mirror MP1, the ratio of the sampling current flowing through the CS port to the reference current is kept constant, thereby participating in the regulation of the LED driving current. The sampling port CS is connected to the sampling resistor R cs , the sampling resistor R cs One end is connected to the CS port and the other end is grounded, which is used to detect the current flowing through the first power tube MN1 and feed the sampled voltage back to the negative input terminal of the operational amplifier so as to pass through the sampling resistor R cs The operational amplifier can adjust the voltage output to the Gate terminal of the first power tube MN1 based on the voltage feedback signal, thereby controlling the current flowing through the first power tube MN1 to be maintained within a preset range.

2. The adaptive inter-chip current balancing circuit according to claim 1, characterized in that: The adaptive inter-chip current balancing circuit further includes: a third current mirror MP3 and a fourth current mirror MP4, The Gate and Drain terminals of the third current mirror MP3 are short-circuited and connected to the Drain terminal of the second current mirror MP2. The Source terminal of the third current mirror MP3 is connected to the internal power supply VDD, so as to form a second set of proportional current feedback mechanism with the second current mirror MP2. The output current of the third current mirror MP3 is adjusted according to the output current of the second current mirror MP2, so as to balance the current distribution of multiple chips in the multi-chip parallel working mode in the circuit. The Gate terminal of the fourth current mirror MP4 is connected to the Gate terminal of the third current mirror MP3, the Drain terminal of the fourth current mirror MP4 is connected to the negative input of the operational amplifier, and the Source terminal of the fourth current mirror MP4 is connected to the internal power supply VDD; the fourth current mirror MP4 guides the current fed back by the second current mirror MP2 to the negative electrode of the operational amplifier through the proportional current relationship formed with the third current mirror MP3 to form an overall negative feedback regulation, thereby regulating the current flowing through the first power tube MN1, so as to balance the current of each chip in the multi-chip working mode.

3. The adaptive inter-chip current balancing circuit according to claim 2, characterized in that: The adaptive inter-chip current balancing circuit further includes: a second power tube MN2, The Gate end of the second power tube MN2 is connected to the Gate end of the first power tube MN1, and the Source end of the second power tube MN2 and the Source end of the first power tube MN1 are both connected to the sampling port CS, and the Drain end of the current sampling tube is connected to the Drain end of the second current mirror MP2, which is used to form a current distribution circuit together with the first power tube MN1, so that current diversion can be achieved in the multi-chip parallel working mode, and the current balance flowing through each chip is adjusted by combining with the second current mirror MP2.

4. The adaptive inter-chip current balancing circuit according to claim 3, characterized in that: The adaptive inter-chip current balancing circuit also includes a feedback resistor R fb , The feedback resistor R fb connected between the negative input of the operational amplifier and the sampling port CS, and generates a negative feedback regulation voltage together with the current of the fourth current mirror MP4, wherein when the feedback current flowing through the fourth current mirror MP4 is I1, the feedback resistor R fb The feedback voltage generated is I1*R fb and transmits the voltage to the negative input of the operational amplifier to dynamically adjust the control voltage output by the operational amplifier to the Gate terminal of the first power tube MN1.

5. An adaptive inter-chip current balancing circuit group for linear LED driving, characterized in that: The adaptive inter-chip current balancing circuit group includes: a plurality of adaptive inter-chip current balancing circuits, wherein the adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group described in claim 4, and the adaptive inter-chip current balancing circuits are arranged in parallel.

6. A circuit control method based on an adaptive inter-chip current sharing circuit, characterized in that: The adaptive inter-chip current balancing circuit is the adaptive inter-chip current balancing circuit according to any one of claims 1 to 4, and the circuit control method includes: Control the reference circuit module to start up to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify subsequent current regulation standards; The operational amplifier is controlled to start, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and the sampling resistor R cs Feedback the current current state, and transmit the output voltage of the operational amplifier to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; Under the control of the operational amplifier, the Drain end of the first power tube MN1 is connected to the N port, and the Source end of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R cs The voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; The second current mirror MP2 is controlled to cooperate with the first current mirror MP1, a reference current is formed by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

7. A circuit control method based on an adaptive inter-chip current sharing circuit group, characterized in that: The adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group according to claim 5, and the circuit control method comprises: Controlling the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each operational amplifier, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; In each parallel adaptive inter-chip current balancing circuit, the positive electrode of the operational amplifier is controlled to receive the reference voltage, and the negative electrode is connected to the sampling port and the sampling resistor, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time through the sampling resistor R cs feedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; Control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 is connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs , to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; When a plurality of the adaptive inter-chip current balancing circuits are connected in parallel, a proportional current feedback relationship is formed between the first current mirror MP1 and the second current mirror MP2, wherein the first current mirror MP1 generates a reference current, the Gate terminal of the second current mirror MP2 is connected to the first current mirror MP1, and the Drain terminal of the second power transistor MN2 is connected to the sampling port CS; When it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, the second power tube MN2 is started, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, the Source terminal of the second power tube MN2 is connected to the sampling port CS, the Drain terminal of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting, so as to alleviate the overload of the first power tube MN1; When the feedback current of the second current mirror MP2 exceeds the set value, the third current mirror MP3 and the fourth current mirror MP4 are started, the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

8. A circuit control device based on an adaptive inter-chip current balancing circuit, characterized in that: The adaptive inter-chip current balancing circuit is the adaptive inter-chip current balancing circuit according to any one of claims 1 to 4, and the circuit control device comprises: A first control unit, used for controlling the start-up of the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of the operational amplifier as a control voltage reference, and the reference current source is transmitted to the Gate and Drain terminals of the first current mirror MP1 to generate a reference current to unify subsequent current regulation standards; The second control unit is used to control the operational amplifier to start, the positive electrode of the operational amplifier receives the reference voltage, the negative electrode of the operational amplifier is connected to the sampling port CS, and the sampling resistor R cs Feedback the current current state, and transmit the output voltage of the operational amplifier to the Gate terminal of the first power tube MN1 to drive the first power tube MN1 to work and maintain the current flowing through the first power tube MN1; The first feedback unit is used to connect the Drain end of the first power tube MN1 to the N port and the Source end of the first power tube MN1 to the sampling port CS and the sampling resistor R under the control of the operational amplifier. cs , so that the first power tube MN1 passes through the sampling resistor R cs Detect the current value flowing through and set the sampling resistor R cs The voltage is fed back to the negative electrode of the operational amplifier to adjust the output of the operational amplifier in real time; The third control unit is used to control the second current mirror MP2 to cooperate with the first current mirror MP1, to form a reference current by short-circuiting the Gate and Drain terminals of the first current mirror MP1, and the Source terminal of the first current mirror MP1 is connected to the internal power supply VDD to keep the reference current source generating a stable current.

9. A circuit control device based on an adaptive inter-chip current sharing circuit group, characterized in that: The adaptive inter-chip current balancing circuit group is the adaptive inter-chip current balancing circuit group according to claim 5, and the circuit control device comprises: a fourth control unit, configured to control the reference circuit module to provide a reference voltage and a reference current source, wherein the reference voltage is transmitted to the positive electrode of each of the operational amplifiers, and the reference current source is input to the first current mirror MP1 to generate a reference voltage; A fifth control unit is used to control the positive electrode of the operational amplifier to receive the reference voltage and the negative electrode to be connected to the sampling port and the sampling resistor in each parallel adaptive inter-chip current balancing circuit, wherein the output of the operational amplifier is connected to the Gate segment of the first power tube MN1, and the operational amplifier adjusts the Gate terminal voltage in real time through the sampling resistor R cs feedback, so that the current of the first power tube MN1 in each of the adaptive inter-chip current balancing circuits reaches a preset value; A sixth control unit, configured to control the first power tube MN1 of each of the adaptive inter-chip current balancing circuits to be connected to the N port, and the Source end of each of the first power tube MN1 to be connected to the sampling port CS and the sampling resistor R of its respective adaptive inter-chip current balancing circuit cs , to detect the current of each of the adaptive inter-chip current balancing circuits, wherein the operational amplifier adjusts the driving current of the first power tube MN1 according to the sampling feedback signal, so that the current of each of the adaptive inter-chip current balancing circuits reaches a preset value; a second feedback unit, configured to establish a proportional current feedback relationship between the first current mirror MP1 and the second current mirror MP2 when a plurality of the adaptive inter-chip current balancing circuits are connected in parallel, wherein the first current mirror MP1 generates a reference current, a Gate terminal of the second current mirror MP2 is connected to the first current mirror MP1, and a Drain terminal of the second power transistor MN2 is connected to the sampling port CS; a first starting unit, used for starting the second power tube MN2 when it is detected that the current of the first power tube MN1 of a single adaptive inter-chip current balancing circuit exceeds the rated value, wherein the second power tube MN2 is connected to the Gate of the first power tube MN1, the Source terminal of the second power tube MN2 is connected to the sampling port CS, the Drain terminal of the second power tube MN2 is connected to the second current mirror MP2, and the current ratio of the second power tube MN2 to the first power tube MN1 is predetermined, and the second power tube MN2 feeds back the excess current to the second current mirror MP2 through current shunting to alleviate the overload of the first power tube MN1; The second startup unit is used to start the third current mirror MP3 and the fourth current mirror MP4 when the feedback current of the second current mirror MP2 exceeds the set value, the Gate and Drain of the third current mirror MP3 are connected to the Drain end of the second current mirror MP2 to form a current proportional relationship, the Gate of the fourth current mirror MP4 is connected to the Gate of the third current mirror MP3, and the Drain of the fourth current mirror MP4 is connected to the negative electrode of the operational amplifier to generate negative feedback, wherein when the fourth current mirror MP4 is turned on, the feedback current I1 of the fourth current mirror MP4 passes through the feedback resistor R fb , generating negative feedback voltage I1*R fb , and fed back to the negative electrode of the operational amplifier, so as to limit the current of the first power tube MN1 within the range of the maximum rated value to achieve current balance.

10. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method described in claim 6 or 7 are implemented.

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