Semiconductor device

Abstract

A semiconductor device includes: a substrate having a top surface and a bottom surface opposite to each other; a gate structure on the top surface of the substrate; a plurality of source / drain patterns on the top surface of the substrate and on opposite sides of the gate structure; a rear-side conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure and a first source / drain pattern of the plurality of source / drain patterns; and a magnetic tunnel junction pattern electrically connected to a second source / drain pattern of the plurality of source / drain patterns.

Description

Technical Field

[0001] Various example embodiments relate to a semiconductor device and / or a method of manufacturing the same, and more particularly, to a semiconductor device including a magnetic tunnel junction and / or a method of manufacturing the same. Background Art

[0002] As electronic products tend to be high speed and / or low power consumption, there is an increasing need or expectation for high speed and low operating voltage for semiconductor memory devices included in electronic products. In order to meet or at least partially meet the above expectations, magnetic memory devices have been developed as semiconductor memory devices. Since magnetic memory devices operate at high speeds and have non-volatile properties, they have attracted considerable attention as next generation semiconductor memory devices.

[0003] Generally, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern includes two magnetic structures and an insulating layer interposed therebetween. The resistance of the magnetic tunnel junction pattern varies according to the magnetization directions of the two magnetic structures. For example, the magnetic tunnel junction pattern has a high resistance when the magnetization directions of the two magnetic structures are antiparallel to each other, and has a low resistance when the magnetization directions of the two magnetic structures are parallel to each other. The magnetic memory device may write and read data using the resistance difference between the high resistance and the low resistance of the magnetic tunnel junction pattern.

[0004] According to various demands or expectations of the electronics industry, various studies are being conducted on semiconductor devices having an embedded structure in which a magnetic tunnel junction pattern is provided between metal lines. Summary of the invention

[0005] Some example embodiments provide a semiconductor device having improved electrical performance and / or a method of manufacturing the same.

[0006] Alternatively or additionally, some example embodiments may provide a semiconductor device including a magnetic tunnel junction pattern having different switching characteristics and a method of manufacturing the same.

[0007] According to some example embodiments, a semiconductor device may include: a substrate having a top surface and a bottom surface opposite to each other; a gate structure on the top surface of the substrate; a plurality of source / drain patterns on the top surface of the substrate and on opposite sides of the gate structure; a backside conductive line on the bottom surface of the substrate and electrically connected to the gate structure and at least one of a first source / drain pattern of the plurality of source / drain patterns; and a magnetic tunnel junction pattern electrically connected to a second source / drain pattern of the plurality of source / drain patterns.

[0008] Alternatively or additionally, according to some example embodiments, a semiconductor device may include: a substrate having a top surface and a bottom surface opposite to each other; a gate structure on the top surface of the substrate; a plurality of source / drain patterns on the top surface of the substrate and on opposite sides of the gate structure; a front-side conductive line on the top surface of the substrate and electrically connected to the gate structure and at least one of the first source / drain patterns of the plurality of source / drain patterns; a back-side conductive line on the bottom surface of the substrate and electrically connected to the first source / drain pattern and at least one of the gate structure; and a through-via penetrating at least a portion of the substrate and connected to the back-side conductive line and the front-side conductive line.

[0009] Optionally or additionally, according to some example embodiments, a semiconductor device may include: a substrate having a top surface and a bottom surface opposite to each other, the substrate including a first region and a second region horizontally spaced apart from each other; a first transistor on the top surface of the first region of the substrate; a first magnetic tunnel junction pattern on the top surface of the first region of the substrate and electrically connected to a first drain terminal of the first transistor; a first back-side conductive line on the bottom surface of the first region of the substrate and electrically connected to at least one of a first source terminal and a first gate terminal of the first transistor; a second transistor on the top surface of the second region of the substrate; and a second magnetic tunnel junction pattern on the bottom surface of the second region of the substrate and electrically connected to a second drain terminal of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A circuit diagram showing a unit memory cell of a semiconductor device according to some example embodiments is shown.

[0011] Figure 2 A plan view showing a semiconductor device according to some example embodiments is shown.

[0012] Figure 3A , Figure 3B and Figure 3C Shown along Figure 2 Cross-sectional views taken along lines AA', BB' and CC'.

[0013] Figure 4A and Figure 4B A cross-sectional view showing an example of a magnetic tunnel junction pattern in a semiconductor device according to some example embodiments is illustrated.

[0014] FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C Diagrams showing a method of manufacturing a semiconductor device according to some example embodiments are shown.

[0015] Figure 7 A plan view showing a semiconductor device according to some example embodiments is shown.

[0016] Fig. 8A and Figure 8B Shown along Figure 7 A cross-sectional view taken along lines BB' and CC'.

[0017] Fig. 9 A plan view showing a semiconductor device according to some example embodiments is shown.

[0018] Fig.10 Shown along Fig. 9 A cross-sectional view taken along line CC'.

[0019] Fig.11 A plan view showing a semiconductor device according to some example embodiments is shown.

[0020] Fig. 12A , Fig. 12B and Fig. 12C Shown along Fig.11 Cross-sectional views taken along lines AA', BB' and CC'.

[0021] Fig.13A , Fig. 13B and Fig. 13C Shown along Fig.11 , which are cross-sectional views taken along lines AA′, BB′, and CC′, illustrate methods of fabricating a semiconductor device according to some example embodiments.

[0022] Fig.14 A plan view showing a semiconductor device according to some example embodiments is shown.

[0023] Fig.15A , Fig. 15B and Fig. 15C Shown along Fig.14 Cross-sectional views taken along lines AA', BB' and CC'.

[0024] Fig.16 A plan view showing a semiconductor device according to some example embodiments is shown.

[0025] Fig.17A , Fig. 17B and Fig. 17C Shown along Fig.16 Cross-sectional views taken along lines AA', BB' and CC'.

[0026] Fig.18A , Fig.18B and Fig. 18C Shown along Figure 2 2 , cross-sectional views taken along lines AA′, BB′, and CC′ of FIG. 1 show semiconductor devices according to some example embodiments.

[0027] Fig.19A , Fig.19B and Fig.19C Shown along Figure 2 , which are cross-sectional views taken along lines AA′, BB′, and CC′, illustrate methods of fabricating a semiconductor device according to some example embodiments.

[0028] Fig. 20A and Fig. 20B Shown along Figure 7 sectional views taken along lines BB′ and CC′ of FIG. 1 show semiconductor devices according to some example embodiments.

[0029] Fig.21 Shown along Fig. 9 1 is a cross-sectional view taken along line CC' of FIG. 1 , showing a semiconductor device according to some example embodiments.

[0030] Fig. 22 Shown along Fig. 9 A cross-sectional view taken along line CC' of FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments.

[0031] Fig.23A , Fig. 23B and Fig.23C Shown along Fig.11 2 , cross-sectional views taken along lines AA′, BB′, and CC′ of FIG. 1 show semiconductor devices according to some example embodiments.

[0032] Fig.24A , Fig. 24B and Fig.24C Shown along Fig.14 2 , cross-sectional views taken along lines AA′, BB′, and CC′ of FIG. 1 show semiconductor devices according to some example embodiments.

[0033] Fig.25 A simplified plan view showing a semiconductor device according to some example embodiments is shown.

[0034] Fig.26 Shown in Fig.25 A cross-sectional view of a component on a first area and a second area. DETAILED DESCRIPTION

[0035] Some example embodiments will now be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 A circuit diagram showing a unit memory cell of a semiconductor device according to some example embodiments is shown.

[0037] Reference Figure 1, the unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME and the selection element SE may be electrically connected in series with each other. The memory element ME may be connected between the bit line BL and the selection element SE. The selection element SE may be connected between the memory element ME and the source line SL, and may be controlled by a row line or a word line WL. The selection element SE may be or may include, for example, a bipolar transistor (such as an NPN and / or PNP transistor), and / or may include a metal oxide semiconductor (MOS) field effect transistor (such as an NMOS and / or PMOS transistor).

[0038] The storage element ME may include a magnetic tunnel junction pattern MTJ, which includes magnetic patterns MP1 and MP2 spaced apart from each other and also includes a tunnel barrier pattern TBP between the magnetic patterns MP1 and MP2. One of the magnetic patterns MP1 and MP2 may be a reference magnetic pattern or may include a reference magnetic pattern or be included in the reference magnetic pattern, which has a magnetization direction fixed under a normal use environment regardless of an external magnetic field. The other of the magnetic patterns MP1 and MP2 may be a free magnetic pattern or may include a free magnetic pattern or be included in the free magnetic pattern, the magnetization direction of which changes between two stable magnetization directions due to an external magnetic field. The magnetic tunnel junction pattern MTJ may have a much larger (e.g., several orders of magnitude) resistance value when the magnetization direction of the reference magnetic pattern and the magnetization direction of the free magnetic pattern are antiparallel to each other than when the magnetization direction of the reference magnetic pattern and the magnetization direction of the free magnetic pattern are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ may be controlled by changing the magnetization direction of the free magnetic pattern. The memory element ME may utilize a resistance difference depending on a magnetization direction of a reference magnetic pattern and a magnetization direction of a free magnetic pattern, and this mechanism may enable the unit memory cell MC to store data therein.

[0039] Figure 2 A plan view showing a semiconductor device according to some example embodiments is shown. Figure 3A , Figure 3B and Figure 3C Shown along Figure 2 Cross-sectional views taken along lines AA', BB' and CC'. Figure 4A and Figure 4B A cross-sectional view showing an example of a magnetic tunnel junction pattern in a semiconductor device according to some example embodiments is illustrated.

[0040] Reference Figure 2 and FIG. 3A to FIG. 3C, a substrate 100 including an active region AR may be provided. The substrate 100 may be or may include a semiconductor substrate, such as one or more of a silicon substrate, a germanium substrate, and a silicon germanium substrate. The substrate 100 may be undoped, or may be doped, for example, lightly doped with impurities. The substrate 100 may be provided with a device isolation layer 102 defining the active region AR therein. The active region AR may extend in a first direction D1, and may be spaced apart from each other in a second direction D2 via the device isolation layer 102. The first direction D1 and the second direction D2 may be parallel to the bottom surface 100L of the substrate 100, and may intersect each other. The active region AR may be a PMOSFET region, such as a region doped with a high concentration of p-type impurities (such as, but not limited to, boron), or alternatively, may be an NMOSFET region, such as a region doped with a high concentration of n-type impurities (such as arsenic and / or phosphorus). The device isolation layer 102 may include at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In some example embodiments, the device isolation layer 102 may be a shallow trench isolation (STI) layer; example embodiments are not limited thereto.

[0041] The active pattern AP may be disposed on the active region AR. The active pattern AP may protrude from the corresponding active region AR in a third direction D3, which may be perpendicular to the bottom surface 100L of the substrate 100. The active patterns AP may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. The device isolation layer 102 may extend onto the top surface of each active region AR and may cover the side surface of the active pattern AP. The active region AR and the active pattern AP may be or may correspond to a portion of the substrate 100 protruding from the lower portion of the substrate 100 in the third direction D3.

[0042] Each active pattern AP may include a channel pattern CH protruding from a top surface AP_U of a corresponding one of the active patterns AP in a third direction D3. The channel pattern CH may be referred to as an active fin. The channel pattern CH may protrude upward from the device isolation layer 102 and may not be covered with the device isolation layer 102. For example, the device isolation layer 102 may expose the top surface CH_U and the side surface of the channel pattern CH. The source / drain pattern SD may be correspondingly disposed on the top surface AP_U of the active pattern AP. The channel pattern CH may be interposed between the source / drain patterns SD. The source / drain pattern SD may be an epitaxial pattern such as a heterogeneous or homogeneous epitaxial pattern, for example, formed by a selective epitaxial growth process in which each active pattern AP is used as a seed crystal. The source / drain pattern SD may include, for example, at least one selected from silicon, silicon germanium, and silicon carbide. The top surface AP_U of each active pattern AP, the top surface CH_U of the channel pattern CH, and the side surface of the channel pattern CH may be referred to as the top surface 100U of the substrate 100. The top surface 100U of the substrate 100 may be located opposite to the bottom surface 100L of the substrate 100 .

[0043] The gate structure GS may be disposed on the top surface 100U of the substrate 100. The gate structure GS may extend in the second direction D2 to extend across the active pattern AP. The gate structure GS may overlap the channel pattern CH vertically (e.g., in the third direction D3). The gate structure GS may cover the top surface CH_U and side surfaces of the channel pattern CH and may extend onto the top surface of the device isolation layer 102. The source / drain pattern SD may be disposed on opposite sides of the gate structure GS.

[0044] The gate structure GS may include a gate electrode GE, a gate dielectric pattern GI between the gate electrode GE and the channel pattern CH, a gate spacer GSP on a side surface of the gate electrode GE, and a gate capping pattern CAP on a top surface of the gate electrode GE. The gate dielectric pattern GI may extend between the gate electrode GE and the gate spacer GSP, and may have an uppermost surface substantially coplanar with a top surface of the gate electrode GE. The gate electrode GE may cover a top surface CH_U and a side surface of the channel pattern CH, and may extend onto a top surface of the device isolation layer 102. The gate dielectric pattern GI may be interposed between the gate electrode GE and the top surface CH_U of the channel pattern CH and between the gate electrode GE and each side surface of the channel pattern CH, and may extend between the gate electrode GE and the top surface of the device isolation layer 102.

[0045] The gate structure GS, the channel pattern CH and the source / drain pattern SD may constitute or be included in a fin field effect transistor (FinFET). The gate electrode GE may be referred to as a gate terminal of the transistor, and the source / drain pattern SD may be referred to as a source / drain terminal of the transistor.

[0046] The gate electrode GE may include one or more of a doped semiconductor (such as doped polysilicon), a conductive metal nitride, and a metal. The gate dielectric pattern GI may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer. The high-k dielectric layer may include a material whose dielectric constant is greater than that of the silicon oxide layer, such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO). The gate spacer GSP and the gate capping pattern CAP may each simultaneously or independently include at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0047] The first interlayer dielectric layer 110 may be disposed on the top surface 100U of the substrate 100 and may cover top surfaces of the gate structure GS, the source / drain pattern SD, and the device isolation layer 102. The first interlayer dielectric layer 110 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0048] The source / drain contact 112 may penetrate the first interlayer dielectric layer 110 to be connected to the source / drain pattern SD. The source / drain contact 112 may be disposed on opposite sides of the gate structure GS and may have a strip shape extending in the second direction D2. The gate contact 114 may penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP to be connected to the gate electrode GE. The source / drain contact 112 and the gate contact 114 may have a top surface substantially coplanar with the top surface of the first interlayer dielectric layer 110. For example, the top surface of the source / drain contact 112 and the top surface of the gate contact 114 may be located at the same height as the top surface of the first interlayer dielectric layer 110. As described herein, the term "height" may be a distance measured from the bottom surface 100L of the substrate 100 in the third direction D3. The source / drain contact 112 and the gate contact 114 may include the same conductive material, may include or may not include different materials. The source / drain contacts 112 and the gate contact 114 may include a metal material such as at least one selected from aluminum, copper, tungsten, molybdenum, and cobalt.

[0049] The second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110 and may cover the top surfaces of the source / drain contacts 112 and the top surfaces of the gate contacts 114. The second interlayer dielectric layer 120 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer, and may include the same material as the first interlayer dielectric layer 110 or may not include the same material as the first interlayer dielectric layer 110.

[0050] The first via contacts 122 may be disposed in the second interlayer dielectric layer 120. Each first via contact 122 may penetrate the second interlayer dielectric layer 120 to connect with a corresponding one of the source / drain contacts 112 and the gate contact 114. The first via contacts 122 may include a conductive material (e.g., a metal such as one or more of aluminum, tungsten, and copper).

[0051] The second interlayer dielectric layer 120 may be provided with front side conductive lines 132A and 134A and a first conductive line 136 thereon. The front side conductive lines 132A and 134A and the first conductive line 136 may be located at the same height from the bottom surface 100L of the substrate 100. The front side conductive lines 132A and 134A and the first conductive line 136 may include the same conductive material (such as metal), may include different materials, or may not include different materials. The front side conductive lines 132A and 134A may include a front side source line 132A and a front side word line 134A. The front side source line 132A and the front side word line 134A may extend in the second direction D2 and may be spaced apart from each other in the first direction D1.

[0052] The front side source line 132A may be connected to a first source / drain contact 112 of the source / drain contacts 112 through a corresponding one of the first via contacts 122, and may be electrically connected to a first source / drain pattern SD of the source / drain patterns SD through the first source / drain contact 112. In some example embodiments, the first source / drain contact 112 may be referred to as a source contact, and the first source / drain pattern SD may be referred to as a source pattern or a source terminal.

[0053] The front-side word line 134A may be connected to the gate contact 114 through a corresponding one of the first via contacts 122 , and may be electrically connected to the gate structure GS (eg, the gate electrode GE) through the gate contact 114 .

[0054] The first conductive line 136 may be connected to a second one of the source / drain contacts 112 through a corresponding one of the first via contacts 122, and may be electrically connected to a second one of the source / drain patterns SD through the second source / drain contact 112. In some example embodiments, the second source / drain contact 112 may be referred to as a drain contact, and the second source / drain pattern SD may be referred to as a drain pattern or a drain terminal.

[0055] The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120, and may cover the front-side conductive lines 132A and 134A and the first conductive line 136. The third interlayer dielectric layer 130 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer, and may include the same material as that of the first interlayer dielectric layer 110 and / or the second interlayer dielectric layer 120 or may not include the same material as that of the first interlayer dielectric layer 110 and / or the second interlayer dielectric layer 120.

[0056] The data storage pattern DS may be disposed on the third interlayer dielectric layer 130, and the lower electrode contact 138 may be disposed in the third interlayer dielectric layer 130 and under the data storage pattern DS. The lower electrode contact 138 may penetrate the third interlayer dielectric layer 130 to be connected to the first conductive line 136 and the data storage pattern DS. The lower electrode contact 138 may include at least one of a doped semiconductor material (e.g., doped silicon, such as doped polysilicon), a metal (e.g., tungsten, titanium, and / or tantalum), a metal-semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride).

[0057] The data storage pattern DS may be electrically connected to the first conductive line 136 through the lower electrode contact 138. The first conductive line 136 may be connected to the second source / drain contact 112 through a corresponding one of the first via contacts 122, and may be electrically connected to the second source / drain pattern SD through the second source / drain contact 112. For example, the data storage pattern DS may be electrically connected to the second source / drain pattern SD through the lower electrode contact 138, the first conductive line 136, the corresponding first via contact 122, and the second source / drain contact 112.

[0058] Reference Figure 4A and Figure 4B, the data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the third interlayer dielectric layer 130 in the third direction D3. The magnetic tunnel junction pattern MTJ may be disposed between the bottom electrode BE and the top electrode TE. The lower electrode contact 138 may be connected to the bottom electrode BE of the data storage pattern DS. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride and / or tantalum nitride). The top electrode TE may include at least one selected from a metal (e.g., one or more of Ta, W, Ru, and Ir) and / or a conductive metal nitride (e.g., TiN).

[0059] In some example embodiments, the first magnetic pattern MP1 may be a reference layer having a unidirectionally fixed magnetization direction MD1, and the second magnetic pattern MP2 may be a free layer having a magnetization direction MD2 that can be changed to be parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 4A and Figure 4B An example is shown in which the second magnetic pattern MP2 is a free layer, but example embodiments are not limited thereto. Figure 4A and Figure 4B Different from what is shown, the first magnetic pattern MP1 may be a free layer, and the second magnetic pattern MP2 may be a reference layer.

[0060] Reference Figure 4A , for example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include at least one selected from an intrinsic perpendicular magnetic material and an extrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material may include a material having a perpendicular magnetization property even in the absence of external factors. The intrinsic perpendicular magnetic material may include a perpendicular magnetic material (e.g., one or more of CoFeTb, CoFeGd, CoFeDy), a material having L1 0 At least one selected from a perpendicular magnetic material with a structure, a CoPt with a hexagonal close-packed (HCP) lattice structure, and a perpendicular magnetic structure. 0 The vertical magnetic material of the structure can include L1 0 Structure of FePt, L1 0Structure of FePd, L1 0 CoPd and L1 of the structure 0 At least one selected from CoPt of the structure. The vertical magnetic structure may include magnetic layers and non-magnetic layers stacked alternately and repeatedly, for example, having the same or different or varying thicknesses in each layer. For example, the vertical magnetic structure may include at least one selected from (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n and (CoCr / Pd)n (where n is the number of stacked layers). The non-intrinsic vertical magnetic material may include a material having an intrinsic horizontal magnetization characteristic or a vertical magnetization characteristic caused by an external factor. For example, the non-intrinsic vertical magnetic material may have a vertical magnetization characteristic due to the magnetic anisotropy caused by the junction between the tunnel barrier pattern TBP and the first magnetic pattern MP1 (or the second magnetic pattern MP2). The non-intrinsic vertical magnetic material may include, for example, CoFeB.

[0061] Reference Figure 4B As another example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be parallel to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a ferromagnetic material. The first magnetic pattern MP1 may also include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material in the first magnetic pattern MP1.

[0062] Each of the first and second magnetic patterns MP1 and MP2 may include a Heusler alloy including Co. The tunnel barrier pattern TBP may include at least one selected from a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (MgZn) oxide layer, and a magnesium-boron (MgB) oxide layer.

[0063] Return to reference Figure 2 and FIG. 3A to FIG. 3C The third interlayer dielectric layer 130 may be provided thereon with a fourth interlayer dielectric layer 140 surrounding the data storage pattern DS. The fourth interlayer dielectric layer 140 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0064] The first unit conductive line 152 may be provided on the fourth interlayer dielectric layer 140. The first unit conductive line 152 may extend in the first direction D1 and may extend across the front side conductive lines 132A and 134A and the first conductive line 136. The first unit conductive line 152 may be electrically connected to the data storage pattern DS and may be connected to the top electrode TE of the data storage pattern DS. The first unit conductive line 152 may include a conductive material such as a metal (e.g., copper and / or aluminum and / or tungsten).

[0065] The fourth interlayer dielectric layer 140 may be provided thereon with a fifth interlayer dielectric layer 150 covering the first unit conductive line 152. The fifth interlayer dielectric layer 150 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0066] The second unit conductive line 154 may be disposed on the fifth interlayer dielectric layer 150. The second unit conductive line 154 may extend in the first direction D1, and may extend across the front-side conductive lines 132A and 134A and the first conductive line 136. The second unit conductive line 154 may overlap the first unit conductive line 152 vertically (eg, in the third direction D3).

[0067] The second via contact 156 may be disposed in the fifth interlayer dielectric layer 150 and may be interposed between the first unit conductive line 152 and the second unit conductive line 154. The first unit conductive line 152 and the second unit conductive line 154 may be electrically connected to each other through the second via contact 156. The first unit conductive line 152, the second via contact 156, and the second unit conductive line 154 may constitute or correspond to a column line, such as a bit line (see Figure 1 The second via contact 156 and the second cell conductive line 154 may include a conductive material such as a metal (eg, copper and / or tungsten and / or aluminum).

[0068] The backside conductive lines 132B and 134B may be disposed on the bottom surface 100L of the substrate 100, and the lower dielectric layer 210 may be interposed between the bottom surface 100L of the substrate 100 and the backside conductive lines 132B and 134B. The lower dielectric layer 210 may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer. The backside conductive lines 132B and 134B may include a conductive material (e.g., metal).

[0069] The backside conductive lines 132B and 134B may include a backside source line 132B and a backside word line 134B. The backside source line 132B and the backside word line 134B may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The backside source line 132B may overlap or at least partially overlap with the frontside source line 132A vertically (e.g., in the third direction D3), and the backside word line 134B may overlap with the frontside word line 134A vertically (e.g., in the third direction D3).

[0070] Through vias 200 and 202 may be provided to penetrate at least a portion of the substrate 100. Each of the through vias 200 and 202 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to a corresponding one of the backside conductive lines 132B and 134B and a corresponding one of the frontside conductive lines 132A and 134A. The through vias 200 and 202 may include a first through via 200 connecting the frontside word line 134A to the backside word line 134B, and may also include a second through via 202 connecting the frontside source line 132A to the backside source line 132B. The first through vias 200 may be spaced apart from each other in the second direction D2 between the frontside word line 134A and the backside word line 134B. Each first through-via 200 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to the front side word line 134A and the back side word line 134B. The second through-vias 202 may be spaced apart from each other in the second direction D2 between the front side source line 132A and the back side source line 132B. Each second through-via 202 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to the front side source line 132A and the back side source line 132B. The through-vias 200 and 202 may include a conductive material (e.g., a metal, such as, but not limited to, one or more of aluminum, copper, and tungsten).

[0071] The back word line 134B may be connected to the front word line 134A through the first through via 200, and the front word line 134A may be electrically connected to the gate structure GS (or gate electrode GE) through the corresponding first through via contact 122 and the gate contact 114. The front word line 134A, the back word line 134B, and the first through via 200 may constitute a row line such as a word line (see Figure 1 word line WL), or is included in the row line such as the word line (see Figure 1 word line WL).

[0072] The backside source line 132B may be connected to the frontside source line 132A through the second through via 202, and the frontside source line 132A may be electrically connected to the first source / drain pattern SD through the corresponding first via contact 122 and the first source / drain contact 112. The frontside source line 132A, the backside source line 132B, and the second through via 202 may constitute a source line (see Figure 1 source line SL) or is included in the source line (see Figure 1 The source line SL).

[0073] According to various example embodiments, the substrate 100 may be provided with a transistor including a gate structure GS, a channel pattern CH, and a source / drain pattern SD on its top surface 100U, and may be provided with a backside word line 134B and a backside source line 132B on its bottom surface 100L. The backside word line 134B and the backside source line 132B may be electrically connected to the frontside word line 134A and the frontside source line 132A through penetration vias 200 and 202, respectively. The word line connected to the gate terminal (such as the gate electrode GE) of the transistor may include the frontside word line 134A, the backside word line 134B, and the first penetration via 200. Since the word line includes the frontside word line 134A and the backside word line 134B connected in parallel to each other, the word line may be reduced in resistance, which may improve electrical performance. Alternatively or additionally, a source line connected to a source terminal of the transistor (e.g., a first source / drain pattern SD) may include a front source line 132A, a back source line 132B, and a second through via 202. Since the source line includes the front source line 132A and the back source line 132B connected in parallel to each other, the source line may be reduced in resistance, which may improve electrical performance.

[0074] Therefore, a semiconductor device having improved electrical characteristics such as speed and / or power consumption and / or reliability can be provided.

[0075] FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C Diagrams showing a method of manufacturing a semiconductor device according to some example embodiments are shown. Figure 5A and Fig. 6A Shown along Figure 2 A cross-sectional view taken along line AA'. Figure 5B and Figure 6B Shown along Figure 2 A cross-sectional view taken along line BB'. Figure 5C and Figure 6C Shown along Figure 2 For the sake of simplicity, reference will be omitted. Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A and Figure 4B Descriptions are repeated of those discussed for the semiconductor device.

[0076] Reference Figure 2 and FIG. 5A to FIG. 5C , a trench T may be formed (e.g., etched) at an upper portion of the substrate 100, and the trench T may define an active area AR and an active pattern AP. The trench T may be formed by patterning an upper portion of the substrate 100. The active area AR may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. The active pattern AP may be formed to protrude upward (e.g., in the third direction D3) from the active area AR. The active pattern AP may extend in the first direction D1 and may be spaced apart from each other in the second direction D2.

[0077] A device isolation layer 102 may be formed to fill the trench T. The device isolation layer 102 may be recessed to expose an upper portion of each active pattern AP. In some example embodiments, the device isolation layer 102 may be formed with a shallow trench isolation (STI) process; example embodiments are not limited thereto. A sacrificial gate structure may be formed to extend across the active pattern AP. The sacrificial gate structure may include a sacrificial gate pattern extending across the active pattern AP and a gate spacer GSP on a side surface of the sacrificial gate pattern. A source / drain pattern SD may be formed on the active pattern AP on opposite sides of the sacrificial gate structure. The formation of the source / drain pattern SD may include, for example, recessing portions of each active pattern AP on opposite sides of the sacrificial gate structure and performing a homogeneous and / or heteroepitaxial growth process on the recessed portion of each active pattern AP. In some example embodiments, the source / drain pattern SD may be doped, for example, by an ion implantation process and / or an in-situ doping process. The upper portion of each active pattern AP between the source / drain patterns SD may be referred to as a channel pattern CH.

[0078] The lower portion of the first interlayer dielectric layer 110 may be formed to cover the sacrificial gate structure and the source / drain pattern SD, and the gate structure GS may be formed in the lower portion of the first interlayer dielectric layer 110. The formation of the gate structure GS may include, for example, removing the sacrificial gate pattern to form an empty space exposing the channel pattern CH between the gate spacers GSP and forming the gate dielectric pattern GI, the gate electrode GE, and the gate capping pattern CAP in the empty space. The gate structure GS may include a gate electrode GE extending across the active pattern AP, a gate dielectric pattern GI between the gate electrode GE and the channel pattern CH, a gate spacer GSP on the side surface of the gate electrode GE, and a gate capping pattern CAP on the top surface of the gate electrode GE. The gate electrode GE may be formed to overlap vertically with the channel pattern CH. The gate electrode GE may cover the top surface CH_U of the channel pattern CH, and may cover the side surfaces of the channel pattern CH opposite to each other in the second direction D2. The source / drain pattern SD may be disposed on opposite sides of the gate structure GS. Thereafter, an upper portion of the first interlayer dielectric layer 110 may be formed to cover the gate structure GS.

[0079] A source / drain contact 112 and a gate contact 114 may be formed in the first interlayer dielectric layer 110. The source / drain contact 112 may penetrate the first interlayer dielectric layer 110 to be connected to the source / drain pattern SD, and the gate contact 114 may penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP to be connected to the gate electrode GE. The formation of the source / drain contact 112 and the gate contact 114 may, for example, include: forming a source / drain contact hole to penetrate the first interlayer dielectric layer 110 and expose the source / drain pattern SD; forming a gate contact hole to penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP and expose the gate electrode GE; forming a conductive layer to fill the source / drain contact hole and the gate contact hole; and planarizing the conductive layer until the top surface of the first interlayer dielectric layer 110 is exposed. The planarization process may be performed with an etch-back process and / or a chemical mechanical polishing (CMP) process; example embodiments are not limited thereto.

[0080] The second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110, for example, by a CVD process, and first via contacts 122 may be formed in the second interlayer dielectric layer 120. Each first via contact 122 may be formed to be connected to a corresponding one of the source / drain contacts 112 and the gate contact 114. The formation of the first via contacts 122 may include, for example, forming a first via hole to penetrate the second interlayer dielectric layer 120 and forming a conductive layer to fill the first via hole.

[0081] Front side conductive lines 132A and 134A and a first conductive line 136 may be formed on the second interlayer dielectric layer 120. The formation of the front side conductive lines 132A and 134A and the first conductive line 136 may include, for example, forming a conductive layer on the second interlayer dielectric layer 120 and patterning the conductive layer. Forming the conductive layer may include, for example, one or more of a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process; example embodiments are not limited thereto. The front side conductive lines 132A and 134A may include a front side source line 132A and a front side word line 134A. The front side source line 132A may be connected to a first source / drain contact 112 of the source / drain contacts 112 through a corresponding one of the first via contacts 122, and may be electrically connected to a first source / drain pattern SD of the source / drain patterns SD through the first source / drain contact 112. The front word line 134A may be connected to the gate contact 114 through a corresponding one of the first via contacts 122, and may be electrically connected to the gate structure GS (or the gate electrode GE) through the gate contact 114. The first conductive line 136 may be connected to a second one of the source / drain contacts 112 through a corresponding one of the first via contacts 122, and may be electrically connected to a second one of the source / drain patterns SD through the second source / drain contact 112.

[0082] The third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120 (e.g., by a CVD process), and may cover the front-side conductive lines 132A and 134A and the first conductive line 136. A lower electrode contact 138 may be formed in the third interlayer dielectric layer 130. The lower electrode contact 138 may be formed to penetrate an upper portion of the third interlayer dielectric layer 130 and be connected to the first conductive line 136. The formation of the lower electrode contact 138 may include, for example, forming a lower electrode contact hole to penetrate an upper portion of the third interlayer dielectric layer 130 and expose the first conductive line 136, and forming a conductive layer to fill the lower electrode contact hole.

[0083] The data storage pattern DS may be formed on the third interlayer dielectric layer 130. Figure 4A and Figure 4BAs discussed, the data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the third interlayer dielectric layer 130. The formation of the data storage pattern DS may, for example, include: sequentially forming a lower electrode layer and a magnetic tunnel junction layer on the third interlayer dielectric layer 130; forming a conductive mask pattern on the magnetic tunnel junction layer; and sequentially etching the magnetic tunnel junction layer and the lower electrode layer using the conductive mask pattern as an etching mask. The magnetic tunnel junction layer may include a first magnetic layer, a tunnel barrier layer, and a second magnetic layer sequentially stacked on the lower electrode layer. The magnetic tunnel junction layer and the lower electrode layer may be formed by, for example, one or more of a sputtering process, a chemical vapor deposition process, and an atomic layer deposition process.

[0084] The magnetic tunnel junction layer and the lower electrode layer may be etched to form a magnetic tunnel junction pattern MTJ and a bottom electrode BE, respectively. The etching of the magnetic tunnel junction layer may include etching the second magnetic layer, the tunnel barrier layer, and the first magnetic layer in sequence using a conductive mask pattern as an etching mask. The second magnetic layer, the tunnel barrier layer, and the first magnetic layer may be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBP, and a first magnetic pattern MP1, respectively. After the magnetic tunnel junction layer and the lower electrode layer are etched, the conductive mask pattern may remain on the magnetic tunnel junction pattern MTJ, and the retained portion of the conductive mask pattern may be defined as a top electrode TE. An ion beam etching process using an ion beam may be used to perform an etching process for etching the magnetic tunnel junction layer and the lower electrode layer. The ion beam may include inert ions, such as but not limited to inert gas ions.

[0085] The fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130 (e.g., by a CVD process) and may surround the data storage pattern DS. The first unit conductive line 152 may be formed on the fourth interlayer dielectric layer 140. The fifth interlayer dielectric layer 150 may be formed on the fourth interlayer dielectric layer 140 and may cover the first unit conductive line 152. The second via contact 156 may be formed in the fifth interlayer dielectric layer 150 and on the first unit conductive line 152. The second unit conductive line 154 may be formed on the fifth interlayer dielectric layer 150. The second unit conductive line 154 may overlap the first unit conductive line 152 vertically (e.g., in the third direction D3). The first unit conductive line 152 and the second unit conductive line 154 may extend parallel to each other along the first direction D1. The first unit conductive line 152 and the second unit conductive line 154 may be electrically connected to each other through the second via contact 156.

[0086] Reference Figure 2 and FIG. 6A to FIG. 6C, in some example embodiments, the front side may have a passivation layer and / or a protective layer formed thereon, and the substrate 100 may be flipped or rotated. In some example embodiments, the lower dielectric layer 210 may be formed on the bottom surface 100L of the substrate 100. The through via holes 200H and 202H may be formed to penetrate the lower dielectric layer 210 and the substrate 100. The through via holes 200H and 202H may be formed to extend in the third direction D3 and penetrate the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120. The through via holes 200H and 202H may include a first through via hole 200H exposing the bottom surface of the front side word line 134A and a second through via hole 202H exposing the bottom surface of the front side source line 132A.

[0087] Return to reference Figure 2 and FIG. 3A to FIG. 3C , through vias 200 and 202 may be formed in the through via holes 200H and 202H. The formation of the through vias 200 and 202 may, for example, include forming a conductive layer on the bottom surface 100L of the substrate 100 to fill the through via holes 200H and 202H and planarizing the conductive layer until the lower dielectric layer 210 is exposed. The through vias 200 and 202 may include first through vias 200 spaced apart in the second direction D2 along the bottom surface of the front word line 134A and second through vias 202 spaced apart from each other in the second direction D2 along the bottom surface of the front source line 132A.

[0088] The rear conductive lines 132B and 134B may be formed on the bottom surface 100L of the substrate 100, and the lower dielectric layer 210 may be interposed between the bottom surface 100L of the substrate 100 and the rear conductive lines 132B and 134B. The rear conductive lines 132B and 134B may include a rear source line 132B and a rear word line 134B. The rear source line 132B may overlap vertically (e.g., in the third direction D3) with the front source line 132A, and the rear word line 134B may overlap vertically (e.g., in the third direction D3) with the front word line 134A. The rear word line 134B may be connected to the first through-via 200, and may be electrically connected to the front word line 134A through the first through-via 200. The rear source line 132B may be connected to the second through-via 202, and may be electrically connected to the front source line 132A through the second through-via 202. The formation of the backside conductive lines 132B and 134B may include, for example, forming a backside conductive layer on the lower dielectric layer 210 and patterning the conductive layer.

[0089] Figure 7 A plan view showing a semiconductor device according to some example embodiments is shown. Fig. 8A and Figure 8B Shown along Figure 7A cross-sectional view taken along the lines BB' and CC'. Figure 7 The cross-sectional view taken along the line A-A' can be compared with Figure 3A The cross-sectional view is basically the same. For the sake of simplicity, the following will mainly discuss Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0090] Reference Figure 7 , Fig. 8A and Figure 8B , the first through via 200 may connect the front word line 134A to the back word line 134B, and may be spaced apart from each other in the second direction D2 between the front word line 134A and the back word line 134B. Each first through via 200 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, and may connect the front word line 134A to the back word line 134B. According to some example embodiments, each first through via 200 may be connected to a side surface of the gate contact 114. For example, a side surface of each first through via 200 may contact a side surface of the gate contact 114. The gate contact 114 may not be connected to the first through via contact 122. In this case, the front word line 134A and the back word line 134B may be electrically connected to the gate structure GS (or the gate electrode GE) through the first through via 200 and the gate contact 114.

[0091] The second through via 202 may connect the front source line 132A to the back source line 132B, and may be spaced apart from each other in the second direction D2 between the front source line 132A and the back source line 132B. Each second through via 202 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may connect the front source line 132A to the back source line 132B. According to some example embodiments, each second through via 202 may be connected to a side surface of the first source / drain contact 112. For example, a side surface of each second through via 202 may be in contact with a side surface of the first source / drain contact 112. The first source / drain contact 112 may not be connected to the first via contact 122. In this case, the front side source line 132A and the back side source line 132B may be electrically connected to the first source / drain pattern SD through the second through via 202 and the first source / drain contact 112 .

[0092] Fig. 9 A plan view showing a semiconductor device according to some example embodiments is shown. Fig.10 Shown along Fig. 9 A cross-sectional view taken along the line C-C'. Fig. 9 The cross-sectional views taken along the lines A-A' and BB' can be respectively Figure 3A and Figure 3B The cross-sectional view is basically the same. For the sake of simplicity, the following will mainly discuss Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0093] Reference Fig. 9 and Fig.10 The front-side source lines 132A may be connected to the first source / drain contacts 112 through the corresponding first via contacts 122 , and may be electrically connected to the first source / drain patterns SD through the first source / drain contacts 112 .

[0094] The second through via 202 may penetrate the lower dielectric layer 210 and the substrate 100, and may be connected to the backside source line 132B. According to some example embodiments, each second through via 202 may penetrate the lower dielectric layer 210, the corresponding active region AR, and the corresponding active pattern AP, and may be connected to the first source / drain pattern SD. The backside source line 132B may be electrically connected to the first source / drain pattern SD through the second through via 202.

[0095] The first source / drain pattern SD may be interposed between the second through via 202 and the first source / drain contact 112. The second through via 202 may be connected to a lower portion of the first source / drain pattern SD, and the first source / drain contact 112 may be connected to an upper portion of the first source / drain pattern SD.

[0096] Fig.11 A plan view showing a semiconductor device according to some example embodiments is shown. Fig. 12A , Fig. 12B and Fig. 12C Shown along Fig.11 For the sake of simplicity, the following will mainly discuss the cross-sectional view taken along the lines A-A', B-B' and CC'. Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0097] Reference Fig.11 and FIG. 12A to FIG. 12C, the first source / drain contact 112 may penetrate the first interlayer dielectric layer 110 to be connected to the first source / drain pattern SD. The first source / drain contact 112 may be disposed on one side of the gate structure GS and may have a strip shape extending in the second direction D2. The gate contact 114 may penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP and may be connected to the gate electrode GE. The first source / drain contact 112 and the gate contact 114 may have a top surface substantially coplanar with a top surface of the first interlayer dielectric layer 110. The first source / drain contact 112 and the gate contact 114 may include the same conductive material.

[0098] The second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110 , and may cover top surfaces of the first source / drain contacts 112 and the gate contacts 114 .

[0099] The first via contacts 122 may be disposed in the second interlayer dielectric layer 120. Each of the first via contacts 122 may penetrate the second interlayer dielectric layer 120 to be connected to a corresponding one of the first source / drain contacts 112 and the gate contact 114.

[0100] The front side conductive lines 132A and 134A may be disposed on the second interlayer dielectric layer 120. The front side conductive lines 132A and 134A may include a front side source line 132A and a front side word line 134A. The front side source line 132A may be connected to the first source / drain contact 112 through a corresponding one of the first via contacts 122, and may be electrically connected to the first source / drain pattern SD through the first source / drain contact 112. The front side word line 134A may be connected to the gate contact 114 through a corresponding one of the first via contacts 122, and may be electrically connected to the gate structure GS (or gate electrode GE) through the gate contact 114.

[0101] The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120 , and may cover the front-side conductive lines 132A and 134A.

[0102] According to some example embodiments, the backside conductive lines 132B and 134B and the first conductive line 136 may be disposed on the bottom surface 100L of the substrate 100. The lower dielectric layer 210 may be interposed between the bottom surface 100L of the substrate 100 and the backside conductive lines 132B and 134B and between the bottom surface 100L of the substrate 100 and the first conductive line 136. The backside conductive lines 132B and 134B and the first conductive line 136 may include the same conductive material, such as metal. The backside conductive lines 132B and 134B may include a backside source line 132B and a backside word line 134B.

[0103] The second source / drain contact 112 may be provided to penetrate at least a portion of the substrate 100. The second source / drain contact 112 may penetrate the lower dielectric layer 210 and the substrate 100 and may be connected to the second source / drain pattern SD. The second source / drain contact 112 may be connected to the first conductive line 136. The first conductive line 136 may be electrically connected to the second source / drain pattern SD through the second source / drain contact 112.

[0104] The first lower interlayer dielectric layer 230 may be disposed on the lower dielectric layer 210 and the bottom surface 100L of the substrate 100, and may cover the backside conductive lines 132B and 134B and the first conductive line 136. The first lower interlayer dielectric layer 230 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0105] The data storage pattern DS may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100. The lower electrode contact 138 may be disposed in the first lower interlayer dielectric layer 230 and may be interposed between the data storage pattern DS and the first conductive line 136. The lower electrode contact 138 may penetrate the lower portion of the first lower interlayer dielectric layer 230 to be connected to the first conductive line 136 and the data storage pattern DS. The lower electrode contact 138 may be connected to the bottom electrode BE of the data storage pattern DS. The data storage pattern DS may be electrically connected to the first conductive line 136 through the lower electrode contact 138. The data storage pattern DS may be electrically connected to the second source / drain pattern SD through the lower electrode contact 138, the first conductive line 136, and the second source / drain contact 112.

[0106] The second lower interlayer dielectric layer 240 may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100 and may surround the data storage pattern DS. The second lower interlayer dielectric layer 240 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0107] The first unit conductive line 152 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100. The first unit conductive line 152 may be electrically connected to the data storage pattern DS, and may be connected to the top electrode TE of the data storage pattern DS.

[0108] The third lower interlayer dielectric layer 250 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100, and may cover the first unit conductive line 152. The third lower interlayer dielectric layer 250 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0109] The second unit conductive line 154 may be disposed on the third lower interlayer dielectric layer 250 and the bottom surface 100L of the substrate 100. The second via contact 156 may be disposed in the third lower interlayer dielectric layer 250 and may be interposed between the first unit conductive line 152 and the second unit conductive line 154. The first unit conductive line 152 and the second unit conductive line 154 may be electrically connected to each other through the second via contact 156.

[0110] According to various example embodiments, the substrate 100 may be provided on a bottom surface 100L thereof with a first conductive line 136, a lower electrode contact 138, a data storage pattern DS, a first unit conductive line 152 and a second unit conductive line 154, and a second via contact 156. The second source / drain contact 112 may penetrate the lower dielectric layer 210 and the substrate 100 and may be connected to the first conductive line 136 and the second source / drain pattern SD.

[0111] Fig.13A , Fig. 13B and Fig. 13C Shown along Fig.11 The cross-sectional views taken along the lines A-A', B-B' and CC' show methods of manufacturing semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C Discuss the differences in methods of manufacturing semiconductor devices.

[0112] Reference Fig.11 and FIG. 13A to FIG. 13C , a first source / drain contact 112 and a gate contact 114 may be formed in the first interlayer dielectric layer 110. The first source / drain contact 112 may penetrate the first interlayer dielectric layer 110 to be connected to the first source / drain pattern SD, and the gate contact 114 may penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP to be connected to the gate electrode GE. The first source / drain contact 112 and the gate contact 114 may be connected to the first source / drain pattern SD by contacting the first interlayer dielectric layer 110. FIG. 5A to FIG. 5C The methods discussed for forming the source / drain contacts 112 and the gate contact 114 are formed by substantially the same methods.

[0113] The second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110, and first via contacts 122 may be formed in the second interlayer dielectric layer 120. Each first via contact 122 may be formed to be connected to a corresponding one of the first source / drain contact 112 and the gate contact 114.

[0114] The front side conductive lines 132A and 134A may be formed on the second interlayer dielectric layer 120. The front side conductive lines 132A and 134A may be formed by contacting the reference FIG. 5A to FIG. 5CThe front conductive lines 132A and 134A may include a front source line 132A and a front word line 134A. The front source line 132A may be connected to the first source / drain contact 112 through a corresponding one of the first via contacts 122, and may be electrically connected to the first source / drain pattern SD through the first source / drain contact 112. The front word line 134A may be connected to the gate contact 114 through a corresponding one of the first via contacts 122, and may be electrically connected to the gate structure GS (or gate electrode GE) through the gate contact 114.

[0115] The third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120 , and may cover the front-side conductive lines 132A and 134A.

[0116] The lower dielectric layer 210 may be formed on the bottom surface 100L of the substrate 100. The through via holes 200H and 202H and the second source / drain contact hole 112H may be formed to penetrate the lower dielectric layer 210 and the substrate 100. The second source / drain contact hole 112H may be formed to penetrate the lower dielectric layer 210 and the substrate 100 and expose the bottom surface of the second source / drain pattern SD.

[0117] Return to reference Fig.11 and FIG. 12A to FIG. 12C , the through vias 200 and 202 may be formed in the through via holes 200H and 202H, respectively, and the second source / drain contact 112 may be formed in the second source / drain contact hole 112H. The formation of the through vias 200 and 202 and the second source / drain contact 112 may, for example, include: forming a conductive layer on the bottom surface 100L of the substrate 100 to fill the through via holes 200H and 202H and the second source / drain contact hole 112H; and planarizing the conductive layer until the lower dielectric layer 210 is exposed.

[0118] Backside conductive lines 132B and 134B and first conductive line 136 may be formed on lower dielectric layer 210 and bottom surface 100L of substrate 100. Formation of backside conductive lines 132B and 134B and first conductive line 136 may include, for example, forming a backside conductive layer on lower dielectric layer 210 and patterning the backside conductive layer.

[0119] The first lower interlayer dielectric layer 230 may be formed on the lower dielectric layer 210 and the bottom surface 100L of the substrate 100 , thereby covering the backside conductive lines 132B and 134B and the first conductive lines 136 .

[0120] The data storage pattern DS may be formed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100. The data storage pattern DS may be formed by contacting the reference FIG. 5A to FIG. 5CThe second lower interlayer dielectric layer 240 may be formed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100 to surround the data storage pattern DS.

[0121] The first unit conductive line 152 may be formed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100. The third lower interlayer dielectric layer 250 may be formed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100 to cover the first unit conductive line 152.

[0122] The second unit conductive line 154 may be formed on the third lower interlayer dielectric layer 250 and the bottom surface 100L of the substrate 100. The second via contact 156 may be formed in the third lower interlayer dielectric layer 250 so as to be interposed between the first unit conductive line 152 and the second unit conductive line 154. The first unit conductive line 152 and the second unit conductive line 154 may be electrically connected to each other through the second via contact 156.

[0123] Fig.14 A plan view showing a semiconductor device according to some example embodiments is shown. Fig.15A , Fig. 15B and Fig. 15C Shown along Fig.14 For the sake of simplicity, the following will mainly discuss the cross-sectional view taken along the lines A-A', B-B' and CC'. Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0124] Reference Fig.14 and FIG. 15A to FIG. 15C , the first via contacts 122 may be disposed in the second interlayer dielectric layer 120. Each of the first via contacts 122 may penetrate the second interlayer dielectric layer 120 to be connected to the second source / drain contact 112. According to some example embodiments, the first via contact 122 may not be provided on any one of the first source / drain contact 112 and the gate contact 114, and may not be connected to any one of the first source / drain contact 112 and the gate contact 114.

[0125] According to some example embodiments, the front-side conductive lines 132A and 134A may be omitted. The first conductive line 136 may be disposed on the second interlayer dielectric layer 120. The first conductive line 136 may be connected to the second source / drain contact 112 through a corresponding one of the first via contacts 122, and may be electrically connected to the second source / drain pattern SD through the second source / drain contact 112. The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120, and may cover the first conductive line 136.

[0126] According to some example embodiments, the first rear conductive lines 132B1 and 134B1 may be disposed on the bottom surface 100L of the substrate 100, and the lower dielectric layer 210 may be interposed between the bottom surface 100L of the substrate 100 and the first rear conductive lines 132B1 and 134B1. The first rear conductive lines 132B1 and 134B1 may include a first rear source line 132B1 and a first rear word line 134B1. The first rear source line 132B1 and the first rear word line 134B1 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1.

[0127] Through vias 200 and 202 may be provided to penetrate at least a portion of the substrate 100. Each of the through vias 200 and 202 may penetrate the lower dielectric layer 210, the substrate 100, the device isolation layer 102, and the first interlayer dielectric layer 110, and may be connected to a corresponding one of the first rear side conductive lines 132B1 and 134B1. The through vias 200 and 202 may include a first through via 200 connected to the first rear side word line 134B1 and a second through via 202 connected to the first rear side source line 132B1.

[0128] Each first through via 200 may be connected to a side surface of the gate contact 114. For example, a side surface of each first through via 200 may be in contact with a side surface of the gate contact 114. The gate contact 114 may not be connected to the first via contact 122. In this case, the first backside word line 134B1 may be electrically connected to the gate structure GS (or the gate electrode GE) through the first through via 200 and the gate contact 114.

[0129] Each second through via 202 may be connected to a side surface of the first source / drain contact 112. For example, a side surface of each second through via 202 may be in contact with a side surface of the first source / drain contact 112. The first source / drain contact 112 may not be connected to the first via contact 122. In this case, the first backside source line 132B1 may be electrically connected to the first source / drain pattern SD through the second through via 202 and the first source / drain contact 112.

[0130] According to some example embodiments, a first lower interlayer dielectric layer 230 may be disposed on the lower dielectric layer 210 and the bottom surface 100L of the substrate 100 and may cover the first backside conductive lines 132B1 and 134B1. The first lower interlayer dielectric layer 230 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0131] The second rear conductive lines 132B2 and 134B2 may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100. The second rear conductive lines 132B2 and 134B2 may include a second rear source line 132B2 and a second rear word line 134B2. The second rear source line 132B2 and the second rear word line 134B2 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The second rear source line 132B2 may overlap the first rear source line 132B1 vertically (e.g., in the third direction D3), and the second rear word line 134B2 may overlap the first rear word line 134B1 vertically (e.g., in the third direction D3).

[0132] The first backside contact 132C may be disposed in the first lower interlayer dielectric layer 230 and may be located between the first backside source line 132B1 and the second backside source line 132B2. The first backside contact 132C may be spaced apart from each other in the second direction D2 between the first backside source line 132B1 and the second backside source line 132B2. The first backside source line 132B1 and the second backside source line 132B2 may be connected to each other through the first backside contact 132C and may be electrically connected to the first source / drain pattern SD through the second through via 202 and the first source / drain contact 112. According to some example embodiments, the first backside source line 132B1, the second backside source line 132B2, and the first backside contact 132C may constitute a source line (see Figure 1 source line SL).

[0133] The second backside contact 134C may be disposed in the first lower interlayer dielectric layer 230 and may be located between the first backside word line 134B1 and the second backside word line 134B2. The second backside contact 134C may be spaced apart from each other in the second direction D2 between the first backside word line 134B1 and the second backside word line 134B2. The first backside word line 134B1 and the second backside word line 134B2 may be connected to each other through the second backside contact 134C and may be electrically connected to the gate structure GS (or gate electrode GE) through the first through via 200 and the gate contact 114. According to some example embodiments, the first backside word line 134B1, the second backside word line 134B2, and the second backside contact 134C may constitute a word line (see Figure 1 word line WL).

[0134] According to various example embodiments, the substrate 100 may be provided with a transistor including a gate structure GS, a channel pattern CH, and a source / drain pattern SD on its top surface 100U. A word line connected to the gate terminal (or gate electrode GE) of the transistor may include a first backside word line 134B1, a second backside word line 134B2, and a second backside contact 134C disposed on the bottom surface 100L of the substrate 100. Since the word line includes the first backside word line 134B1 and the second backside word line 134B2 connected in parallel to each other, the word line may be reduced in resistance. In addition, a source line connected to the source terminal (e.g., the first source / drain pattern SD) of the transistor may include a first backside source line 132B1, a second backside source line 132B2, and a first backside contact 132C disposed on the bottom surface 100L of the substrate 100. Since the source line includes the first backside source line 132B1 and the second backside source line 132B2 connected in parallel to each other, the source line can be reduced in resistance. Therefore, a semiconductor device with improved electrical characteristics can be provided.

[0135] Fig.16 A plan view showing a semiconductor device according to some example embodiments is shown. Fig.17A , Fig. 17B and Fig. 17C Shown along Fig.16 For the sake of simplicity, the following will mainly discuss the cross-sectional view taken along the lines A-A', B-B' and CC'. Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0136] Reference Fig.16 and 17A to 17C , the first source / drain contact 112 may penetrate the first interlayer dielectric layer 110 to be connected to the first source / drain pattern SD. The first source / drain contact 112 may be disposed on one side of the gate structure GS and may have a strip shape extending in the second direction D2. The gate contact 114 may penetrate the first interlayer dielectric layer 110 and the gate capping pattern CAP and may be connected to the gate electrode GE. The first source / drain contact 112 and the gate contact 114 may have a top surface substantially coplanar with a top surface of the first interlayer dielectric layer 110. The first source / drain contact 112 and the gate contact 114 may include the same conductive material.

[0137] The second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110 , and may cover top surfaces of the first source / drain contacts 112 and the gate contacts 114 .

[0138] The first via contacts 122 may be disposed in the second interlayer dielectric layer 120. Each of the first via contacts 122 may penetrate the second interlayer dielectric layer 120 to be connected to a corresponding one of the first source / drain contacts 112 and the gate contact 114.

[0139] The first front side conductive lines 132A1 and 134A1 may be disposed on the second interlayer dielectric layer 120. The first front side conductive lines 132A1 and 134A1 may include a first front side source line 132A1 and a first front side word line 134A1. The first front side source line 132A1 and the first front side word line 134A1 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The first front side source line 132A1 may be connected to the first source / drain contact 112 through a corresponding one of the first via contacts 122, and may be electrically connected to the first source / drain pattern SD through the first source / drain contact 112. The first front side word line 134A1 may be connected to the gate contact 114 through a corresponding one of the first via contacts 122, and may be electrically connected to the gate structure GS (or the gate electrode GE) through the gate contact 114.

[0140] The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120 , and may cover the first front-side conductive lines 132A1 and 134A1 .

[0141] The second front conductive lines 132A2 and 134A2 may be disposed on the third interlayer dielectric layer 130. The second front conductive lines 132A2 and 134A2 may include a second front source line 132A2 and a second front word line 134A2. The second front source line 132A2 and the second front word line 134A2 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The second front source line 132A2 may overlap the first front source line 132A1 vertically (e.g., in the third direction D3), and the second front word line 134A2 may overlap the first front word line 134A1 vertically (e.g., in the third direction D3).

[0142] The first front side contact 132D may be disposed in the third interlayer dielectric layer 130 and may be located between the first front side source line 132A1 and the second front side source line 132A2. The first front side contact 132D may be spaced apart from each other in the second direction D2 between the first front side source line 132A1 and the second front side source line 132A2. The first front side source line 132A1 and the second front side source line 132A2 may be connected to each other through the first front side contact 132D and may be electrically connected to the first source / drain pattern SD through the corresponding first via contact 122 and the first source / drain contact 112. According to some example embodiments, the first front side source line 132A1, the second front side source line 132A2, and the first front side contact 132D may constitute a source line (see Figure 1 source line SL).

[0143] The second front side contact 134D may be disposed in the third interlayer dielectric layer 130 and may be located between the first front side word line 134A1 and the second front side word line 134A2. The second front side contact 134D may be spaced apart from each other in the second direction D2 between the first front side word line 134A1 and the second front side word line 134A2. The first front side word line 134A1 and the second front side word line 134A2 may be connected to each other through the second front side contact 134D and may be electrically connected to the gate structure GS (or the gate electrode GE) through the corresponding first via contact 122 and the gate contact 114. According to some example embodiments, the first front side word line 134A1, the second front side word line 134A2, and the second front side contact 134D may constitute a word line (see Figure 1 word line WL).

[0144] According to some example embodiments, the first conductive line 136 may be disposed on the bottom surface 100L of the substrate 100. The lower dielectric layer 210 may be interposed between the first conductive line 136 and the bottom surface 100L of the substrate 100. The second source / drain contact 112 may be provided to penetrate at least a portion of the substrate 100. The second source / drain contact 112 may penetrate the lower dielectric layer 210 and the substrate 100, and may be connected to the second source / drain pattern SD. The second source / drain contact 112 may be connected to the first conductive line 136. The first conductive line 136 may be electrically connected to the second source / drain pattern SD through the second source / drain contact 112.

[0145] The first lower interlayer dielectric layer 230 may be disposed on the lower dielectric layer 210 and the bottom surface 100L of the substrate 100, and may cover the first conductive line 136. According to some example embodiments, the backside conductive lines 132B and 134B may be omitted. The first lower interlayer dielectric layer 230 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0146] The data storage pattern DS may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100. The lower electrode contact 138 may be disposed in the first lower interlayer dielectric layer 230 and may be interposed between the data storage pattern DS and the first conductive line 136. The lower electrode contact 138 may penetrate the first lower interlayer dielectric layer 230 to be connected to the first conductive line 136 and the data storage pattern DS. The lower electrode contact 138 may be connected to the bottom electrode BE of the data storage pattern DS. The data storage pattern DS may be electrically connected to the first conductive line 136 through the lower electrode contact 138. The data storage pattern DS may be electrically connected to the second source / drain pattern SD through the lower electrode contact 138, the first conductive line 136, and the second source / drain contact 112.

[0147] The second lower interlayer dielectric layer 240 may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100 and may surround the data storage pattern DS. The second lower interlayer dielectric layer 240 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0148] The first unit conductive line 152 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100. The first unit conductive line 152 may be electrically connected to the data storage pattern DS, and may be connected to the top electrode TE of the data storage pattern DS.

[0149] The third lower interlayer dielectric layer 250 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100, and may cover the first unit conductive line 152. The third lower interlayer dielectric layer 250 may include, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0150] The second unit conductive line 154 may be disposed on the third lower interlayer dielectric layer 250 and the bottom surface 100L of the substrate 100. The second via contact 156 may be disposed in the third lower interlayer dielectric layer 250 and may be interposed between the first unit conductive line 152 and the second unit conductive line 154. The first unit conductive line 152 and the second unit conductive line 154 may be electrically connected to each other through the second via contact 156.

[0151] According to various example embodiments, the substrate 100 may be provided with a transistor including a gate structure GS, a channel pattern CH, and a source / drain pattern SD on a top surface 100U thereof, and a data storage pattern DS may be disposed on a bottom surface 100L of the substrate 100. The semiconductor device may easily have an advantage of high integration.

[0152] Alternatively or additionally, the word line connected to the gate terminal (or gate electrode GE) of the transistor may include a first front side word line 134A1, a second front side word line 134A2, and a second front side contact 134D disposed on the top surface 100U of the substrate 100. Since the word line includes the first front side word line 134A1 and the second front side word line 134A2 connected in parallel to each other, the word line can be reduced in resistance. In addition, the source line connected to the source terminal (or the first source / drain pattern SD) of the transistor may include a first front side source line 132A1, a second front side source line 132A2, and a first front side contact 132D disposed on the top surface 100U of the substrate 100. Since the source line includes the first front side source line 132A1 and the second front side source line 132A2 connected in parallel to each other, the source line can be reduced in resistance. Therefore, a semiconductor device with improved electrical characteristics can be provided.

[0153] Fig.18A , Fig.18B and Fig. 18C Shown along Figure 2 The cross-sectional views taken along the lines A-A', B-B' and CC' show semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss Figure 2 , FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The differences in semiconductor devices discussed.

[0154] Reference Figure 2 and 18A to 18C , a first buried dielectric layer 105 may be provided in the lower substrate 100A, and the backside conductive lines 132B and 134B may be provided on the first buried dielectric layer 105. The first buried dielectric layer 105 is provided therein with a second buried dielectric layer 107 covering the backside conductive lines 132B and 134B. The upper substrate 100B may be provided on the second buried dielectric layer 107.

[0155] The lower substrate 100A may be or may include one or more of a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon germanium substrate). The first buried dielectric layer 105 and the second buried dielectric layer 107 may include at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The upper substrate 100B may be connected to the reference substrate 100B. Figure 2 and FIG. 3A to FIG. 3C The substrates 100 discussed are substantially the same. The first buried dielectric layer 105 and the second buried dielectric layer 107 may be referred to as buried dielectric layers. The backside conductive lines 132B and 134B may be buried in the buried dielectric layers 105 and 107 between the lower substrate 100A and the upper substrate 100B.

[0156] Each of the through vias 200 and 202 may penetrate an upper portion of the second buried dielectric layer 107, the upper substrate 100B, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to a corresponding one of the backside conductive lines 132B and 134B and a corresponding one of the frontside conductive lines 132A and 134A.

[0157] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference FIG. 3A to FIG. 3C , Figure 4A and Figure 4B The semiconductor devices discussed are essentially the same.

[0158] Fig.19A , Fig.19B and Fig.19C Shown along Figure 2 The cross-sectional views taken along the lines A-A', B-B' and CC' show methods of manufacturing semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C Discuss the differences in methods of manufacturing semiconductor devices.

[0159] Reference Figure 2 and FIG. 19A to FIG. 19C , a first buried dielectric layer 105 may be formed on the lower substrate 100A, and backside conductive lines 132B and 134B may be formed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be formed on the first buried dielectric layer 105 to cover the backside conductive lines 132B and 134B. An upper substrate 100B may be formed on the second buried dielectric layer 107. The formation of the upper substrate 100B may include, for example, depositing one of a silicon layer, a germanium layer, and a silicon germanium layer on the second buried dielectric layer 107.

[0160] A trench T may be formed at an upper portion of the upper substrate 100B to define an active region AR and an active pattern AP. A device isolation layer 102 may be formed to fill the trench T and may be recessed to expose an upper portion of each active pattern AP. A sacrificial gate structure may be formed to extend across the active pattern AP. The sacrificial gate structure may include a sacrificial gate pattern extending across the active pattern AP, and may further include a gate spacer GSP on a side surface of the sacrificial gate pattern. Source / drain patterns SD may be formed on the active pattern AP on opposite sides of the sacrificial gate structure.

[0161] The lower portion of the first interlayer dielectric layer 110 may be formed to cover the sacrificial gate structure and the source / drain pattern SD, and the gate structure GS may be formed in the lower portion of the first interlayer dielectric layer 110. The formation of the gate structure GS may, for example, include: removing the sacrificial gate pattern to form an empty space exposing the channel pattern CH between the gate spacers GSP; and forming the gate dielectric pattern GI, the gate electrode GE, and the gate capping pattern CAP in the empty space. The gate structure GS may include the gate electrode GE extending across the active pattern AP, the gate dielectric pattern GI between the gate electrode GE and the channel pattern CH, the gate spacer GSP on the side surface of the gate electrode GE, and the gate capping pattern CAP on the top surface of the gate electrode GE. The upper portion of the first interlayer dielectric layer 110 may be formed to cover the gate structure GS.

[0162] Source / drain contacts 112 and gate contacts 114 may be formed in the first interlayer dielectric layer 110 . A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110 , and a first via contact 122 may be formed in the second interlayer dielectric layer 120 .

[0163] According to some example embodiments, the through via holes 200H and 202H may be formed to penetrate the second interlayer dielectric layer 120, the first interlayer dielectric layer 110, the device isolation layer 102, and the upper substrate 100B, and penetrate a portion of the second buried dielectric layer 107 to expose the top surface of the backside conductive lines 132B and 134B. The through via holes 200H and 202H may include a first through via hole 200H exposing the top surface of the backside word line 134B among the backside conductive lines 132B and 134B, and may also include a second through via hole 202H exposing the top surface of the backside source line 132B among the backside conductive lines 132B and 134B.

[0164] Return to reference Figure 2 and 18A to 18C , the through vias 200 and 202 may be formed in the through via holes 200H and 202H, respectively. The formation of the through vias 200 and 202 may include, for example, forming a conductive layer on the second interlayer dielectric layer 120 to fill the through via holes 200H and 202H and planarizing the conductive layer until the second interlayer dielectric layer 120 is exposed. The through vias 200 and 202 may include first through vias 200 spaced apart from each other in the second direction D2 along the top surface of the rear side word line 134B, and may also include second through vias 202 spaced apart from each other in the second direction D2 along the top surface of the rear side source line 132B.

[0165] Afterwards, front conductive lines 132A and 134A and first conductive lines 136 may be formed on the second interlayer dielectric layer 120. The front conductive lines 132A and 134A may include a front source line 132A and a front word line 134A. The rear source line 132B may overlap the front source line 132A vertically (e.g., in the third direction D3), and the rear word line 134B may overlap the front word line 134A vertically (e.g., in the third direction D3). The rear word line 134B may be connected to the first through-via 200 and may be electrically connected to the front word line 134A through the first through-via 200. The rear source line 132B may be connected to the second through-via 202 and may be electrically connected to the front source line 132A through the second through-via 202.

[0166] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C The semiconductor devices discussed are essentially the same.

[0167] Fig. 20A and Fig. 20B Shown along Figure 7 The cross-sectional views taken along the lines BB' and CC' of FIG. 1 and FIG. 2 show semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss Figure 7 , Fig. 8A and Figure 8B The differences in semiconductor devices discussed.

[0168] Reference Figure 7 , Fig. 20A and Fig. 20B , a first buried dielectric layer 105 may be disposed on the lower substrate 100A, and the backside conductive lines 132B and 134B may be disposed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be disposed on the first buried dielectric layer 105 and may cover the backside conductive lines 132B and 134B. An upper substrate 100B may be disposed on the second buried dielectric layer 107. The upper substrate 100B may be connected to the reference substrate 100A. Figure 2 and FIG. 3A to FIG. 3C The substrates 100 discussed are substantially the same. The first buried dielectric layer 105 and the second buried dielectric layer 107 may be referred to as buried dielectric layers. The backside conductive lines 132B and 134B may be buried in the buried dielectric layers 105 and 107 between the lower substrate 100A and the upper substrate 100B.

[0169] Each of the through vias 200 and 202 may penetrate an upper portion of the second buried dielectric layer 107, the upper substrate 100B, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to a corresponding one of the backside conductive lines 132B and 134B and a corresponding one of the frontside conductive lines 132A and 134A.

[0170] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference Figure 7 , Fig. 8A and Figure 8B The semiconductor devices discussed are essentially the same.

[0171] Fig.21 Shown along Fig. 9 The cross-sectional view taken along the line CC' of FIG. 1 shows a semiconductor device according to some example embodiments. For the sake of simplicity of description, the following mainly describes Fig. 9 and Fig.10 The differences in semiconductor devices discussed.

[0172] Reference Fig. 9 and Fig.21 , a first buried dielectric layer 105 may be disposed on the lower substrate 100A, and the backside conductive lines 132B and 134B may be disposed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be disposed on the first buried dielectric layer 105 and may cover the backside conductive lines 132B and 134B. An upper substrate 100B may be disposed on the second buried dielectric layer 107. The upper substrate 100B may be connected to the reference substrate 100A. Figure 2 and FIG. 3A to FIG. 3C The substrates 100 discussed are substantially the same. The first buried dielectric layer 105 and the second buried dielectric layer 107 may be referred to as buried dielectric layers. The backside conductive lines 132B and 134B may be buried in the buried dielectric layers 105 and 107 between the lower substrate 100A and the upper substrate 100B.

[0173] The second through via 202 may penetrate the upper substrate 100B, and may also penetrate a portion of the second buried dielectric layer 107 to be connected to the backside source line 132B. Each second through via 202 may penetrate a portion of the second buried dielectric layer 107, a corresponding active region AR, and a corresponding active pattern AP, and may be connected to the first source / drain pattern SD. The backside source line 132B may be electrically connected to the first source / drain pattern SD through the second through via 202.

[0174] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference Fig. 9 and Fig.10 The semiconductor devices discussed are essentially the same.

[0175] Fig. 22 Shown along Fig. 9 The cross-sectional view taken along the line CC' of FIG. 1 shows a method for manufacturing a semiconductor device according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C Discuss the differences in methods of manufacturing semiconductor devices.

[0176] Reference Fig. 9 and Fig. 22 , a first buried dielectric layer 105 may be formed on the lower substrate 100A, and the backside conductive lines 132B and 134B may be formed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be formed on the first buried dielectric layer 105, thereby covering the backside conductive lines 132B and 134B. An upper substrate 100B may be formed on the second buried dielectric layer 107. The formation of the upper substrate 100B may include, for example, depositing one of a silicon layer, a germanium layer, and a silicon germanium layer on the second buried dielectric layer 107.

[0177] A trench T may be formed at an upper portion of the upper substrate 100B to define an active region AR and an active pattern AP. A device isolation layer 102 may be formed to fill the trench T and may be recessed to expose an upper portion of each active pattern AP. A sacrificial gate structure may be formed to extend across the active pattern AP. Portions of each active pattern AP on opposite sides of the sacrificial gate structure may be recessed.

[0178] The second through via holes 202H may be formed to penetrate the upper substrate 100B and also penetrate a portion of the second buried dielectric layer 107 to expose the top surface of the backside source line 132B. On one side of the sacrificial gate structure, each second through via hole 202H may penetrate a portion of the second buried dielectric layer 107, a corresponding active region AR, and a corresponding active pattern AP, and may expose the top surface of the backside source line 132B.

[0179] Return to reference Fig. 9 and Fig.21 , a second through via 202 may be formed to fill the second through via hole 202H. Thereafter, source / drain patterns SD may be formed on the active pattern AP at opposite sides of the sacrificial gate structure. Each second through via 202 may be connected to a first source / drain pattern SD among the source / drain patterns SD. The backside source line 132B may be electrically connected to the first source / drain pattern SD through the second through via 202.

[0180] In addition to the above, the method of manufacturing a semiconductor device according to various example embodiments may be the same as that described with reference to FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6CThe methods of manufacturing semiconductor devices discussed are basically the same.

[0181] Fig.23A , Fig. 23B and Fig.23C Shown along Fig.11 The cross-sectional views taken along the lines A-A', B-B' and CC' show semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss Fig.11 and FIG. 12A to FIG. 12C The differences in semiconductor devices discussed.

[0182] Reference Fig.11 and FIG. 23A to FIG. 23C , a first buried dielectric layer 105 may be disposed on the lower substrate 100A, and the backside conductive lines 132B and 134B and the first conductive line 136 may be disposed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be disposed on the first buried dielectric layer 105 and may cover the backside conductive lines 132B and 134B and the first conductive line 136. An upper substrate 100B may be disposed on the second buried dielectric layer 107. The upper substrate 100B may be connected to the reference substrate 100A. Figure 2 and FIG. 3A to FIG. 3C The substrate 100 discussed is substantially the same. The first buried dielectric layer 105 and the second buried dielectric layer 107 may be referred to or referred to as buried dielectric layers. The backside conductive lines 132B and 134B and the first conductive line 136 may be buried in the buried dielectric layers 105 and 107 between the lower substrate 100A and the upper substrate 100B.

[0183] Each of the through vias 200 and 202 may penetrate an upper portion of the second buried dielectric layer 107, the upper substrate 100B, the device isolation layer 102, the first interlayer dielectric layer 110, and the second interlayer dielectric layer 120, and may be connected to a corresponding one of the backside conductive lines 132B and 134B and a corresponding one of the frontside conductive lines 132A and 134A.

[0184] A second source / drain contact 112 of the source / drain contacts 112 may penetrate the upper substrate 100B and the upper portion of the second buried dielectric layer 107 and may be connected to a second source / drain pattern SD of the source / drain patterns SD. The second source / drain contact 112 may be connected to the first conductive line 136. The first conductive line 136 may be electrically connected to the second source / drain pattern SD through the second source / drain contact 112.

[0185] The lower dielectric layer 210 may be disposed on the bottom surface 100AL of the lower substrate 100A. The data storage pattern DS may be disposed on the lower dielectric layer 210 and the bottom surface 100AL of the lower substrate 100A. The lower electrode contact 138 may penetrate the first buried dielectric layer 105, the lower substrate 100A, and the lower dielectric layer 210, and may be connected to the first conductive line 136 and the data storage pattern DS. The data storage pattern DS may be electrically connected to the first conductive line 136 through the lower electrode contact 138. The data storage pattern DS may be electrically connected to the second source / drain pattern SD through the lower electrode contact 138, the first conductive line 136, and the second source / drain contact 112.

[0186] The second lower interlayer dielectric layer 240 may be disposed on the lower dielectric layer 210 and the bottom surface 100AL of the lower substrate 100A and may surround the data storage pattern DS. The first unit conductive line 152 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100AL of the lower substrate 100A. The first unit conductive line 152 may be connected to the data storage pattern DS.

[0187] The third lower interlayer dielectric layer 250 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100AL of the lower substrate 100A, and may cover the first unit conductive line 152. The second unit conductive line 154 may be disposed on the third lower interlayer dielectric layer 250 and the bottom surface 100AL of the lower substrate 100A. The second via contact 156 may be disposed in the third lower interlayer dielectric layer 250, and may be interposed between the first unit conductive line 152 and the second unit conductive line 154.

[0188] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference Fig.11 and FIG. 12A to FIG. 12C The semiconductor devices discussed are essentially the same.

[0189] Fig.24A , Fig. 24B and Fig.24C Shown along Fig.14 The cross-sectional views taken along the lines A-A', B-B' and CC' show semiconductor devices according to some example embodiments. For the sake of simplicity of description, the following will mainly discuss Fig.14 and FIG. 15A to FIG. 15C The differences in semiconductor devices discussed.

[0190] Reference Fig.14 and FIG. 24A to FIG. 24C, a first buried dielectric layer 105 may be disposed on the lower substrate 100A, and first rear-side conductive lines 132B1 and 134B1 and second rear-side conductive lines 132B2 and 134B2 may be disposed on the first buried dielectric layer 105. A second buried dielectric layer 107 may be disposed on the first buried dielectric layer 105 and may cover the first rear-side conductive lines 132B1 and 134B1 and the second rear-side conductive lines 132B2 and 134B2. The upper substrate 100B may be disposed on the second buried dielectric layer 107. The first buried dielectric layer 105 and the second buried dielectric layer 107 may be referred to as buried dielectric layers. The first rear-side conductive lines 132B1 and 134B1 and the second rear-side conductive lines 132B2 and 134B2 may be buried in the buried dielectric layers 105 and 107 between the lower substrate 100A and the upper substrate 100B.

[0191] Each of the through vias 200 and 202 may penetrate an upper portion of the second buried dielectric layer 107 , the upper substrate 100B, the device isolation layer 102 , the first interlayer dielectric layer 110 , and the second interlayer dielectric layer 120 , and may be connected to a corresponding one of the first backside conductive lines 132B1 and 134B1 .

[0192] The first backside contact 132C may be disposed in the buried dielectric layers 105 and 107 and may be interposed between the first backside source line 132B1 of the first backside conductive lines 132B1 and 134B1 and the second backside source line 132B2 of the second backside conductive lines 132B2 and 134B2. The first backside source line 132B1 and the second backside source line 132B2 may be connected to each other through the first backside contact 132C.

[0193] The second backside contact 134C may be disposed in the buried dielectric layers 105 and 107 and may be interposed between a first backside word line 134B1 of the first backside conductive lines 132B1 and 134B1 and a second backside word line 134B2 of the second backside conductive lines 132B2 and 134B2. The first backside word line 134B1 and the second backside word line 134B2 may be connected to each other through the second backside contact 134C.

[0194] In addition to the above, the semiconductor device according to various example embodiments may be used in conjunction with the reference Fig.14 and FIG. 15A to FIG. 15C The semiconductor devices discussed are essentially the same.

[0195] Fig.25 A simplified plan view showing a semiconductor device according to some example embodiments is shown. Fig.26 Shown in Fig.25 A cross-sectional view of a component on a first area and a second area.

[0196] Reference Fig.25 and Fig.26 , the substrate 100 may include a first region R1 and a second region R2. The first region R1 of the substrate 100 may be Figure 2 and FIG. 3A to FIG. 3C The semiconductor device discussed is configured substantially the same, and the second region R2 of the substrate 100 may be the same as that of the reference Fig.11 and FIG. 12A to FIG. 12C The semiconductor devices discussed are configured substantially the same.

[0197] According to some example embodiments, the data storage pattern DS on the first region R1 may be disposed on the third interlayer dielectric layer 130. The fourth interlayer dielectric layer 140 may surround the data storage pattern DS on the first region R1 and may extend onto the third interlayer dielectric layer 130 on the second region R2. The first unit conductive line 152 on the first region R1 may be disposed on the fourth interlayer dielectric layer 140. The fifth interlayer dielectric layer 150 may cover the first unit conductive line 152 on the first region R1 and may extend onto the fourth interlayer dielectric layer 140 on the second region R2. The second unit conductive line 154 on the first region R1 may be disposed on the fifth interlayer dielectric layer 150. The second via contact 156 on the first region R1 may be disposed in the fifth interlayer dielectric layer 150 and may be interposed between the first unit conductive line 152 and the second unit conductive line 154.

[0198] The backside conductive lines 132B and 134B on the first region R1 may be disposed on the bottom surface 100L of the substrate 100, and the lower dielectric layer 210 may be interposed between the bottom surface 100L of the substrate 100 and the backside conductive lines 132B and 134B. The backside conductive lines 132B and 134B and the first conductive line 136 on the second region R2 may be disposed on the bottom surface 100L of the substrate 100, and the lower dielectric layer 210 may extend between the bottom surface 100L of the substrate 100 and the backside conductive lines 132B and 134B and between the bottom surface 100L of the substrate 100 and the first conductive line 136.

[0199] The first lower interlayer dielectric layer 230 may cover the backside conductive lines 132B and 134B on the first region R1 , and may also cover the first conductive lines 136 and the backside conductive lines 132B and 134B on the second region R2 .

[0200] The data storage pattern DS on the second region R2 may be disposed on the first lower interlayer dielectric layer 230 and the bottom surface 100L of the substrate 100. The lower electrode contact 138 on the second region R2 may be disposed in the first lower interlayer dielectric layer 230 and may be interposed between the data storage pattern DS and the first conductive line 136.

[0201] The second lower interlayer dielectric layer 240 may surround the data storage pattern DS on the second region R2 and may extend onto the first lower interlayer dielectric layer 230 on the first region R1. The first unit conductive line 152 on the second region R2 may be disposed on the second lower interlayer dielectric layer 240 and the bottom surface 100L of the substrate 100. The third lower interlayer dielectric layer 250 may cover the first unit conductive line 152 on the second region R2 and may extend onto the second lower interlayer dielectric layer 240 on the first region R1. The second unit conductive line 154 on the second region R2 may be disposed on the third lower interlayer dielectric layer 250 and the bottom surface 100L of the substrate 100. The second via contact 156 on the second region R2 may be disposed in the third lower interlayer dielectric layer 250 and may be interposed between the first unit conductive line 152 and the second unit conductive line 154.

[0202] The data storage pattern DS on the first region R1 and the data storage pattern DS on the second region R2 may each be configured as a reference Figure 4A and Figure 4B The data storage patterns DS discussed are substantially the same. The data storage pattern DS on the first region R1 may include a first magnetic tunnel junction pattern, and the data storage pattern DS on the second region R2 may include a second magnetic tunnel junction pattern. The first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may have different storage characteristics from each other. For example, the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may have different switching characteristics, for example, the critical current density required for the magnetization reversal of the first magnetic tunnel junction pattern may be different from the critical current density required for the magnetization reversal of the second magnetic tunnel junction pattern. In this case, the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may have different switching speeds or different retention characteristics. Optionally, the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may have different endurances. According to some example embodiments, one of the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may be used as a memory storage unit (e.g., a non-volatile memory (NVM) unit), and the other of the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may be used as a cache storage unit (e.g., a random access memory (RAM) unit).

[0203] For example, the critical current density required for magnetization reversal of the first magnetic tunnel junction pattern may be less than the critical current density required for magnetization reversal of the second magnetic tunnel junction pattern. In this case, the first magnetic tunnel junction pattern may be more easily switched than the second magnetic tunnel junction pattern, and the second magnetic tunnel junction pattern may have a greater retention characteristic than the retention characteristic of the first magnetic tunnel junction pattern. Therefore, the data storage pattern DS including the first magnetic tunnel junction pattern on the first region R1 may be used as a cache memory cell (e.g., a random access memory (RAM) cell), and the data storage pattern DS including the second magnetic tunnel junction pattern on the second region R2 may be used as a memory storage cell (e.g., a non-volatile memory (NVM) cell).

[0204] According to various example embodiments, the transistor may be disposed on the top surface of the substrate, and at least one rear conductive line may be disposed on the bottom surface of the substrate. When the word line connected to the gate terminal (or gate electrode) of the transistor includes at least one rear conductive line and one of the front conductive line and the additional rear conductive line connected in parallel thereto, the word line may be reduced in resistance. When the source line connected to the source terminal (or first source / drain pattern) of the transistor includes at least one rear conductive line and one of the front conductive line and the additional rear conductive line connected in parallel thereto, the source line may be reduced in resistance. Therefore, a semiconductor device with improved electrical characteristics may be provided.

[0205] Alternatively or additionally, a data storage pattern connected to the drain terminal (or second source / drain pattern) of the transistor may be disposed on the top or bottom surface of the substrate. The data storage pattern may include a magnetic tunnel junction pattern. Therefore, magnetic tunnel junction patterns with different switching characteristics may be easily disposed on the top or bottom surface of the substrate. Therefore, a semiconductor device including a magnetic tunnel junction pattern with different switching characteristics may be provided.

[0206] The above description provides some example embodiments for explaining the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and it will be understood by those of ordinary skill in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the inventive concept. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

[0207] This application claims the priority of Korean Patent Application No. 10-2023-0117952 filed on September 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a substrate having a top surface and a bottom surface opposite to each other; a gate structure on the top surface of the substrate; a plurality of source / drain patterns on the top surface of the substrate and on opposite sides of the gate structure; a backside conductive line on the bottom surface of the substrate and electrically connected to the gate structure and at least one of a first source / drain pattern of the plurality of source / drain patterns; as well as A magnetic tunnel junction pattern is electrically connected to a second source / drain pattern among the plurality of source / drain patterns.

2. The semiconductor device according to claim 1, further comprising: a front-side conductive line on the top surface of the substrate and electrically connected to at least one of the first source / drain pattern and the gate structure, wherein the front-side conductive line is at a height from the top surface of the substrate that is higher than a height of the gate structure and a height of the source / drain pattern.

3. The semiconductor device according to claim 2, further comprising: a through-hole penetrating at least a portion of the substrate, The front conductive line and the rear conductive line are connected to each other through the through via.

4. The semiconductor device according to claim 3, further comprising: a gate contact, on said gate structure, A front word line among the front conductive lines and a rear word line among the rear conductive lines are electrically connected to the gate structure through the through via and the gate contact.

5. The semiconductor device according to claim 3, further comprising: a first source / drain contact on the first source / drain pattern, A front source line among the front conductive lines and a rear source line among the rear conductive lines are electrically connected to the first source / drain pattern through the through via and the first source / drain contact.

6. The semiconductor device according to claim 2, further comprising: a first source / drain contact between the first source / drain pattern and the front-side conductive line; and a through via penetrating at least a portion of the substrate and interposed between the first source / drain pattern and the rear conductive line, wherein A front side source line among the front side conductive lines is electrically connected to the first source / drain pattern through the first source / drain contact, and A rear-side source line among the rear-side conductive lines is electrically connected to the first source / drain pattern through the through via.

7. The semiconductor device according to claim 1, further comprising: a through via penetrating at least a portion of the substrate and connected to the rear-side conductive line, The backside conductive line is electrically connected to at least one of the first source / drain pattern and the gate structure through the through via.

8. The semiconductor device according to claim 7, further comprising: a first source / drain contact on the first source / drain pattern; and a gate contact, on said gate structure, wherein the through via is connected to at least one of a side surface of the first source / drain contact and a side surface of the gate contact.

9. The semiconductor device according to claim 7, further comprising: an additional rear-side conductive line on the bottom surface of the substrate, the rear-side conductive line being between the additional rear-side conductive line and the bottom surface of the substrate; as well as a plurality of backside contacts between the backside conductive lines and the additional backside conductive lines, The backside conductive lines and the additional backside conductive lines are connected to each other through the plurality of backside contacts.

10. The semiconductor device according to claim 1, further comprising: lower base plate; and a buried dielectric layer between the lower substrate and the bottom surface of the substrate, The backside conductive lines are buried in the buried dielectric layer.

11. A semiconductor device comprising: a substrate having a top surface and a bottom surface opposite to each other; a gate structure on the top surface of the substrate; a plurality of source / drain patterns on the top surface of the substrate and on opposite sides of the gate structure; a front-side conductive line on the top surface of the substrate and electrically connected to the gate structure and at least one of a first source / drain pattern of the plurality of source / drain patterns; a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the first source / drain pattern and the gate structure; as well as A through via penetrates at least a portion of the substrate and is connected to the rear-side conductive line and the front-side conductive line.

12. The semiconductor device according to claim 11, further comprising: a gate contact, on said gate structure, A front word line among the front conductive lines and a rear word line among the rear conductive lines are electrically connected to the gate structure through the through via and the gate contact. 13 . The semiconductor device according to claim 12 , wherein the through via is in contact with a side surface of the gate contact.

14. The semiconductor device according to claim 12, further comprising: a first source / drain contact on the first source / drain pattern, A front source line among the front conductive lines and a rear source line among the rear conductive lines are electrically connected to the first source / drain pattern through the through via and the first source / drain contact. 15 . The semiconductor device according to claim 14 , wherein the through via is in contact with a side surface of the first source / drain contact.

16. The semiconductor device according to claim 11, further comprising: A data storage pattern is on the top surface of the substrate and is electrically connected to a second source / drain pattern among the plurality of source / drain patterns.

17. The semiconductor device according to claim 11, further comprising: A data storage pattern is on the bottom surface of the substrate and is electrically connected to a second source / drain pattern among the plurality of source / drain patterns.

18. A semiconductor device comprising: a substrate having a top surface and a bottom surface opposite to each other, the substrate including a first region and a second region horizontally spaced apart from each other; a first transistor on the top surface of the first region of the substrate; a first magnetic tunnel junction pattern on the top surface of the first region of the substrate and electrically connected to a first drain terminal of the first transistor; a first backside conductive line on the bottom surface of the first region of the substrate and electrically connected to at least one of a first source terminal and a first gate terminal of the first transistor; a second transistor on the top surface of the second region of the substrate; as well as A second magnetic tunnel junction pattern is on the bottom surface of the second region of the substrate and is electrically connected to a second drain terminal of the second transistor.

19. The semiconductor device according to claim 18, further comprising: A first front-side conductive line is on the top surface of the first region of the substrate and is electrically connected to at least one of the first source terminal and the first gate terminal of the first transistor.

20. The semiconductor device according to claim 19, further comprising: A second front-side conductive line is on the top surface of the second region of the substrate and is electrically connected to at least one of a second source terminal and a second gate terminal of the second transistor.

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