Preparation method for improving mobility of indium gallium zinc oxide thin film transistor

Abstract

The present application relates to display panel technical field, especially in a kind of for promoting indium gallium zinc oxide thin film transistor mobility preparation method, comprising: forming gate metal film on target substrate, and patterning is carried out, to obtain back gate;Metal oxide is generated on back gate, and the metal oxide on target transistor gate is etched using inductive coupling plasma, to form gate oxide layer;Indium gallium zinc oxide is grown as active layer on gate oxide layer;Source-drain metal film is evaporated on active layer, and patterning is carried out, to obtain drain-source metal;The channel region of indium gallium zinc oxide is defined by photoetching, and channel region is isolated;Yttrium metal is grown on drain-source metal using magnetron sputtering process, and yttrium metal is annealed at preset temperature, to obtain cover layer, to prepare target transistor.Therefore, it solves the existing promotion IGZO mobility method to influence transistor original performance, and not applicable to display field and after process etc.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel, and particularly relates to a preparation method for improving mobility of an indium gallium zinc oxide thin film transistor. BACKGROUND

[0002] A thin film transistor (TFT) is a kind of field effect transistor, and a basic manufacturing method is to deposit various thin films such as a semiconductor active layer, a dielectric layer and a metal electrode layer on a substrate. According to different materials of the TFT active layer, the TFT technology is mainly divided into the following four types: hydrogenated amorphous silicon (a-Si:H) TFT, low-temperature polysilicon (LTPS) TFT, amorphous metal oxide TFT and organic semiconductor TFT. Among them, the metal oxide TFT represented by indium gallium zinc oxide (IGZO) is widely favored due to its advantages such as high uniformity in a large area and low-temperature preparation process.

[0003] IGZO is a kind of transparent oxide semiconductor, which is composed of indium (In), gallium (Ga), zinc (Zn) and oxygen (O). It has become a hot spot in research and industry in recent years due to its various excellent electrical and optical properties. At present, IGZO is mainly applied in the field of display technology: the mobility of IGZO is much higher than that of traditional a-Si, so that the pixel refresh speed is faster, so that higher screen refresh rate can be realized; its low leakage characteristic makes the screen can still keep the pixel state without current refresh, thereby greatly reducing the power consumption. In addition to the field of display technology, IGZO also shows great potential in new storage technology, such as the new memory 2T0C DRAM structure, which uses the low leakage characteristic of IGZO to reduce the process complexity and improve the retention time.

[0004] The mobility of IGZO is an important topic of common concern in the scientific research and industrial fields in recent years. For display technology, high mobility can bring higher refresh rate, resolution and color saturation, which is beneficial to produce high-end screens; for storage technology, high mobility can bring lower power consumption, faster speed, and can broaden its application.

[0005] Currently, the main means to improve the mobility of IGZO are: (1) adjusting the proportion of each component in IGZO, but this method needs to make a trade-off between mobility and stability, and it is difficult to greatly improve the mobility under the premise of meeting the normal performance of the transistor; (2) post-processing method: the mobility of IGZO is improved by annealing and other post-processing methods, but the performance of the device will degrade in the subsequent process; (3) forming crystals: the temperature for forming crystals is relatively high (> 600℃), which is not suitable for the display field and the subsequent process, and the use range is relatively limited, and after the transition from amorphous state to polycrystalline state, the mobility may even decrease due to the influence of the grain boundary. SUMMARY

[0006] The present application provides a preparation method for improving the mobility of indium gallium zinc oxide thin film transistor, to solve the problems that the existing methods for improving the mobility of IGZO are not suitable for the display field and the subsequent process, it is difficult to greatly improve the mobility under the premise of meeting the normal performance of the transistor, and the performance of the device will degrade in the subsequent process.

[0007] The first aspect of the present application provides a preparation method for improving the mobility of indium gallium zinc oxide thin film transistor, comprising the following steps: forming a gate metal thin film on a target substrate, and patterning the gate metal thin film to obtain a patterned gate metal as a back gate of a target transistor; generating a metal oxide on the back gate, and etching the metal oxide on the gate of the target transistor by using inductive coupled plasma to form a gate oxide layer of the target transistor; growing indium gallium zinc oxide on the gate oxide layer with a gate metal to use the indium gallium zinc oxide as an active layer of the target transistor; evaporating a source-drain metal thin film on the active layer, and patterning the source-drain metal thin film to obtain a patterned source-drain metal as a drain-source metal of the target transistor; defining a channel region of the indium gallium zinc oxide by photolithography, and etching the indium gallium zinc oxide outside the channel region by wet etching or dry etching to isolate the channel region; growing yttrium metal on the drain-source metal by using a magnetron sputtering process, and performing annealing treatment on the yttrium metal at a preset temperature to obtain a cover layer of the target transistor.

[0008] Optionally, the step of forming a gate metal thin film on a target substrate, and patterning the gate metal thin film to obtain a patterned gate metal as a back gate of a target transistor comprises:

[0009] evaporating a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and a gate oxide, or a gate metal, an adhesion layer and an adhesion layer of a gate and a gate oxide on the target substrate by photolithography and electron beam to form the gate metal thin film;

[0010] peeling off the gate metal thin film to form the patterned gate metal and taking the patterned gate metal as a back gate of a target transistor; or

[0011] generating a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of gate and gate oxide, or a gate metal, an adhesion layer and an adhesion layer of gate and gate oxide on the target substrate to form the gate metal thin film;

[0012] performing photolithography and etching on the gate metal thin film to form the patterned gate metal and taking the patterned gate metal as a back gate of a target transistor.

[0013] Optionally, the gate metal adopts any one of palladium, molybdenum, titanium nitride and platinum.

[0014] Optionally, the generating a metal oxide on the back gate comprises:

[0015] generating the metal oxide on the back gate by an atomic layer deposition method, a plasma enhanced chemical vapor deposition method or a plasma enhanced atomic layer deposition method, wherein the metal oxide adopts at least one of hafnium dioxide and aluminum oxide.

[0016] Optionally, the growing the indium gallium zinc oxide on the gate oxide layer with the gate metal by an atomic layer deposition method to take the indium gallium zinc oxide as an active layer of the target transistor; or

[0017] the growing the indium gallium zinc oxide on the gate oxide layer with the gate metal by a plasma enhanced atomic layer deposition method and a sputtering method to take the indium gallium zinc oxide as an active layer of the target transistor.

[0018] Optionally, evaporating source-drain metal and protective metal on the active layer by photolithography and electron beam to form the source-drain metal thin film;

[0019] peeling off the source-drain metal thin film to form the patterned source-drain metal and taking the patterned source-drain metal as the source-drain metal of the target transistor; or

[0020] generating evaporated source-drain metal and protective metal on the active layer to form the source-drain metal thin film;

[0021] performing photolithography and etching on the source-drain metal thin film to form the patterned source-drain metal and taking the patterned source-drain metal as the source-drain metal of the target transistor.

[0022] Optionally, the preset temperature is 100-250℃.

[0023] The second aspect embodiment of the present application provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the preparation method for improving mobility of indium gallium zinc oxide thin film transistor as described in the above embodiments.

[0024] The third aspect embodiment of the present application provides a computer program product, wherein the computer program / instruction is executed by the processor to implement the preparation method for improving mobility of indium gallium zinc oxide thin film transistor as described above.

[0025] The fourth aspect embodiment of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the program is executed by the processor to implement the preparation method for improving mobility of indium gallium zinc oxide thin film transistor as described above.

[0026] The preparation method for improving mobility of indium gallium zinc oxide thin film transistor provided by the embodiments of the present application first grows a layer of metal by physical vapor deposition (PVD) method (evaporation or sputtering), and then performs appropriate annealing, wherein the covered metal absorbs oxygen from the IGZO channel and injects electrons in the annealing process, thereby improving the carrier concentration in the channel and improving the effective mobility of the transistor. The method has low process complexity, can be prepared in a large area, can greatly improve the mobility of IGZO TFT at low temperature (<200 DEG C), maintains the original characteristics of the transistor, and is suitable for a wider application scenario.

[0027] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flowchart of a preparation method for improving mobility of indium gallium zinc oxide thin film transistor provided by the embodiments of the present application is shown in the figure;

[0030] Figure 2 A preparation flowchart for improving mobility of indium gallium zinc oxide thin film transistor provided by the embodiments of the present application is shown in the figure;

[0031] Figure 3 A back gate IGZO TFT structure diagram provided by the embodiments of the present application is shown in the figure;

[0032] Figure 4This is a schematic diagram comparing the transfer characteristics of the Baseline (device without a cover layer) and the IGZOTFT device with a Y-cover layer provided in the embodiments of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0034] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0035] The following describes a method for fabricating an indium gallium zinc oxide thin-film transistor to improve mobility, according to an embodiment of the present invention, with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic flowchart of a method for improving the mobility of indium gallium zinc oxide thin-film transistors provided in an embodiment of the present invention.

[0037] like Figure 1 As shown, the fabrication method for improving the mobility of indium gallium zinc oxide thin-film transistors includes the following steps:

[0038] In step S101, a gate metal thin film is formed on the target substrate, and the gate metal thin film is patterned to obtain a patterned gate metal as the back gate of the target transistor.

[0039] In some embodiments, a gate metal thin film is formed on a target substrate, and the gate metal thin film is patterned to obtain a patterned gate metal as the back gate of the target transistor, including:

[0040] A gate metal thin film is formed by evaporating gate metal, or gate metal and an adhesion layer, or gate metal and an adhesion layer of gate and gate oxide, or gate metal, an adhesion layer and an adhesion layer of gate and gate oxide on a target substrate using photolithography and electron beam.

[0041] The gate metal film is peeled off to form a patterned gate metal, which is then used as the back gate of the target transistor; or

[0042] A gate metal thin film is formed on a target substrate by forming a gate metal film, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of gate and gate oxide, or a gate metal, an adhesion layer and an adhesion layer of gate and gate oxide.

[0043] The gate metal film is photolithographically and etched to form a patterned gate metal, which is then used as the back gate of the target transistor.

[0044] like Figure 2 As shown, in the actual execution process, 15nm Pd / 10nm Ti / 1nm Ti films are deposited on the target substrate using photolithography and electron beam deposition to form a gate metal film. The gate metal film is then peeled off to form a patterned gate metal, which serves as the back gate of the target transistor. The 15nm Pd is the gate metal, which is mandatory and can be of other thicknesses; it can be made of materials other than Pd, such as Ti, Mo, TiN, Pt, etc. The 10nm Ti is the adhesion layer, which can be absent or of other thicknesses, and can be made of Ti or other adhesion layer materials such as TaN. The 1nm Ti is the adhesion layer between the gate and gate oxide, which can be absent or of other thicknesses, and can be made of Ti or other materials such as Al.

[0045] In addition to the photolithography-lift process mentioned above, the patterning of the gate metal thin film can also be achieved using a growth-etching process. That is, the gate metal embodied in the above material is first grown, then photolithography is performed, followed by etching (including plasma etching) to form a patterned gate metal as the back gate of the target transistor.

[0046] In step S102, a metal oxide is generated on the back gate, and the metal oxide on the gate of the target transistor is etched using inductively coupled plasma to form the gate oxide layer of the target transistor.

[0047] In some embodiments, forming a metal oxide on the back gate includes:

[0048] Metal oxides are generated on a back grid using atomic layer deposition, plasma-enhanced chemical vapor deposition, or plasma-enhanced atomic layer deposition, wherein the metal oxides are at least one of hafnium dioxide and aluminum oxide.

[0049] like Figure 2 As shown, in the actual execution process, 10nm HfO2 is grown using atomic layer deposition (ALD) as the gate oxide layer of the target transistor, and the HfO2 on the gate of the target transistor is etched away using inductively coupled plasma (ICP) etching to expose the gate metal for subsequent interconnection and form the gate oxide layer of the target transistor.

[0050] The metal oxide for the back gate can be 10nm HfO2, or other thicknesses, or other materials such as Al2O3, or combinations thereof, such as 10nm Al2O3 + 5nm HfO2. The growth method can be ALD, plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), etc.

[0051] In step S103, indium gallium zinc oxide is grown on the gate oxide layer with gate metal to use the indium gallium zinc oxide as the active layer of the target transistor.

[0052] In some embodiments, indium gallium zinc oxide is grown on a gate oxide layer with gate metal to serve as the active layer of the target transistor, including:

[0053] Indium gallium zinc oxide (IGZO) is grown on a gate oxide layer with gate metal using atomic layer deposition (ALD) to serve as the active layer of the target transistor; or

[0054] Indium gallium zinc oxide (IGZO) is grown on a gate oxide layer with gate metal using plasma-enhanced atomic layer deposition (PEALD) and sputtering methods, so that IGZO can be used as the active layer of the target transistor.

[0055] like Figure 2 As shown, in actual implementation, the ALD method can be used to grow a 10nm IGZO on the gate oxide layer with gate metal as the active layer of the target transistor; the PEALD method and sputtering technology can also be used to grow a 10nm IGZO on the gate oxide layer with gate metal, or other thicknesses can be used as the active layer of the target transistor.

[0056] It should be noted that, in addition to IGZO, other materials such as indium gallium zinc oxide (IGZO) or combinations of materials such as 5nm IGZO + 2nm InO + 5nm IGZO can also be used.

[0057] In step S104, a source / drain metal thin film is deposited on the active layer and patterned to obtain patterned source / drain metal as the drain / source metal of the target transistor.

[0058] In some embodiments, a source / drain metal thin film is deposited on the active layer, and the source / drain metal thin film is patterned to obtain patterned source / drain metal as the drain / source metal of the target transistor, including:

[0059] Source / drain metals and protective metals are deposited on the active layer by photolithography and electron beam to form a source / drain metal thin film;

[0060] The source / drain metal film is peeled off to form patterned source / drain metal, which is then used as the drain / source metal of the target transistor; or

[0061] Source / drain metals and protective metals are deposited on the active layer to form a source / drain metal thin film;

[0062] The source and drain metal films are photolithographically and etched to form patterned source and drain metals, which are then used as the source and drain metals of the target transistor.

[0063] In actual implementation, as shown in Figure 2 , 20nm Ti / 45nm Pd is evaporated on the active layer by means of photolithography and electron beam to form source-drain metal film, and then the source-drain metal film is patterned by lift-off to form the source and the drain of the target transistor. Among them, 20nm Ti is used as the source-drain contact metal of IGZO, and other thicknesses can be used, and the material can be replaced by Mo, TiN, ITO, etc. 45nm Pd is used as a protective metal, and other thicknesses can be used, and the material can be replaced by Pt, etc.

[0064] In addition, the patterning of the source-drain metal can also use the growth-etching process, that is, the source-drain metal represented by the above-mentioned material is first grown, then photolithography is performed, and then etching (including plasma etching, etc.) is used to form patterned source-drain metal as the source-drain metal of the target transistor.

[0065] In step S105, the channel region of indium gallium zinc oxide is defined by photolithography, and the indium gallium zinc oxide outside the channel region is etched by wet or dry etching to isolate the channel region.

[0066] In actual implementation, as shown in Figure 2 , the channel region of IGZO is defined by photolithography, and the IGZO outside the channel region is etched by wet or dry etching to achieve channel isolation.

[0067] In step S106, yttrium metal is grown on the source-drain metal by means of magnetron sputtering process, and the yttrium metal is annealed at a preset temperature to obtain the cover layer of the target transistor.

[0068] In some embodiments, the preset temperature is 100-250°C.

[0069] In actual implementation, as shown in Figure 2 and 3 , 2nm yttrium (Y) is grown by means of magnetron sputtering process, and then annealed at 200°C in air for 5min to obtain the cover layer of the target transistor, so as to prepare a back-gate field effect transistor stacked by metal layer / insulating layer / semiconductor layer in the vertical direction, that is, the target transistor.

[0070] It should be noted that, in addition to the magnetron sputtering process, other PVD methods such as evaporation can also be used, and 2nm Y can use other thicknesses, and the material can be replaced by Al, etc. The annealing condition can use other temperature and other time length, and the temperature can be lower than 200°C.

[0071] Further, as shown in Figure 4As shown, the embodiment of the present application performs a transfer characteristic test on the prepared target transistor, and it can be seen from the figure that the mobility of the IGZO TFT device with the Y covering layer is 7 times that of the device baseline without the covering layer.

[0072] In summary, according to the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor provided by the embodiment of the present application, a layer of metal is first grown by using a physical vapor deposition (PVD) method (evaporation or sputtering), and then proper annealing is performed, in which the covering metal absorbs oxygen from the IGZO channel and injects electrons, thereby improving the carrier concentration in the channel and improving the effective mobility of the transistor. The method not only has low process complexity, can be prepared in a large area, and can realize a large improvement in the mobility of the IGZO TFT at a low temperature (< 200 DEG C), but also maintains the original characteristics of the transistor and is suitable for a wider range of applications.

[0073] Figure 5 A structural schematic diagram of an electronic device provided by the embodiment of the present application is shown. The electronic device can include:

[0074] The memory 501, the processor 502, and a computer program stored in the memory 501 and executable on the processor 502.

[0075] The processor 502 implements the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor provided by the above-described embodiments when executing the program.

[0076] Further, the electronic device further includes:

[0077] The communication interface 503 is used for communication between the memory 501 and the processor 502.

[0078] The memory 501 is used for storing a computer program executable on the processor 502.

[0079] The memory 501 can include a high-speed RAM memory, and can also include a non-volatile memory, for example, at least one disk memory.

[0080] If the memory 501, the processor 502 and the communication interface 503 are implemented independently, the communication interface 503, the memory 501 and the processor 502 can be connected with each other through a bus and complete communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 5 Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0081] Optionally, in a specific implementation, if the memory 501, the processor 502 and the communication interface 503 are integrated on a chip, the memory 501, the processor 502 and the communication interface 503 can complete communication between each other through an internal interface.

[0082] The processor 502 can be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application.

[0083] The embodiment of the present application further provides a computer program product, and the computer program / instruction is executed by the processor to realize the preparation method for improving mobility of an indium gallium zinc oxide thin film transistor as above.

[0084] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the program is executed by the processor to realize the preparation method for improving mobility of an indium gallium zinc oxide thin film transistor as above.

[0085] In the description of the application, reference to "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. In addition, the usage of "first", "second" and the like does not indicate any order but rather serves merely to name various components. Moreover, the usage of "top", "bottom", and the like is made for the purpose of illustration only and does not indicate any orientation. The terms "coupled" and "connected", along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, particular features are described as being coupled or connected where the feature is in some way present, for example through shared use of one or more components, and can be communicatively, electrically, structurally, and / or mechanically connected, for example. Similarly, "coupled" or "connected" can be used to indicate that two or more members are either directly in contact or indirectly in contact through one or more intermediate members.

[0086] Furthermore, the terms "first", "second", and the like, merely denote different categories, and do not imply a relative importance or a specific order. Thus, features defined with "first", "second" and the like can include at least one of the features, either explicitly or implicitly. In the description of the application, the term "N" means at least two, for example two, three, etc., unless explicitly specified otherwise.

[0087] Any process or method descriptions or blocks in flow charts or otherwise described herein represent embodiments of modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps, and alternate implementations are possible. In some embodiments, the processes or methods described can be accomplished with one or more hardware items, for example, hardwired circuits, memory, logic circuits, look-up tables, microcode or the like, software programs, firmware programs, microcode routines, embedded logic, embedded software, or any combination thereof, which work together to cause a general purpose computer, a special purpose computer, or both, to perform the processes or methods described. The various embodiments further can interact with a user through one or more computer programs, software applications, firmware applications, operating systems, or the like, which interact with a user. Such software can be written in any of a variety of suitable programming languages and can be executed using a variety of suitable hardware and software configurations. It will be appreciated that computer programs, software applications, firmware applications, operating systems, or the like, can be written in any combination of one or more suitable programming languages, and that such software can be executed using one or more computing devices capable of netlist generation as described herein.

[0088] The logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be considered as a sequence of instructions to implement logic functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this specification, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a machine-readable storage device (e.g., magnetic, optical or other) a machine-readable storage diskette (e.g., floppy disk, optical disk, etc.), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), optical fibers, and a portable device (e.g., compact disk read-only memory (CDROM), digital versatile disk (DVD), etc.) that can be read by the instruction execution system, apparatus, or device. In addition, the computer-readable medium can even be paper or other suitable medium upon which the program is printed, as the program can be electronically captured, via optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in the computer memory.

[0089] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware and in another embodiment, any of the following technologies, known in the art, or their combinations can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0090] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiments can be completed by programs instructing related hardware, and the programs can be stored in a computer-readable storage medium. When the programs are executed, they include one or a combination of the steps of the method embodiments.

[0091] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for improving the mobility of indium gallium zinc oxide thin film transistors, comprising: The method comprises the following steps: ​ forming a gate metal film on a target substrate, and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor; generating metal oxide on the back gate, and etching the metal oxide on the gate of the target transistor by inductive coupling plasma to form a gate oxide layer of the target transistor; growing indium gallium zinc oxide on the gate oxide layer with the gate metal to take the indium gallium zinc oxide as an active layer of the target transistor; evaporating a source-drain metal film on the active layer, and patterning the source-drain metal film to obtain a patterned source-drain metal as a source-drain metal of the target transistor; defining a channel region of the indium gallium zinc oxide by photolithography, and etching the indium gallium zinc oxide outside the channel region by wet etching or dry etching to isolate the channel region; growing yttrium metal on the source-drain metal by a magnetron sputtering process, and annealing the yttrium metal at a preset temperature to obtain a cover layer of the target transistor.

2. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The step of forming a gate metal film on a target substrate, and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor comprises: evaporating gate metal, or gate metal and an adhesion layer, or gate metal and an adhesion layer of gate and gate oxide, or gate metal, an adhesion layer and an adhesion layer of gate and gate oxide on the target substrate by photolithography and electron beam to form the gate metal film; stripping the gate metal film to form the patterned gate metal, and taking the patterned gate metal as the back gate of the target transistor; or evaporating gate metal, or gate metal and an adhesion layer, or gate metal and an adhesion layer of gate and gate oxide, or gate metal, an adhesion layer and an adhesion layer of gate and gate oxide on the target substrate to form the gate metal film; photolithography and etching the gate metal film to form the patterned gate metal, and taking the patterned gate metal as the back gate of the target transistor.

3. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The gate metal adopts any one of palladium, molybdenum, titanium nitride and platinum.

4. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The step of generating metal oxide on the back gate comprises: generating the metal oxide on the back gate by an atomic layer deposition method, a plasma enhanced chemical vapor deposition method or a plasma enhanced atomic layer deposition method, wherein the metal oxide adopts at least one of hafnium dioxide and aluminum oxide.

5. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The step of growing indium gallium zinc oxide on the gate oxide layer with the gate metal to take the indium gallium zinc oxide as an active layer of the target transistor comprises: growing the indium gallium zinc oxide on the gate oxide layer with the gate metal by an atomic layer deposition method to take the indium gallium zinc oxide as the active layer of the target transistor; or growing the indium gallium zinc oxide on the gate oxide layer with the gate metal by a plasma enhanced atomic layer deposition method and a sputtering method to take the indium gallium zinc oxide as the active layer of the target transistor.

6. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The step of evaporating a source-drain metal film on the active layer, and patterning the source-drain metal film to obtain a patterned source-drain metal as a source-drain metal of the target transistor comprises: forming the source-drain metal thin film by evaporating source-drain metal and protective metal on the active layer through photolithography and electron beam; performing stripping on the source-drain metal thin film to form the patterned source-drain metal and taking the patterned source-drain metal as the source-drain metal of the target transistor; or forming the source-drain metal thin film by evaporating source-drain metal and protective metal on the active layer; performing photolithography and etching on the source-drain metal thin film to form the patterned source-drain metal and taking the patterned source-drain metal as the source-drain metal of the target transistor.

7. The method of claim 1, wherein the method is performed at a temperature of 200- 400 °C. The preset temperature is 100-250℃.

8. An electronic device, comprising: The application further provides a computer program product, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor according to any one of claims 1-6. The computer program / instruction is executed by the processor to implement the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor according to any one of claims 1-6.

9. A computer program product, characterised in that, The program is executed by the processor to implement the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor according to any one of claims 1-6.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, ​

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