A gallium nitride-based device and a method for preparing the same

Abstract

The present invention provides a gallium nitride-based device and a preparation method thereof, belonging to the field of semiconductor technology. It includes a substrate layer, a gallium nitride layer, and a barrier layer, and a gate P-type gallium nitride layer and a first gate metal layer are arranged on the barrier layer. A source ohmic metal layer, a drain ohmic metal layer, and a source field plate metal layer and a drain field plate metal layer connected above each other are arranged on both sides of the gate P-type gallium nitride layer, and a hole injection structure is arranged between the gate P-type gallium nitride layer and the drain ohmic metal layer, and the hole injection structure includes a rectangular P-type gallium nitride layer, a second gate metal layer, and an ohmic metal column that penetrates the middle of the rectangular P-type gallium nitride layer and the second gate metal layer and connects the gallium nitride layer, and the ohmic metal column is connected to the drain field plate metal layer. By introducing this special structure, hole injection can be achieved, thereby effectively releasing the electrons captured in the device surface traps and buffer layer traps during hard switching operation, thereby improving the reliability of long-term operation of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride-based device and a preparation method thereof. Background Art

[0002] Gallium nitride materials have excellent properties such as wide bandgap, high breakdown electric field and high electron mobility, which enable gallium nitride-based devices to operate at higher voltages and frequencies while achieving low power consumption and high efficiency. Therefore, in the field of high-frequency and high-power switching devices, which have strict requirements on device switching speed, on-resistance and long-term reliability, gallium nitride-based devices have broad application prospects.

[0003] In the related art, under hard switching conditions, existing GaN high electron mobility transistors will suffer from the synergistic effect of high voltage and high current during the switching process. The trap state in the device material under the off-state bias will affect the channel carrier characteristics, leading to the current collapse effect, increasing the dynamic on-resistance of the device and deteriorating the switching characteristics of the device. This phenomenon will be more significant especially under high voltage stress and high frequency environment.

[0004] Therefore, in order to meet the application needs of GaN high electron mobility transistors as switching devices, it is urgent to solve the problems of increased on-resistance and current collapse caused by the thermal electron effect of this type of device under hard switching conditions, so that the trapped electrons can be released to ensure the normal operation and service life of the device. Summary of the invention

[0005] The present invention provides a gallium nitride-based device and a method for preparing the same. The present invention can solve the problems of increased on-resistance and current collapse under hard switching conditions caused by structural defects in conventional gallium nitride-based devices in the prior art, and improve the reliability of the device in long-term operation. The technical solution is as follows:

[0006] In a first aspect, the present invention provides a gallium nitride-based device, comprising a substrate layer, a gallium nitride layer, and a barrier layer arranged from bottom to top, wherein a gate P-type gallium nitride layer in a strip shape and extending along a first direction is arranged on the barrier layer, a first gate metal layer is arranged on the gate P-type gallium nitride layer, a source ohmic metal layer and a drain ohmic metal layer connected to the gallium nitride layer are arranged on both sides of the gate P-type gallium nitride layer, a source field plate metal layer is connected to the source ohmic metal layer, and a drain field plate metal layer is connected to the drain ohmic metal layer. A gate P-type gallium nitride layer and a drain ohmic metal layer are provided with a hole injection structure, wherein the hole injection structure comprises a rectangular P-type gallium nitride layer and a second gate metal layer provided on the barrier layer from bottom to top, and an ohmic metal column penetrating the middle of the rectangular P-type gallium nitride layer and the second gate metal layer and connecting the gallium nitride layer, wherein the top of the ohmic metal column is connected to the drain field plate metal layer, and the area from the barrier layer to the source field plate metal layer and the drain field plate metal layer is filled with a dielectric layer.

[0007] Optionally, a plurality of hole injection structures are provided and arranged at intervals along the first direction.

[0008] Optionally, in a second direction perpendicular to the first direction, widths of the rectangular P-type gallium nitride layers in at least two of the hole injection structures are different.

[0009] Optionally, in the second direction, the width of the second gate metal layer in the plurality of hole injection structures varies with the width of the rectangular P-type gallium nitride layer below.

[0010] Optionally, a thickness of the second gate metal layer surrounding the ohmic metal column is smaller than a minimum thickness of the rectangular P-type gallium nitride layer surrounding the ohmic metal column.

[0011] Optionally, the contour of the inner hole in the middle of the second gate metal layer for the ohmic metal column to pass through is smaller than or equal to the contour of the inner hole in the middle of the rectangular P-type gallium nitride layer for the ohmic metal column to pass through.

[0012] Optionally, the height of the ohmic metal column is equal to the height of the source ohmic metal layer and the drain ohmic metal layer.

[0013] Optionally, the cross-sectional profile of the ohmic metal column is square, circular or irregular.

[0014] Optionally, through holes are etched in the dielectric layer between the source ohmic metal layer and the source field plate metal layer, between the drain ohmic metal layer and the drain field plate metal layer, and between the ohmic metal column and the drain field plate metal layer, and the source ohmic metal layer and the source field plate metal layer, the drain ohmic metal layer and the drain field plate metal layer, and the ohmic metal column and the drain field plate metal layer are all connected by depositing metal through the through holes.

[0015] In a second aspect, an embodiment of the present invention provides a preparation method for manufacturing the gallium nitride-based device described in the first aspect, comprising:

[0016] Step 1: growing the substrate layer, the gallium nitride layer, the barrier layer and the P-type gallium nitride metal layer in sequence from bottom to top on the epitaxial wafer, and etching away the P-type gallium nitride metal layer in the non-patterned area to form the gate P-type gallium nitride layer and the rectangular P-type gallium nitride layer;

[0017] Step 2: depositing a dielectric layer on the entire barrier layer, etching and thinning the rectangular P-type gallium nitride layer, and etching away the source and drain regions and the dielectric layer and the barrier layer in the middle of the rectangular P-type gallium nitride layer;

[0018] Step 3: depositing the source ohmic metal layer, the drain ohmic metal layer and the ohmic metal column in the source and drain regions and in the middle of the rectangular P-type gallium nitride layer;

[0019] Step 4: etching and depositing the first gate metal layer on the gate P-type gallium nitride layer, and etching and depositing a second gate metal layer surrounding the ohmic metal column on the rectangular P-type gallium nitride layer;

[0020] Step 5: depositing a layer of the dielectric layer again, etching through holes on the source ohmic metal layer, the drain ohmic metal layer and the ohmic metal column respectively, and depositing metal;

[0021] Step 6: depositing a layer of the dielectric layer again, etching and depositing the source field plate metal layer connected to the source ohmic metal layer, and the drain field plate metal layer connected to the ohmic metal column and the drain ohmic metal layer.

[0022] The beneficial effects brought about by the technical solution provided by the present invention include at least:

[0023] The gallium nitride-based device provided by the embodiment of the present invention is compared with the traditional gallium nitride high electron mobility transistor structure. It introduces a hole injection structure consisting of a rectangular P-type gallium nitride layer, a second gate metal layer and an ohmic metal column in the region between the gate P-type gallium nitride layer as a gate structure and the drain ohmic metal layer of the drain structure. When a bias voltage is applied to the drain, holes are injected into the barrier layer and the gallium nitride layer through the rectangular P-type gallium nitride layer. The injected holes can effectively release the trapped electrons near the drain through carrier recombination and other means, thereby solving the problems of device current collapse and dynamic on-resistance degradation. Furthermore, the bottom surface of the ohmic metal column surrounded by the rectangular P-type gallium nitride layer and the second gate metal layer is in contact with the gallium nitride layer, so that the distance between the gate and the drain of the device is reduced, which to a certain extent balances the current reduction problem caused by setting a rectangular P-type gallium nitride layer near the drain side of the device, and weakens the influence of the rectangular P-type gallium nitride layer on the concentration of the two-dimensional electron gas in the device channel. The device structure is simple to manufacture, and the hole injection structure is grown simultaneously with the gate, source, and drain structures of the device, which is compatible with existing processes. Without affecting the normal operation of the device, it solves the problems of current collapse and dynamic on-resistance degradation caused by thermal electron effects under hard switching conditions, effectively improving the long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic diagram of a conventional gallium nitride-based device structure in the related art;

[0026] Figure 2 It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a barrier layer, a gate P-type gallium nitride layer and a rectangular P-type gallium nitride layer for a gallium nitride-based device provided in an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of the steps of etching a rectangular P-type gallium nitride layer and a source and drain region of a gallium nitride-based device in an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the steps of preparing a source ohmic metal layer, a drain ohmic metal layer and an ohmic metal column for a gallium nitride-based device in an embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of steps for preparing a first gate metal layer and a second gate metal layer of a gallium nitride-based device in an embodiment of the present invention;

[0030] Figure 6 It is a schematic diagram of the steps of preparing a through hole in a gallium nitride-based device provided by an embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of the overall structure of a gallium nitride-based device provided in an embodiment of the present invention;

[0032] Figure 8 is a schematic front view of the structure of a gallium nitride-based device provided in an embodiment of the present invention;

[0033] Fig. 9 It is a flow chart of the preparation method provided in an embodiment of the present invention.

[0034] In the figure: 1-substrate layer; 2-gallium nitride layer; 3-barrier layer; 4-gate P-type gallium nitride layer; 5-source ohmic metal layer; 6-drain ohmic metal layer; 7-hole injection structure; 8-dielectric layer; 9-through hole; 41-first gate metal layer; 51-source field plate metal layer; 61-drain field plate metal layer; 71-rectangular P-type gallium nitride layer; 72-second gate metal layer; 73-ohmic metal column; a-conventional substrate layer; b-conventional gallium nitride layer; c-conventional barrier layer; d-gate; e-drain. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0036] Figure 1 Schematic diagram of a conventional gallium nitride-based device structure in the related art. Figure 1As shown, the existing GaN-based device structure usually includes a conventional substrate layer a, a conventional GaN layer b, and a conventional barrier layer c arranged in sequence from bottom to top. A strip-shaped P-type GaN layer is provided in the gate region above the conventional barrier layer c to form an enhanced gate structure. For existing devices, when the device operates under hard switching conditions, the device will be subjected to the combined effects of high voltage and high current, causing the surface traps of the conventional barrier layer c and the buffer layer (conventional GaN layer b) traps to capture injected hot electrons in the off state. The trap here refers to the crystal defect center in the semiconductor that can capture electrons or holes. For GaN-based materials, there are traps of a certain concentration on the surface of the conventional barrier layer c and in the conventional GaN layer b, which will capture carriers. Under hard switching conditions, the device will be subjected to the combined effects of high voltage and high current. Electron-hole pairs will be generated in the region between the gate d and drain e of the device. Electrons move toward the drain e under the traction of the source-drain lateral electric field, while holes move in the opposite direction. In this process, electrons are easily captured by traps on the surface of the conventional barrier layer c and in the conventional gallium nitride layer b, which in turn depletes the two-dimensional electron gas in the channel, ultimately leading to current collapse and degradation of the dynamic on-resistance, which will have a serious impact on the long-term reliability of the device.

[0037] Figure 2 It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a barrier layer, a gate P-type gallium nitride layer and a rectangular P-type gallium nitride layer for a gallium nitride-based device provided in an embodiment of the present invention; Figure 3 Schematic diagram of the steps of etching a rectangular P-type gallium nitride layer and a source and drain region of a gallium nitride-based device in an embodiment of the present invention; Figure 4 It is a schematic diagram of the steps of preparing a source ohmic metal layer, a drain ohmic metal layer and an ohmic metal column for a gallium nitride-based device in an embodiment of the present invention; Figure 5 is a schematic diagram of steps for preparing a first gate metal layer and a second gate metal layer of a gallium nitride-based device in an embodiment of the present invention; Figure 6 It is a schematic diagram of the steps of preparing a through hole in a gallium nitride-based device provided by an embodiment of the present invention; Figure 7 is a schematic diagram of the overall structure of a gallium nitride-based device provided in an embodiment of the present invention; Figure 8 1 is a schematic diagram of the front view structure of a gallium nitride-based device provided in an embodiment of the present invention.

[0038] The embodiment of the present invention provides a gallium nitride-based device, comprising a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 arranged from bottom to top. A gate P-type gallium nitride layer 4 in a strip shape and extending along a first direction is arranged on the barrier layer 3, and a first gate metal layer 41 is arranged on the gate P-type gallium nitride layer 4. A source ohmic metal layer 5 and a drain ohmic metal layer 6 connected to the gallium nitride layer 2 are arranged on both sides of the gate P-type gallium nitride layer 4, a source field plate metal layer 51 is connected to the source ohmic metal layer 5, and a drain field plate metal layer 61 is connected to the drain ohmic metal layer 6. A hole injection structure 7 is arranged between the gate P-type gallium nitride layer 4 and the drain ohmic metal layer 6, and the hole injection structure 7 includes a rectangular P-type gallium nitride layer 71 and a second gate metal layer 72 arranged from bottom to top on the barrier layer 3, and an ohmic metal column 73 penetrating the middle of the rectangular P-type gallium nitride layer 71 and the second gate metal layer 72 and connected to the gallium nitride layer 2. The top of the ohmic metal column 73 is connected to the drain field plate metal layer 61 , and the area from the barrier layer 3 to the source field plate metal layer 51 and the drain field plate metal layer 61 is filled with a dielectric layer 8 .

[0039] In the embodiment of the present invention, when manufacturing the gallium nitride-based device, first refer to Figure 2 First, a silicon substrate layer 1 with a thickness of 0.65 mm, a gallium nitride layer 2 with a thickness of 2 μm, a barrier layer 3 with a thickness of 20 nm, and a P-type gallium nitride metal layer with a thickness of 100 nm are grown on the epitaxial wafer from bottom to top. Then, the P-type gallium nitride metal layer in the non-patterned area is removed by etching by inductively coupled plasma dry etching to form a long strip gate P-type gallium nitride layer 4 extending along the first direction, and a rectangular P-type gallium nitride layer 71 located on the side of the gate P-type gallium nitride layer 4 close to the drain of the subsequent device. It should be noted that in the embodiment of the present invention, the first direction is the extension direction of the long strip gate P-type gallium nitride layer 4 on the straight line, that is, the spacing arrangement direction when multiple rectangular P-type gallium nitride layers 71 are set in the figure.

[0040] Afterwards, refer to Figure 3 , a dielectric layer 8 is grown on the entire epitaxial wafer by plasma enhanced chemical vapor deposition, and the rectangular P-type gallium nitride layer 71 is thinned by etching by inductively coupled plasma dry etching. Then the dielectric layer 8 is grown again, and the source and drain regions, that is, the preset regions on both sides of the gate P-type gallium nitride layer 4 for setting the source and drain structures of the device, and the dielectric layer 8 and barrier layer 3 in the middle of the rectangular P-type gallium nitride layer 71 are etched away by inductively coupled plasma dry etching. The rectangular P-type gallium nitride layer 71 is processed into a structure with an opening in the middle connected to the gallium nitride layer 2, and the overall structure is in the shape of a "U".

[0041] Afterwards, refer to Figure 4 ,exist Figure 3The source and drain regions etched in the middle and the opening region in the middle of the rectangular P-type gallium nitride layer 71 are sequentially deposited with metal layers of Ti / Al (300nm / 700nm) to form a source ohmic metal layer 5, a drain ohmic metal layer 6 and an ohmic metal column 73, and the source ohmic metal layer 5, the drain ohmic metal layer 6 and the ohmic metal column 73 are all in contact with the top surface of the gallium nitride layer 2. The aforementioned "sequentially" means that when depositing the ohmic metal layer structure, a titanium metal layer with a thickness of 300nm is first deposited, and then an aluminum metal layer with a thickness of 700nm is deposited. Subsequent similar expressions have similar meanings.

[0042] Afterwards, refer to Figure 5 , a dielectric layer 8 is grown on the entire epitaxial wafer again, and the gate P-type gallium nitride layer 4 and the dielectric layer 8 above the rectangular P-type gallium nitride layer 71 are etched away by inductively coupled plasma dry etching and photolithography stripping, and gate metals of Ni / Al (300nm / 500nm) are deposited in sequence to form a first gate metal layer 41 that is also in a strip shape, and a second gate metal layer 72 that is also in a "U"-shaped structure and surrounds the ohmic metal column 73.

[0043] Afterwards, refer to Figure 6 , a dielectric layer 8 is grown on the entire epitaxial wafer again, and through holes 9 are etched on the source ohmic metal layer 5, the drain ohmic metal layer 6 and the ohmic metal column 73 by inductively coupled plasma dry etching and photolithography stripping, and tungsten metal is deposited to form a connecting section of the top field plate structure of the connected device. Exemplarily, in another possible implementation method, the ohmic metal column 73 can also be directly deposited upward during preparation to achieve the same Figure 6 The through holes 9 etched above the source ohmic metal layer 5 and the drain ohmic metal layer 6 are at the same height for subsequent direct connection with the drain field plate metal layer 61 above. At this time, there is no need to etch the through holes 9 and deposit metal above the ohmic metal column 73.

[0044] Finally, reference Figure 7 and Figure 8 , a dielectric layer 8 is deposited again, and a source field plate metal layer 51 connected to the source ohmic metal layer 5 and a drain field plate metal layer 61 connected to the ohmic metal column 73 and the drain ohmic metal layer 6 are etched and deposited above the through hole 9 by using a photolithography lift-off method, so as to complete the preparation of the transistor core part of the gallium nitride-based device.

[0045] Illustratively, in the embodiment of the present invention, the gate P-type gallium nitride layer 4 and the first gate metal layer thereon are collectively referred to as the gate of the gallium nitride-based device, the source ohmic metal layer 5 and the through hole 9 thereon, and the source field plate metal layer 51 are collectively referred to as the source of the gallium nitride-based device, and the drain ohmic metal layer 6 and the through hole thereon, and the drain field plate metal layer 61 are collectively referred to as the drain of the gallium nitride-based device.

[0046] Compared with the conventional GaN high electron mobility transistor structure, the GaN-based device provided by the embodiment of the present invention introduces a hole injection structure 7 composed of a rectangular P-type GaN layer 71, a second gate metal layer 72 and an ohmic metal column 73 in the region between the gate P-type GaN layer 4 as a gate structure and the drain ohmic metal layer 6 of the drain structure. When a bias voltage is applied to the drain, holes are injected into the barrier layer 3 and the GaN layer 2 through the rectangular P-type GaN layer 71. The injected holes can effectively release trapped electrons near the drain through carrier recombination and other means, thereby solving the problems of device current collapse and dynamic on-resistance degradation. Furthermore, the bottom surface of the ohmic metal column 73 surrounded by the rectangular P-type gallium nitride layer 71 and the second gate metal layer 72 is in contact with the gallium nitride layer 2, so that the distance between the gate and the drain of the device is reduced, which to a certain extent balances the current reduction problem caused by setting the rectangular P-type gallium nitride layer 71 on the side close to the drain of the device, and weakens the influence of the rectangular P-type gallium nitride layer on the concentration of the two-dimensional electron gas in the device channel. The device structure is simple to manufacture, and the hole injection structure 7 grows simultaneously with the gate, source, and drain structures of the device, which is compatible with the existing process. Without affecting the normal operation of the device, it solves the problems of current collapse and dynamic on-resistance degradation caused by the hot electron effect under hard switching conditions, and effectively improves the reliability of the long-term operation of the device.

[0047] Optionally, a plurality of hole injection structures 7 are provided and arranged at intervals along the first direction. Exemplarily, the total number of rectangular P-type gallium nitride layers 71 is n, n ≥ 1; the length of the outer contour of the nth rectangular P-type gallium nitride layer 71 along the first direction is l yn , 4≤l yn ≤50μm, the width along the second direction is l xn , 4≤l xn ≤16μm; the length and width of the inner hole of each rectangular P-type gallium nitride layer 71 distributed along the first direction are consistent, the length of the inner hole is f, 2≤f≤40μm, and the width is g, 2≤g≤5μm.

[0048] In the embodiment of the present invention, the thickness of the rectangular P-type gallium nitride layer 71 is 20 nm, which is less than the thickness of the gate P-type gallium nitride layer 4. The total number of rectangular P-type gallium nitride layers 71 is 3, so that multiple discharge channels can be formed at intervals in the length range of the entire device in the first direction to ensure the release efficiency of trapped electrons. In other possible implementations, according to the overall length of the device in the first direction, a larger number of rectangular P-type gallium nitride layers 71 can also be set to form a hole injection structure 7, and the embodiment of the present invention does not limit its specific number. The length l of the outer contour of the three rectangular P-type gallium nitride layers 71 distributed along the first direction y1 =l y2 =ly3 = 8 μm, the width in the second direction is l x1 =5μm, l x2 =7μm, l x3 =9 μm. The three rectangular openings inside the P-type gallium nitride layer 71 distributed along the first direction have a length f=4 μm and a width g=2 μm.

[0049] It should be noted that, in other possible implementations, the inner hole of the rectangular P-type gallium nitride layer 71, that is, the shape of the side of the ohmic metal column 73 is not limited to a rectangle, and can also be a square, a circle or other irregular shapes, such as various polygons. The use of the overall "U"-shaped rectangular P-type gallium nitride layer 71 structure and the rectangular columnar ohmic metal column 73 surrounded inside is based on the selection of standardized deposition and etching processes to ensure processing efficiency and accuracy.

[0050] Optionally, in a second direction perpendicular to the first direction, the widths of the rectangular P-type gallium nitride layers 71 in at least two hole injection structures 7 are different. Further, in the second direction, the width of the second gate metal layer 72 in the plurality of hole injection structures 7 varies with the width of the rectangular P-type gallium nitride layer 71 below. Exemplarily, in an embodiment of the present invention, from the perspective of injecting holes into the rectangular P-type gallium nitride layer 71 to release trapped electrons, solve current collapse and dynamic on-resistance degradation, the width of the rectangular P-type gallium nitride layer 71 along the second direction is as wide as possible. A too narrow rectangular P-type gallium nitride layer 71 has poor hole injection capability and cannot well release electrons captured by traps. The best choice is that the left side of the rectangular P-type gallium nitride layer 71 is very close to the gate P-type gallium nitride layer 4, the right side is very close to the drain ohmic metal layer 6, and the length and width of each rectangular P-type gallium nitride layer 71 distributed along the first direction are consistent. From the perspective of the influence of the rectangular P-type gallium nitride layer 71 on the current capability of the device itself, although the rectangular P-type gallium nitride layer 71 is etched and thinned, and there is an ohmic metal column 73 in the middle to pass the on-state current of the device, due to the existence of the heterogeneous pn junction barrier of the rectangular P-type gallium nitride layer 71-barrier layer 3 / gallium nitride layer 2, the rectangular P-type gallium nitride layer 71 will still have a certain depletion effect on the two-dimensional electron gas in the channel below it, so that the concentration of the two-dimensional electron gas is reduced. If multiple rectangular P-type gallium nitride layers 71 all adopt the design with the highest hole injection capability, it will have a certain negative impact on the performance of the device such as the on-state current capability. Therefore, in summary, the embodiment of the present invention adopts a design in which the rectangular P-type gallium nitride layer 71 is gradually widened in the second direction, which can better solve the device reliability problems of current collapse and dynamic on-resistance degradation by using the rectangular P-type gallium nitride layer 71, and balance the influence of the rectangular P-type gallium nitride layer 71 on the output current capability and other performance of the device, thereby ensuring the performance and reliability of the device for long-term operation. Furthermore, since the rectangular P-type gallium nitride layer 71 needs to be controlled by the second gate metal layer 72 to inject holes to release electrons captured in the device surface and buffer layer traps under hard switching conditions, as the width of the rectangular P-type gallium nitride layer 71 increases, the second gate metal layer 72 also needs to be widened to a certain extent to better control the rectangular P-type gallium nitride layer 71.

[0051] It should be noted that in other possible implementations, in the arrangement in the first direction, the widths of the plurality of rectangular P-type gallium nitride layers 71 in the second direction may also be arranged in other forms, such as: x1 =7μm, l x2 =5μm, l x3 =9μm, or l x1 =5μm, l x2 =5μm, l x3=7 μm, etc. As long as the widths of at least two rectangular P-type gallium nitride layers 71 are different in the first direction, the embodiment of the present invention does not limit the specific length and the arrangement order according to the length.

[0052] Furthermore, in other possible implementations, in the arrangement in the first direction, the lengths of the plurality of rectangular P-type gallium nitride layers 71 in the first direction and the spacing between adjacent rectangular P-type gallium nitride layers 71 may also be different. Accordingly, the length and width of the second gate metal layer 72 also increase or decrease adaptively according to the increase or decrease in the length and width of the rectangular P-type gallium nitride layer 71 below, and the amount of change is consistent with the amount of change in the length and width of the rectangular P-type gallium nitride layer 71.

[0053] Optionally, the distance between the right side of the n-th rectangular P-type gallium nitride layer 71 and the left side of the drain ohmic metal layer 6 along the first direction is d 1n , 2≤d 1n ≤5μm; along the first direction, the distance between the left side of the n-th rectangular P-type gallium nitride layer 71 and the right side of the gate P-type gallium nitride layer 4 is d 2n , 1≤d 2n ≤24μm; the distance between the rectangular P-type gallium nitride layer 71 and the right side of the gate P-type gallium nitride layer 4 and the left side of the drain ohmic metal layer 6 satisfies the relationship L GD =l xn +d 1n +d 2n , where L GD is the distance from the right side of the gate P-type gallium nitride layer 4 to the left side of the drain ohmic metal layer 6 of the device, 7≤L GD ≤30μm; if the total number of rectangular P-type gallium nitride layers 71 n>1, the interval between the mth and m+1th rectangular P-type gallium nitride layers 71 along the first direction is d m,m+1 , 1≤m≤n-1, 2≤d m,m+1 ≤50μm; the dimensions of the rectangular P-type gallium nitride layer 71 in the first direction satisfy the relationship W o =∑l yn +∑d m,m+1 , W o is the length of the source ohmic metal layer 5 and the drain ohmic metal layer 6 in the first direction, 10≤W o ≤500μm.

[0054] Preferably, the distance between the right side of the three rectangular P-type gallium nitride layers 71 distributed along the first direction and the left side of the drain ohmic metal layer 6 is d 11 =d 12 =d 13 =2μm; the distance between the rectangular P-type gallium nitride layer 71 and the right side of the gate P-type gallium nitride layer 4 and the left side of the drain ohmic metal layer 6 satisfies the relationship L GD =lxn +d 1n +d 2n = 20 μm, where L GD is the distance between the right side of the gate P-type gallium nitride layer 4 and the left side of the drain ohmic metal layer 6, and the distances between the left side of the three rectangular P-type gallium nitride layers 71 distributed along the first direction and the right side of the gate P-type gallium nitride layer 4 are d 21 =13μm, d 22 = 11 μm and d 23 =9 μm. The interval between the adjacent mth and m+1th rectangular P-type gallium nitride layers 71 distributed along the first direction is d 1,2 =d 2,3 =8μm. The dimensions of the rectangular P-type gallium nitride layer 71 in the first direction satisfy the relationship W o =∑l yn +∑d m,m+1 =40μm, W o is the length of the source ohmic metal layer 5 and the drain ohmic metal layer 6 in the first direction.

[0055] Optionally, the length of the outer contour of the nth second gate metal layer 72 along the first direction is c n , 3≤c n ≤49μm, the width in the second direction is e n ,3≤e n ≤15μm; the length and width of each inner hole of the second gate metal layer 72 distributed along the first direction are consistent, the length is f, 2≤f≤40μm, and the width is g, 2≤g≤5μm.

[0056] Preferably, the thickness of the second gate metal layer 72 is equal to the thickness of the first gate metal layer 41; the length of the outer contours of the three second gate metal layers 72 distributed along the first direction is c1=c2=c3=6μm, and the widths are e1=3μm, e2=5μm, and e3=7μm respectively. The length of the inner holes of the three second gate metal layers 72 distributed along the first direction is f=4μm, and the width is g=2μm. The spacing of the multiple second gate metal layers 72 in the first direction is 10μm.

[0057] Optionally, the thickness of the second gate metal layer 72 surrounding the ohmic metal column 73 is less than the minimum thickness of the rectangular P-type gallium nitride layer 71 surrounding the ohmic metal column 73. Exemplarily, in the embodiment of the present invention, the rectangular P-type gallium nitride layer 71 needs to wrap the ohmic metal column 73 on the side, and the thinnest wrapping thickness is 1 μm, and the front / rear side surfaces of the three ohmic metal columns 73 distributed along the first direction have the same thickness t wrapped by the rectangular P-type gallium nitride layer 71. y1n , t y1n =(l yn -l oy ) / 2,ty11 =t y12 =t y13 =2μm; the thickness t of the left / right side (second direction) of the three ohmic metal pillars 73 distributed along the first direction is wrapped by the rectangular P-type gallium nitride layer 71 l11 =1μm, t l12 =3μm, t l13 =6μm, t r11 =t r12 =t r13 =1μm; the second gate metal layer 72 needs to wrap the ohmic metal column 73 on the side, and the thinnest wrapping thickness is 0.5μm, and the front / rear sides of the three ohmic metal columns 73 distributed along the first direction have the same thickness t wrapped by the second gate metal layer 72 y2n , t y2n =(c n -l oy ) / 2,t y21 =t y22 =t y33 =1 μm; the thickness t of the left / right side (second direction) of the three ohmic metal pillars 73 distributed along the first direction being wrapped by the second gate metal layer 72 l2n = 0.5 μm, t l2n =1.5μm, t l2n =2.5μm, t r21 =t r22 =t r23 =0.5μm.

[0058] Optionally, the inner hole profile of the middle part of the second gate metal layer 72 for the ohmic metal column 73 to pass through is less than or equal to the inner hole profile of the middle part of the rectangular P-type gallium nitride layer 71 for the ohmic metal column 73 to pass through. Exemplarily, in an embodiment of the present invention, ideally, the inner hole of the rectangular P-type gallium nitride layer 71 and the inner hole of the second gate metal layer 72 are exactly the same in length and width, and the length / width of the ohmic metal column 73 at different heights are also consistent. However, in actual device preparation, the entire ohmic metal column 73 is first deposited, and then the second gate metal layer 72 is etched. When etching the dielectric layer 8 in the area corresponding to the rectangular P-type gallium nitride layer 71 to prepare for depositing the second gate metal layer 72, it is difficult to ensure that the ohmic metal column 73 is not etched in the process, that is, the length and width of the inner hole of the rectangular P-type gallium nitride layer 71 and the inner hole of the second gate metal layer 72 are exactly the same, which will add additional difficulty to the etching process. Therefore, in the actual device preparation process, there is a situation where a small part of the ohmic metal column 73 is also etched around, and then the second gate metal layer 72 is deposited. Therefore, the length / width of the ohmic metal column 73 at different heights depends on the length / width of the inner hole of the outer layer it wraps. Using this process to prepare the second gate metal layer 72 will not add additional difficulty to the process, and can also ensure that the second gate metal layer 72 has good control over the rectangular P-type gallium nitride layer 71 below, thereby improving the preparation efficiency.

[0059] Optionally, the side of the ohmic metal column 73 is tightly wrapped by the barrier layer 3, the rectangular P-type gallium nitride layer 71 and the second gate metal layer 72 from bottom to top, and the length / width of the ohmic metal column 73 at different heights depends on the length / width of the inner hole of the outer layer it wraps. The length of the ohmic metal column 73 wrapped by the rectangular P-type gallium nitride layer 71 is l oy1 , 2≤l oy1 ≤40μm, width l ox1 , 2≤l ox1 ≤5μm; the length of the ohmic metal column 73 wrapped by the second gate metal layer 72 is l oy2 , 2≤l oy2 ≤40μm, width l ox2 , 2≤l ox2 ≤5μm.

[0060] Preferably, the height of the ohmic metal column 73 is equal to the height of the source ohmic metal layer 5 and the drain ohmic metal layer 6. Exemplarily, in the embodiment of the present invention, the length and width of each ohmic metal column 73 distributed along the first direction are consistent at the same height, and the center of the upper top surface of each ohmic metal column 73 is located on the same straight line parallel to the first direction, which is convenient for the subsequent structural preparation of the source ohmic metal layer 5 and the drain ohmic metal layer 6 connected to the top field plate structure. The length of the ohmic metal column 73 surrounded by the rectangular P-type gallium nitride layer 71 is l oy1 =4μm, width l ox1 =2μm. The length of the ohmic metal column wrapped by the second gate metal layer 72 is l oy2 =4μm, width l ox2 =2μm.

[0061] Optionally, a through hole 9 is etched in the dielectric layer 8 between the source ohmic metal layer 5 and the source field plate metal layer 51, between the drain ohmic metal layer 6 and the drain field plate metal layer 61, and between the ohmic metal column 73 and the drain field plate metal layer 61, and the source ohmic metal layer 5 and the source field plate metal layer 51, the drain ohmic metal layer 6 and the drain field plate metal layer 61, and the ohmic metal column 73 and the drain field plate metal layer 61 are all connected by depositing metal through the through hole 9. Exemplarily, in an embodiment of the present invention, the length of the through hole 9 in the longitudinal direction is 0.5 μm, and the length in the first direction and the width in the second direction are both 1 μm. The through hole 9 is located at the top center of the ohmic metal column 73, and its edge is at least 0.5 μm away from the edge of the top surface of the ohmic metal column, or the edge of the source ohmic metal layer 5 and the drain ohmic metal layer 6.

[0062] Preferably, in the embodiment of the present invention, the width of the gate P-type gallium nitride layer 4 in the second direction is 2 μm, and the length in the first direction is 40 μm. The width and length of the first gate metal layer 41 are equal to the width and length of the gate P-type gallium nitride layer 4. The thickness of the gate P-type gallium nitride layer 4 in the longitudinal direction is 100 nm, and the thickness of the first gate metal layer 41 is 0.8 μm.

[0063] Preferably, in the embodiment of the present invention, the distance between the gate P-type gallium nitride layer 4 and the source ohmic metal layer 5 is 2 μm, and the distance between the gate P-type gallium nitride layer 4 and the drain ohmic metal layer 6 is L GD is 20 μm.

[0064] Preferably, in the embodiment of the present invention, the length W of the source ohmic metal layer 5 and the drain ohmic metal layer 6 in the first direction is o The width in the second direction is 40 μm, the width in the second direction is 3 μm, and the thickness in the longitudinal direction is 1 μm.

[0065] Preferably, the source field plate metal layer 51 and the drain field plate metal layer 61 have a thickness of 1 μm in the longitudinal direction and a length of 40 μm in the first direction. The width of the source field plate metal layer 51 in the second direction is 13 μm, the left side is flush with the source ohmic metal layer 5, and the right side is 10 μm away from the right side of the source ohmic metal layer 5. The width of the drain field plate metal layer 61 is 15 μm, the right side is flush with the drain ohmic metal layer 6, and the left side is 12 μm away from the left side of the drain ohmic metal layer 6. The source field plate metal layer 51 is 2 μm away from the drain field plate metal layer 61.

[0066] Fig. 9 Schematic diagram of the preparation method provided in the embodiment of the present invention. Fig. 9 As shown, the embodiment of the present invention also provides a preparation method for preparing Figures 2 to 8 The gallium nitride-based device shown comprises the following steps:

[0067] S1, the epitaxial wafer sequentially grows a substrate layer 1, a gallium nitride layer 2, a barrier layer 3 and a P-type gallium nitride metal layer from bottom to top, and etches away the P-type gallium nitride metal layer in the non-patterned area to form a gate P-type gallium nitride layer 4 and a rectangular P-type gallium nitride layer 71.

[0068] Specifically, first, a silicon substrate layer 1 with a thickness of 0.65 mm, a gallium nitride layer 2 with a thickness of 2 μm, a barrier layer 3 with a thickness of 20 nm, and a P-type gallium nitride metal layer with a thickness of 100 nm are grown on the epitaxial wafer from bottom to top. Then, the P-type gallium nitride metal layer in the non-patterned area is removed by etching using an inductively coupled plasma dry etching method to form a long strip gate P-type gallium nitride layer 4 extending along the first direction, and a rectangular P-type gallium nitride layer 71 located on the gate P-type gallium nitride layer 4 close to the drain of the subsequent device.

[0069] S2, depositing a dielectric layer 8 on the entire barrier layer 3, etching and thinning the rectangular P-type gallium nitride layer 71, and etching away the dielectric layer 8 and the barrier layer 3 in the source and drain region and the middle part of the rectangular P-type gallium nitride layer 71.

[0070] Specifically, a dielectric layer 8 is grown on the entire epitaxial wafer by plasma enhanced chemical vapor deposition, and the rectangular P-type gallium nitride layer 71 is thinned by etching by inductively coupled plasma dry etching. Then, the dielectric layer 8 is grown again, and the source and drain regions, that is, the preset regions on both sides of the gate P-type gallium nitride layer 4 for setting the source and drain structures of the device, and the dielectric layer 8 and the barrier layer 3 in the middle of the rectangular P-type gallium nitride layer 71 are etched and removed by inductively coupled plasma dry etching. The rectangular P-type gallium nitride layer 71 is processed into a structure with an opening in the middle connected to the gallium nitride layer 2, and the overall structure is in the shape of a "U".

[0071] S3 , depositing a source ohmic metal layer 5 , a drain ohmic metal layer 6 and an ohmic metal column 73 in the source and drain regions and in the middle of the rectangular P-type gallium nitride layer 71 .

[0072] Specifically, metal layers made of Ti / Al (300nm / 700nm) are sequentially deposited in the etched source and drain regions and the opening region in the middle of the rectangular P-type gallium nitride layer 71 to form a source ohmic metal layer 5, a drain ohmic metal layer 6 and an ohmic metal column 73. The source ohmic metal layer 5, the drain ohmic metal layer 6 and the ohmic metal column 73 are all in contact with the top surface of the gallium nitride layer 2.

[0073] S4, etching and depositing a first gate metal layer 41 on the gate P-type gallium nitride layer 4, and etching and depositing a second gate metal layer 72 surrounding the ohmic metal column 73 on the rectangular P-type gallium nitride layer 71.

[0074] Specifically, a dielectric layer 8 is grown on the entire epitaxial wafer again, and the gate P-type gallium nitride layer 4 and the dielectric layer 8 above the rectangular P-type gallium nitride layer 71 are etched away by inductively coupled plasma dry etching and photolithography stripping. Gate metals made of Ni / Al (300nm / 500nm) are deposited in sequence to form a first gate metal layer 41 that is also in a strip shape, and a second gate metal layer 72 that is also in a "U"-shaped structure and surrounds the ohmic metal column 73.

[0075] S5 , depositing a dielectric layer 8 again, etching through holes 9 on the source ohmic metal layer 5 , the drain ohmic metal layer 6 and the ohmic metal pillar 73 , and depositing metal.

[0076] Specifically, a dielectric layer 8 is grown on the entire epitaxial wafer again, and through-holes 9 are etched on the source ohmic metal layer 5, the drain ohmic metal layer 6 and the ohmic metal column 73 by inductively coupled plasma dry etching and photolithography stripping, and tungsten metal is deposited to form a connecting section of the top field plate structure of the connecting device.

[0077] S6 , deposit a dielectric layer 8 again, etch and deposit a source field plate metal layer 51 connected to the source ohmic metal layer 5 , and a drain field plate metal layer 61 connected to the ohmic metal column 73 and the drain ohmic metal layer 6 .

[0078] Specifically, a dielectric layer 8 is deposited again, and a source field plate metal layer 51 connected to the source ohmic metal layer 5 and a drain field plate metal layer 61 connected to the ohmic metal column 73 and the drain ohmic metal layer 6 are etched and deposited above the through hole 9 by using a photolithography lift-off method, so as to complete the preparation of the transistor core part of the gallium nitride-based device.

[0079] Compared with the conventional GaN high electron mobility transistor structure, the GaN-based device manufactured by the manufacturing method provided by the embodiment of the present invention introduces a hole injection structure 7 composed of a rectangular P-type GaN layer 71, a second gate metal layer 72 and an ohmic metal column 73 in the region between the gate P-type GaN layer 4 as a gate structure and the drain ohmic metal layer 6 of the drain structure. When a bias voltage is applied to the drain, holes are injected into the barrier layer 3 and the GaN layer 2 through the rectangular P-type GaN layer 71, and the injected holes can effectively release trapped electrons near the drain through carrier recombination and other means, thereby solving the problems of device current collapse and dynamic on-resistance degradation. Furthermore, the bottom surface of the ohmic metal column 73 surrounded by the rectangular P-type gallium nitride layer 71 and the second gate metal layer 72 is in contact with the gallium nitride layer 2, so that the distance between the gate and the drain of the device is reduced, which to a certain extent balances the current reduction problem caused by setting the rectangular P-type gallium nitride layer 71 on the side close to the drain of the device, and weakens the influence of the rectangular P-type gallium nitride layer on the concentration of the two-dimensional electron gas in the device channel. The device structure is simple to manufacture, and the hole injection structure 7 grows simultaneously with the gate, source, and drain structures of the device, which is compatible with the existing process. Without affecting the normal operation of the device, it solves the problems of current collapse and dynamic on-resistance degradation caused by the hot electron effect under hard switching conditions, and effectively improves the reliability of the long-term operation of the device.

[0080] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar words used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0081] The above descriptions are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A gallium nitride-based device, characterized in that: The invention comprises a substrate layer (1), a gallium nitride layer (2), and a barrier layer (3) arranged from bottom to top; a gate P-type gallium nitride layer (4) in a strip shape and extending along a first direction is arranged on the barrier layer (3); a first gate metal layer (41) is arranged on the gate P-type gallium nitride layer (4); a source ohmic metal layer (5) and a drain ohmic metal layer (6) connected to the gallium nitride layer (2) are arranged on both sides of the gate P-type gallium nitride layer (4); a source field plate metal layer (51) is connected to the source ohmic metal layer (5); a drain field plate metal layer (61) is connected to the drain ohmic metal layer (6); the gate P-type gallium nitride layer (4) is provided with a plurality of gate electrodes, and a plurality of gate electrodes are provided with a plurality of gate electrodes. A hole injection structure (7) is provided between the layer (4) and the drain ohmic metal layer (6), the hole injection structure (7) comprising a rectangular P-type gallium nitride layer (71) and a second gate metal layer (72) provided on the barrier layer (3) from bottom to top, and an ohmic metal column (73) penetrating the middle of the rectangular P-type gallium nitride layer (71) and the second gate metal layer (72) and connected to the gallium nitride layer (2), the top of the ohmic metal column (73) being connected to the drain field plate metal layer (61), and the region from the barrier layer (3) to the source field plate metal layer (51) and the drain field plate metal layer (61) being filled with a dielectric layer (8).

2. The gallium nitride-based device according to claim 1, characterized in that: A plurality of hole injection structures (7) are provided and are arranged at intervals along the first direction.

3. The gallium nitride-based device according to claim 2, characterized in that: In a second direction perpendicular to the first direction, the widths of the rectangular P-type gallium nitride layers (71) in at least two of the hole injection structures (7) are different.

4. The gallium nitride-based device according to claim 3, characterized in that: In the second direction, the width of the second gate metal layer (72) in the plurality of hole injection structures (7) varies with the width of the rectangular P-type gallium nitride layer (71) below.

5. The gallium nitride-based device according to claim 4, characterized in that: The thickness of the second gate metal layer (72) surrounding the ohmic metal column (73) is less than the minimum thickness of the rectangular P-type gallium nitride layer (71) surrounding the ohmic metal column (73).

6. The gallium nitride-based device according to claim 1, characterized in that: The profile of the inner hole in the middle of the second gate metal layer (72) through which the ohmic metal column (73) passes is smaller than or equal to the profile of the inner hole in the middle of the rectangular P-type gallium nitride layer (71) through which the ohmic metal column (73) passes.

7. The gallium nitride-based device according to claim 1, characterized in that: The height of the ohmic metal column (73) is equal to the height of the source ohmic metal layer (5) and the drain ohmic metal layer (6).

8. The gallium nitride-based device according to claim 1, characterized in that: The cross-sectional profile of the ohmic metal column (73) is square, circular or irregular.

9. The gallium nitride-based device according to claim 1, characterized in that: Through holes (9) are etched in the dielectric layer (8) between the source ohmic metal layer (5) and the source field plate metal layer (51), between the drain ohmic metal layer (6) and the drain field plate metal layer (61), and between the ohmic metal column (73) and the drain field plate metal layer (61); the source ohmic metal layer (5) and the source field plate metal layer (51), the drain ohmic metal layer (6) and the drain field plate metal layer (61), and the ohmic metal column (73) and the drain field plate metal layer (61) are all connected by depositing metal through the through holes (9).

10. A preparation method for manufacturing a gallium nitride-based device according to any one of claims 1 to 9, characterized in that: include: Step 1: growing the substrate layer (1), the gallium nitride layer (2), the barrier layer (3) and the P-type gallium nitride metal layer in sequence from bottom to top on the epitaxial wafer, and etching away the P-type gallium nitride metal layer in the non-patterned area to form the gate P-type gallium nitride layer (4) and the rectangular P-type gallium nitride layer (71); Step 2: depositing a layer of the dielectric layer (8) on the entire barrier layer (3), etching and thinning the rectangular P-type gallium nitride layer (71), and etching away the source and drain region and the dielectric layer (8) and the barrier layer (3) in the middle of the rectangular P-type gallium nitride layer (71); Step 3: depositing the source ohmic metal layer (5), the drain ohmic metal layer (6) and the ohmic metal column (73) in the source-drain region and in the middle of the rectangular P-type gallium nitride layer (71); Step 4: etching and depositing the first gate metal layer (41) on the gate P-type gallium nitride layer (4), and etching and depositing the second gate metal layer (72) surrounding the ohmic metal column (73) on the rectangular P-type gallium nitride layer (71); Step 5: depositing a layer of the dielectric layer (8) again, etching through holes (9) on the source ohmic metal layer (5), the drain ohmic metal layer (6) and the ohmic metal column (73), and depositing metal; Step 6: depositing a layer of the dielectric layer (8) again, etching and depositing the source field plate metal layer (51) connected to the source ohmic metal layer (5), and the drain field plate metal layer (61) connected to the ohmic metal column (73) and the drain ohmic metal layer (6).

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