A novel shield-gate MOSFET structure, its manufacturing method, and a chip

Abstract

This application belongs to the technical field of power devices, and provides a novel shield-gate MOSFET structure, a preparation method thereof, and a chip. A composite dielectric material layer and a shield-gate polysilicon layer are arranged in a groove of an N-type drift region. The composite dielectric material layer isolates the shield-gate polysilicon layer from the bottom and two side walls of the groove of the N-type drift region. Moreover, the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer. The first dielectric material layer is in contact with the N-type drift region. By arranging the first dielectric material layer with a lower dielectric constant on the side close to the N-type drift region and arranging the second dielectric material layer with a higher dielectric constant on the side close to the shield-gate polysilicon layer, the high dielectric constant characteristic of the second dielectric material layer can be used to achieve the same auxiliary depletion effect in the case of a thicker shield-gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate. At the same time, due to the proximity of the auxiliary depletion effect, the influence on the on-resistance of the device is relatively low.

Description

Technical Field

[0001] This application belongs to the technical field of power devices, and particularly relates to a novel shield-gate MOSFET structure, a preparation method thereof, and a chip. Background Art

[0002] The shield-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) has the advantages of low internal resistance, large saturation current, strong output ability, low power consumption, etc., and has been widely used in the fields of digital circuits, analog circuits, power management, radio frequency applications, etc.

[0003] The existing shield-gate MOSFET usually uses silicon dioxide (SiO2) as the gate oxide layer of the shield gate. This design can improve the breakdown voltage of the device to a certain extent. However, limited by the physical property of the relatively low dielectric constant of silicon dioxide, the thickness of the gate oxide layer of the shield gate cannot be too thick, otherwise the depletion of the drift region by the shield gate cannot be achieved. And although the thin SiO2 layer can achieve a good auxiliary depletion effect, it will cause breakdown at the thin SiO2 part of the device. For the above two reasons, the breakdown voltage of the device is relatively low. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of this application provide a novel shield-gate MOSFET structure, a preparation method thereof, and a chip, which can improve the breakdown voltage of the device with the novel shield-gate MOSFET structure.

[0005] The first aspect of the embodiments of this application provides a novel shield-gate MOSFET structure, including:

[0006] An N-type substrate;

[0007] An N-type drift region, and the N-type drift region is of a concave structure;

[0008] A composite dielectric material layer and a shield-gate polysilicon layer, and the composite dielectric material layer is used to isolate the shield-gate polysilicon layer from the bottom and two side walls of the groove of the N-type drift region; wherein, the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer, the dielectric constant of the first dielectric material layer is less than that of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region;

[0009] A gate dielectric material layer and a control gate polysilicon layer, the gate dielectric material layer is disposed in the groove of the N-type drift region, and the gate dielectric material layer wraps the control gate polysilicon layer;

[0010] A first P-type base region and a second P-type base region, the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively arranged on two side portions of the N-type drift region;

[0011] A first N-type doping region and a second N-type doping region, the first N-type doping region is located on the horizontal portion of the first P-type base region of the L-shaped structure and is in contact with the gate dielectric material layer, and the second N-type doping region is located on the horizontal portion of the second P-type base region of the L-shaped structure and is in contact with the gate dielectric material layer;

[0012] A source electrode layer, which is in contact with the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and is in contact with the shield gate polysilicon layer;

[0013] A drain electrode layer, the drain electrode layer is arranged on the back surface of the N-type substrate.

[0014] In some embodiments, the gate dielectric material layer is located above the first dielectric material layer, the second dielectric material layer and the shield gate polysilicon layer. The bottom of the gate dielectric material layer forms a closed cavity with the first dielectric material layer, and the shield gate polysilicon layer and the second dielectric material layer are located in the closed cavity.

[0015] In some embodiments, the material of the first dielectric material layer is the same as that of the gate dielectric material layer.

[0016] In some embodiments, the first dielectric material layer and the gate dielectric material layer are silicon dioxide; the second dielectric material layer is hafnium dioxide.

[0017] In some embodiments, the composite dielectric material layer further includes: a third dielectric material layer, the third dielectric material layer is arranged between the second dielectric material layer and the shield gate polysilicon layer, and the dielectric constant of the third dielectric material layer is greater than or equal to the dielectric constant of the first dielectric material layer.

[0018] In some embodiments, the shield gate polysilicon layer is in a stepped structure, and the width of the shield gate polysilicon layer gradually increases in the direction from the drain electrode layer to the source electrode layer.

[0019] In some embodiments, the thickness of the second dielectric material layer gradually decreases in the direction from the drain electrode layer to the source electrode layer.

[0020] In some embodiments, the first dielectric material layer and the second dielectric material layer are in a stepped structure.

[0021] In the second aspect of the embodiments of the present application, a preparation method of a novel shield gate MOSFET structure is further provided, and the preparation method includes:

[0022] An N-type drift layer is epitaxially formed on the front surface of the N-type substrate;

[0023] A first deep groove is formed in the central region of the N-type drift layer by an etching process, and an N-type drift region with a concave structure is formed;

[0024] A first dielectric material layer and a second dielectric material layer are sequentially formed along the inner wall of the N-type drift region to form a composite dielectric material layer, and a shield gate polysilicon layer is formed in the groove of the composite dielectric material layer; wherein, the composite dielectric material layer is used to isolate the shield gate polysilicon layer from the bottom and both side walls of the groove of the N-type drift region, the dielectric constant of the first dielectric material layer is less than that of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region;

[0025] A concave gate dielectric material layer is formed in the first deep groove, and a polysilicon layer material is filled to obtain a control gate polysilicon layer; the gate dielectric material layer wraps the control gate polysilicon layer;

[0026] P-type doping ions are implanted into the side portions of the N-type drift region to form a first P-type base region and a second P-type base region, and the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region;

[0027] N-type doping ions are implanted into partial regions of the first P-type base region and the second P-type base region to form a first N-type doped region and a second N-type doped region, and the first P-type base region and the second P-type base region are in an L-shaped structure. The first N-type doped region is located on the horizontal portion of the first P-type base region of the L-shaped structure and is in contact with the gate dielectric material layer, and the second N-type doped region is located on the horizontal portion of the second P-type base region of the L-shaped structure and is in contact with the gate dielectric material layer;

[0028] A source layer that is in contact with the first N-type doped region, the second N-type doped region, the first P-type base region, and the second P-type base region and is in contact with the shield gate polysilicon layer is formed;

[0029] A drain layer is formed on the back surface of the N-type substrate.

[0030] In the third aspect of the embodiments of the present application, a chip is further provided, including the novel shield gate MOSFET structure described in any one of the above embodiments.

[0031] Advantages of the embodiments of the present application: By providing a composite dielectric material layer and a shield gate polysilicon layer in the groove of the N-type drift region, the composite dielectric material layer isolates the shield gate polysilicon layer from the bottom and both side walls of the groove of the N-type drift region. Moreover, the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer. The first dielectric material layer is in contact with the N-type drift region. By providing the first dielectric material layer with a lower dielectric constant on the side close to the N-type drift region and the second dielectric material layer with a higher dielectric constant on the side close to the shield gate polysilicon layer, and utilizing the high dielectric constant characteristic of the second dielectric material layer, it is possible to achieve the same auxiliary depletion effect in the case of a thicker shield gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate. At the same time, since the auxiliary depletion effect is close, the influence on the on-resistance of the device is low. The proposed novel shield gate MOSFET structure of the present application optimizes the breakdown voltage of the device without changing the trench width and the platform width of the device, and does not increase the design cost of the shield gate device. Description of the Drawings

[0032] Figure 1 is the first schematic structural diagram of the novel shield gate MOSFET structure provided by the embodiments of the present application;

[0033] Figure 2 is the second schematic structural diagram of the novel shield gate MOSFET structure provided by the embodiments of the present application;

[0034] Figure 3 is the third schematic structural diagram of the novel shield gate MOSFET structure provided by the embodiments of the present application;

[0035] Figure 4 is the fourth schematic structural diagram of the novel shield gate MOSFET structure provided by the embodiments of the present application;

[0036] Figure 5 is a comparison diagram of the simulation results of the output characteristic curves of Comparative Structure 1, Comparative Structure 2, and the improved structure provided by the embodiments of the present application;

[0037] Figure 6 is a comparison diagram of the simulation results of the breakdown voltages of Comparative Structure 1, Comparative Structure 2, and the improved structure provided by the embodiments of the present application;

[0038] Figure 7 is the schematic flow diagram of the manufacturing method of the novel shield gate MOSFET structure provided by the embodiments of the present application;

[0039] Figure 8 is the schematic diagram of forming an N-type drift layer on an N-type substrate layer provided by the embodiments of the present application;

[0040] Figure 9It is a schematic diagram of forming an N-type drift region provided by an embodiment of the present application;

[0041] Figure 10 It is a schematic diagram of forming a first dielectric material layer in a first deep trench provided by an embodiment of the present application;

[0042] Figure 11 It is a schematic diagram of forming a second dielectric material layer provided by an embodiment of the present application;

[0043] Figure 12 It is a first schematic diagram of forming a shielding gate polysilicon layer provided by an embodiment of the present application;

[0044] Figure 13 It is a second schematic diagram of forming a shielding gate polysilicon layer provided by an embodiment of the present application;

[0045] Figure 14 It is a schematic diagram of forming a gate dielectric material layer provided by an embodiment of the present application;

[0046] Figure 15 It is a schematic diagram of forming a control gate polysilicon layer provided by an embodiment of the present application;

[0047] Figure 16 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type doping region, and a second N-type doping region provided by an embodiment of the present application. Detailed implementation manners

[0048] In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0050] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means one or more unless otherwise specifically defined.

[0052] Existing shield-gate MOSFETs typically use silicon dioxide (SiO2) as the gate oxide layer of the shield gate. This design can improve the breakdown voltage of the device to a certain extent. However, due to the physical property of the relatively low dielectric constant of silicon dioxide, the thickness of the gate oxide layer of the shield gate cannot be too thick, otherwise the depletion of the drift region by the shield gate cannot be achieved. Moreover, although a thinner SiO2 layer can achieve a better auxiliary depletion effect, it will cause breakdown at the thin SiO2 part of the device. Considering the above two points, the breakdown voltage of the device is relatively low.

[0053] A currently better solution is to replace silicon dioxide with an oxide having a higher dielectric constant, such as hafnium dioxide, etc. However, after replacing with a material having a high dielectric constant, under the same auxiliary depletion effect, a thicker oxide layer can be designed. But due to the large change in the dielectric constant, it is usually necessary to redesign the trench width and the platform width of the device, thereby increasing the design cost of the device. In addition, limited by the physical properties of the material, the dielectric constant of a single oxide layer can usually only change abruptly and cannot be flexibly selected.

[0054] The embodiment of this application provides a novel shield-gate MOSFET structure, which can improve the breakdown voltage of the device of the novel shield-gate MOSFET structure, and moreover, there is no need to redesign the trench width and the platform width of the device.

[0055] See Figure 1 As shown, the first aspect of the embodiment of this application provides a novel shield-gate MOSFET structure, including: an N-type substrate 210, an N-type drift region 220, a composite dielectric material layer 31, a shield-gate polysilicon layer 320, a gate dielectric material layer 411, a control-gate polysilicon layer 412, a first P-type base region 521, a second P-type base region 522, a first N-type doped region 511, a second N-type doped region 512, a source layer 120, and a drain layer 110.

[0056] Among them, the N-type drift region 220 has a concave structure. The composite dielectric material layer 31 is used to isolate the shield gate polysilicon layer 320 from the bottom and both side walls of the groove of the N-type drift region 220. The composite dielectric material layer 31 includes a first dielectric material layer 311 and a second dielectric material layer 312. The dielectric constant of the first dielectric material layer 311 is less than that of the second dielectric material layer 312. The first dielectric material layer 311 is in contact with the N-type drift region 220. The gate dielectric material layer 411 is disposed in the groove of the N-type drift region 220, and the gate dielectric material layer 411 wraps the control gate polysilicon layer 412. The first P-type base region 521 and the second P-type base region 522 have an L-shaped structure and are respectively disposed on both side portions of the N-type drift region 220. The first N-type doped region 511 is located on the horizontal portion of the first P-type base region 521 of the L-shaped structure and is in contact with the gate dielectric material layer 411. The second N-type doped region 512 is located on the horizontal portion of the second P-type base region 522 of the L-shaped structure and is in contact with the gate dielectric material layer 411. The source layer 120 is in contact with the first N-type doped region 511, the second N-type doped region 512, the first P-type base region 521, and the second P-type base region 522, and is in contact with the shield gate polysilicon layer 320. The drain layer 110 is disposed on the back surface of the N-type substrate 210.

[0057] In this application, by disposing the composite dielectric material layer 31 and the shield gate polysilicon layer 320 in the groove of the N-type drift region 220, the composite dielectric material layer 31 isolates the shield gate polysilicon layer 320 from the bottom and both side walls of the groove of the N-type drift region 220. The composite dielectric material layer 31 includes a first dielectric material layer 311 and a second dielectric material layer 312. The first dielectric material layer 311 is in contact with the N-type drift region 220. By disposing the first dielectric material layer 311 with a lower dielectric constant on the side close to the N-type drift region 220 and the second dielectric material layer 312 with a higher dielectric constant on the side close to the shield gate polysilicon layer 320, and utilizing the high dielectric constant characteristic of the second dielectric material layer 312, it is possible to achieve the same auxiliary depletion effect in the case of a thicker shield gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate. Moreover, since the auxiliary depletion effect is similar, the influence on the on-resistance of the device is relatively low. The novel shield gate MOSFET structure proposed in this application realizes the optimization of the breakdown voltage of the device without changing the trench width and the platform width of the device, and does not increase the design cost of the shield gate device.

[0058] In an embodiment of the present application, as Figure 1As shown, the gate dielectric material layer 411 can be located above the first dielectric material layer 311, the second dielectric material layer 312, and the shield gate polysilicon layer 320, such that the control gate polysilicon layer 412 and the shield gate polysilicon layer 320 are arranged in a vertical distribution structure. Moreover, the bottom of the gate dielectric material layer 411 can form a closed cavity with the first dielectric material layer 311, and the shield gate polysilicon layer 320 and the second dielectric material layer 312 are located within this closed cavity.

[0059] In an embodiment of the present application, as Figure 1 shown, when the control gate polysilicon layer 412 and the shield gate polysilicon layer 320 are arranged in a vertical distribution structure, the first dielectric material layer 311 is disposed on the inner wall of the N-type drift region 220, the second dielectric material layer 312 is disposed on the inner wall of the first dielectric material layer 311, the control gate polysilicon layer 412 is located within the groove of the second dielectric material layer 312, the first P-type base region 521 and the second P-type base region 522 are respectively disposed on the sides of the N-type drift region 220; the gate dielectric material layer 411 is located above the first dielectric material layer 311, the second dielectric material layer 312, and the control gate polysilicon layer 412, and the gate dielectric material layer 411 wraps the second shield gate polysilicon layer 320; the first N-type doped region 511 and the second N-type doped region 512, the first N-type doped region 511 is located on the horizontal portion of the first P-type base region 521 and is in contact with the first sidewall of the gate dielectric material layer 411, and the second N-type doped region 512 is located on the horizontal portion of the second P-type base region 522 and is in contact with the second sidewall of the gate dielectric material layer 411.

[0060] In an embodiment of the present application, in addition to the vertical distribution structure between the control gate polysilicon layer 412 and the shield gate polysilicon layer 320, they can also be arranged in a left-middle-right distribution structure.

[0061] As Figure 2 shown, the gate dielectric material layer 411 can be located on the left and right sides of the first dielectric material layer 311, the second dielectric material layer 312, and the shield gate polysilicon layer 320, and moreover, the control gate polysilicon layer 412 is located on both sides of the shield gate polysilicon layer 320, thereby making the control gate polysilicon layer 412 and the shield gate polysilicon layer 320 arranged in a left-middle-right distribution structure.

[0062] The present application does not limit the distribution manner of the shield gate polysilicon layer 320 and the control gate polysilicon layer 412. For the convenience of description, hereinafter, the solution of the present application will be mainly described by taking the vertical distribution structure between the control gate polysilicon layer 412 and the shield gate polysilicon layer 320 as an example.

[0063] In an embodiment of the present application, as Figure 1 shown, the second dielectric material layer 312 can be in a concave structure and semi-wrap the shield gate polysilicon layer 320.

[0064] In one embodiment of the present application, as Figure 4 shown, the second dielectric material layer 312 may also have a square structure and completely wrap the shield gate polysilicon layer 320.

[0065] In one embodiment of the present application, the materials of the first dielectric material layer 311 and the gate dielectric material layer 411 may be the same.

[0066] In one embodiment of the present application, the first dielectric material layer 311 and the gate dielectric material layer 411 are silicon dioxide, and the second dielectric material layer 312 is hafnium dioxide.

[0067] In one embodiment of the present application, the first dielectric material layer 311 and the gate dielectric material layer 411 are silicon dioxide, and the second dielectric material layer 312 is silicon nitride.

[0068] In one embodiment of the present application, the composite dielectric material layer 31 may further include a third dielectric material layer.

[0069] As Figure 3 shown, the third dielectric material layer may be disposed between the second dielectric material layer 312 and the shield gate polysilicon layer 320, and the dielectric constant of the third dielectric material layer is greater than or equal to the dielectric constant of the first dielectric material layer 311.

[0070] For example, in one embodiment of the present application, the first dielectric material layer 311 is silicon dioxide, the second dielectric material layer 312 is silicon nitride, and the third dielectric material layer is hafnium dioxide. That is, the dielectric constant of the third dielectric material layer is greater than the dielectric constants of the first dielectric material layer 311 and the second dielectric material layer 312, and the dielectric constant of the first dielectric material layer 311 is less than the dielectric constant of the second dielectric material layer 312.

[0071] Another example is that in one embodiment of the present application, the first dielectric material layer 311 is silicon dioxide, the second dielectric material layer 312 is hafnium dioxide, and the third dielectric material layer is silicon dioxide. That is, the dielectric constant of the third dielectric material layer is equal to the dielectric constant of the first dielectric material layer 311, and the dielectric constant of the first dielectric material layer 311 is less than the dielectric constant of the second dielectric material layer 312.

[0072] It should be noted that the above is only an example of the structure of the composite dielectric material layer 31, and does not represent a limitation on the protection scope of the present application. In other embodiments of the present application, the composite dielectric material layer 31 can also be implemented by other structures, as long as it satisfies at least including a first dielectric material layer and a second dielectric material layer. For example, the composite dielectric material layer 31 can also include more than three dielectric material layers, and at least includes two dielectric material layers with different dielectric constants. In the embodiments of the present application, all materials with different dielectric constants can be used to prepare the composite dielectric material layer 31.

[0073] In an embodiment of the present application, the shield gate polysilicon layer 320 can be a stepped structure, and the width of the shield gate polysilicon layer 320 gradually increases in the direction from the drain layer 110 to the source layer 120; correspondingly, the thickness of the second dielectric material layer 312 gradually decreases in the direction from the drain layer 110 to the source layer 120, so as to further optimize the electric field of the N-type drift layer.

[0074] For example, as Figure 4 shown, the shield gate polysilicon layer 320 is a stepped structure including one step, and the width of the shield gate polysilicon layer 320 near the drain layer 110 is smaller than the width near the source layer 120.

[0075] In an embodiment of the present application, the first dielectric material layer 311 and the second dielectric material layer 312 are stepped structures. That is, the thickness change of the first dielectric material layer 311 changes with the thickness change of the second dielectric material layer 312, so that the thickness difference between the first dielectric material layer 311 and the second dielectric material layer 312 at different depths is the same.

[0076] In some embodiments, the thickness of the second dielectric material layer 312 is less than the thickness of the first dielectric material layer 311.

[0077] In some embodiments, the thickness of the third dielectric material layer is greater than the thickness of the second dielectric material layer 312.

[0078] The performance of the novel shield gate MOSFET structure provided by the embodiments of the present application and the comparison structure provided by the embodiments of the present application is compared as follows:

[0079] The structure that uses a single silicon dioxide (SiO2) as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as Comparative Structure 1, the structure that uses a single hafnium dioxide (HfO2) as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as Comparative Structure 2, and the structure that uses the composite dielectric material layer 31 provided in the embodiment of the present application (the first dielectric material layer 311 is silicon dioxide, and the second dielectric material layer 312 is hafnium dioxide, that is, the composite dielectric material layer 31 of SiO2 + HfO2) as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as the improved structure (that is, the novel shielding gate MOSFET structure provided in the embodiment of the present application). The simulation results of these three structures are shown in Tables 1, 2, 3, and 4 below.

[0080] Among them, Table 1 shows the on-resistance Ron, breakdown voltage BV, and threshold voltage Vth corresponding to Comparative Structure 1 under silicon dioxide shielding gate oxide layers with different thicknesses; Table 2 shows the on-resistance Ron, breakdown voltage BV, and threshold voltage Vth corresponding to Comparative Structure 2 under hafnium dioxide shielding gate oxide layers with different thicknesses; Table 3 shows the on-resistance Ron, breakdown voltage BV, and threshold voltage Vth corresponding to the improved structure under silicon dioxide shielding gate oxide layers with different thicknesses when the total thickness of the shielding gate oxide layer is 0.45 um; the data of the structure in Table 4 are from the device structures with the optimal figure of merit (FOM) values (i.e., BV 2 / Ron) in Tables 1, 2, and 3 respectively.

[0081] Table 1:

[0082]

[0083] Table 2:

[0084]

[0085] Table 3:

[0086]

[0087] Table 4:

[0088]

[0089] As can be seen from Table 4 above, the breakdown voltage (BV) of the novel shield gate MOSFET structure with SiO2 + HfO2 as the shield gate oxide layer is increased by 24 V compared to that of the shield gate MOSFET structure with SiO2 as the shield gate oxide layer, and is increased by 34 V compared to that of the shield gate MOSFET structure with HfO2 as the shield gate oxide layer. In terms of the figure of merit (FOM) value, the FOM value of the novel shield gate MOSFET structure with SiO2 + HfO2 as the shield gate oxide layer is 286.6, which is increased by 125 (77.6%) compared to the FOM value of the shield gate MOSFET structure with SiO2 as the shield gate oxide layer, and is increased by 162 (131.7%) compared to the FOM value of the shield gate MOSFET structure with HfO2 as the shield gate oxide layer. There is no obvious change in the Ron and Vth of the three. The novel shield gate MOSFET structure with the composite dielectric material layer 31 as the shield gate oxide layer of the shield gate MOSFET can significantly improve the BV characteristic of the shield gate MOSFET and achieve a better FOM value.

[0090] Figure 5 FIG. is a comparative diagram of the simulation results of the output characteristic curves of the above three structures. Among them, the abscissa is the source-drain voltage Vds, and the ordinate is the source-drain current Ids. Figure 6 FIG. is a comparative diagram of the simulation results of the breakdown voltages of the above three structures. Among them, the abscissa is the source-drain voltage Vds, and the ordinate is the source-drain current Ids. Combining the above Tables 1, 2, 3, 4 and Figure 5 and Figure 6 as shown, compared with the shield gate MOSFET only including a single dielectric material layer, the on-resistance (Ron) and threshold voltage (Vth) of the novel shield gate MOSFET provided by the embodiment of the present application do not change significantly, but the breakdown voltage (BV) is significantly improved.

[0091] As Figure 7 shown, in the second aspect of the embodiment of the present application, a preparation method of a novel shield gate MOSFET structure is further provided, and the preparation method includes steps S100 to S800.

[0092] Step S100, epitaxially form an N-type drift layer on the front surface of the N-type substrate 210.

[0093] As Figure 8 shown, an N-type drift layer 221 with a thickness greater than that of the N-type substrate 210 can be formed by epitaxially growing on the front surface of the N-type substrate 210.

[0094] In an embodiment of the present application, the thickness of the N-type substrate 210 is 2 - 6 μm, and the concentration of N-type doping ions is 1e21 - 1.5e21 cm -3, the thickness of the N-type drift layer is 7 - 15 μm, and the concentration of N-type doping ions is 1e15 - 2e17 cm -3 .

[0095] Step S200, a first deep groove is formed in the central region of the N-type drift layer 221 through an etching process, and an N-type drift region 220 with a concave structure is formed.

[0096] As Figure 9 shown, the depth of the first deep groove can be greater than half of the depth of the N-type drift layer.

[0097] In an embodiment of the present application, the depth of the first deep groove is 4.5 - 7.5 μm, and the width is 0.7 - 1.2 μm.

[0098] Step S300, a first dielectric material layer 311 and a second dielectric material layer 312 are sequentially formed along the inner wall of the N-type drift region 220, and then a composite dielectric material layer 31 is formed, and a shield gate polysilicon layer 320 is formed in the groove of the composite dielectric material layer 31; wherein, the composite dielectric material layer 31 is used to isolate the shield gate polysilicon layer 320 from the bottom and both side walls of the groove of the N-type drift region 220, the dielectric constant of the first dielectric material layer 311 is less than that of the second dielectric material layer 312, and the first dielectric material layer 311 is in contact with the N-type drift region 220.

[0099] Step S400, a concave gate dielectric material layer 411 is formed in the first deep groove, and a polysilicon layer material is filled to obtain a control gate polysilicon layer 412; the gate dielectric material layer 411 wraps the control gate polysilicon layer 412.

[0100] As Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 shown, when the control gate polysilicon layer 412 and the shield gate polysilicon layer 320 are in an up-and-down distribution structure, in step S300 and step S400, a first dielectric material layer 311, a second dielectric material layer 312 can be sequentially formed along the inner wall of the N-type drift region 220 through a thermal oxidation process and a deposition process, and then a composite dielectric material layer 31 is formed to obtain Figure 11 the structure, wherein, the thickness of the second dielectric material layer 312 can be 0.1 - 0.3 μm. Then, a shield gate polysilicon layer 320 is formed in the groove of the composite dielectric material layer 31 to obtain Figure 12 the structure, and then, the first deep groove is etched back through an etching process, the etching depth is about 1.5 μm, and the thickness of the formed shield gate polysilicon layer 320 can be 0.5 - 5 μm to obtain as Figure 13 shown structure.

[0101] Next, a concave gate dielectric material layer 411 is formed in the first deep groove, and the polysilicon layer material is filled to obtain a control gate polysilicon layer 412, resulting in Figure 14 the structure. For example, first fill the first deep groove with SiO2 and etch back to form an oxide layer with a sidewall thickness of 0.2 - 0.4 um, and then form a gate oxide layer with a bottom thickness of about 0.5 - 1 um through the gate oxide process, thereby obtaining Figure 14 the gate dielectric material layer 411 in

[0102] Finally, deposit N-type polysilicon material in the gate dielectric material layer 411 to form a control gate polysilicon layer 412, and obtain Figure 15 the structure, where the thickness of the control gate polysilicon layer 412 can be 0.5 - 5 um, and the doping concentration is 1e18 - 1e21 cm -3 .

[0103] It should be noted that in the embodiments of the present application, in addition to the up-and-down distribution structure between the control gate polysilicon layer 412 and the shielding gate polysilicon layer 320, a left-middle-right distribution structure can also be adopted. For example, as Figure 2 shown, the gate dielectric material layer 411 can be located on the left and right sides of the first dielectric material layer 311, the second dielectric material layer 312, and the shielding gate polysilicon layer 320, and the control gate polysilicon layer 412 is located on both sides of the shielding gate polysilicon layer 320, so that a left-middle-right distribution structure is formed between the control gate polysilicon layer 412 and the shielding gate polysilicon layer 320.

[0104] The present application does not limit the distribution manner of the shielding gate polysilicon layer 320 and the control gate polysilicon layer 412.

[0105] Step S500, P-type doping ions are implanted into the side portions of the N-type drift region 220 to form a first P-type base region 521 and a second P-type base region 522, and the first P-type base region 521 and the second P-type base region 522 are respectively arranged on both sides of the N-type drift region 220.

[0106] In the embodiments of the present application, as Figure 16 shown, the widths of the first P-type base region 521 and the second P-type base region 522 can be equal to the widths of the two side portions of the N-type drift region 220 having a concave structure, and the depths of the first P-type base region 521 and the second P-type base region 522 can be equal to the depth of the control gate polysilicon layer 412.

[0107] Step S600: Inject N-type doping ions into partial regions of the first P-type base region 521 and the second P-type base region 522 to form a first N-type doped region 511 and a second N-type doped region 512, and make the first P-type base region 521 and the second P-type base region 522 have an L-shaped structure. The first N-type doped region 511 is located on the horizontal part of the first P-type base region 521 and is in contact with the gate dielectric material layer 411. The second N-type doped region 512 is located on the horizontal part of the second P-type base region 522 and is in contact with the gate dielectric material layer 411.

[0108] As Figure 16 shown, in an embodiment of the present application, the first N-type doped region 511 and the second N-type doped region 512 are located on both sides of the gate dielectric material layer 411, and the widths of the first N-type doped region 511 and the second N-type doped region 512 are greater than one-half of the widths of the first P-type base region 521 and the second P-type base region 522.

[0109] Step S700: Form a source layer 120 that is in contact with the first N-type doped region 511, the second N-type doped region 512, the first P-type base region 521, and the second P-type base region 522, and is in contact with the shield gate polysilicon layer 320.

[0110] Step S800: Form a drain layer 110 on the back surface of the N-type substrate 210.

[0111] The third aspect of the embodiment of the present application further provides a chip, including the novel shield gate MOSFET structure as described in any one of the above embodiments.

[0112] The beneficial effects of the embodiment of the present application: By arranging a composite dielectric material layer and a shield gate polysilicon layer in the groove of the N-type drift region, the composite dielectric material layer isolates the shield gate polysilicon layer from the bottom and two side walls of the N-type drift region groove. And the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer. The first dielectric material layer is in contact with the N-type drift region. By arranging the first dielectric material layer with a lower dielectric constant on the side close to the N-type drift region and the second dielectric material layer with a higher dielectric constant on the side close to the shield gate polysilicon layer, using the high dielectric constant characteristic of the second dielectric material layer, it is possible to achieve the same auxiliary depletion effect in the case of a thicker shield gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate. At the same time, due to the similar auxiliary depletion effect, the influence on the on-resistance of the device is relatively low. It realizes the optimization of the breakdown voltage of the novel shield gate MOSFET structure proposed in the present application without changing the trench width and the platform width of the device, and does not increase the design cost of the shield gate device.

[0113] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned divisions of each doping region and device are used as examples. In actual applications, the above functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. Each doping region and device in the embodiments can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0114] In addition, the specific names of each doping region and device are only for the convenience of mutual distinction and do not limit the protection scope of this application.

[0115] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0116] In addition, each doping region in each embodiment of this application can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0117] The above embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of this application, and should all be included in the protection scope of this application.

Claims

1. A novel shielded gate MOSFET structure, characterized in that: include: N-type substrate; An N-type drift region, wherein the N-type drift region is a concave structure; A composite dielectric material layer and a shielding gate polysilicon layer, wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the N-type drift region groove; wherein the composite dielectric material layer comprises a first dielectric material layer and a second dielectric material layer, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A gate dielectric material layer and a control gate polysilicon layer, wherein the gate dielectric material layer is disposed in the groove of the N-type drift region, and the gate dielectric material layer wraps the control gate polysilicon layer; A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively arranged at two sides of the N-type drift region; a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and contacting the shield gate polysilicon layer; a drain layer, the drain layer being arranged on the back side of the N-type substrate; the first dielectric material layer and the second dielectric material layer being in a stepped structure, the thickness of the second dielectric material layer gradually decreasing from the drain layer to the source layer, the thickness of the first dielectric material layer changing as the thickness of the second dielectric material layer changes, so that the thickness difference between the first dielectric material layer and the second dielectric material layer at different depths is the same; The shielding gate polysilicon layer is a stepped structure, and the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer.

2. The novel shielded gate MOSFET structure as claimed in claim 1, characterized in that: The gate dielectric material layer is located on the first dielectric material layer, the second dielectric material layer and the shielding gate polysilicon layer. The bottom of the gate dielectric material layer and the first dielectric material layer form a closed cavity. The shielding gate polysilicon layer and the second dielectric material layer are located in the closed cavity.

3. The novel shielded gate MOSFET structure as claimed in claim 2, characterized in that: The first dielectric material layer is made of the same material as the gate dielectric material layer.

4. The novel shielded gate MOSFET structure as claimed in claim 1, characterized in that: The first dielectric material layer and the gate dielectric material layer are silicon dioxide; the second dielectric material layer is hafnium dioxide.

5. The novel shielded gate MOSFET structure according to any one of claims 1 to 4, characterized in that: The composite dielectric material layer further comprises: A third dielectric material layer is disposed between the second dielectric material layer and the shielding gate polysilicon layer, and a dielectric constant of the third dielectric material layer is greater than or equal to a dielectric constant of the first dielectric material layer.

6. A method for preparing a novel shielded gate MOSFET structure, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench in the central region of the N-type drift layer by etching, and forming an N-type drift region with a concave structure; A composite dielectric material layer is formed after a first dielectric material layer and a second dielectric material layer are sequentially formed along the inner wall of the N-type drift region, and a shielding gate polysilicon layer is formed in the groove of the composite dielectric material layer; wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the groove of the N-type drift region, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A concave gate dielectric material layer is formed in the first deep groove, and is filled with a polysilicon layer material to obtain a control gate polysilicon layer; the gate dielectric material layer wraps the control gate polysilicon layer; Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region; Implanting N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and making the first P-type base region and the second P-type base region present an L-shaped structure, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and in contact with the shield gate polysilicon layer; forming a drain layer on the back side of the N-type substrate; The first dielectric material layer and the second dielectric material layer are of a stepped structure, the thickness of the second dielectric material layer gradually decreases from the drain layer to the source layer, and the thickness of the first dielectric material layer changes with the thickness of the second dielectric material layer, so that the thickness difference between the first dielectric material layer and the second dielectric material layer at different depths is the same; the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer, the shielding gate polysilicon layer is of a stepped structure, and the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer.

7. A chip, characterized in that: It comprises a novel shielded gate MOSFET structure as claimed in any one of claims 1 to 5.

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